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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2014-2017 Broadcom
4 */
5
6#ifndef __BCMGENET_H__
7#define __BCMGENET_H__
8
9#include <linux/skbuff.h>
10#include <linux/netdevice.h>
11#include <linux/spinlock.h>
12#include <linux/clk.h>
13#include <linux/mii.h>
14#include <linux/if_vlan.h>
15#include <linux/phy.h>
16#include <linux/dim.h>
17
18/* total number of Buffer Descriptors, same for Rx/Tx */
19#define TOTAL_DESC 256
20
21/* which ring is descriptor based */
22#define DESC_INDEX 16
23
24/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
25 * 1536 is multiple of 256 bytes
26 */
27#define ENET_BRCM_TAG_LEN 6
28#define ENET_PAD 8
29#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
30 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
31#define DMA_MAX_BURST_LENGTH 0x10
32
33/* misc. configuration */
34#define CLEAR_ALL_HFB 0xFF
35#define DMA_FC_THRESH_HI (TOTAL_DESC >> 4)
36#define DMA_FC_THRESH_LO 5
37
38/* 64B receive/transmit status block */
39struct status_64 {
40 u32 length_status; /* length and peripheral status */
41 u32 ext_status; /* Extended status*/
42 u32 rx_csum; /* partial rx checksum */
43 u32 unused1[9]; /* unused */
44 u32 tx_csum_info; /* Tx checksum info. */
45 u32 unused2[3]; /* unused */
46};
47
48/* Rx status bits */
49#define STATUS_RX_EXT_MASK 0x1FFFFF
50#define STATUS_RX_CSUM_MASK 0xFFFF
51#define STATUS_RX_CSUM_OK 0x10000
52#define STATUS_RX_CSUM_FR 0x20000
53#define STATUS_RX_PROTO_TCP 0
54#define STATUS_RX_PROTO_UDP 1
55#define STATUS_RX_PROTO_ICMP 2
56#define STATUS_RX_PROTO_OTHER 3
57#define STATUS_RX_PROTO_MASK 3
58#define STATUS_RX_PROTO_SHIFT 18
59#define STATUS_FILTER_INDEX_MASK 0xFFFF
60/* Tx status bits */
61#define STATUS_TX_CSUM_START_MASK 0X7FFF
62#define STATUS_TX_CSUM_START_SHIFT 16
63#define STATUS_TX_CSUM_PROTO_UDP 0x8000
64#define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF
65#define STATUS_TX_CSUM_LV 0x80000000
66
67/* DMA Descriptor */
68#define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */
69#define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */
70#define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */
71
72/* Rx/Tx common counter group */
73struct bcmgenet_pkt_counters {
74 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */
75 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */
76 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */
77 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */
78 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */
79 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */
80 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */
81 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/
82 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/
83 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/
84};
85
86/* RSV, Receive Status Vector */
87struct bcmgenet_rx_counters {
88 struct bcmgenet_pkt_counters pkt_cnt;
89 u32 pkt; /* RO (0x428) Received pkt count*/
90 u32 bytes; /* RO Received byte count */
91 u32 mca; /* RO # of Received multicast pkt */
92 u32 bca; /* RO # of Receive broadcast pkt */
93 u32 fcs; /* RO # of Received FCS error */
94 u32 cf; /* RO # of Received control frame pkt*/
95 u32 pf; /* RO # of Received pause frame pkt */
96 u32 uo; /* RO # of unknown op code pkt */
97 u32 aln; /* RO # of alignment error count */
98 u32 flr; /* RO # of frame length out of range count */
99 u32 cde; /* RO # of code error pkt */
100 u32 fcr; /* RO # of carrier sense error pkt */
101 u32 ovr; /* RO # of oversize pkt*/
102 u32 jbr; /* RO # of jabber count */
103 u32 mtue; /* RO # of MTU error pkt*/
104 u32 pok; /* RO # of Received good pkt */
105 u32 uc; /* RO # of unicast pkt */
106 u32 ppp; /* RO # of PPP pkt */
107 u32 rcrc; /* RO (0x470),# of CRC match pkt */
108};
109
110/* TSV, Transmit Status Vector */
111struct bcmgenet_tx_counters {
112 struct bcmgenet_pkt_counters pkt_cnt;
113 u32 pkts; /* RO (0x4a8) Transmited pkt */
114 u32 mca; /* RO # of xmited multicast pkt */
115 u32 bca; /* RO # of xmited broadcast pkt */
116 u32 pf; /* RO # of xmited pause frame count */
117 u32 cf; /* RO # of xmited control frame count */
118 u32 fcs; /* RO # of xmited FCS error count */
119 u32 ovr; /* RO # of xmited oversize pkt */
120 u32 drf; /* RO # of xmited deferral pkt */
121 u32 edf; /* RO # of xmited Excessive deferral pkt*/
122 u32 scl; /* RO # of xmited single collision pkt */
123 u32 mcl; /* RO # of xmited multiple collision pkt*/
124 u32 lcl; /* RO # of xmited late collision pkt */
125 u32 ecl; /* RO # of xmited excessive collision pkt*/
126 u32 frg; /* RO # of xmited fragments pkt*/
127 u32 ncl; /* RO # of xmited total collision count */
128 u32 jbr; /* RO # of xmited jabber count*/
129 u32 bytes; /* RO # of xmited byte count */
130 u32 pok; /* RO # of xmited good pkt */
131 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */
132};
133
134struct bcmgenet_mib_counters {
135 struct bcmgenet_rx_counters rx;
136 struct bcmgenet_tx_counters tx;
137 u32 rx_runt_cnt;
138 u32 rx_runt_fcs;
139 u32 rx_runt_fcs_align;
140 u32 rx_runt_bytes;
141 u32 rbuf_ovflow_cnt;
142 u32 rbuf_err_cnt;
143 u32 mdf_err_cnt;
144 u32 alloc_rx_buff_failed;
145 u32 rx_dma_failed;
146 u32 tx_dma_failed;
147};
148
149#define UMAC_HD_BKP_CTRL 0x004
150#define HD_FC_EN (1 << 0)
151#define HD_FC_BKOFF_OK (1 << 1)
152#define IPG_CONFIG_RX_SHIFT 2
153#define IPG_CONFIG_RX_MASK 0x1F
154
155#define UMAC_CMD 0x008
156#define CMD_TX_EN (1 << 0)
157#define CMD_RX_EN (1 << 1)
158#define UMAC_SPEED_10 0
159#define UMAC_SPEED_100 1
160#define UMAC_SPEED_1000 2
161#define UMAC_SPEED_2500 3
162#define CMD_SPEED_SHIFT 2
163#define CMD_SPEED_MASK 3
164#define CMD_PROMISC (1 << 4)
165#define CMD_PAD_EN (1 << 5)
166#define CMD_CRC_FWD (1 << 6)
167#define CMD_PAUSE_FWD (1 << 7)
168#define CMD_RX_PAUSE_IGNORE (1 << 8)
169#define CMD_TX_ADDR_INS (1 << 9)
170#define CMD_HD_EN (1 << 10)
171#define CMD_SW_RESET (1 << 13)
172#define CMD_LCL_LOOP_EN (1 << 15)
173#define CMD_AUTO_CONFIG (1 << 22)
174#define CMD_CNTL_FRM_EN (1 << 23)
175#define CMD_NO_LEN_CHK (1 << 24)
176#define CMD_RMT_LOOP_EN (1 << 25)
177#define CMD_PRBL_EN (1 << 27)
178#define CMD_TX_PAUSE_IGNORE (1 << 28)
179#define CMD_TX_RX_EN (1 << 29)
180#define CMD_RUNT_FILTER_DIS (1 << 30)
181
182#define UMAC_MAC0 0x00C
183#define UMAC_MAC1 0x010
184#define UMAC_MAX_FRAME_LEN 0x014
185
186#define UMAC_MODE 0x44
187#define MODE_LINK_STATUS (1 << 5)
188
189#define UMAC_EEE_CTRL 0x064
190#define EN_LPI_RX_PAUSE (1 << 0)
191#define EN_LPI_TX_PFC (1 << 1)
192#define EN_LPI_TX_PAUSE (1 << 2)
193#define EEE_EN (1 << 3)
194#define RX_FIFO_CHECK (1 << 4)
195#define EEE_TX_CLK_DIS (1 << 5)
196#define DIS_EEE_10M (1 << 6)
197#define LP_IDLE_PREDICTION_MODE (1 << 7)
198
199#define UMAC_EEE_LPI_TIMER 0x068
200#define UMAC_EEE_WAKE_TIMER 0x06C
201#define UMAC_EEE_REF_COUNT 0x070
202#define EEE_REFERENCE_COUNT_MASK 0xffff
203
204#define UMAC_TX_FLUSH 0x334
205
206#define UMAC_MIB_START 0x400
207
208#define UMAC_MDIO_CMD 0x614
209#define MDIO_START_BUSY (1 << 29)
210#define MDIO_READ_FAIL (1 << 28)
211#define MDIO_RD (2 << 26)
212#define MDIO_WR (1 << 26)
213#define MDIO_PMD_SHIFT 21
214#define MDIO_PMD_MASK 0x1F
215#define MDIO_REG_SHIFT 16
216#define MDIO_REG_MASK 0x1F
217
218#define UMAC_RBUF_OVFL_CNT_V1 0x61C
219#define RBUF_OVFL_CNT_V2 0x80
220#define RBUF_OVFL_CNT_V3PLUS 0x94
221
222#define UMAC_MPD_CTRL 0x620
223#define MPD_EN (1 << 0)
224#define MPD_PW_EN (1 << 27)
225#define MPD_MSEQ_LEN_SHIFT 16
226#define MPD_MSEQ_LEN_MASK 0xFF
227
228#define UMAC_MPD_PW_MS 0x624
229#define UMAC_MPD_PW_LS 0x628
230#define UMAC_RBUF_ERR_CNT_V1 0x634
231#define RBUF_ERR_CNT_V2 0x84
232#define RBUF_ERR_CNT_V3PLUS 0x98
233#define UMAC_MDF_ERR_CNT 0x638
234#define UMAC_MDF_CTRL 0x650
235#define UMAC_MDF_ADDR 0x654
236#define UMAC_MIB_CTRL 0x580
237#define MIB_RESET_RX (1 << 0)
238#define MIB_RESET_RUNT (1 << 1)
239#define MIB_RESET_TX (1 << 2)
240
241#define RBUF_CTRL 0x00
242#define RBUF_64B_EN (1 << 0)
243#define RBUF_ALIGN_2B (1 << 1)
244#define RBUF_BAD_DIS (1 << 2)
245
246#define RBUF_STATUS 0x0C
247#define RBUF_STATUS_WOL (1 << 0)
248#define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1)
249#define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2)
250
251#define RBUF_CHK_CTRL 0x14
252#define RBUF_RXCHK_EN (1 << 0)
253#define RBUF_SKIP_FCS (1 << 4)
254
255#define RBUF_ENERGY_CTRL 0x9c
256#define RBUF_EEE_EN (1 << 0)
257#define RBUF_PM_EN (1 << 1)
258
259#define RBUF_TBUF_SIZE_CTRL 0xb4
260
261#define RBUF_HFB_CTRL_V1 0x38
262#define RBUF_HFB_FILTER_EN_SHIFT 16
263#define RBUF_HFB_FILTER_EN_MASK 0xffff0000
264#define RBUF_HFB_EN (1 << 0)
265#define RBUF_HFB_256B (1 << 1)
266#define RBUF_ACPI_EN (1 << 2)
267
268#define RBUF_HFB_LEN_V1 0x3C
269#define RBUF_FLTR_LEN_MASK 0xFF
270#define RBUF_FLTR_LEN_SHIFT 8
271
272#define TBUF_CTRL 0x00
273#define TBUF_BP_MC 0x0C
274#define TBUF_ENERGY_CTRL 0x14
275#define TBUF_EEE_EN (1 << 0)
276#define TBUF_PM_EN (1 << 1)
277
278#define TBUF_CTRL_V1 0x80
279#define TBUF_BP_MC_V1 0xA0
280
281#define HFB_CTRL 0x00
282#define HFB_FLT_ENABLE_V3PLUS 0x04
283#define HFB_FLT_LEN_V2 0x04
284#define HFB_FLT_LEN_V3PLUS 0x1C
285
286/* uniMac intrl2 registers */
287#define INTRL2_CPU_STAT 0x00
288#define INTRL2_CPU_SET 0x04
289#define INTRL2_CPU_CLEAR 0x08
290#define INTRL2_CPU_MASK_STATUS 0x0C
291#define INTRL2_CPU_MASK_SET 0x10
292#define INTRL2_CPU_MASK_CLEAR 0x14
293
294/* INTRL2 instance 0 definitions */
295#define UMAC_IRQ_SCB (1 << 0)
296#define UMAC_IRQ_EPHY (1 << 1)
297#define UMAC_IRQ_PHY_DET_R (1 << 2)
298#define UMAC_IRQ_PHY_DET_F (1 << 3)
299#define UMAC_IRQ_LINK_UP (1 << 4)
300#define UMAC_IRQ_LINK_DOWN (1 << 5)
301#define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
302#define UMAC_IRQ_UMAC (1 << 6)
303#define UMAC_IRQ_UMAC_TSV (1 << 7)
304#define UMAC_IRQ_TBUF_UNDERRUN (1 << 8)
305#define UMAC_IRQ_RBUF_OVERFLOW (1 << 9)
306#define UMAC_IRQ_HFB_SM (1 << 10)
307#define UMAC_IRQ_HFB_MM (1 << 11)
308#define UMAC_IRQ_MPD_R (1 << 12)
309#define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
310#define UMAC_IRQ_RXDMA_PDONE (1 << 14)
311#define UMAC_IRQ_RXDMA_BDONE (1 << 15)
312#define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE
313#define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
314#define UMAC_IRQ_TXDMA_PDONE (1 << 17)
315#define UMAC_IRQ_TXDMA_BDONE (1 << 18)
316#define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE
317
318/* Only valid for GENETv3+ */
319#define UMAC_IRQ_MDIO_DONE (1 << 23)
320#define UMAC_IRQ_MDIO_ERROR (1 << 24)
321
322/* INTRL2 instance 1 definitions */
323#define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
324#define UMAC_IRQ1_RX_INTR_MASK 0xFFFF
325#define UMAC_IRQ1_RX_INTR_SHIFT 16
326
327/* Register block offsets */
328#define GENET_SYS_OFF 0x0000
329#define GENET_GR_BRIDGE_OFF 0x0040
330#define GENET_EXT_OFF 0x0080
331#define GENET_INTRL2_0_OFF 0x0200
332#define GENET_INTRL2_1_OFF 0x0240
333#define GENET_RBUF_OFF 0x0300
334#define GENET_UMAC_OFF 0x0800
335
336/* SYS block offsets and register definitions */
337#define SYS_REV_CTRL 0x00
338#define SYS_PORT_CTRL 0x04
339#define PORT_MODE_INT_EPHY 0
340#define PORT_MODE_INT_GPHY 1
341#define PORT_MODE_EXT_EPHY 2
342#define PORT_MODE_EXT_GPHY 3
343#define PORT_MODE_EXT_RVMII_25 (4 | BIT(4))
344#define PORT_MODE_EXT_RVMII_50 4
345#define LED_ACT_SOURCE_MAC (1 << 9)
346
347#define SYS_RBUF_FLUSH_CTRL 0x08
348#define SYS_TBUF_FLUSH_CTRL 0x0C
349#define RBUF_FLUSH_CTRL_V1 0x04
350
351/* Ext block register offsets and definitions */
352#define EXT_EXT_PWR_MGMT 0x00
353#define EXT_PWR_DOWN_BIAS (1 << 0)
354#define EXT_PWR_DOWN_DLL (1 << 1)
355#define EXT_PWR_DOWN_PHY (1 << 2)
356#define EXT_PWR_DN_EN_LD (1 << 3)
357#define EXT_ENERGY_DET (1 << 4)
358#define EXT_IDDQ_FROM_PHY (1 << 5)
359#define EXT_IDDQ_GLBL_PWR (1 << 7)
360#define EXT_PHY_RESET (1 << 8)
361#define EXT_ENERGY_DET_MASK (1 << 12)
362#define EXT_PWR_DOWN_PHY_TX (1 << 16)
363#define EXT_PWR_DOWN_PHY_RX (1 << 17)
364#define EXT_PWR_DOWN_PHY_SD (1 << 18)
365#define EXT_PWR_DOWN_PHY_RD (1 << 19)
366#define EXT_PWR_DOWN_PHY_EN (1 << 20)
367
368#define EXT_RGMII_OOB_CTRL 0x0C
369#define RGMII_MODE_EN_V123 (1 << 0)
370#define RGMII_LINK (1 << 4)
371#define OOB_DISABLE (1 << 5)
372#define RGMII_MODE_EN (1 << 6)
373#define ID_MODE_DIS (1 << 16)
374
375#define EXT_GPHY_CTRL 0x1C
376#define EXT_CFG_IDDQ_BIAS (1 << 0)
377#define EXT_CFG_PWR_DOWN (1 << 1)
378#define EXT_CK25_DIS (1 << 4)
379#define EXT_GPHY_RESET (1 << 5)
380
381/* DMA rings size */
382#define DMA_RING_SIZE (0x40)
383#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1))
384
385/* DMA registers common definitions */
386#define DMA_RW_POINTER_MASK 0x1FF
387#define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF
388#define DMA_P_INDEX_DISCARD_CNT_SHIFT 16
389#define DMA_BUFFER_DONE_CNT_MASK 0xFFFF
390#define DMA_BUFFER_DONE_CNT_SHIFT 16
391#define DMA_P_INDEX_MASK 0xFFFF
392#define DMA_C_INDEX_MASK 0xFFFF
393
394/* DMA ring size register */
395#define DMA_RING_SIZE_MASK 0xFFFF
396#define DMA_RING_SIZE_SHIFT 16
397#define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
398
399/* DMA interrupt threshold register */
400#define DMA_INTR_THRESHOLD_MASK 0x01FF
401
402/* DMA XON/XOFF register */
403#define DMA_XON_THREHOLD_MASK 0xFFFF
404#define DMA_XOFF_THRESHOLD_MASK 0xFFFF
405#define DMA_XOFF_THRESHOLD_SHIFT 16
406
407/* DMA flow period register */
408#define DMA_FLOW_PERIOD_MASK 0xFFFF
409#define DMA_MAX_PKT_SIZE_MASK 0xFFFF
410#define DMA_MAX_PKT_SIZE_SHIFT 16
411
412
413/* DMA control register */
414#define DMA_EN (1 << 0)
415#define DMA_RING_BUF_EN_SHIFT 0x01
416#define DMA_RING_BUF_EN_MASK 0xFFFF
417#define DMA_TSB_SWAP_EN (1 << 20)
418
419/* DMA status register */
420#define DMA_DISABLED (1 << 0)
421#define DMA_DESC_RAM_INIT_BUSY (1 << 1)
422
423/* DMA SCB burst size register */
424#define DMA_SCB_BURST_SIZE_MASK 0x1F
425
426/* DMA activity vector register */
427#define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF
428
429/* DMA backpressure mask register */
430#define DMA_BACKPRESSURE_MASK 0x1FFFF
431#define DMA_PFC_ENABLE (1 << 31)
432
433/* DMA backpressure status register */
434#define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF
435
436/* DMA override register */
437#define DMA_LITTLE_ENDIAN_MODE (1 << 0)
438#define DMA_REGISTER_MODE (1 << 1)
439
440/* DMA timeout register */
441#define DMA_TIMEOUT_MASK 0xFFFF
442#define DMA_TIMEOUT_VAL 5000 /* micro seconds */
443
444/* TDMA rate limiting control register */
445#define DMA_RATE_LIMIT_EN_MASK 0xFFFF
446
447/* TDMA arbitration control register */
448#define DMA_ARBITER_MODE_MASK 0x03
449#define DMA_RING_BUF_PRIORITY_MASK 0x1F
450#define DMA_RING_BUF_PRIORITY_SHIFT 5
451#define DMA_PRIO_REG_INDEX(q) ((q) / 6)
452#define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
453#define DMA_RATE_ADJ_MASK 0xFF
454
455/* Tx/Rx Dma Descriptor common bits*/
456#define DMA_BUFLENGTH_MASK 0x0fff
457#define DMA_BUFLENGTH_SHIFT 16
458#define DMA_OWN 0x8000
459#define DMA_EOP 0x4000
460#define DMA_SOP 0x2000
461#define DMA_WRAP 0x1000
462/* Tx specific Dma descriptor bits */
463#define DMA_TX_UNDERRUN 0x0200
464#define DMA_TX_APPEND_CRC 0x0040
465#define DMA_TX_OW_CRC 0x0020
466#define DMA_TX_DO_CSUM 0x0010
467#define DMA_TX_QTAG_SHIFT 7
468
469/* Rx Specific Dma descriptor bits */
470#define DMA_RX_CHK_V3PLUS 0x8000
471#define DMA_RX_CHK_V12 0x1000
472#define DMA_RX_BRDCAST 0x0040
473#define DMA_RX_MULT 0x0020
474#define DMA_RX_LG 0x0010
475#define DMA_RX_NO 0x0008
476#define DMA_RX_RXER 0x0004
477#define DMA_RX_CRC_ERROR 0x0002
478#define DMA_RX_OV 0x0001
479#define DMA_RX_FI_MASK 0x001F
480#define DMA_RX_FI_SHIFT 0x0007
481#define DMA_DESC_ALLOC_MASK 0x00FF
482
483#define DMA_ARBITER_RR 0x00
484#define DMA_ARBITER_WRR 0x01
485#define DMA_ARBITER_SP 0x02
486
487struct enet_cb {
488 struct sk_buff *skb;
489 void __iomem *bd_addr;
490 DEFINE_DMA_UNMAP_ADDR(dma_addr);
491 DEFINE_DMA_UNMAP_LEN(dma_len);
492};
493
494/* power management mode */
495enum bcmgenet_power_mode {
496 GENET_POWER_CABLE_SENSE = 0,
497 GENET_POWER_PASSIVE,
498 GENET_POWER_WOL_MAGIC,
499};
500
501struct bcmgenet_priv;
502
503/* We support both runtime GENET detection and compile-time
504 * to optimize code-paths for a given hardware
505 */
506enum bcmgenet_version {
507 GENET_V1 = 1,
508 GENET_V2,
509 GENET_V3,
510 GENET_V4,
511 GENET_V5
512};
513
514#define GENET_IS_V1(p) ((p)->version == GENET_V1)
515#define GENET_IS_V2(p) ((p)->version == GENET_V2)
516#define GENET_IS_V3(p) ((p)->version == GENET_V3)
517#define GENET_IS_V4(p) ((p)->version == GENET_V4)
518#define GENET_IS_V5(p) ((p)->version == GENET_V5)
519
520/* Hardware flags */
521#define GENET_HAS_40BITS (1 << 0)
522#define GENET_HAS_EXT (1 << 1)
523#define GENET_HAS_MDIO_INTR (1 << 2)
524#define GENET_HAS_MOCA_LINK_DET (1 << 3)
525
526/* BCMGENET hardware parameters, keep this structure nicely aligned
527 * since it is going to be used in hot paths
528 */
529struct bcmgenet_hw_params {
530 u8 tx_queues;
531 u8 tx_bds_per_q;
532 u8 rx_queues;
533 u8 rx_bds_per_q;
534 u8 bp_in_en_shift;
535 u32 bp_in_mask;
536 u8 hfb_filter_cnt;
537 u8 hfb_filter_size;
538 u8 qtag_mask;
539 u16 tbuf_offset;
540 u32 hfb_offset;
541 u32 hfb_reg_offset;
542 u32 rdma_offset;
543 u32 tdma_offset;
544 u32 words_per_bd;
545 u32 flags;
546};
547
548struct bcmgenet_skb_cb {
549 struct enet_cb *first_cb; /* First control block of SKB */
550 struct enet_cb *last_cb; /* Last control block of SKB */
551 unsigned int bytes_sent; /* bytes on the wire (no TSB) */
552};
553
554#define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb))
555
556struct bcmgenet_tx_ring {
557 spinlock_t lock; /* ring lock */
558 struct napi_struct napi; /* NAPI per tx queue */
559 unsigned long packets;
560 unsigned long bytes;
561 unsigned int index; /* ring index */
562 unsigned int queue; /* queue index */
563 struct enet_cb *cbs; /* tx ring buffer control block*/
564 unsigned int size; /* size of each tx ring */
565 unsigned int clean_ptr; /* Tx ring clean pointer */
566 unsigned int c_index; /* last consumer index of each ring*/
567 unsigned int free_bds; /* # of free bds for each ring */
568 unsigned int write_ptr; /* Tx ring write pointer SW copy */
569 unsigned int prod_index; /* Tx ring producer index SW copy */
570 unsigned int cb_ptr; /* Tx ring initial CB ptr */
571 unsigned int end_ptr; /* Tx ring end CB ptr */
572 void (*int_enable)(struct bcmgenet_tx_ring *);
573 void (*int_disable)(struct bcmgenet_tx_ring *);
574 struct bcmgenet_priv *priv;
575};
576
577struct bcmgenet_net_dim {
578 u16 use_dim;
579 u16 event_ctr;
580 unsigned long packets;
581 unsigned long bytes;
582 struct dim dim;
583};
584
585struct bcmgenet_rx_ring {
586 struct napi_struct napi; /* Rx NAPI struct */
587 unsigned long bytes;
588 unsigned long packets;
589 unsigned long errors;
590 unsigned long dropped;
591 unsigned int index; /* Rx ring index */
592 struct enet_cb *cbs; /* Rx ring buffer control block */
593 unsigned int size; /* Rx ring size */
594 unsigned int c_index; /* Rx last consumer index */
595 unsigned int read_ptr; /* Rx ring read pointer */
596 unsigned int cb_ptr; /* Rx ring initial CB ptr */
597 unsigned int end_ptr; /* Rx ring end CB ptr */
598 unsigned int old_discards;
599 struct bcmgenet_net_dim dim;
600 u32 rx_max_coalesced_frames;
601 u32 rx_coalesce_usecs;
602 void (*int_enable)(struct bcmgenet_rx_ring *);
603 void (*int_disable)(struct bcmgenet_rx_ring *);
604 struct bcmgenet_priv *priv;
605};
606
607/* device context */
608struct bcmgenet_priv {
609 void __iomem *base;
610 enum bcmgenet_version version;
611 struct net_device *dev;
612
613 /* transmit variables */
614 void __iomem *tx_bds;
615 struct enet_cb *tx_cbs;
616 unsigned int num_tx_bds;
617
618 struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1];
619
620 /* receive variables */
621 void __iomem *rx_bds;
622 struct enet_cb *rx_cbs;
623 unsigned int num_rx_bds;
624 unsigned int rx_buf_len;
625
626 struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1];
627
628 /* other misc variables */
629 struct bcmgenet_hw_params *hw_params;
630
631 /* MDIO bus variables */
632 wait_queue_head_t wq;
633 bool internal_phy;
634 struct device_node *phy_dn;
635 struct device_node *mdio_dn;
636 struct mii_bus *mii_bus;
637 u16 gphy_rev;
638 struct clk *clk_eee;
639 bool clk_eee_enabled;
640
641 /* PHY device variables */
642 int old_link;
643 int old_speed;
644 int old_duplex;
645 int old_pause;
646 phy_interface_t phy_interface;
647 int phy_addr;
648 int ext_phy;
649
650 /* Interrupt variables */
651 struct work_struct bcmgenet_irq_work;
652 int irq0;
653 int irq1;
654 int wol_irq;
655 bool wol_irq_disabled;
656
657 /* shared status */
658 spinlock_t lock;
659 unsigned int irq0_stat;
660
661 /* HW descriptors/checksum variables */
662 bool desc_64b_en;
663 bool desc_rxchk_en;
664 bool crc_fwd_en;
665
666 unsigned int dma_rx_chk_bit;
667
668 u32 msg_enable;
669
670 struct clk *clk;
671 struct platform_device *pdev;
672 struct platform_device *mii_pdev;
673
674 /* WOL */
675 struct clk *clk_wol;
676 u32 wolopts;
677
678 struct bcmgenet_mib_counters mib;
679
680 struct ethtool_eee eee;
681};
682
683#define GENET_IO_MACRO(name, offset) \
684static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \
685 u32 off) \
686{ \
687 /* MIPS chips strapped for BE will automagically configure the \
688 * peripheral registers for CPU-native byte order. \
689 */ \
690 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
691 return __raw_readl(priv->base + offset + off); \
692 else \
693 return readl_relaxed(priv->base + offset + off); \
694} \
695static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
696 u32 val, u32 off) \
697{ \
698 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
699 __raw_writel(val, priv->base + offset + off); \
700 else \
701 writel_relaxed(val, priv->base + offset + off); \
702}
703
704GENET_IO_MACRO(ext, GENET_EXT_OFF);
705GENET_IO_MACRO(umac, GENET_UMAC_OFF);
706GENET_IO_MACRO(sys, GENET_SYS_OFF);
707
708/* interrupt l2 registers accessors */
709GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
710GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
711
712/* HFB register accessors */
713GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
714
715/* GENET v2+ HFB control and filter len helpers */
716GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
717
718/* RBUF register accessors */
719GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
720
721/* MDIO routines */
722int bcmgenet_mii_init(struct net_device *dev);
723int bcmgenet_mii_config(struct net_device *dev, bool init);
724int bcmgenet_mii_probe(struct net_device *dev);
725void bcmgenet_mii_exit(struct net_device *dev);
726void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
727void bcmgenet_mii_setup(struct net_device *dev);
728
729/* Wake-on-LAN routines */
730void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
731int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
732int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
733 enum bcmgenet_power_mode mode);
734void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
735 enum bcmgenet_power_mode mode);
736
737#endif /* __BCMGENET_H__ */