1/*
  2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
  3 *
  4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
  5 *
  6 * This software is available to you under a choice of one of two
  7 * licenses.  You may choose to be licensed under the terms of the GNU
  8 * General Public License (GPL) Version 2, available from the file
  9 * COPYING in the main directory of this source tree, or the
 10 * OpenIB.org BSD license below:
 11 *
 12 *     Redistribution and use in source and binary forms, with or
 13 *     without modification, are permitted provided that the following
 14 *     conditions are met:
 15 *
 16 *      - Redistributions of source code must retain the above
 17 *        copyright notice, this list of conditions and the following
 18 *        disclaimer.
 19 *
 20 *      - Redistributions in binary form must reproduce the above
 21 *        copyright notice, this list of conditions and the following
 22 *        disclaimer in the documentation and/or other materials
 23 *        provided with the distribution.
 24 *
 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 32 * SOFTWARE.
 33 */
 34
 35#ifndef __T4_HW_H
 36#define __T4_HW_H
 37
 38#include <linux/types.h>
 39
 40enum {
 41	NCHAN          = 4,     /* # of HW channels */
 42	MAX_MTU        = 9600,  /* max MAC MTU, excluding header + FCS */
 43	EEPROMSIZE     = 17408, /* Serial EEPROM physical size */
 44	EEPROMVSIZE    = 32768, /* Serial EEPROM virtual address space size */
 45	EEPROMPFSIZE   = 1024,  /* EEPROM writable area size for PFn, n>0 */
 46	RSS_NENTRIES   = 2048,  /* # of entries in RSS mapping table */
 47	TCB_SIZE       = 128,   /* TCB size */
 48	NMTUS          = 16,    /* size of MTU table */
 49	NCCTRL_WIN     = 32,    /* # of congestion control windows */
 50	NEXACT_MAC     = 336,   /* # of exact MAC address filters */
 51	L2T_SIZE       = 4096,  /* # of L2T entries */
 52	MBOX_LEN       = 64,    /* mailbox size in bytes */
 53	TRACE_LEN      = 112,   /* length of trace data and mask */
 54	FILTER_OPT_LEN = 36,    /* filter tuple width for optional components */
 55	NWOL_PAT       = 8,     /* # of WoL patterns */
 56	WOL_PAT_LEN    = 128,   /* length of WoL patterns */
 57};
 58
 59enum {
 60	SF_PAGE_SIZE = 256,           /* serial flash page size */
 61};
 62
 63enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
 64
 65enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
 66
 67enum {
 68	SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
 69	SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
 70	SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
 71
 72	SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
 73	SGE_TIMER_UPD_CIDX = 7,   /* update cidx only */
 74
 75	SGE_EQ_IDXSIZE = 64,      /* egress queue pidx/cidx unit size */
 76
 77	SGE_INTRDST_PCI = 0,      /* interrupt destination is PCI-E */
 78	SGE_INTRDST_IQ = 1,       /*   destination is an ingress queue */
 79
 80	SGE_UPDATEDEL_NONE = 0,   /* ingress queue pidx update delivery */
 81	SGE_UPDATEDEL_INTR = 1,   /*   interrupt */
 82	SGE_UPDATEDEL_STPG = 2,   /*   status page */
 83	SGE_UPDATEDEL_BOTH = 3,   /*   interrupt and status page */
 84
 85	SGE_HOSTFCMODE_NONE = 0,  /* egress queue cidx updates */
 86	SGE_HOSTFCMODE_IQ = 1,    /*   sent to ingress queue */
 87	SGE_HOSTFCMODE_STPG = 2,  /*   sent to status page */
 88	SGE_HOSTFCMODE_BOTH = 3,  /*   ingress queue and status page */
 89
 90	SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
 91	SGE_FETCHBURSTMIN_32B = 1,
 92	SGE_FETCHBURSTMIN_64B = 2,
 93	SGE_FETCHBURSTMIN_128B = 3,
 94
 95	SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
 96	SGE_FETCHBURSTMAX_128B = 1,
 97	SGE_FETCHBURSTMAX_256B = 2,
 98	SGE_FETCHBURSTMAX_512B = 3,
 99
100	SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
101	SGE_CIDXFLUSHTHRESH_2 = 1,
102	SGE_CIDXFLUSHTHRESH_4 = 2,
103	SGE_CIDXFLUSHTHRESH_8 = 3,
104	SGE_CIDXFLUSHTHRESH_16 = 4,
105	SGE_CIDXFLUSHTHRESH_32 = 5,
106	SGE_CIDXFLUSHTHRESH_64 = 6,
107	SGE_CIDXFLUSHTHRESH_128 = 7,
108
109	SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
110};
111
112struct sge_qstat {                /* data written to SGE queue status entries */
113	__be32 qid;
114	__be16 cidx;
115	__be16 pidx;
116};
117
118/*
119 * Structure for last 128 bits of response descriptors
120 */
121struct rsp_ctrl {
122	__be32 hdrbuflen_pidx;
123	__be32 pldbuflen_qid;
124	union {
125		u8 type_gen;
126		__be64 last_flit;
127	};
128};
129
130#define RSPD_NEWBUF 0x80000000U
131#define RSPD_LEN(x) (((x) >> 0) & 0x7fffffffU)
132#define RSPD_QID(x) RSPD_LEN(x)
133
134#define RSPD_GEN(x)  ((x) >> 7)
135#define RSPD_TYPE(x) (((x) >> 4) & 3)
136
137#define QINTR_CNT_EN       0x1
138#define QINTR_TIMER_IDX(x) ((x) << 1)
139#define QINTR_TIMER_IDX_GET(x) (((x) >> 1) & 0x7)
140#endif /* __T4_HW_H */