1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 *  Copyright (C) 2015 Atmel Corporation,
  4 *                     Nicolas Ferre <nicolas.ferre@atmel.com>
  5 *
  6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
  7 */
  8
  9#include <linux/bitfield.h>
 10#include <linux/clk-provider.h>
 11#include <linux/clkdev.h>
 12#include <linux/clk/at91_pmc.h>
 13#include <linux/of.h>
 14#include <linux/mfd/syscon.h>
 15#include <linux/regmap.h>
 16
 17#include "pmc.h"
 18
 19#define GENERATED_MAX_DIV	255
 20
 21#define GCK_INDEX_DT_AUDIO_PLL	5
 22
 23struct clk_generated {
 24	struct clk_hw hw;
 25	struct regmap *regmap;
 26	struct clk_range range;
 27	spinlock_t *lock;
 28	u32 id;
 29	u32 gckdiv;
 30	const struct clk_pcr_layout *layout;
 31	u8 parent_id;
 32	bool audio_pll_allowed;
 33};
 34
 35#define to_clk_generated(hw) \
 36	container_of(hw, struct clk_generated, hw)
 37
 38static int clk_generated_enable(struct clk_hw *hw)
 39{
 40	struct clk_generated *gck = to_clk_generated(hw);
 41	unsigned long flags;
 42
 43	pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
 44		 __func__, gck->gckdiv, gck->parent_id);
 45
 46	spin_lock_irqsave(gck->lock, flags);
 47	regmap_write(gck->regmap, gck->layout->offset,
 48		     (gck->id & gck->layout->pid_mask));
 49	regmap_update_bits(gck->regmap, gck->layout->offset,
 50			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
 51			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
 52			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |
 53			   gck->layout->cmd |
 54			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
 55			   AT91_PMC_PCR_GCKEN);
 56	spin_unlock_irqrestore(gck->lock, flags);
 57	return 0;
 58}
 59
 60static void clk_generated_disable(struct clk_hw *hw)
 61{
 62	struct clk_generated *gck = to_clk_generated(hw);
 63	unsigned long flags;
 64
 65	spin_lock_irqsave(gck->lock, flags);
 66	regmap_write(gck->regmap, gck->layout->offset,
 67		     (gck->id & gck->layout->pid_mask));
 68	regmap_update_bits(gck->regmap, gck->layout->offset,
 69			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
 70			   gck->layout->cmd);
 71	spin_unlock_irqrestore(gck->lock, flags);
 72}
 73
 74static int clk_generated_is_enabled(struct clk_hw *hw)
 75{
 76	struct clk_generated *gck = to_clk_generated(hw);
 77	unsigned long flags;
 78	unsigned int status;
 79
 80	spin_lock_irqsave(gck->lock, flags);
 81	regmap_write(gck->regmap, gck->layout->offset,
 82		     (gck->id & gck->layout->pid_mask));
 83	regmap_read(gck->regmap, gck->layout->offset, &status);
 84	spin_unlock_irqrestore(gck->lock, flags);
 85
 86	return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
 87}
 88
 89static unsigned long
 90clk_generated_recalc_rate(struct clk_hw *hw,
 91			  unsigned long parent_rate)
 92{
 93	struct clk_generated *gck = to_clk_generated(hw);
 94
 95	return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
 96}
 97
 98static void clk_generated_best_diff(struct clk_rate_request *req,
 99				    struct clk_hw *parent,
100				    unsigned long parent_rate, u32 div,
101				    int *best_diff, long *best_rate)
102{
103	unsigned long tmp_rate;
104	int tmp_diff;
105
106	if (!div)
107		tmp_rate = parent_rate;
108	else
109		tmp_rate = parent_rate / div;
110	tmp_diff = abs(req->rate - tmp_rate);
111
112	if (*best_diff < 0 || *best_diff > tmp_diff) {
113		*best_rate = tmp_rate;
114		*best_diff = tmp_diff;
115		req->best_parent_rate = parent_rate;
116		req->best_parent_hw = parent;
117	}
118}
119
120static int clk_generated_determine_rate(struct clk_hw *hw,
121					struct clk_rate_request *req)
122{
123	struct clk_generated *gck = to_clk_generated(hw);
124	struct clk_hw *parent = NULL;
125	struct clk_rate_request req_parent = *req;
126	long best_rate = -EINVAL;
127	unsigned long min_rate, parent_rate;
128	int best_diff = -1;
129	int i;
130	u32 div;
131
132	for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
133		parent = clk_hw_get_parent_by_index(hw, i);
134		if (!parent)
135			continue;
136
137		parent_rate = clk_hw_get_rate(parent);
138		min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
139		if (!parent_rate ||
140		    (gck->range.max && min_rate > gck->range.max))
141			continue;
142
143		div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
144		if (div > GENERATED_MAX_DIV + 1)
145			div = GENERATED_MAX_DIV + 1;
146
147		clk_generated_best_diff(req, parent, parent_rate, div,
148					&best_diff, &best_rate);
149
150		if (!best_diff)
151			break;
152	}
153
154	/*
155	 * The audio_pll rate can be modified, unlike the five others clocks
156	 * that should never be altered.
157	 * The audio_pll can technically be used by multiple consumers. However,
158	 * with the rate locking, the first consumer to enable to clock will be
159	 * the one definitely setting the rate of the clock.
160	 * Since audio IPs are most likely to request the same rate, we enforce
161	 * that the only clks able to modify gck rate are those of audio IPs.
162	 */
163
164	if (!gck->audio_pll_allowed)
165		goto end;
166
167	parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
168	if (!parent)
169		goto end;
170
171	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
172		req_parent.rate = req->rate * div;
173		__clk_determine_rate(parent, &req_parent);
174		clk_generated_best_diff(req, parent, req_parent.rate, div,
175					&best_diff, &best_rate);
176
177		if (!best_diff)
178			break;
179	}
180
181end:
182	pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
183		 __func__, best_rate,
184		 __clk_get_name((req->best_parent_hw)->clk),
185		 req->best_parent_rate);
186
187	if (best_rate < 0)
188		return best_rate;
189
190	req->rate = best_rate;
191	return 0;
192}
193
194/* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
195static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
196{
197	struct clk_generated *gck = to_clk_generated(hw);
198
199	if (index >= clk_hw_get_num_parents(hw))
200		return -EINVAL;
201
202	gck->parent_id = index;
203	return 0;
204}
205
206static u8 clk_generated_get_parent(struct clk_hw *hw)
207{
208	struct clk_generated *gck = to_clk_generated(hw);
209
210	return gck->parent_id;
211}
212
213/* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
214static int clk_generated_set_rate(struct clk_hw *hw,
215				  unsigned long rate,
216				  unsigned long parent_rate)
217{
218	struct clk_generated *gck = to_clk_generated(hw);
219	u32 div;
220
221	if (!rate)
222		return -EINVAL;
223
224	if (gck->range.max && rate > gck->range.max)
225		return -EINVAL;
226
227	div = DIV_ROUND_CLOSEST(parent_rate, rate);
228	if (div > GENERATED_MAX_DIV + 1 || !div)
229		return -EINVAL;
230
231	gck->gckdiv = div - 1;
232	return 0;
233}
234
235static const struct clk_ops generated_ops = {
236	.enable = clk_generated_enable,
237	.disable = clk_generated_disable,
238	.is_enabled = clk_generated_is_enabled,
239	.recalc_rate = clk_generated_recalc_rate,
240	.determine_rate = clk_generated_determine_rate,
241	.get_parent = clk_generated_get_parent,
242	.set_parent = clk_generated_set_parent,
243	.set_rate = clk_generated_set_rate,
244};
245
246/**
247 * clk_generated_startup - Initialize a given clock to its default parent and
248 * divisor parameter.
249 *
250 * @gck:	Generated clock to set the startup parameters for.
251 *
252 * Take parameters from the hardware and update local clock configuration
253 * accordingly.
254 */
255static void clk_generated_startup(struct clk_generated *gck)
256{
257	u32 tmp;
258	unsigned long flags;
259
260	spin_lock_irqsave(gck->lock, flags);
261	regmap_write(gck->regmap, gck->layout->offset,
262		     (gck->id & gck->layout->pid_mask));
263	regmap_read(gck->regmap, gck->layout->offset, &tmp);
264	spin_unlock_irqrestore(gck->lock, flags);
265
266	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
267	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
268}
269
270struct clk_hw * __init
271at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
272			    const struct clk_pcr_layout *layout,
273			    const char *name, const char **parent_names,
274			    u8 num_parents, u8 id, bool pll_audio,
275			    const struct clk_range *range)
276{
277	struct clk_generated *gck;
278	struct clk_init_data init;
279	struct clk_hw *hw;
280	int ret;
281
282	gck = kzalloc(sizeof(*gck), GFP_KERNEL);
283	if (!gck)
284		return ERR_PTR(-ENOMEM);
285
286	init.name = name;
287	init.ops = &generated_ops;
288	init.parent_names = parent_names;
289	init.num_parents = num_parents;
290	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
291		CLK_SET_RATE_PARENT;
292
293	gck->id = id;
294	gck->hw.init = &init;
295	gck->regmap = regmap;
296	gck->lock = lock;
297	gck->range = *range;
298	gck->audio_pll_allowed = pll_audio;
299	gck->layout = layout;
300
301	clk_generated_startup(gck);
302	hw = &gck->hw;
303	ret = clk_hw_register(NULL, &gck->hw);
304	if (ret) {
305		kfree(gck);
306		hw = ERR_PTR(ret);
307	} else {
308		pmc_register_id(id);
309	}
310
311	return hw;
312}