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1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/stackprotector.h>
55#include <linux/gfp.h>
56#include <linux/cpuidle.h>
57#include <linux/numa.h>
58
59#include <asm/acpi.h>
60#include <asm/desc.h>
61#include <asm/nmi.h>
62#include <asm/irq.h>
63#include <asm/realmode.h>
64#include <asm/cpu.h>
65#include <asm/numa.h>
66#include <asm/pgtable.h>
67#include <asm/tlbflush.h>
68#include <asm/mtrr.h>
69#include <asm/mwait.h>
70#include <asm/apic.h>
71#include <asm/io_apic.h>
72#include <asm/fpu/internal.h>
73#include <asm/setup.h>
74#include <asm/uv/uv.h>
75#include <linux/mc146818rtc.h>
76#include <asm/i8259.h>
77#include <asm/misc.h>
78#include <asm/qspinlock.h>
79#include <asm/intel-family.h>
80#include <asm/cpu_device_id.h>
81#include <asm/spec-ctrl.h>
82#include <asm/hw_irq.h>
83
84/* representing HT siblings of each logical CPU */
85DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
87
88/* representing HT and core siblings of each logical CPU */
89DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91
92/* representing HT, core, and die siblings of each logical CPU */
93DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
94EXPORT_PER_CPU_SYMBOL(cpu_die_map);
95
96DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
97
98/* Per CPU bogomips and other parameters */
99DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
100EXPORT_PER_CPU_SYMBOL(cpu_info);
101
102/* Logical package management. We might want to allocate that dynamically */
103unsigned int __max_logical_packages __read_mostly;
104EXPORT_SYMBOL(__max_logical_packages);
105static unsigned int logical_packages __read_mostly;
106static unsigned int logical_die __read_mostly;
107
108/* Maximum number of SMT threads on any online core */
109int __read_mostly __max_smt_threads = 1;
110
111/* Flag to indicate if a complete sched domain rebuild is required */
112bool x86_topology_update;
113
114int arch_update_cpu_topology(void)
115{
116 int retval = x86_topology_update;
117
118 x86_topology_update = false;
119 return retval;
120}
121
122static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
130 start_eip >> 4;
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
132 start_eip & 0xf;
133}
134
135static inline void smpboot_restore_warm_reset_vector(void)
136{
137 unsigned long flags;
138
139 /*
140 * Paranoid: Set warm reset code and vector here back
141 * to default values.
142 */
143 spin_lock_irqsave(&rtc_lock, flags);
144 CMOS_WRITE(0, 0xf);
145 spin_unlock_irqrestore(&rtc_lock, flags);
146
147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
148}
149
150/*
151 * Report back to the Boot Processor during boot time or to the caller processor
152 * during CPU online.
153 */
154static void smp_callin(void)
155{
156 int cpuid;
157
158 /*
159 * If waken up by an INIT in an 82489DX configuration
160 * cpu_callout_mask guarantees we don't get here before
161 * an INIT_deassert IPI reaches our local APIC, so it is
162 * now safe to touch our local APIC.
163 */
164 cpuid = smp_processor_id();
165
166 /*
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
170 * boards)
171 */
172 apic_ap_setup();
173
174 /*
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
177 */
178 smp_store_cpu_info(cpuid);
179
180 /*
181 * The topology information must be up to date before
182 * calibrate_delay() and notify_cpu_starting().
183 */
184 set_cpu_sibling_map(raw_smp_processor_id());
185
186 /*
187 * Get our bogomips.
188 * Update loops_per_jiffy in cpu_data. Previous call to
189 * smp_store_cpu_info() stored a value that is close but not as
190 * accurate as the value just calculated.
191 */
192 calibrate_delay();
193 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
194 pr_debug("Stack at about %p\n", &cpuid);
195
196 wmb();
197
198 notify_cpu_starting(cpuid);
199
200 /*
201 * Allow the master to continue.
202 */
203 cpumask_set_cpu(cpuid, cpu_callin_mask);
204}
205
206static int cpu0_logical_apicid;
207static int enable_start_cpu0;
208/*
209 * Activate a secondary processor.
210 */
211static void notrace start_secondary(void *unused)
212{
213 /*
214 * Don't put *anything* except direct CPU state initialization
215 * before cpu_init(), SMP booting is too fragile that we want to
216 * limit the things done here to the most necessary things.
217 */
218 cr4_init();
219
220#ifdef CONFIG_X86_32
221 /* switch away from the initial page table */
222 load_cr3(swapper_pg_dir);
223 __flush_tlb_all();
224#endif
225 load_current_idt();
226 cpu_init();
227 x86_cpuinit.early_percpu_clock_init();
228 preempt_disable();
229 smp_callin();
230
231 enable_start_cpu0 = 0;
232
233 /* otherwise gcc will move up smp_processor_id before the cpu_init */
234 barrier();
235 /*
236 * Check TSC synchronization with the boot CPU:
237 */
238 check_tsc_sync_target();
239
240 speculative_store_bypass_ht_init();
241
242 /*
243 * Lock vector_lock, set CPU online and bring the vector
244 * allocator online. Online must be set with vector_lock held
245 * to prevent a concurrent irq setup/teardown from seeing a
246 * half valid vector space.
247 */
248 lock_vector_lock();
249 set_cpu_online(smp_processor_id(), true);
250 lapic_online();
251 unlock_vector_lock();
252 cpu_set_state_online(smp_processor_id());
253 x86_platform.nmi_init();
254
255 /* enable local interrupts */
256 local_irq_enable();
257
258 /* to prevent fake stack check failure in clock setup */
259 boot_init_stack_canary();
260
261 x86_cpuinit.setup_percpu_clockev();
262
263 wmb();
264 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
265}
266
267/**
268 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
269 * @cpu: CPU to check
270 */
271bool topology_is_primary_thread(unsigned int cpu)
272{
273 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
274}
275
276/**
277 * topology_smt_supported - Check whether SMT is supported by the CPUs
278 */
279bool topology_smt_supported(void)
280{
281 return smp_num_siblings > 1;
282}
283
284/**
285 * topology_phys_to_logical_pkg - Map a physical package id to a logical
286 *
287 * Returns logical package id or -1 if not found
288 */
289int topology_phys_to_logical_pkg(unsigned int phys_pkg)
290{
291 int cpu;
292
293 for_each_possible_cpu(cpu) {
294 struct cpuinfo_x86 *c = &cpu_data(cpu);
295
296 if (c->initialized && c->phys_proc_id == phys_pkg)
297 return c->logical_proc_id;
298 }
299 return -1;
300}
301EXPORT_SYMBOL(topology_phys_to_logical_pkg);
302/**
303 * topology_phys_to_logical_die - Map a physical die id to logical
304 *
305 * Returns logical die id or -1 if not found
306 */
307int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
308{
309 int cpu;
310 int proc_id = cpu_data(cur_cpu).phys_proc_id;
311
312 for_each_possible_cpu(cpu) {
313 struct cpuinfo_x86 *c = &cpu_data(cpu);
314
315 if (c->initialized && c->cpu_die_id == die_id &&
316 c->phys_proc_id == proc_id)
317 return c->logical_die_id;
318 }
319 return -1;
320}
321EXPORT_SYMBOL(topology_phys_to_logical_die);
322
323/**
324 * topology_update_package_map - Update the physical to logical package map
325 * @pkg: The physical package id as retrieved via CPUID
326 * @cpu: The cpu for which this is updated
327 */
328int topology_update_package_map(unsigned int pkg, unsigned int cpu)
329{
330 int new;
331
332 /* Already available somewhere? */
333 new = topology_phys_to_logical_pkg(pkg);
334 if (new >= 0)
335 goto found;
336
337 new = logical_packages++;
338 if (new != pkg) {
339 pr_info("CPU %u Converting physical %u to logical package %u\n",
340 cpu, pkg, new);
341 }
342found:
343 cpu_data(cpu).logical_proc_id = new;
344 return 0;
345}
346/**
347 * topology_update_die_map - Update the physical to logical die map
348 * @die: The die id as retrieved via CPUID
349 * @cpu: The cpu for which this is updated
350 */
351int topology_update_die_map(unsigned int die, unsigned int cpu)
352{
353 int new;
354
355 /* Already available somewhere? */
356 new = topology_phys_to_logical_die(die, cpu);
357 if (new >= 0)
358 goto found;
359
360 new = logical_die++;
361 if (new != die) {
362 pr_info("CPU %u Converting physical %u to logical die %u\n",
363 cpu, die, new);
364 }
365found:
366 cpu_data(cpu).logical_die_id = new;
367 return 0;
368}
369
370void __init smp_store_boot_cpu_info(void)
371{
372 int id = 0; /* CPU 0 */
373 struct cpuinfo_x86 *c = &cpu_data(id);
374
375 *c = boot_cpu_data;
376 c->cpu_index = id;
377 topology_update_package_map(c->phys_proc_id, id);
378 topology_update_die_map(c->cpu_die_id, id);
379 c->initialized = true;
380}
381
382/*
383 * The bootstrap kernel entry code has set these up. Save them for
384 * a given CPU
385 */
386void smp_store_cpu_info(int id)
387{
388 struct cpuinfo_x86 *c = &cpu_data(id);
389
390 /* Copy boot_cpu_data only on the first bringup */
391 if (!c->initialized)
392 *c = boot_cpu_data;
393 c->cpu_index = id;
394 /*
395 * During boot time, CPU0 has this setup already. Save the info when
396 * bringing up AP or offlined CPU0.
397 */
398 identify_secondary_cpu(c);
399 c->initialized = true;
400}
401
402static bool
403topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
404{
405 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
406
407 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
408}
409
410static bool
411topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
412{
413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
414
415 return !WARN_ONCE(!topology_same_node(c, o),
416 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
417 "[node: %d != %d]. Ignoring dependency.\n",
418 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
419}
420
421#define link_mask(mfunc, c1, c2) \
422do { \
423 cpumask_set_cpu((c1), mfunc(c2)); \
424 cpumask_set_cpu((c2), mfunc(c1)); \
425} while (0)
426
427static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
428{
429 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
431
432 if (c->phys_proc_id == o->phys_proc_id &&
433 c->cpu_die_id == o->cpu_die_id &&
434 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
435 if (c->cpu_core_id == o->cpu_core_id)
436 return topology_sane(c, o, "smt");
437
438 if ((c->cu_id != 0xff) &&
439 (o->cu_id != 0xff) &&
440 (c->cu_id == o->cu_id))
441 return topology_sane(c, o, "smt");
442 }
443
444 } else if (c->phys_proc_id == o->phys_proc_id &&
445 c->cpu_die_id == o->cpu_die_id &&
446 c->cpu_core_id == o->cpu_core_id) {
447 return topology_sane(c, o, "smt");
448 }
449
450 return false;
451}
452
453/*
454 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
455 *
456 * These are Intel CPUs that enumerate an LLC that is shared by
457 * multiple NUMA nodes. The LLC on these systems is shared for
458 * off-package data access but private to the NUMA node (half
459 * of the package) for on-package access.
460 *
461 * CPUID (the source of the information about the LLC) can only
462 * enumerate the cache as being shared *or* unshared, but not
463 * this particular configuration. The CPU in this case enumerates
464 * the cache to be shared across the entire package (spanning both
465 * NUMA nodes).
466 */
467
468static const struct x86_cpu_id snc_cpu[] = {
469 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
470 {}
471};
472
473static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
474{
475 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
476
477 /* Do not match if we do not have a valid APICID for cpu: */
478 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
479 return false;
480
481 /* Do not match if LLC id does not match: */
482 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
483 return false;
484
485 /*
486 * Allow the SNC topology without warning. Return of false
487 * means 'c' does not share the LLC of 'o'. This will be
488 * reflected to userspace.
489 */
490 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
491 return false;
492
493 return topology_sane(c, o, "llc");
494}
495
496/*
497 * Unlike the other levels, we do not enforce keeping a
498 * multicore group inside a NUMA node. If this happens, we will
499 * discard the MC level of the topology later.
500 */
501static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
502{
503 if (c->phys_proc_id == o->phys_proc_id)
504 return true;
505 return false;
506}
507
508static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
509{
510 if ((c->phys_proc_id == o->phys_proc_id) &&
511 (c->cpu_die_id == o->cpu_die_id))
512 return true;
513 return false;
514}
515
516
517#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
518static inline int x86_sched_itmt_flags(void)
519{
520 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
521}
522
523#ifdef CONFIG_SCHED_MC
524static int x86_core_flags(void)
525{
526 return cpu_core_flags() | x86_sched_itmt_flags();
527}
528#endif
529#ifdef CONFIG_SCHED_SMT
530static int x86_smt_flags(void)
531{
532 return cpu_smt_flags() | x86_sched_itmt_flags();
533}
534#endif
535#endif
536
537static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
538#ifdef CONFIG_SCHED_SMT
539 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
540#endif
541#ifdef CONFIG_SCHED_MC
542 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
543#endif
544 { NULL, },
545};
546
547static struct sched_domain_topology_level x86_topology[] = {
548#ifdef CONFIG_SCHED_SMT
549 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
550#endif
551#ifdef CONFIG_SCHED_MC
552 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
553#endif
554 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
555 { NULL, },
556};
557
558/*
559 * Set if a package/die has multiple NUMA nodes inside.
560 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
561 * Sub-NUMA Clustering have this.
562 */
563static bool x86_has_numa_in_package;
564
565void set_cpu_sibling_map(int cpu)
566{
567 bool has_smt = smp_num_siblings > 1;
568 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
569 struct cpuinfo_x86 *c = &cpu_data(cpu);
570 struct cpuinfo_x86 *o;
571 int i, threads;
572
573 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
574
575 if (!has_mp) {
576 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
577 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
578 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
579 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
580 c->booted_cores = 1;
581 return;
582 }
583
584 for_each_cpu(i, cpu_sibling_setup_mask) {
585 o = &cpu_data(i);
586
587 if ((i == cpu) || (has_smt && match_smt(c, o)))
588 link_mask(topology_sibling_cpumask, cpu, i);
589
590 if ((i == cpu) || (has_mp && match_llc(c, o)))
591 link_mask(cpu_llc_shared_mask, cpu, i);
592
593 }
594
595 /*
596 * This needs a separate iteration over the cpus because we rely on all
597 * topology_sibling_cpumask links to be set-up.
598 */
599 for_each_cpu(i, cpu_sibling_setup_mask) {
600 o = &cpu_data(i);
601
602 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
603 link_mask(topology_core_cpumask, cpu, i);
604
605 /*
606 * Does this new cpu bringup a new core?
607 */
608 if (cpumask_weight(
609 topology_sibling_cpumask(cpu)) == 1) {
610 /*
611 * for each core in package, increment
612 * the booted_cores for this new cpu
613 */
614 if (cpumask_first(
615 topology_sibling_cpumask(i)) == i)
616 c->booted_cores++;
617 /*
618 * increment the core count for all
619 * the other cpus in this package
620 */
621 if (i != cpu)
622 cpu_data(i).booted_cores++;
623 } else if (i != cpu && !c->booted_cores)
624 c->booted_cores = cpu_data(i).booted_cores;
625 }
626 if (match_pkg(c, o) && !topology_same_node(c, o))
627 x86_has_numa_in_package = true;
628
629 if ((i == cpu) || (has_mp && match_die(c, o)))
630 link_mask(topology_die_cpumask, cpu, i);
631 }
632
633 threads = cpumask_weight(topology_sibling_cpumask(cpu));
634 if (threads > __max_smt_threads)
635 __max_smt_threads = threads;
636}
637
638/* maps the cpu to the sched domain representing multi-core */
639const struct cpumask *cpu_coregroup_mask(int cpu)
640{
641 return cpu_llc_shared_mask(cpu);
642}
643
644static void impress_friends(void)
645{
646 int cpu;
647 unsigned long bogosum = 0;
648 /*
649 * Allow the user to impress friends.
650 */
651 pr_debug("Before bogomips\n");
652 for_each_possible_cpu(cpu)
653 if (cpumask_test_cpu(cpu, cpu_callout_mask))
654 bogosum += cpu_data(cpu).loops_per_jiffy;
655 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
656 num_online_cpus(),
657 bogosum/(500000/HZ),
658 (bogosum/(5000/HZ))%100);
659
660 pr_debug("Before bogocount - setting activated=1\n");
661}
662
663void __inquire_remote_apic(int apicid)
664{
665 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
666 const char * const names[] = { "ID", "VERSION", "SPIV" };
667 int timeout;
668 u32 status;
669
670 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
671
672 for (i = 0; i < ARRAY_SIZE(regs); i++) {
673 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
674
675 /*
676 * Wait for idle.
677 */
678 status = safe_apic_wait_icr_idle();
679 if (status)
680 pr_cont("a previous APIC delivery may have failed\n");
681
682 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
683
684 timeout = 0;
685 do {
686 udelay(100);
687 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
688 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
689
690 switch (status) {
691 case APIC_ICR_RR_VALID:
692 status = apic_read(APIC_RRR);
693 pr_cont("%08x\n", status);
694 break;
695 default:
696 pr_cont("failed\n");
697 }
698 }
699}
700
701/*
702 * The Multiprocessor Specification 1.4 (1997) example code suggests
703 * that there should be a 10ms delay between the BSP asserting INIT
704 * and de-asserting INIT, when starting a remote processor.
705 * But that slows boot and resume on modern processors, which include
706 * many cores and don't require that delay.
707 *
708 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
709 * Modern processor families are quirked to remove the delay entirely.
710 */
711#define UDELAY_10MS_DEFAULT 10000
712
713static unsigned int init_udelay = UINT_MAX;
714
715static int __init cpu_init_udelay(char *str)
716{
717 get_option(&str, &init_udelay);
718
719 return 0;
720}
721early_param("cpu_init_udelay", cpu_init_udelay);
722
723static void __init smp_quirk_init_udelay(void)
724{
725 /* if cmdline changed it from default, leave it alone */
726 if (init_udelay != UINT_MAX)
727 return;
728
729 /* if modern processor, use no delay */
730 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
731 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
732 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
733 init_udelay = 0;
734 return;
735 }
736 /* else, use legacy delay */
737 init_udelay = UDELAY_10MS_DEFAULT;
738}
739
740/*
741 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
742 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
743 * won't ... remember to clear down the APIC, etc later.
744 */
745int
746wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
747{
748 unsigned long send_status, accept_status = 0;
749 int maxlvt;
750
751 /* Target chip */
752 /* Boot on the stack */
753 /* Kick the second */
754 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
755
756 pr_debug("Waiting for send to finish...\n");
757 send_status = safe_apic_wait_icr_idle();
758
759 /*
760 * Give the other CPU some time to accept the IPI.
761 */
762 udelay(200);
763 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
764 maxlvt = lapic_get_maxlvt();
765 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
766 apic_write(APIC_ESR, 0);
767 accept_status = (apic_read(APIC_ESR) & 0xEF);
768 }
769 pr_debug("NMI sent\n");
770
771 if (send_status)
772 pr_err("APIC never delivered???\n");
773 if (accept_status)
774 pr_err("APIC delivery error (%lx)\n", accept_status);
775
776 return (send_status | accept_status);
777}
778
779static int
780wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
781{
782 unsigned long send_status = 0, accept_status = 0;
783 int maxlvt, num_starts, j;
784
785 maxlvt = lapic_get_maxlvt();
786
787 /*
788 * Be paranoid about clearing APIC errors.
789 */
790 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
791 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
792 apic_write(APIC_ESR, 0);
793 apic_read(APIC_ESR);
794 }
795
796 pr_debug("Asserting INIT\n");
797
798 /*
799 * Turn INIT on target chip
800 */
801 /*
802 * Send IPI
803 */
804 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
805 phys_apicid);
806
807 pr_debug("Waiting for send to finish...\n");
808 send_status = safe_apic_wait_icr_idle();
809
810 udelay(init_udelay);
811
812 pr_debug("Deasserting INIT\n");
813
814 /* Target chip */
815 /* Send IPI */
816 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
817
818 pr_debug("Waiting for send to finish...\n");
819 send_status = safe_apic_wait_icr_idle();
820
821 mb();
822
823 /*
824 * Should we send STARTUP IPIs ?
825 *
826 * Determine this based on the APIC version.
827 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
828 */
829 if (APIC_INTEGRATED(boot_cpu_apic_version))
830 num_starts = 2;
831 else
832 num_starts = 0;
833
834 /*
835 * Run STARTUP IPI loop.
836 */
837 pr_debug("#startup loops: %d\n", num_starts);
838
839 for (j = 1; j <= num_starts; j++) {
840 pr_debug("Sending STARTUP #%d\n", j);
841 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
842 apic_write(APIC_ESR, 0);
843 apic_read(APIC_ESR);
844 pr_debug("After apic_write\n");
845
846 /*
847 * STARTUP IPI
848 */
849
850 /* Target chip */
851 /* Boot on the stack */
852 /* Kick the second */
853 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
854 phys_apicid);
855
856 /*
857 * Give the other CPU some time to accept the IPI.
858 */
859 if (init_udelay == 0)
860 udelay(10);
861 else
862 udelay(300);
863
864 pr_debug("Startup point 1\n");
865
866 pr_debug("Waiting for send to finish...\n");
867 send_status = safe_apic_wait_icr_idle();
868
869 /*
870 * Give the other CPU some time to accept the IPI.
871 */
872 if (init_udelay == 0)
873 udelay(10);
874 else
875 udelay(200);
876
877 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
878 apic_write(APIC_ESR, 0);
879 accept_status = (apic_read(APIC_ESR) & 0xEF);
880 if (send_status || accept_status)
881 break;
882 }
883 pr_debug("After Startup\n");
884
885 if (send_status)
886 pr_err("APIC never delivered???\n");
887 if (accept_status)
888 pr_err("APIC delivery error (%lx)\n", accept_status);
889
890 return (send_status | accept_status);
891}
892
893/* reduce the number of lines printed when booting a large cpu count system */
894static void announce_cpu(int cpu, int apicid)
895{
896 static int current_node = NUMA_NO_NODE;
897 int node = early_cpu_to_node(cpu);
898 static int width, node_width;
899
900 if (!width)
901 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
902
903 if (!node_width)
904 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
905
906 if (cpu == 1)
907 printk(KERN_INFO "x86: Booting SMP configuration:\n");
908
909 if (system_state < SYSTEM_RUNNING) {
910 if (node != current_node) {
911 if (current_node > (-1))
912 pr_cont("\n");
913 current_node = node;
914
915 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
916 node_width - num_digits(node), " ", node);
917 }
918
919 /* Add padding for the BSP */
920 if (cpu == 1)
921 pr_cont("%*s", width + 1, " ");
922
923 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
924
925 } else
926 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
927 node, cpu, apicid);
928}
929
930static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
931{
932 int cpu;
933
934 cpu = smp_processor_id();
935 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
936 return NMI_HANDLED;
937
938 return NMI_DONE;
939}
940
941/*
942 * Wake up AP by INIT, INIT, STARTUP sequence.
943 *
944 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
945 * boot-strap code which is not a desired behavior for waking up BSP. To
946 * void the boot-strap code, wake up CPU0 by NMI instead.
947 *
948 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
949 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
950 * We'll change this code in the future to wake up hard offlined CPU0 if
951 * real platform and request are available.
952 */
953static int
954wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
955 int *cpu0_nmi_registered)
956{
957 int id;
958 int boot_error;
959
960 preempt_disable();
961
962 /*
963 * Wake up AP by INIT, INIT, STARTUP sequence.
964 */
965 if (cpu) {
966 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
967 goto out;
968 }
969
970 /*
971 * Wake up BSP by nmi.
972 *
973 * Register a NMI handler to help wake up CPU0.
974 */
975 boot_error = register_nmi_handler(NMI_LOCAL,
976 wakeup_cpu0_nmi, 0, "wake_cpu0");
977
978 if (!boot_error) {
979 enable_start_cpu0 = 1;
980 *cpu0_nmi_registered = 1;
981 if (apic->dest_logical == APIC_DEST_LOGICAL)
982 id = cpu0_logical_apicid;
983 else
984 id = apicid;
985 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
986 }
987
988out:
989 preempt_enable();
990
991 return boot_error;
992}
993
994int common_cpu_up(unsigned int cpu, struct task_struct *idle)
995{
996 int ret;
997
998 /* Just in case we booted with a single CPU. */
999 alternatives_enable_smp();
1000
1001 per_cpu(current_task, cpu) = idle;
1002
1003 /* Initialize the interrupt stack(s) */
1004 ret = irq_init_percpu_irqstack(cpu);
1005 if (ret)
1006 return ret;
1007
1008#ifdef CONFIG_X86_32
1009 /* Stack for startup_32 can be just as for start_secondary onwards */
1010 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1011#else
1012 initial_gs = per_cpu_offset(cpu);
1013#endif
1014 return 0;
1015}
1016
1017/*
1018 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1019 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1020 * Returns zero if CPU booted OK, else error code from
1021 * ->wakeup_secondary_cpu.
1022 */
1023static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1024 int *cpu0_nmi_registered)
1025{
1026 /* start_ip had better be page-aligned! */
1027 unsigned long start_ip = real_mode_header->trampoline_start;
1028
1029 unsigned long boot_error = 0;
1030 unsigned long timeout;
1031
1032 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1033 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1034 initial_code = (unsigned long)start_secondary;
1035 initial_stack = idle->thread.sp;
1036
1037 /* Enable the espfix hack for this CPU */
1038 init_espfix_ap(cpu);
1039
1040 /* So we see what's up */
1041 announce_cpu(cpu, apicid);
1042
1043 /*
1044 * This grunge runs the startup process for
1045 * the targeted processor.
1046 */
1047
1048 if (x86_platform.legacy.warm_reset) {
1049
1050 pr_debug("Setting warm reset code and vector.\n");
1051
1052 smpboot_setup_warm_reset_vector(start_ip);
1053 /*
1054 * Be paranoid about clearing APIC errors.
1055 */
1056 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1057 apic_write(APIC_ESR, 0);
1058 apic_read(APIC_ESR);
1059 }
1060 }
1061
1062 /*
1063 * AP might wait on cpu_callout_mask in cpu_init() with
1064 * cpu_initialized_mask set if previous attempt to online
1065 * it timed-out. Clear cpu_initialized_mask so that after
1066 * INIT/SIPI it could start with a clean state.
1067 */
1068 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1069 smp_mb();
1070
1071 /*
1072 * Wake up a CPU in difference cases:
1073 * - Use the method in the APIC driver if it's defined
1074 * Otherwise,
1075 * - Use an INIT boot APIC message for APs or NMI for BSP.
1076 */
1077 if (apic->wakeup_secondary_cpu)
1078 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1079 else
1080 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1081 cpu0_nmi_registered);
1082
1083 if (!boot_error) {
1084 /*
1085 * Wait 10s total for first sign of life from AP
1086 */
1087 boot_error = -1;
1088 timeout = jiffies + 10*HZ;
1089 while (time_before(jiffies, timeout)) {
1090 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1091 /*
1092 * Tell AP to proceed with initialization
1093 */
1094 cpumask_set_cpu(cpu, cpu_callout_mask);
1095 boot_error = 0;
1096 break;
1097 }
1098 schedule();
1099 }
1100 }
1101
1102 if (!boot_error) {
1103 /*
1104 * Wait till AP completes initial initialization
1105 */
1106 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1107 /*
1108 * Allow other tasks to run while we wait for the
1109 * AP to come online. This also gives a chance
1110 * for the MTRR work(triggered by the AP coming online)
1111 * to be completed in the stop machine context.
1112 */
1113 schedule();
1114 }
1115 }
1116
1117 if (x86_platform.legacy.warm_reset) {
1118 /*
1119 * Cleanup possible dangling ends...
1120 */
1121 smpboot_restore_warm_reset_vector();
1122 }
1123
1124 return boot_error;
1125}
1126
1127int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1128{
1129 int apicid = apic->cpu_present_to_apicid(cpu);
1130 int cpu0_nmi_registered = 0;
1131 unsigned long flags;
1132 int err, ret = 0;
1133
1134 lockdep_assert_irqs_enabled();
1135
1136 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1137
1138 if (apicid == BAD_APICID ||
1139 !physid_isset(apicid, phys_cpu_present_map) ||
1140 !apic->apic_id_valid(apicid)) {
1141 pr_err("%s: bad cpu %d\n", __func__, cpu);
1142 return -EINVAL;
1143 }
1144
1145 /*
1146 * Already booted CPU?
1147 */
1148 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1149 pr_debug("do_boot_cpu %d Already started\n", cpu);
1150 return -ENOSYS;
1151 }
1152
1153 /*
1154 * Save current MTRR state in case it was changed since early boot
1155 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1156 */
1157 mtrr_save_state();
1158
1159 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1160 err = cpu_check_up_prepare(cpu);
1161 if (err && err != -EBUSY)
1162 return err;
1163
1164 /* the FPU context is blank, nobody can own it */
1165 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1166
1167 err = common_cpu_up(cpu, tidle);
1168 if (err)
1169 return err;
1170
1171 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1172 if (err) {
1173 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1174 ret = -EIO;
1175 goto unreg_nmi;
1176 }
1177
1178 /*
1179 * Check TSC synchronization with the AP (keep irqs disabled
1180 * while doing so):
1181 */
1182 local_irq_save(flags);
1183 check_tsc_sync_source(cpu);
1184 local_irq_restore(flags);
1185
1186 while (!cpu_online(cpu)) {
1187 cpu_relax();
1188 touch_nmi_watchdog();
1189 }
1190
1191unreg_nmi:
1192 /*
1193 * Clean up the nmi handler. Do this after the callin and callout sync
1194 * to avoid impact of possible long unregister time.
1195 */
1196 if (cpu0_nmi_registered)
1197 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1198
1199 return ret;
1200}
1201
1202/**
1203 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1204 */
1205void arch_disable_smp_support(void)
1206{
1207 disable_ioapic_support();
1208}
1209
1210/*
1211 * Fall back to non SMP mode after errors.
1212 *
1213 * RED-PEN audit/test this more. I bet there is more state messed up here.
1214 */
1215static __init void disable_smp(void)
1216{
1217 pr_info("SMP disabled\n");
1218
1219 disable_ioapic_support();
1220
1221 init_cpu_present(cpumask_of(0));
1222 init_cpu_possible(cpumask_of(0));
1223
1224 if (smp_found_config)
1225 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1226 else
1227 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1228 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1229 cpumask_set_cpu(0, topology_core_cpumask(0));
1230 cpumask_set_cpu(0, topology_die_cpumask(0));
1231}
1232
1233/*
1234 * Various sanity checks.
1235 */
1236static void __init smp_sanity_check(void)
1237{
1238 preempt_disable();
1239
1240#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1241 if (def_to_bigsmp && nr_cpu_ids > 8) {
1242 unsigned int cpu;
1243 unsigned nr;
1244
1245 pr_warn("More than 8 CPUs detected - skipping them\n"
1246 "Use CONFIG_X86_BIGSMP\n");
1247
1248 nr = 0;
1249 for_each_present_cpu(cpu) {
1250 if (nr >= 8)
1251 set_cpu_present(cpu, false);
1252 nr++;
1253 }
1254
1255 nr = 0;
1256 for_each_possible_cpu(cpu) {
1257 if (nr >= 8)
1258 set_cpu_possible(cpu, false);
1259 nr++;
1260 }
1261
1262 nr_cpu_ids = 8;
1263 }
1264#endif
1265
1266 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1267 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1268 hard_smp_processor_id());
1269
1270 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1271 }
1272
1273 /*
1274 * Should not be necessary because the MP table should list the boot
1275 * CPU too, but we do it for the sake of robustness anyway.
1276 */
1277 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1278 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1279 boot_cpu_physical_apicid);
1280 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1281 }
1282 preempt_enable();
1283}
1284
1285static void __init smp_cpu_index_default(void)
1286{
1287 int i;
1288 struct cpuinfo_x86 *c;
1289
1290 for_each_possible_cpu(i) {
1291 c = &cpu_data(i);
1292 /* mark all to hotplug */
1293 c->cpu_index = nr_cpu_ids;
1294 }
1295}
1296
1297static void __init smp_get_logical_apicid(void)
1298{
1299 if (x2apic_mode)
1300 cpu0_logical_apicid = apic_read(APIC_LDR);
1301 else
1302 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1303}
1304
1305/*
1306 * Prepare for SMP bootup.
1307 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1308 * for common interface support.
1309 */
1310void __init native_smp_prepare_cpus(unsigned int max_cpus)
1311{
1312 unsigned int i;
1313
1314 smp_cpu_index_default();
1315
1316 /*
1317 * Setup boot CPU information
1318 */
1319 smp_store_boot_cpu_info(); /* Final full version of the data */
1320 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1321 mb();
1322
1323 for_each_possible_cpu(i) {
1324 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1325 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1326 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1327 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1328 }
1329
1330 /*
1331 * Set 'default' x86 topology, this matches default_topology() in that
1332 * it has NUMA nodes as a topology level. See also
1333 * native_smp_cpus_done().
1334 *
1335 * Must be done before set_cpus_sibling_map() is ran.
1336 */
1337 set_sched_topology(x86_topology);
1338
1339 set_cpu_sibling_map(0);
1340
1341 smp_sanity_check();
1342
1343 switch (apic_intr_mode) {
1344 case APIC_PIC:
1345 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1346 disable_smp();
1347 return;
1348 case APIC_SYMMETRIC_IO_NO_ROUTING:
1349 disable_smp();
1350 /* Setup local timer */
1351 x86_init.timers.setup_percpu_clockev();
1352 return;
1353 case APIC_VIRTUAL_WIRE:
1354 case APIC_SYMMETRIC_IO:
1355 break;
1356 }
1357
1358 /* Setup local timer */
1359 x86_init.timers.setup_percpu_clockev();
1360
1361 smp_get_logical_apicid();
1362
1363 pr_info("CPU0: ");
1364 print_cpu_info(&cpu_data(0));
1365
1366 uv_system_init();
1367
1368 set_mtrr_aps_delayed_init();
1369
1370 smp_quirk_init_udelay();
1371
1372 speculative_store_bypass_ht_init();
1373}
1374
1375void arch_enable_nonboot_cpus_begin(void)
1376{
1377 set_mtrr_aps_delayed_init();
1378}
1379
1380void arch_enable_nonboot_cpus_end(void)
1381{
1382 mtrr_aps_init();
1383}
1384
1385/*
1386 * Early setup to make printk work.
1387 */
1388void __init native_smp_prepare_boot_cpu(void)
1389{
1390 int me = smp_processor_id();
1391 switch_to_new_gdt(me);
1392 /* already set me in cpu_online_mask in boot_cpu_init() */
1393 cpumask_set_cpu(me, cpu_callout_mask);
1394 cpu_set_state_online(me);
1395 native_pv_lock_init();
1396}
1397
1398void __init calculate_max_logical_packages(void)
1399{
1400 int ncpus;
1401
1402 /*
1403 * Today neither Intel nor AMD support heterogenous systems so
1404 * extrapolate the boot cpu's data to all packages.
1405 */
1406 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1407 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1408 pr_info("Max logical packages: %u\n", __max_logical_packages);
1409}
1410
1411void __init native_smp_cpus_done(unsigned int max_cpus)
1412{
1413 pr_debug("Boot done\n");
1414
1415 calculate_max_logical_packages();
1416
1417 if (x86_has_numa_in_package)
1418 set_sched_topology(x86_numa_in_package_topology);
1419
1420 nmi_selftest();
1421 impress_friends();
1422 mtrr_aps_init();
1423}
1424
1425static int __initdata setup_possible_cpus = -1;
1426static int __init _setup_possible_cpus(char *str)
1427{
1428 get_option(&str, &setup_possible_cpus);
1429 return 0;
1430}
1431early_param("possible_cpus", _setup_possible_cpus);
1432
1433
1434/*
1435 * cpu_possible_mask should be static, it cannot change as cpu's
1436 * are onlined, or offlined. The reason is per-cpu data-structures
1437 * are allocated by some modules at init time, and dont expect to
1438 * do this dynamically on cpu arrival/departure.
1439 * cpu_present_mask on the other hand can change dynamically.
1440 * In case when cpu_hotplug is not compiled, then we resort to current
1441 * behaviour, which is cpu_possible == cpu_present.
1442 * - Ashok Raj
1443 *
1444 * Three ways to find out the number of additional hotplug CPUs:
1445 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1446 * - The user can overwrite it with possible_cpus=NUM
1447 * - Otherwise don't reserve additional CPUs.
1448 * We do this because additional CPUs waste a lot of memory.
1449 * -AK
1450 */
1451__init void prefill_possible_map(void)
1452{
1453 int i, possible;
1454
1455 /* No boot processor was found in mptable or ACPI MADT */
1456 if (!num_processors) {
1457 if (boot_cpu_has(X86_FEATURE_APIC)) {
1458 int apicid = boot_cpu_physical_apicid;
1459 int cpu = hard_smp_processor_id();
1460
1461 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1462
1463 /* Make sure boot cpu is enumerated */
1464 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1465 apic->apic_id_valid(apicid))
1466 generic_processor_info(apicid, boot_cpu_apic_version);
1467 }
1468
1469 if (!num_processors)
1470 num_processors = 1;
1471 }
1472
1473 i = setup_max_cpus ?: 1;
1474 if (setup_possible_cpus == -1) {
1475 possible = num_processors;
1476#ifdef CONFIG_HOTPLUG_CPU
1477 if (setup_max_cpus)
1478 possible += disabled_cpus;
1479#else
1480 if (possible > i)
1481 possible = i;
1482#endif
1483 } else
1484 possible = setup_possible_cpus;
1485
1486 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1487
1488 /* nr_cpu_ids could be reduced via nr_cpus= */
1489 if (possible > nr_cpu_ids) {
1490 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1491 possible, nr_cpu_ids);
1492 possible = nr_cpu_ids;
1493 }
1494
1495#ifdef CONFIG_HOTPLUG_CPU
1496 if (!setup_max_cpus)
1497#endif
1498 if (possible > i) {
1499 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1500 possible, setup_max_cpus);
1501 possible = i;
1502 }
1503
1504 nr_cpu_ids = possible;
1505
1506 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1507 possible, max_t(int, possible - num_processors, 0));
1508
1509 reset_cpu_possible_mask();
1510
1511 for (i = 0; i < possible; i++)
1512 set_cpu_possible(i, true);
1513}
1514
1515#ifdef CONFIG_HOTPLUG_CPU
1516
1517/* Recompute SMT state for all CPUs on offline */
1518static void recompute_smt_state(void)
1519{
1520 int max_threads, cpu;
1521
1522 max_threads = 0;
1523 for_each_online_cpu (cpu) {
1524 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1525
1526 if (threads > max_threads)
1527 max_threads = threads;
1528 }
1529 __max_smt_threads = max_threads;
1530}
1531
1532static void remove_siblinginfo(int cpu)
1533{
1534 int sibling;
1535 struct cpuinfo_x86 *c = &cpu_data(cpu);
1536
1537 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1538 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1539 /*/
1540 * last thread sibling in this cpu core going down
1541 */
1542 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1543 cpu_data(sibling).booted_cores--;
1544 }
1545
1546 for_each_cpu(sibling, topology_die_cpumask(cpu))
1547 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1548 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1549 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1550 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1551 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1552 cpumask_clear(cpu_llc_shared_mask(cpu));
1553 cpumask_clear(topology_sibling_cpumask(cpu));
1554 cpumask_clear(topology_core_cpumask(cpu));
1555 cpumask_clear(topology_die_cpumask(cpu));
1556 c->cpu_core_id = 0;
1557 c->booted_cores = 0;
1558 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1559 recompute_smt_state();
1560}
1561
1562static void remove_cpu_from_maps(int cpu)
1563{
1564 set_cpu_online(cpu, false);
1565 cpumask_clear_cpu(cpu, cpu_callout_mask);
1566 cpumask_clear_cpu(cpu, cpu_callin_mask);
1567 /* was set by cpu_init() */
1568 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1569 numa_remove_cpu(cpu);
1570}
1571
1572void cpu_disable_common(void)
1573{
1574 int cpu = smp_processor_id();
1575
1576 remove_siblinginfo(cpu);
1577
1578 /* It's now safe to remove this processor from the online map */
1579 lock_vector_lock();
1580 remove_cpu_from_maps(cpu);
1581 unlock_vector_lock();
1582 fixup_irqs();
1583 lapic_offline();
1584}
1585
1586int native_cpu_disable(void)
1587{
1588 int ret;
1589
1590 ret = lapic_can_unplug_cpu();
1591 if (ret)
1592 return ret;
1593
1594 /*
1595 * Disable the local APIC. Otherwise IPI broadcasts will reach
1596 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1597 * messages.
1598 */
1599 apic_soft_disable();
1600 cpu_disable_common();
1601
1602 return 0;
1603}
1604
1605int common_cpu_die(unsigned int cpu)
1606{
1607 int ret = 0;
1608
1609 /* We don't do anything here: idle task is faking death itself. */
1610
1611 /* They ack this in play_dead() by setting CPU_DEAD */
1612 if (cpu_wait_death(cpu, 5)) {
1613 if (system_state == SYSTEM_RUNNING)
1614 pr_info("CPU %u is now offline\n", cpu);
1615 } else {
1616 pr_err("CPU %u didn't die...\n", cpu);
1617 ret = -1;
1618 }
1619
1620 return ret;
1621}
1622
1623void native_cpu_die(unsigned int cpu)
1624{
1625 common_cpu_die(cpu);
1626}
1627
1628void play_dead_common(void)
1629{
1630 idle_task_exit();
1631
1632 /* Ack it */
1633 (void)cpu_report_death();
1634
1635 /*
1636 * With physical CPU hotplug, we should halt the cpu
1637 */
1638 local_irq_disable();
1639}
1640
1641static bool wakeup_cpu0(void)
1642{
1643 if (smp_processor_id() == 0 && enable_start_cpu0)
1644 return true;
1645
1646 return false;
1647}
1648
1649/*
1650 * We need to flush the caches before going to sleep, lest we have
1651 * dirty data in our caches when we come back up.
1652 */
1653static inline void mwait_play_dead(void)
1654{
1655 unsigned int eax, ebx, ecx, edx;
1656 unsigned int highest_cstate = 0;
1657 unsigned int highest_subcstate = 0;
1658 void *mwait_ptr;
1659 int i;
1660
1661 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1662 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1663 return;
1664 if (!this_cpu_has(X86_FEATURE_MWAIT))
1665 return;
1666 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1667 return;
1668 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1669 return;
1670
1671 eax = CPUID_MWAIT_LEAF;
1672 ecx = 0;
1673 native_cpuid(&eax, &ebx, &ecx, &edx);
1674
1675 /*
1676 * eax will be 0 if EDX enumeration is not valid.
1677 * Initialized below to cstate, sub_cstate value when EDX is valid.
1678 */
1679 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1680 eax = 0;
1681 } else {
1682 edx >>= MWAIT_SUBSTATE_SIZE;
1683 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1684 if (edx & MWAIT_SUBSTATE_MASK) {
1685 highest_cstate = i;
1686 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1687 }
1688 }
1689 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1690 (highest_subcstate - 1);
1691 }
1692
1693 /*
1694 * This should be a memory location in a cache line which is
1695 * unlikely to be touched by other processors. The actual
1696 * content is immaterial as it is not actually modified in any way.
1697 */
1698 mwait_ptr = ¤t_thread_info()->flags;
1699
1700 wbinvd();
1701
1702 while (1) {
1703 /*
1704 * The CLFLUSH is a workaround for erratum AAI65 for
1705 * the Xeon 7400 series. It's not clear it is actually
1706 * needed, but it should be harmless in either case.
1707 * The WBINVD is insufficient due to the spurious-wakeup
1708 * case where we return around the loop.
1709 */
1710 mb();
1711 clflush(mwait_ptr);
1712 mb();
1713 __monitor(mwait_ptr, 0, 0);
1714 mb();
1715 __mwait(eax, 0);
1716 /*
1717 * If NMI wants to wake up CPU0, start CPU0.
1718 */
1719 if (wakeup_cpu0())
1720 start_cpu0();
1721 }
1722}
1723
1724void hlt_play_dead(void)
1725{
1726 if (__this_cpu_read(cpu_info.x86) >= 4)
1727 wbinvd();
1728
1729 while (1) {
1730 native_halt();
1731 /*
1732 * If NMI wants to wake up CPU0, start CPU0.
1733 */
1734 if (wakeup_cpu0())
1735 start_cpu0();
1736 }
1737}
1738
1739void native_play_dead(void)
1740{
1741 play_dead_common();
1742 tboot_shutdown(TB_SHUTDOWN_WFS);
1743
1744 mwait_play_dead(); /* Only returns on failure */
1745 if (cpuidle_play_dead())
1746 hlt_play_dead();
1747}
1748
1749#else /* ... !CONFIG_HOTPLUG_CPU */
1750int native_cpu_disable(void)
1751{
1752 return -ENOSYS;
1753}
1754
1755void native_cpu_die(unsigned int cpu)
1756{
1757 /* We said "no" in __cpu_disable */
1758 BUG();
1759}
1760
1761void native_play_dead(void)
1762{
1763 BUG();
1764}
1765
1766#endif
1/*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/module.h>
45#include <linux/sched.h>
46#include <linux/percpu.h>
47#include <linux/bootmem.h>
48#include <linux/err.h>
49#include <linux/nmi.h>
50#include <linux/tboot.h>
51#include <linux/stackprotector.h>
52#include <linux/gfp.h>
53
54#include <asm/acpi.h>
55#include <asm/desc.h>
56#include <asm/nmi.h>
57#include <asm/irq.h>
58#include <asm/idle.h>
59#include <asm/trampoline.h>
60#include <asm/cpu.h>
61#include <asm/numa.h>
62#include <asm/pgtable.h>
63#include <asm/tlbflush.h>
64#include <asm/mtrr.h>
65#include <asm/mwait.h>
66#include <asm/apic.h>
67#include <asm/io_apic.h>
68#include <asm/setup.h>
69#include <asm/uv/uv.h>
70#include <linux/mc146818rtc.h>
71
72#include <asm/smpboot_hooks.h>
73#include <asm/i8259.h>
74
75/* State of each CPU */
76DEFINE_PER_CPU(int, cpu_state) = { 0 };
77
78/* Store all idle threads, this can be reused instead of creating
79* a new thread. Also avoids complicated thread destroy functionality
80* for idle threads.
81*/
82#ifdef CONFIG_HOTPLUG_CPU
83/*
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
86 */
87static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
90
91/*
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
94 */
95static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
96
97void cpu_hotplug_driver_lock(void)
98{
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
100}
101
102void cpu_hotplug_driver_unlock(void)
103{
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
105}
106
107ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
109#else
110static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111#define get_idle_for_cpu(x) (idle_thread_array[(x)])
112#define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
113#endif
114
115/* Number of siblings per CPU package */
116int smp_num_siblings = 1;
117EXPORT_SYMBOL(smp_num_siblings);
118
119/* Last level cache ID of each logical CPU */
120DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
121
122/* representing HT siblings of each logical CPU */
123DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
125
126/* representing HT and core siblings of each logical CPU */
127DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128EXPORT_PER_CPU_SYMBOL(cpu_core_map);
129
130DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
131
132/* Per CPU bogomips and other parameters */
133DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134EXPORT_PER_CPU_SYMBOL(cpu_info);
135
136atomic_t init_deasserted;
137
138/*
139 * Report back to the Boot Processor.
140 * Running on AP.
141 */
142static void __cpuinit smp_callin(void)
143{
144 int cpuid, phys_id;
145 unsigned long timeout;
146
147 /*
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
152 */
153 if (apic->wait_for_init_deassert)
154 apic->wait_for_init_deassert(&init_deasserted);
155
156 /*
157 * (This works even if the APIC is not enabled.)
158 */
159 phys_id = read_apic_id();
160 cpuid = smp_processor_id();
161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
163 phys_id, cpuid);
164 }
165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
166
167 /*
168 * STARTUP IPIs are fragile beasts as they might sometimes
169 * trigger some glue motherboard logic. Complete APIC bus
170 * silence for 1 second, this overestimates the time the
171 * boot CPU is spending to send the up to 2 STARTUP IPIs
172 * by a factor of two. This should be enough.
173 */
174
175 /*
176 * Waiting 2s total for startup (udelay is not yet working)
177 */
178 timeout = jiffies + 2*HZ;
179 while (time_before(jiffies, timeout)) {
180 /*
181 * Has the boot CPU finished it's STARTUP sequence?
182 */
183 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
184 break;
185 cpu_relax();
186 }
187
188 if (!time_before(jiffies, timeout)) {
189 panic("%s: CPU%d started up but did not get a callout!\n",
190 __func__, cpuid);
191 }
192
193 /*
194 * the boot CPU has finished the init stage and is spinning
195 * on callin_map until we finish. We are free to set up this
196 * CPU, first the APIC. (this is probably redundant on most
197 * boards)
198 */
199
200 pr_debug("CALLIN, before setup_local_APIC().\n");
201 if (apic->smp_callin_clear_local_apic)
202 apic->smp_callin_clear_local_apic();
203 setup_local_APIC();
204 end_local_APIC_setup();
205
206 /*
207 * Need to setup vector mappings before we enable interrupts.
208 */
209 setup_vector_irq(smp_processor_id());
210 /*
211 * Get our bogomips.
212 *
213 * Need to enable IRQs because it can take longer and then
214 * the NMI watchdog might kill us.
215 */
216 local_irq_enable();
217 calibrate_delay();
218 local_irq_disable();
219 pr_debug("Stack at about %p\n", &cpuid);
220
221 /*
222 * Save our processor parameters
223 */
224 smp_store_cpu_info(cpuid);
225
226 /*
227 * This must be done before setting cpu_online_mask
228 * or calling notify_cpu_starting.
229 */
230 set_cpu_sibling_map(raw_smp_processor_id());
231 wmb();
232
233 notify_cpu_starting(cpuid);
234
235 /*
236 * Allow the master to continue.
237 */
238 cpumask_set_cpu(cpuid, cpu_callin_mask);
239}
240
241/*
242 * Activate a secondary processor.
243 */
244notrace static void __cpuinit start_secondary(void *unused)
245{
246 /*
247 * Don't put *anything* before cpu_init(), SMP booting is too
248 * fragile that we want to limit the things done here to the
249 * most necessary things.
250 */
251 cpu_init();
252 preempt_disable();
253 smp_callin();
254
255#ifdef CONFIG_X86_32
256 /* switch away from the initial page table */
257 load_cr3(swapper_pg_dir);
258 __flush_tlb_all();
259#endif
260
261 /* otherwise gcc will move up smp_processor_id before the cpu_init */
262 barrier();
263 /*
264 * Check TSC synchronization with the BP:
265 */
266 check_tsc_sync_target();
267
268 /*
269 * We need to hold call_lock, so there is no inconsistency
270 * between the time smp_call_function() determines number of
271 * IPI recipients, and the time when the determination is made
272 * for which cpus receive the IPI. Holding this
273 * lock helps us to not include this cpu in a currently in progress
274 * smp_call_function().
275 *
276 * We need to hold vector_lock so there the set of online cpus
277 * does not change while we are assigning vectors to cpus. Holding
278 * this lock ensures we don't half assign or remove an irq from a cpu.
279 */
280 ipi_call_lock();
281 lock_vector_lock();
282 set_cpu_online(smp_processor_id(), true);
283 unlock_vector_lock();
284 ipi_call_unlock();
285 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
286 x86_platform.nmi_init();
287
288 /*
289 * Wait until the cpu which brought this one up marked it
290 * online before enabling interrupts. If we don't do that then
291 * we can end up waking up the softirq thread before this cpu
292 * reached the active state, which makes the scheduler unhappy
293 * and schedule the softirq thread on the wrong cpu. This is
294 * only observable with forced threaded interrupts, but in
295 * theory it could also happen w/o them. It's just way harder
296 * to achieve.
297 */
298 while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask))
299 cpu_relax();
300
301 /* enable local interrupts */
302 local_irq_enable();
303
304 /* to prevent fake stack check failure in clock setup */
305 boot_init_stack_canary();
306
307 x86_cpuinit.setup_percpu_clockev();
308
309 wmb();
310 cpu_idle();
311}
312
313/*
314 * The bootstrap kernel entry code has set these up. Save them for
315 * a given CPU
316 */
317
318void __cpuinit smp_store_cpu_info(int id)
319{
320 struct cpuinfo_x86 *c = &cpu_data(id);
321
322 *c = boot_cpu_data;
323 c->cpu_index = id;
324 if (id != 0)
325 identify_secondary_cpu(c);
326}
327
328static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
329{
330 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
331 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
332 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
333 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
334 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
335 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
336}
337
338
339void __cpuinit set_cpu_sibling_map(int cpu)
340{
341 int i;
342 struct cpuinfo_x86 *c = &cpu_data(cpu);
343
344 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
345
346 if (smp_num_siblings > 1) {
347 for_each_cpu(i, cpu_sibling_setup_mask) {
348 struct cpuinfo_x86 *o = &cpu_data(i);
349
350 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
351 if (c->phys_proc_id == o->phys_proc_id &&
352 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
353 c->compute_unit_id == o->compute_unit_id)
354 link_thread_siblings(cpu, i);
355 } else if (c->phys_proc_id == o->phys_proc_id &&
356 c->cpu_core_id == o->cpu_core_id) {
357 link_thread_siblings(cpu, i);
358 }
359 }
360 } else {
361 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
362 }
363
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365
366 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
367 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
368 c->booted_cores = 1;
369 return;
370 }
371
372 for_each_cpu(i, cpu_sibling_setup_mask) {
373 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
374 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
375 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
376 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
377 }
378 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
379 cpumask_set_cpu(i, cpu_core_mask(cpu));
380 cpumask_set_cpu(cpu, cpu_core_mask(i));
381 /*
382 * Does this new cpu bringup a new core?
383 */
384 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
385 /*
386 * for each core in package, increment
387 * the booted_cores for this new cpu
388 */
389 if (cpumask_first(cpu_sibling_mask(i)) == i)
390 c->booted_cores++;
391 /*
392 * increment the core count for all
393 * the other cpus in this package
394 */
395 if (i != cpu)
396 cpu_data(i).booted_cores++;
397 } else if (i != cpu && !c->booted_cores)
398 c->booted_cores = cpu_data(i).booted_cores;
399 }
400 }
401}
402
403/* maps the cpu to the sched domain representing multi-core */
404const struct cpumask *cpu_coregroup_mask(int cpu)
405{
406 struct cpuinfo_x86 *c = &cpu_data(cpu);
407 /*
408 * For perf, we return last level cache shared map.
409 * And for power savings, we return cpu_core_map
410 */
411 if ((sched_mc_power_savings || sched_smt_power_savings) &&
412 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
413 return cpu_core_mask(cpu);
414 else
415 return cpu_llc_shared_mask(cpu);
416}
417
418static void impress_friends(void)
419{
420 int cpu;
421 unsigned long bogosum = 0;
422 /*
423 * Allow the user to impress friends.
424 */
425 pr_debug("Before bogomips.\n");
426 for_each_possible_cpu(cpu)
427 if (cpumask_test_cpu(cpu, cpu_callout_mask))
428 bogosum += cpu_data(cpu).loops_per_jiffy;
429 printk(KERN_INFO
430 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
431 num_online_cpus(),
432 bogosum/(500000/HZ),
433 (bogosum/(5000/HZ))%100);
434
435 pr_debug("Before bogocount - setting activated=1.\n");
436}
437
438void __inquire_remote_apic(int apicid)
439{
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 const char * const names[] = { "ID", "VERSION", "SPIV" };
442 int timeout;
443 u32 status;
444
445 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
446
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
449
450 /*
451 * Wait for idle.
452 */
453 status = safe_apic_wait_icr_idle();
454 if (status)
455 printk(KERN_CONT
456 "a previous APIC delivery may have failed\n");
457
458 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
459
460 timeout = 0;
461 do {
462 udelay(100);
463 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
464 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
465
466 switch (status) {
467 case APIC_ICR_RR_VALID:
468 status = apic_read(APIC_RRR);
469 printk(KERN_CONT "%08x\n", status);
470 break;
471 default:
472 printk(KERN_CONT "failed\n");
473 }
474 }
475}
476
477/*
478 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
479 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
480 * won't ... remember to clear down the APIC, etc later.
481 */
482int __cpuinit
483wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
484{
485 unsigned long send_status, accept_status = 0;
486 int maxlvt;
487
488 /* Target chip */
489 /* Boot on the stack */
490 /* Kick the second */
491 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
492
493 pr_debug("Waiting for send to finish...\n");
494 send_status = safe_apic_wait_icr_idle();
495
496 /*
497 * Give the other CPU some time to accept the IPI.
498 */
499 udelay(200);
500 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
501 maxlvt = lapic_get_maxlvt();
502 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
503 apic_write(APIC_ESR, 0);
504 accept_status = (apic_read(APIC_ESR) & 0xEF);
505 }
506 pr_debug("NMI sent.\n");
507
508 if (send_status)
509 printk(KERN_ERR "APIC never delivered???\n");
510 if (accept_status)
511 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
512
513 return (send_status | accept_status);
514}
515
516static int __cpuinit
517wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
518{
519 unsigned long send_status, accept_status = 0;
520 int maxlvt, num_starts, j;
521
522 maxlvt = lapic_get_maxlvt();
523
524 /*
525 * Be paranoid about clearing APIC errors.
526 */
527 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
529 apic_write(APIC_ESR, 0);
530 apic_read(APIC_ESR);
531 }
532
533 pr_debug("Asserting INIT.\n");
534
535 /*
536 * Turn INIT on target chip
537 */
538 /*
539 * Send IPI
540 */
541 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
542 phys_apicid);
543
544 pr_debug("Waiting for send to finish...\n");
545 send_status = safe_apic_wait_icr_idle();
546
547 mdelay(10);
548
549 pr_debug("Deasserting INIT.\n");
550
551 /* Target chip */
552 /* Send IPI */
553 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
554
555 pr_debug("Waiting for send to finish...\n");
556 send_status = safe_apic_wait_icr_idle();
557
558 mb();
559 atomic_set(&init_deasserted, 1);
560
561 /*
562 * Should we send STARTUP IPIs ?
563 *
564 * Determine this based on the APIC version.
565 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
566 */
567 if (APIC_INTEGRATED(apic_version[phys_apicid]))
568 num_starts = 2;
569 else
570 num_starts = 0;
571
572 /*
573 * Paravirt / VMI wants a startup IPI hook here to set up the
574 * target processor state.
575 */
576 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
577 stack_start);
578
579 /*
580 * Run STARTUP IPI loop.
581 */
582 pr_debug("#startup loops: %d.\n", num_starts);
583
584 for (j = 1; j <= num_starts; j++) {
585 pr_debug("Sending STARTUP #%d.\n", j);
586 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
587 apic_write(APIC_ESR, 0);
588 apic_read(APIC_ESR);
589 pr_debug("After apic_write.\n");
590
591 /*
592 * STARTUP IPI
593 */
594
595 /* Target chip */
596 /* Boot on the stack */
597 /* Kick the second */
598 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
599 phys_apicid);
600
601 /*
602 * Give the other CPU some time to accept the IPI.
603 */
604 udelay(300);
605
606 pr_debug("Startup point 1.\n");
607
608 pr_debug("Waiting for send to finish...\n");
609 send_status = safe_apic_wait_icr_idle();
610
611 /*
612 * Give the other CPU some time to accept the IPI.
613 */
614 udelay(200);
615 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
616 apic_write(APIC_ESR, 0);
617 accept_status = (apic_read(APIC_ESR) & 0xEF);
618 if (send_status || accept_status)
619 break;
620 }
621 pr_debug("After Startup.\n");
622
623 if (send_status)
624 printk(KERN_ERR "APIC never delivered???\n");
625 if (accept_status)
626 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
627
628 return (send_status | accept_status);
629}
630
631struct create_idle {
632 struct work_struct work;
633 struct task_struct *idle;
634 struct completion done;
635 int cpu;
636};
637
638static void __cpuinit do_fork_idle(struct work_struct *work)
639{
640 struct create_idle *c_idle =
641 container_of(work, struct create_idle, work);
642
643 c_idle->idle = fork_idle(c_idle->cpu);
644 complete(&c_idle->done);
645}
646
647/* reduce the number of lines printed when booting a large cpu count system */
648static void __cpuinit announce_cpu(int cpu, int apicid)
649{
650 static int current_node = -1;
651 int node = early_cpu_to_node(cpu);
652
653 if (system_state == SYSTEM_BOOTING) {
654 if (node != current_node) {
655 if (current_node > (-1))
656 pr_cont(" Ok.\n");
657 current_node = node;
658 pr_info("Booting Node %3d, Processors ", node);
659 }
660 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
661 return;
662 } else
663 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
664 node, cpu, apicid);
665}
666
667/*
668 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
669 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
670 * Returns zero if CPU booted OK, else error code from
671 * ->wakeup_secondary_cpu.
672 */
673static int __cpuinit do_boot_cpu(int apicid, int cpu)
674{
675 unsigned long boot_error = 0;
676 unsigned long start_ip;
677 int timeout;
678 struct create_idle c_idle = {
679 .cpu = cpu,
680 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
681 };
682
683 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
684
685 alternatives_smp_switch(1);
686
687 c_idle.idle = get_idle_for_cpu(cpu);
688
689 /*
690 * We can't use kernel_thread since we must avoid to
691 * reschedule the child.
692 */
693 if (c_idle.idle) {
694 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
695 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
696 init_idle(c_idle.idle, cpu);
697 goto do_rest;
698 }
699
700 schedule_work(&c_idle.work);
701 wait_for_completion(&c_idle.done);
702
703 if (IS_ERR(c_idle.idle)) {
704 printk("failed fork for CPU %d\n", cpu);
705 destroy_work_on_stack(&c_idle.work);
706 return PTR_ERR(c_idle.idle);
707 }
708
709 set_idle_for_cpu(cpu, c_idle.idle);
710do_rest:
711 per_cpu(current_task, cpu) = c_idle.idle;
712#ifdef CONFIG_X86_32
713 /* Stack for startup_32 can be just as for start_secondary onwards */
714 irq_ctx_init(cpu);
715#else
716 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
717 initial_gs = per_cpu_offset(cpu);
718 per_cpu(kernel_stack, cpu) =
719 (unsigned long)task_stack_page(c_idle.idle) -
720 KERNEL_STACK_OFFSET + THREAD_SIZE;
721#endif
722 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
723 initial_code = (unsigned long)start_secondary;
724 stack_start = c_idle.idle->thread.sp;
725
726 /* start_ip had better be page-aligned! */
727 start_ip = trampoline_address();
728
729 /* So we see what's up */
730 announce_cpu(cpu, apicid);
731
732 /*
733 * This grunge runs the startup process for
734 * the targeted processor.
735 */
736
737 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
738
739 atomic_set(&init_deasserted, 0);
740
741 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
742
743 pr_debug("Setting warm reset code and vector.\n");
744
745 smpboot_setup_warm_reset_vector(start_ip);
746 /*
747 * Be paranoid about clearing APIC errors.
748 */
749 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
750 apic_write(APIC_ESR, 0);
751 apic_read(APIC_ESR);
752 }
753 }
754
755 /*
756 * Kick the secondary CPU. Use the method in the APIC driver
757 * if it's defined - or use an INIT boot APIC message otherwise:
758 */
759 if (apic->wakeup_secondary_cpu)
760 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
761 else
762 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
763
764 if (!boot_error) {
765 /*
766 * allow APs to start initializing.
767 */
768 pr_debug("Before Callout %d.\n", cpu);
769 cpumask_set_cpu(cpu, cpu_callout_mask);
770 pr_debug("After Callout %d.\n", cpu);
771
772 /*
773 * Wait 5s total for a response
774 */
775 for (timeout = 0; timeout < 50000; timeout++) {
776 if (cpumask_test_cpu(cpu, cpu_callin_mask))
777 break; /* It has booted */
778 udelay(100);
779 /*
780 * Allow other tasks to run while we wait for the
781 * AP to come online. This also gives a chance
782 * for the MTRR work(triggered by the AP coming online)
783 * to be completed in the stop machine context.
784 */
785 schedule();
786 }
787
788 if (cpumask_test_cpu(cpu, cpu_callin_mask))
789 pr_debug("CPU%d: has booted.\n", cpu);
790 else {
791 boot_error = 1;
792 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
793 == 0xA5A5A5A5)
794 /* trampoline started but...? */
795 pr_err("CPU%d: Stuck ??\n", cpu);
796 else
797 /* trampoline code not run */
798 pr_err("CPU%d: Not responding.\n", cpu);
799 if (apic->inquire_remote_apic)
800 apic->inquire_remote_apic(apicid);
801 }
802 }
803
804 if (boot_error) {
805 /* Try to put things back the way they were before ... */
806 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
807
808 /* was set by do_boot_cpu() */
809 cpumask_clear_cpu(cpu, cpu_callout_mask);
810
811 /* was set by cpu_init() */
812 cpumask_clear_cpu(cpu, cpu_initialized_mask);
813
814 set_cpu_present(cpu, false);
815 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
816 }
817
818 /* mark "stuck" area as not stuck */
819 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
820
821 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
822 /*
823 * Cleanup possible dangling ends...
824 */
825 smpboot_restore_warm_reset_vector();
826 }
827
828 destroy_work_on_stack(&c_idle.work);
829 return boot_error;
830}
831
832int __cpuinit native_cpu_up(unsigned int cpu)
833{
834 int apicid = apic->cpu_present_to_apicid(cpu);
835 unsigned long flags;
836 int err;
837
838 WARN_ON(irqs_disabled());
839
840 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
841
842 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
843 !physid_isset(apicid, phys_cpu_present_map)) {
844 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
845 return -EINVAL;
846 }
847
848 /*
849 * Already booted CPU?
850 */
851 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
852 pr_debug("do_boot_cpu %d Already started\n", cpu);
853 return -ENOSYS;
854 }
855
856 /*
857 * Save current MTRR state in case it was changed since early boot
858 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
859 */
860 mtrr_save_state();
861
862 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
863
864 err = do_boot_cpu(apicid, cpu);
865 if (err) {
866 pr_debug("do_boot_cpu failed %d\n", err);
867 return -EIO;
868 }
869
870 /*
871 * Check TSC synchronization with the AP (keep irqs disabled
872 * while doing so):
873 */
874 local_irq_save(flags);
875 check_tsc_sync_source(cpu);
876 local_irq_restore(flags);
877
878 while (!cpu_online(cpu)) {
879 cpu_relax();
880 touch_nmi_watchdog();
881 }
882
883 return 0;
884}
885
886/**
887 * arch_disable_smp_support() - disables SMP support for x86 at runtime
888 */
889void arch_disable_smp_support(void)
890{
891 disable_ioapic_support();
892}
893
894/*
895 * Fall back to non SMP mode after errors.
896 *
897 * RED-PEN audit/test this more. I bet there is more state messed up here.
898 */
899static __init void disable_smp(void)
900{
901 init_cpu_present(cpumask_of(0));
902 init_cpu_possible(cpumask_of(0));
903 smpboot_clear_io_apic_irqs();
904
905 if (smp_found_config)
906 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
907 else
908 physid_set_mask_of_physid(0, &phys_cpu_present_map);
909 cpumask_set_cpu(0, cpu_sibling_mask(0));
910 cpumask_set_cpu(0, cpu_core_mask(0));
911}
912
913/*
914 * Various sanity checks.
915 */
916static int __init smp_sanity_check(unsigned max_cpus)
917{
918 preempt_disable();
919
920#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
921 if (def_to_bigsmp && nr_cpu_ids > 8) {
922 unsigned int cpu;
923 unsigned nr;
924
925 printk(KERN_WARNING
926 "More than 8 CPUs detected - skipping them.\n"
927 "Use CONFIG_X86_BIGSMP.\n");
928
929 nr = 0;
930 for_each_present_cpu(cpu) {
931 if (nr >= 8)
932 set_cpu_present(cpu, false);
933 nr++;
934 }
935
936 nr = 0;
937 for_each_possible_cpu(cpu) {
938 if (nr >= 8)
939 set_cpu_possible(cpu, false);
940 nr++;
941 }
942
943 nr_cpu_ids = 8;
944 }
945#endif
946
947 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
948 printk(KERN_WARNING
949 "weird, boot CPU (#%d) not listed by the BIOS.\n",
950 hard_smp_processor_id());
951
952 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
953 }
954
955 /*
956 * If we couldn't find an SMP configuration at boot time,
957 * get out of here now!
958 */
959 if (!smp_found_config && !acpi_lapic) {
960 preempt_enable();
961 printk(KERN_NOTICE "SMP motherboard not detected.\n");
962 disable_smp();
963 if (APIC_init_uniprocessor())
964 printk(KERN_NOTICE "Local APIC not detected."
965 " Using dummy APIC emulation.\n");
966 return -1;
967 }
968
969 /*
970 * Should not be necessary because the MP table should list the boot
971 * CPU too, but we do it for the sake of robustness anyway.
972 */
973 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
974 printk(KERN_NOTICE
975 "weird, boot CPU (#%d) not listed by the BIOS.\n",
976 boot_cpu_physical_apicid);
977 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
978 }
979 preempt_enable();
980
981 /*
982 * If we couldn't find a local APIC, then get out of here now!
983 */
984 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
985 !cpu_has_apic) {
986 if (!disable_apic) {
987 pr_err("BIOS bug, local APIC #%d not detected!...\n",
988 boot_cpu_physical_apicid);
989 pr_err("... forcing use of dummy APIC emulation."
990 "(tell your hw vendor)\n");
991 }
992 smpboot_clear_io_apic();
993 disable_ioapic_support();
994 return -1;
995 }
996
997 verify_local_APIC();
998
999 /*
1000 * If SMP should be disabled, then really disable it!
1001 */
1002 if (!max_cpus) {
1003 printk(KERN_INFO "SMP mode deactivated.\n");
1004 smpboot_clear_io_apic();
1005
1006 connect_bsp_APIC();
1007 setup_local_APIC();
1008 bsp_end_local_APIC_setup();
1009 return -1;
1010 }
1011
1012 return 0;
1013}
1014
1015static void __init smp_cpu_index_default(void)
1016{
1017 int i;
1018 struct cpuinfo_x86 *c;
1019
1020 for_each_possible_cpu(i) {
1021 c = &cpu_data(i);
1022 /* mark all to hotplug */
1023 c->cpu_index = nr_cpu_ids;
1024 }
1025}
1026
1027/*
1028 * Prepare for SMP bootup. The MP table or ACPI has been read
1029 * earlier. Just do some sanity checking here and enable APIC mode.
1030 */
1031void __init native_smp_prepare_cpus(unsigned int max_cpus)
1032{
1033 unsigned int i;
1034
1035 preempt_disable();
1036 smp_cpu_index_default();
1037
1038 /*
1039 * Setup boot CPU information
1040 */
1041 smp_store_cpu_info(0); /* Final full version of the data */
1042 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1043 mb();
1044
1045 current_thread_info()->cpu = 0; /* needed? */
1046 for_each_possible_cpu(i) {
1047 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1048 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1049 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1050 }
1051 set_cpu_sibling_map(0);
1052
1053
1054 if (smp_sanity_check(max_cpus) < 0) {
1055 printk(KERN_INFO "SMP disabled\n");
1056 disable_smp();
1057 goto out;
1058 }
1059
1060 default_setup_apic_routing();
1061
1062 preempt_disable();
1063 if (read_apic_id() != boot_cpu_physical_apicid) {
1064 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1065 read_apic_id(), boot_cpu_physical_apicid);
1066 /* Or can we switch back to PIC here? */
1067 }
1068 preempt_enable();
1069
1070 connect_bsp_APIC();
1071
1072 /*
1073 * Switch from PIC to APIC mode.
1074 */
1075 setup_local_APIC();
1076
1077 /*
1078 * Enable IO APIC before setting up error vector
1079 */
1080 if (!skip_ioapic_setup && nr_ioapics)
1081 enable_IO_APIC();
1082
1083 bsp_end_local_APIC_setup();
1084
1085 if (apic->setup_portio_remap)
1086 apic->setup_portio_remap();
1087
1088 smpboot_setup_io_apic();
1089 /*
1090 * Set up local APIC timer on boot CPU.
1091 */
1092
1093 printk(KERN_INFO "CPU%d: ", 0);
1094 print_cpu_info(&cpu_data(0));
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 if (is_uv_system())
1098 uv_system_init();
1099
1100 set_mtrr_aps_delayed_init();
1101out:
1102 preempt_enable();
1103}
1104
1105void arch_disable_nonboot_cpus_begin(void)
1106{
1107 /*
1108 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1109 * In the suspend path, we will be back in the SMP mode shortly anyways.
1110 */
1111 skip_smp_alternatives = true;
1112}
1113
1114void arch_disable_nonboot_cpus_end(void)
1115{
1116 skip_smp_alternatives = false;
1117}
1118
1119void arch_enable_nonboot_cpus_begin(void)
1120{
1121 set_mtrr_aps_delayed_init();
1122}
1123
1124void arch_enable_nonboot_cpus_end(void)
1125{
1126 mtrr_aps_init();
1127}
1128
1129/*
1130 * Early setup to make printk work.
1131 */
1132void __init native_smp_prepare_boot_cpu(void)
1133{
1134 int me = smp_processor_id();
1135 switch_to_new_gdt(me);
1136 /* already set me in cpu_online_mask in boot_cpu_init() */
1137 cpumask_set_cpu(me, cpu_callout_mask);
1138 per_cpu(cpu_state, me) = CPU_ONLINE;
1139}
1140
1141void __init native_smp_cpus_done(unsigned int max_cpus)
1142{
1143 pr_debug("Boot done.\n");
1144
1145 impress_friends();
1146#ifdef CONFIG_X86_IO_APIC
1147 setup_ioapic_dest();
1148#endif
1149 mtrr_aps_init();
1150}
1151
1152static int __initdata setup_possible_cpus = -1;
1153static int __init _setup_possible_cpus(char *str)
1154{
1155 get_option(&str, &setup_possible_cpus);
1156 return 0;
1157}
1158early_param("possible_cpus", _setup_possible_cpus);
1159
1160
1161/*
1162 * cpu_possible_mask should be static, it cannot change as cpu's
1163 * are onlined, or offlined. The reason is per-cpu data-structures
1164 * are allocated by some modules at init time, and dont expect to
1165 * do this dynamically on cpu arrival/departure.
1166 * cpu_present_mask on the other hand can change dynamically.
1167 * In case when cpu_hotplug is not compiled, then we resort to current
1168 * behaviour, which is cpu_possible == cpu_present.
1169 * - Ashok Raj
1170 *
1171 * Three ways to find out the number of additional hotplug CPUs:
1172 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1173 * - The user can overwrite it with possible_cpus=NUM
1174 * - Otherwise don't reserve additional CPUs.
1175 * We do this because additional CPUs waste a lot of memory.
1176 * -AK
1177 */
1178__init void prefill_possible_map(void)
1179{
1180 int i, possible;
1181
1182 /* no processor from mptable or madt */
1183 if (!num_processors)
1184 num_processors = 1;
1185
1186 i = setup_max_cpus ?: 1;
1187 if (setup_possible_cpus == -1) {
1188 possible = num_processors;
1189#ifdef CONFIG_HOTPLUG_CPU
1190 if (setup_max_cpus)
1191 possible += disabled_cpus;
1192#else
1193 if (possible > i)
1194 possible = i;
1195#endif
1196 } else
1197 possible = setup_possible_cpus;
1198
1199 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1200
1201 /* nr_cpu_ids could be reduced via nr_cpus= */
1202 if (possible > nr_cpu_ids) {
1203 printk(KERN_WARNING
1204 "%d Processors exceeds NR_CPUS limit of %d\n",
1205 possible, nr_cpu_ids);
1206 possible = nr_cpu_ids;
1207 }
1208
1209#ifdef CONFIG_HOTPLUG_CPU
1210 if (!setup_max_cpus)
1211#endif
1212 if (possible > i) {
1213 printk(KERN_WARNING
1214 "%d Processors exceeds max_cpus limit of %u\n",
1215 possible, setup_max_cpus);
1216 possible = i;
1217 }
1218
1219 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1220 possible, max_t(int, possible - num_processors, 0));
1221
1222 for (i = 0; i < possible; i++)
1223 set_cpu_possible(i, true);
1224 for (; i < NR_CPUS; i++)
1225 set_cpu_possible(i, false);
1226
1227 nr_cpu_ids = possible;
1228}
1229
1230#ifdef CONFIG_HOTPLUG_CPU
1231
1232static void remove_siblinginfo(int cpu)
1233{
1234 int sibling;
1235 struct cpuinfo_x86 *c = &cpu_data(cpu);
1236
1237 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1238 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1239 /*/
1240 * last thread sibling in this cpu core going down
1241 */
1242 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1243 cpu_data(sibling).booted_cores--;
1244 }
1245
1246 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1247 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1248 cpumask_clear(cpu_sibling_mask(cpu));
1249 cpumask_clear(cpu_core_mask(cpu));
1250 c->phys_proc_id = 0;
1251 c->cpu_core_id = 0;
1252 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1253}
1254
1255static void __ref remove_cpu_from_maps(int cpu)
1256{
1257 set_cpu_online(cpu, false);
1258 cpumask_clear_cpu(cpu, cpu_callout_mask);
1259 cpumask_clear_cpu(cpu, cpu_callin_mask);
1260 /* was set by cpu_init() */
1261 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1262 numa_remove_cpu(cpu);
1263}
1264
1265void cpu_disable_common(void)
1266{
1267 int cpu = smp_processor_id();
1268
1269 remove_siblinginfo(cpu);
1270
1271 /* It's now safe to remove this processor from the online map */
1272 lock_vector_lock();
1273 remove_cpu_from_maps(cpu);
1274 unlock_vector_lock();
1275 fixup_irqs();
1276}
1277
1278int native_cpu_disable(void)
1279{
1280 int cpu = smp_processor_id();
1281
1282 /*
1283 * Perhaps use cpufreq to drop frequency, but that could go
1284 * into generic code.
1285 *
1286 * We won't take down the boot processor on i386 due to some
1287 * interrupts only being able to be serviced by the BSP.
1288 * Especially so if we're not using an IOAPIC -zwane
1289 */
1290 if (cpu == 0)
1291 return -EBUSY;
1292
1293 clear_local_APIC();
1294
1295 cpu_disable_common();
1296 return 0;
1297}
1298
1299void native_cpu_die(unsigned int cpu)
1300{
1301 /* We don't do anything here: idle task is faking death itself. */
1302 unsigned int i;
1303
1304 for (i = 0; i < 10; i++) {
1305 /* They ack this in play_dead by setting CPU_DEAD */
1306 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1307 if (system_state == SYSTEM_RUNNING)
1308 pr_info("CPU %u is now offline\n", cpu);
1309
1310 if (1 == num_online_cpus())
1311 alternatives_smp_switch(0);
1312 return;
1313 }
1314 msleep(100);
1315 }
1316 pr_err("CPU %u didn't die...\n", cpu);
1317}
1318
1319void play_dead_common(void)
1320{
1321 idle_task_exit();
1322 reset_lazy_tlbstate();
1323 amd_e400_remove_cpu(raw_smp_processor_id());
1324
1325 mb();
1326 /* Ack it */
1327 __this_cpu_write(cpu_state, CPU_DEAD);
1328
1329 /*
1330 * With physical CPU hotplug, we should halt the cpu
1331 */
1332 local_irq_disable();
1333}
1334
1335/*
1336 * We need to flush the caches before going to sleep, lest we have
1337 * dirty data in our caches when we come back up.
1338 */
1339static inline void mwait_play_dead(void)
1340{
1341 unsigned int eax, ebx, ecx, edx;
1342 unsigned int highest_cstate = 0;
1343 unsigned int highest_subcstate = 0;
1344 int i;
1345 void *mwait_ptr;
1346 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1347
1348 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1349 return;
1350 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1351 return;
1352 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1353 return;
1354
1355 eax = CPUID_MWAIT_LEAF;
1356 ecx = 0;
1357 native_cpuid(&eax, &ebx, &ecx, &edx);
1358
1359 /*
1360 * eax will be 0 if EDX enumeration is not valid.
1361 * Initialized below to cstate, sub_cstate value when EDX is valid.
1362 */
1363 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1364 eax = 0;
1365 } else {
1366 edx >>= MWAIT_SUBSTATE_SIZE;
1367 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1368 if (edx & MWAIT_SUBSTATE_MASK) {
1369 highest_cstate = i;
1370 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1371 }
1372 }
1373 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1374 (highest_subcstate - 1);
1375 }
1376
1377 /*
1378 * This should be a memory location in a cache line which is
1379 * unlikely to be touched by other processors. The actual
1380 * content is immaterial as it is not actually modified in any way.
1381 */
1382 mwait_ptr = ¤t_thread_info()->flags;
1383
1384 wbinvd();
1385
1386 while (1) {
1387 /*
1388 * The CLFLUSH is a workaround for erratum AAI65 for
1389 * the Xeon 7400 series. It's not clear it is actually
1390 * needed, but it should be harmless in either case.
1391 * The WBINVD is insufficient due to the spurious-wakeup
1392 * case where we return around the loop.
1393 */
1394 clflush(mwait_ptr);
1395 __monitor(mwait_ptr, 0, 0);
1396 mb();
1397 __mwait(eax, 0);
1398 }
1399}
1400
1401static inline void hlt_play_dead(void)
1402{
1403 if (__this_cpu_read(cpu_info.x86) >= 4)
1404 wbinvd();
1405
1406 while (1) {
1407 native_halt();
1408 }
1409}
1410
1411void native_play_dead(void)
1412{
1413 play_dead_common();
1414 tboot_shutdown(TB_SHUTDOWN_WFS);
1415
1416 mwait_play_dead(); /* Only returns on failure */
1417 hlt_play_dead();
1418}
1419
1420#else /* ... !CONFIG_HOTPLUG_CPU */
1421int native_cpu_disable(void)
1422{
1423 return -ENOSYS;
1424}
1425
1426void native_cpu_die(unsigned int cpu)
1427{
1428 /* We said "no" in __cpu_disable */
1429 BUG();
1430}
1431
1432void native_play_dead(void)
1433{
1434 BUG();
1435}
1436
1437#endif