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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2007 MIPS Technologies, Inc.
5 * Chris Dearman (chris@mips.com)
6 */
7
8#undef DEBUG
9
10#include <linux/kernel.h>
11#include <linux/sched/task_stack.h>
12#include <linux/smp.h>
13#include <linux/cpumask.h>
14#include <linux/interrupt.h>
15#include <linux/compiler.h>
16
17#include <linux/atomic.h>
18#include <asm/cacheflush.h>
19#include <asm/cpu.h>
20#include <asm/processor.h>
21#include <asm/hardirq.h>
22#include <asm/mmu_context.h>
23#include <asm/smp.h>
24#include <asm/time.h>
25#include <asm/mipsregs.h>
26#include <asm/mipsmtregs.h>
27#include <asm/mips_mt.h>
28#include <asm/amon.h>
29
30static void cmp_init_secondary(void)
31{
32 struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data;
33
34 /* Assume GIC is present */
35 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
36 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
37
38 /* Enable per-cpu interrupts: platform specific */
39
40#ifdef CONFIG_MIPS_MT_SMP
41 if (cpu_has_mipsmt)
42 cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
43 TCBIND_CURVPE);
44#endif
45}
46
47static void cmp_smp_finish(void)
48{
49 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
50
51 /* CDFIXME: remove this? */
52 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
53
54#ifdef CONFIG_MIPS_MT_FPAFF
55 /* If we have an FPU, enroll ourselves in the FPU-full mask */
56 if (cpu_has_fpu)
57 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
58#endif /* CONFIG_MIPS_MT_FPAFF */
59
60 local_irq_enable();
61}
62
63/*
64 * Setup the PC, SP, and GP of a secondary processor and start it running
65 * smp_bootstrap is the place to resume from
66 * __KSTK_TOS(idle) is apparently the stack pointer
67 * (unsigned long)idle->thread_info the gp
68 */
69static int cmp_boot_secondary(int cpu, struct task_struct *idle)
70{
71 struct thread_info *gp = task_thread_info(idle);
72 unsigned long sp = __KSTK_TOS(idle);
73 unsigned long pc = (unsigned long)&smp_bootstrap;
74 unsigned long a0 = 0;
75
76 pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
77 __func__, cpu);
78
79#if 0
80 /* Needed? */
81 flush_icache_range((unsigned long)gp,
82 (unsigned long)(gp + sizeof(struct thread_info)));
83#endif
84
85 amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
86 return 0;
87}
88
89/*
90 * Common setup before any secondaries are started
91 */
92void __init cmp_smp_setup(void)
93{
94 int i;
95 int ncpu = 0;
96
97 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
98
99#ifdef CONFIG_MIPS_MT_FPAFF
100 /* If we have an FPU, enroll ourselves in the FPU-full mask */
101 if (cpu_has_fpu)
102 cpumask_set_cpu(0, &mt_fpu_cpumask);
103#endif /* CONFIG_MIPS_MT_FPAFF */
104
105 for (i = 1; i < NR_CPUS; i++) {
106 if (amon_cpu_avail(i)) {
107 set_cpu_possible(i, true);
108 __cpu_number_map[i] = ++ncpu;
109 __cpu_logical_map[ncpu] = i;
110 }
111 }
112
113 if (cpu_has_mipsmt) {
114 unsigned int nvpe = 1;
115#ifdef CONFIG_MIPS_MT_SMP
116 unsigned int mvpconf0 = read_c0_mvpconf0();
117
118 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
119#endif
120 smp_num_siblings = nvpe;
121 }
122 pr_info("Detected %i available secondary CPU(s)\n", ncpu);
123}
124
125void __init cmp_prepare_cpus(unsigned int max_cpus)
126{
127 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
128 smp_processor_id(), __func__, max_cpus);
129
130#ifdef CONFIG_MIPS_MT
131 /*
132 * FIXME: some of these options are per-system, some per-core and
133 * some per-cpu
134 */
135 mips_mt_set_cpuoptions();
136#endif
137
138}
139
140const struct plat_smp_ops cmp_smp_ops = {
141 .send_ipi_single = mips_smp_send_ipi_single,
142 .send_ipi_mask = mips_smp_send_ipi_mask,
143 .init_secondary = cmp_init_secondary,
144 .smp_finish = cmp_smp_finish,
145 .boot_secondary = cmp_boot_secondary,
146 .smp_setup = cmp_smp_setup,
147 .prepare_cpus = cmp_prepare_cpus,
148};
1/*
2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
9 * for more details.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 *
15 * Copyright (C) 2007 MIPS Technologies, Inc.
16 * Chris Dearman (chris@mips.com)
17 */
18
19#undef DEBUG
20
21#include <linux/kernel.h>
22#include <linux/sched.h>
23#include <linux/smp.h>
24#include <linux/cpumask.h>
25#include <linux/interrupt.h>
26#include <linux/compiler.h>
27
28#include <linux/atomic.h>
29#include <asm/cacheflush.h>
30#include <asm/cpu.h>
31#include <asm/processor.h>
32#include <asm/system.h>
33#include <asm/hardirq.h>
34#include <asm/mmu_context.h>
35#include <asm/smp.h>
36#include <asm/time.h>
37#include <asm/mipsregs.h>
38#include <asm/mipsmtregs.h>
39#include <asm/mips_mt.h>
40#include <asm/amon.h>
41#include <asm/gic.h>
42
43static void ipi_call_function(unsigned int cpu)
44{
45 pr_debug("CPU%d: %s cpu %d status %08x\n",
46 smp_processor_id(), __func__, cpu, read_c0_status());
47
48 gic_send_ipi(plat_ipi_call_int_xlate(cpu));
49}
50
51
52static void ipi_resched(unsigned int cpu)
53{
54 pr_debug("CPU%d: %s cpu %d status %08x\n",
55 smp_processor_id(), __func__, cpu, read_c0_status());
56
57 gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
58}
59
60/*
61 * FIXME: This isn't restricted to CMP
62 * The SMVP kernel could use GIC interrupts if available
63 */
64void cmp_send_ipi_single(int cpu, unsigned int action)
65{
66 unsigned long flags;
67
68 local_irq_save(flags);
69
70 switch (action) {
71 case SMP_CALL_FUNCTION:
72 ipi_call_function(cpu);
73 break;
74
75 case SMP_RESCHEDULE_YOURSELF:
76 ipi_resched(cpu);
77 break;
78 }
79
80 local_irq_restore(flags);
81}
82
83static void cmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
84{
85 unsigned int i;
86
87 for_each_cpu(i, mask)
88 cmp_send_ipi_single(i, action);
89}
90
91static void cmp_init_secondary(void)
92{
93 struct cpuinfo_mips *c = ¤t_cpu_data;
94
95 /* Assume GIC is present */
96 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
97 STATUSF_IP7);
98
99 /* Enable per-cpu interrupts: platform specific */
100
101 c->core = (read_c0_ebase() >> 1) & 0xff;
102#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
103 c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
104#endif
105#ifdef CONFIG_MIPS_MT_SMTC
106 c->tc_id = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC;
107#endif
108}
109
110static void cmp_smp_finish(void)
111{
112 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
113
114 /* CDFIXME: remove this? */
115 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
116
117#ifdef CONFIG_MIPS_MT_FPAFF
118 /* If we have an FPU, enroll ourselves in the FPU-full mask */
119 if (cpu_has_fpu)
120 cpu_set(smp_processor_id(), mt_fpu_cpumask);
121#endif /* CONFIG_MIPS_MT_FPAFF */
122
123 local_irq_enable();
124}
125
126static void cmp_cpus_done(void)
127{
128 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
129}
130
131/*
132 * Setup the PC, SP, and GP of a secondary processor and start it running
133 * smp_bootstrap is the place to resume from
134 * __KSTK_TOS(idle) is apparently the stack pointer
135 * (unsigned long)idle->thread_info the gp
136 */
137static void cmp_boot_secondary(int cpu, struct task_struct *idle)
138{
139 struct thread_info *gp = task_thread_info(idle);
140 unsigned long sp = __KSTK_TOS(idle);
141 unsigned long pc = (unsigned long)&smp_bootstrap;
142 unsigned long a0 = 0;
143
144 pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
145 __func__, cpu);
146
147#if 0
148 /* Needed? */
149 flush_icache_range((unsigned long)gp,
150 (unsigned long)(gp + sizeof(struct thread_info)));
151#endif
152
153 amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
154}
155
156/*
157 * Common setup before any secondaries are started
158 */
159void __init cmp_smp_setup(void)
160{
161 int i;
162 int ncpu = 0;
163
164 pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
165
166#ifdef CONFIG_MIPS_MT_FPAFF
167 /* If we have an FPU, enroll ourselves in the FPU-full mask */
168 if (cpu_has_fpu)
169 cpu_set(0, mt_fpu_cpumask);
170#endif /* CONFIG_MIPS_MT_FPAFF */
171
172 for (i = 1; i < NR_CPUS; i++) {
173 if (amon_cpu_avail(i)) {
174 set_cpu_possible(i, true);
175 __cpu_number_map[i] = ++ncpu;
176 __cpu_logical_map[ncpu] = i;
177 }
178 }
179
180 if (cpu_has_mipsmt) {
181 unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
182
183 nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
184 smp_num_siblings = nvpe;
185 }
186 pr_info("Detected %i available secondary CPU(s)\n", ncpu);
187}
188
189void __init cmp_prepare_cpus(unsigned int max_cpus)
190{
191 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
192 smp_processor_id(), __func__, max_cpus);
193
194 /*
195 * FIXME: some of these options are per-system, some per-core and
196 * some per-cpu
197 */
198 mips_mt_set_cpuoptions();
199}
200
201struct plat_smp_ops cmp_smp_ops = {
202 .send_ipi_single = cmp_send_ipi_single,
203 .send_ipi_mask = cmp_send_ipi_mask,
204 .init_secondary = cmp_init_secondary,
205 .smp_finish = cmp_smp_finish,
206 .cpus_done = cmp_cpus_done,
207 .boot_secondary = cmp_boot_secondary,
208 .smp_setup = cmp_smp_setup,
209 .prepare_cpus = cmp_prepare_cpus,
210};