1/*
  2 *  linux/arch/m32r/platforms/mappi3/setup.c
  3 *
  4 *  Setup routines for Renesas MAPPI-III(M3A-2170) Board
  5 *
  6 *  Copyright (c) 2001-2005  Hiroyuki Kondo, Hirokazu Takata,
  7 *                           Hitoshi Yamamoto, Mamoru Sakugawa
  8 */
  9
 10#include <linux/irq.h>
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13#include <linux/platform_device.h>
 14
 15#include <asm/system.h>
 16#include <asm/m32r.h>
 17#include <asm/io.h>
 18
 19#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
 20
 21icu_data_t icu_data[NR_IRQS];
 22
 23static void disable_mappi3_irq(unsigned int irq)
 24{
 25	unsigned long port, data;
 26
 27	if ((irq == 0) ||(irq >= NR_IRQS))  {
 28		printk("bad irq 0x%08x\n", irq);
 29		return;
 30	}
 31	port = irq2port(irq);
 32	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
 33	outl(data, port);
 34}
 35
 36static void enable_mappi3_irq(unsigned int irq)
 37{
 38	unsigned long port, data;
 39
 40	if ((irq == 0) ||(irq >= NR_IRQS))  {
 41		printk("bad irq 0x%08x\n", irq);
 42		return;
 43	}
 44	port = irq2port(irq);
 45	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
 46	outl(data, port);
 47}
 48
 49static void mask_mappi3(struct irq_data *data)
 50{
 51	disable_mappi3_irq(data->irq);
 52}
 53
 54static void unmask_mappi3(struct irq_data *data)
 55{
 56	enable_mappi3_irq(data->irq);
 57}
 58
 59static void shutdown_mappi3(struct irq_data *data)
 60{
 61	unsigned long port;
 62
 63	port = irq2port(data->irq);
 64	outl(M32R_ICUCR_ILEVEL7, port);
 65}
 66
 67static struct irq_chip mappi3_irq_type = {
 68	.name		= "MAPPI3-IRQ",
 69	.irq_shutdown	= shutdown_mappi3,
 70	.irq_mask	= mask_mappi3,
 71	.irq_unmask	= unmask_mappi3,
 72};
 73
 74void __init init_IRQ(void)
 75{
 76#if defined(CONFIG_SMC91X)
 77	/* INT0 : LAN controller (SMC91111) */
 78	irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
 79				 handle_level_irq);
 80	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 81	disable_mappi3_irq(M32R_IRQ_INT0);
 82#endif  /* CONFIG_SMC91X */
 83
 84	/* MFT2 : system timer */
 85	irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
 86				 handle_level_irq);
 87	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 88	disable_mappi3_irq(M32R_IRQ_MFT2);
 89
 90#ifdef CONFIG_SERIAL_M32R_SIO
 91	/* SIO0_R : uart receive data */
 92	irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
 93				 handle_level_irq);
 94	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 95	disable_mappi3_irq(M32R_IRQ_SIO0_R);
 96
 97	/* SIO0_S : uart send data */
 98	irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
 99				 handle_level_irq);
100	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
101	disable_mappi3_irq(M32R_IRQ_SIO0_S);
102	/* SIO1_R : uart receive data */
103	irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
104				 handle_level_irq);
105	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
106	disable_mappi3_irq(M32R_IRQ_SIO1_R);
107
108	/* SIO1_S : uart send data */
109	irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
110				 handle_level_irq);
111	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
112	disable_mappi3_irq(M32R_IRQ_SIO1_S);
113#endif  /* CONFIG_M32R_USE_DBG_CONSOLE */
114
115#if defined(CONFIG_USB)
116	/* INT1 : USB Host controller interrupt */
117	irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
118				 handle_level_irq);
119	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
120	disable_mappi3_irq(M32R_IRQ_INT1);
121#endif /* CONFIG_USB */
122
123	/* CFC IREQ */
124	irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
125				 handle_level_irq);
126	icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
127	disable_mappi3_irq(PLD_IRQ_CFIREQ);
128
129#if defined(CONFIG_M32R_CFC)
130	/* ICUCR41: CFC Insert & eject */
131	irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
132				 handle_level_irq);
133	icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
134	disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
135
136#endif /* CONFIG_M32R_CFC */
137
138	/* IDE IREQ */
139	irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
140				 handle_level_irq);
141	icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
142	disable_mappi3_irq(PLD_IRQ_IDEIREQ);
143
144}
145
146#if defined(CONFIG_SMC91X)
147
148#define LAN_IOSTART     0x300
149#define LAN_IOEND       0x320
150static struct resource smc91x_resources[] = {
151	[0] = {
152		.start  = (LAN_IOSTART),
153		.end    = (LAN_IOEND),
154		.flags  = IORESOURCE_MEM,
155	},
156	[1] = {
157		.start  = M32R_IRQ_INT0,
158		.end    = M32R_IRQ_INT0,
159		.flags  = IORESOURCE_IRQ,
160	}
161};
162
163static struct platform_device smc91x_device = {
164	.name		= "smc91x",
165	.id		= 0,
166	.num_resources  = ARRAY_SIZE(smc91x_resources),
167	.resource       = smc91x_resources,
168};
169
170#endif
171
172#if defined(CONFIG_FB_S1D13XXX)
173
174#include <video/s1d13xxxfb.h>
175#include <asm/s1d13806.h>
176
177static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
178	.initregs		= s1d13xxxfb_initregs,
179	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
180	.platform_init_video	= NULL,
181#ifdef CONFIG_PM
182	.platform_suspend_video	= NULL,
183	.platform_resume_video	= NULL,
184#endif
185};
186
187static struct resource s1d13xxxfb_resources[] = {
188	[0] = {
189		.start  = 0x1d600000UL,
190		.end    = 0x1d73FFFFUL,
191		.flags  = IORESOURCE_MEM,
192	},
193	[1] = {
194		.start  = 0x1d400000UL,
195		.end    = 0x1d4001FFUL,
196		.flags  = IORESOURCE_MEM,
197	}
198};
199
200static struct platform_device s1d13xxxfb_device = {
201	.name		= S1D_DEVICENAME,
202	.id		= 0,
203	.dev            = {
204		.platform_data  = &s1d13xxxfb_data,
205	},
206	.num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
207	.resource       = s1d13xxxfb_resources,
208};
209#endif
210
211static int __init platform_init(void)
212{
213#if defined(CONFIG_SMC91X)
214	platform_device_register(&smc91x_device);
215#endif
216#if defined(CONFIG_FB_S1D13XXX)
217	platform_device_register(&s1d13xxxfb_device);
218#endif
219	return 0;
220}
221arch_initcall(platform_init);