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1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include <linux/bitfield.h>
29#include <linux/bits.h>
30
31/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * Layout
38 * ~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119/**
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
122 *
123 * Local wrapper for BIT() to force u32, with compile time checks.
124 *
125 * @return: Value with bit @__n set.
126 */
127#define REG_BIT(__n) \
128 ((u32)(BIT(__n) + \
129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
130 ((__n) < 0 || (__n) > 31))))
131
132/**
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
136 *
137 * Local wrapper for GENMASK() to force u32, with compile time checks.
138 *
139 * @return: Continuous bitmask from @__high to @__low, inclusive.
140 */
141#define REG_GENMASK(__high, __low) \
142 ((u32)(GENMASK(__high, __low) + \
143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
144 __is_constexpr(__low) && \
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146
147/*
148 * Local integer constant expression version of is_power_of_2().
149 */
150#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
151
152/**
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
154 * @__mask: shifted mask defining the field's length and position
155 * @__val: value to put in the field
156 *
157 * Local copy of FIELD_PREP() to generate an integer constant expression, force
158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
159 *
160 * @return: @__val masked and shifted into the field defined by @__mask.
161 */
162#define REG_FIELD_PREP(__mask, __val) \
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
168
169/**
170 * REG_FIELD_GET() - Extract a u32 bitfield value
171 * @__mask: shifted mask defining the field's length and position
172 * @__val: value to extract the bitfield value from
173 *
174 * Local wrapper for FIELD_GET() to force u32 and for consistency with
175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176 *
177 * @return: Masked and shifted value of the field defined by @__mask in @__val.
178 */
179#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
180
181typedef struct {
182 u32 reg;
183} i915_reg_t;
184
185#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186
187#define INVALID_MMIO_REG _MMIO(0)
188
189static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
190{
191 return reg.reg;
192}
193
194static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195{
196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197}
198
199static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200{
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202}
203
204#define VLV_DISPLAY_BASE 0x180000
205#define VLV_MIPI_BASE VLV_DISPLAY_BASE
206#define BXT_MIPI_BASE 0x60000
207
208#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
209
210/*
211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212 * numbers, pick the 0-based __index'th value.
213 *
214 * Always prefer this over _PICK() if the numbers are evenly spaced.
215 */
216#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
217
218/*
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
220 *
221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
222 */
223#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
224
225/*
226 * Named helper wrappers around _PICK_EVEN() and _PICK().
227 */
228#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
229#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
230#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
231#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
232#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
233
234#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
235#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
236#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
237#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
238#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
239
240#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
241
242#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
243#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
244#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
245#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
246
247/*
248 * Device info offset array based helpers for groups of registers with unevenly
249 * spaced base offsets.
250 */
251#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
253 DISPLAY_MMIO_BASE(dev_priv))
254#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
255 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
256 DISPLAY_MMIO_BASE(dev_priv))
257#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
258#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
259 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
260 DISPLAY_MMIO_BASE(dev_priv))
261
262#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
263#define _MASKED_FIELD(mask, value) ({ \
264 if (__builtin_constant_p(mask)) \
265 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
266 if (__builtin_constant_p(value)) \
267 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
268 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
269 BUILD_BUG_ON_MSG((value) & ~(mask), \
270 "Incorrect value for mask"); \
271 __MASKED_FIELD(mask, value); })
272#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
273#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
274
275/* PCI config space */
276
277#define MCHBAR_I915 0x44
278#define MCHBAR_I965 0x48
279#define MCHBAR_SIZE (4 * 4096)
280
281#define DEVEN 0x54
282#define DEVEN_MCHBAR_EN (1 << 28)
283
284/* BSM in include/drm/i915_drm.h */
285
286#define HPLLCC 0xc0 /* 85x only */
287#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
288#define GC_CLOCK_133_200 (0 << 0)
289#define GC_CLOCK_100_200 (1 << 0)
290#define GC_CLOCK_100_133 (2 << 0)
291#define GC_CLOCK_133_266 (3 << 0)
292#define GC_CLOCK_133_200_2 (4 << 0)
293#define GC_CLOCK_133_266_2 (5 << 0)
294#define GC_CLOCK_166_266 (6 << 0)
295#define GC_CLOCK_166_250 (7 << 0)
296
297#define I915_GDRST 0xc0 /* PCI config register */
298#define GRDOM_FULL (0 << 2)
299#define GRDOM_RENDER (1 << 2)
300#define GRDOM_MEDIA (3 << 2)
301#define GRDOM_MASK (3 << 2)
302#define GRDOM_RESET_STATUS (1 << 1)
303#define GRDOM_RESET_ENABLE (1 << 0)
304
305/* BSpec only has register offset, PCI device and bit found empirically */
306#define I830_CLOCK_GATE 0xc8 /* device 0 */
307#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
308
309#define GCDGMBUS 0xcc
310
311#define GCFGC2 0xda
312#define GCFGC 0xf0 /* 915+ only */
313#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
314#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
315#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
316#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
317#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
318#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
319#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
320#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
321#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
322#define GC_DISPLAY_CLOCK_MASK (7 << 4)
323#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
324#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
325#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
326#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
327#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
328#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
329#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
330#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
331#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
332#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
333#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
334#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
335#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
336#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
337#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
338#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
339#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
340#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
341#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
342
343#define ASLE 0xe4
344#define ASLS 0xfc
345
346#define SWSCI 0xe8
347#define SWSCI_SCISEL (1 << 15)
348#define SWSCI_GSSCIE (1 << 0)
349
350#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
351
352
353#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
354#define ILK_GRDOM_FULL (0 << 1)
355#define ILK_GRDOM_RENDER (1 << 1)
356#define ILK_GRDOM_MEDIA (3 << 1)
357#define ILK_GRDOM_MASK (3 << 1)
358#define ILK_GRDOM_RESET_ENABLE (1 << 0)
359
360#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
361#define GEN6_MBC_SNPCR_SHIFT 21
362#define GEN6_MBC_SNPCR_MASK (3 << 21)
363#define GEN6_MBC_SNPCR_MAX (0 << 21)
364#define GEN6_MBC_SNPCR_MED (1 << 21)
365#define GEN6_MBC_SNPCR_LOW (2 << 21)
366#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
367
368#define VLV_G3DCTL _MMIO(0x9024)
369#define VLV_GSCKGCTL _MMIO(0x9028)
370
371#define GEN6_MBCTL _MMIO(0x0907c)
372#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
373#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
374#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
375#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
376#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
377
378#define GEN6_GDRST _MMIO(0x941c)
379#define GEN6_GRDOM_FULL (1 << 0)
380#define GEN6_GRDOM_RENDER (1 << 1)
381#define GEN6_GRDOM_MEDIA (1 << 2)
382#define GEN6_GRDOM_BLT (1 << 3)
383#define GEN6_GRDOM_VECS (1 << 4)
384#define GEN9_GRDOM_GUC (1 << 5)
385#define GEN8_GRDOM_MEDIA2 (1 << 7)
386/* GEN11 changed all bit defs except for FULL & RENDER */
387#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
388#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
389#define GEN11_GRDOM_BLT (1 << 2)
390#define GEN11_GRDOM_GUC (1 << 3)
391#define GEN11_GRDOM_MEDIA (1 << 5)
392#define GEN11_GRDOM_MEDIA2 (1 << 6)
393#define GEN11_GRDOM_MEDIA3 (1 << 7)
394#define GEN11_GRDOM_MEDIA4 (1 << 8)
395#define GEN11_GRDOM_VECS (1 << 13)
396#define GEN11_GRDOM_VECS2 (1 << 14)
397#define GEN11_GRDOM_SFC0 (1 << 17)
398#define GEN11_GRDOM_SFC1 (1 << 18)
399
400#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
401#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
402
403#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
404#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
405#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
406#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
407#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
408
409#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
410#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
411#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
412#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
413#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
414#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
415
416#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
417#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
418#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
419#define PP_DIR_DCLV_2G 0xffffffff
420
421#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
422#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
423
424#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
425#define GEN8_RPCS_ENABLE (1 << 31)
426#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
427#define GEN8_RPCS_S_CNT_SHIFT 15
428#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
429#define GEN11_RPCS_S_CNT_SHIFT 12
430#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
431#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
432#define GEN8_RPCS_SS_CNT_SHIFT 8
433#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
434#define GEN8_RPCS_EU_MAX_SHIFT 4
435#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
436#define GEN8_RPCS_EU_MIN_SHIFT 0
437#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
438
439#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
440/* HSW only */
441#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
442#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
443#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
444#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
445/* HSW+ */
446#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
447#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
448#define HSW_RCS_INHIBIT (1 << 8)
449/* Gen8 */
450#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
451#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
452#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
453#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
454#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
455#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
456#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
457#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
458#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
459#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
460
461#define GAM_ECOCHK _MMIO(0x4090)
462#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
463#define ECOCHK_SNB_BIT (1 << 10)
464#define ECOCHK_DIS_TLB (1 << 8)
465#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
466#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
467#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
468#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
469#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
470#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
471#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
472#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
473
474#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
475
476#define GAC_ECO_BITS _MMIO(0x14090)
477#define ECOBITS_SNB_BIT (1 << 13)
478#define ECOBITS_PPGTT_CACHE64B (3 << 8)
479#define ECOBITS_PPGTT_CACHE4B (0 << 8)
480
481#define GAB_CTL _MMIO(0x24000)
482#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
483
484#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
485#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
486#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
487#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
488#define GEN6_STOLEN_RESERVED_1M (0 << 4)
489#define GEN6_STOLEN_RESERVED_512K (1 << 4)
490#define GEN6_STOLEN_RESERVED_256K (2 << 4)
491#define GEN6_STOLEN_RESERVED_128K (3 << 4)
492#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
493#define GEN7_STOLEN_RESERVED_1M (0 << 5)
494#define GEN7_STOLEN_RESERVED_256K (1 << 5)
495#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
496#define GEN8_STOLEN_RESERVED_1M (0 << 7)
497#define GEN8_STOLEN_RESERVED_2M (1 << 7)
498#define GEN8_STOLEN_RESERVED_4M (2 << 7)
499#define GEN8_STOLEN_RESERVED_8M (3 << 7)
500#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
501#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
502
503/* VGA stuff */
504
505#define VGA_ST01_MDA 0x3ba
506#define VGA_ST01_CGA 0x3da
507
508#define _VGA_MSR_WRITE _MMIO(0x3c2)
509#define VGA_MSR_WRITE 0x3c2
510#define VGA_MSR_READ 0x3cc
511#define VGA_MSR_MEM_EN (1 << 1)
512#define VGA_MSR_CGA_MODE (1 << 0)
513
514#define VGA_SR_INDEX 0x3c4
515#define SR01 1
516#define VGA_SR_DATA 0x3c5
517
518#define VGA_AR_INDEX 0x3c0
519#define VGA_AR_VID_EN (1 << 5)
520#define VGA_AR_DATA_WRITE 0x3c0
521#define VGA_AR_DATA_READ 0x3c1
522
523#define VGA_GR_INDEX 0x3ce
524#define VGA_GR_DATA 0x3cf
525/* GR05 */
526#define VGA_GR_MEM_READ_MODE_SHIFT 3
527#define VGA_GR_MEM_READ_MODE_PLANE 1
528/* GR06 */
529#define VGA_GR_MEM_MODE_MASK 0xc
530#define VGA_GR_MEM_MODE_SHIFT 2
531#define VGA_GR_MEM_A0000_AFFFF 0
532#define VGA_GR_MEM_A0000_BFFFF 1
533#define VGA_GR_MEM_B0000_B7FFF 2
534#define VGA_GR_MEM_B0000_BFFFF 3
535
536#define VGA_DACMASK 0x3c6
537#define VGA_DACRX 0x3c7
538#define VGA_DACWX 0x3c8
539#define VGA_DACDATA 0x3c9
540
541#define VGA_CR_INDEX_MDA 0x3b4
542#define VGA_CR_DATA_MDA 0x3b5
543#define VGA_CR_INDEX_CGA 0x3d4
544#define VGA_CR_DATA_CGA 0x3d5
545
546#define MI_PREDICATE_SRC0 _MMIO(0x2400)
547#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
548#define MI_PREDICATE_SRC1 _MMIO(0x2408)
549#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
550
551#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
552#define LOWER_SLICE_ENABLED (1 << 0)
553#define LOWER_SLICE_DISABLED (0 << 0)
554
555/*
556 * Registers used only by the command parser
557 */
558#define BCS_SWCTRL _MMIO(0x22200)
559
560/* There are 16 GPR registers */
561#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
562#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
563
564#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
565#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
566#define HS_INVOCATION_COUNT _MMIO(0x2300)
567#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
568#define DS_INVOCATION_COUNT _MMIO(0x2308)
569#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
570#define IA_VERTICES_COUNT _MMIO(0x2310)
571#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
572#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
573#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
574#define VS_INVOCATION_COUNT _MMIO(0x2320)
575#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
576#define GS_INVOCATION_COUNT _MMIO(0x2328)
577#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
578#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
579#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
580#define CL_INVOCATION_COUNT _MMIO(0x2338)
581#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
582#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
583#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
584#define PS_INVOCATION_COUNT _MMIO(0x2348)
585#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
586#define PS_DEPTH_COUNT _MMIO(0x2350)
587#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
588
589/* There are the 4 64-bit counter registers, one for each stream output */
590#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
591#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
592
593#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
594#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
595
596#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
597#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
598#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
599#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
600#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
601#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
602
603#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
604#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
605#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
606
607/* There are the 16 64-bit CS General Purpose Registers */
608#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
609#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
610
611#define GEN7_OACONTROL _MMIO(0x2360)
612#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
613#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
614#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
615#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
616#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
617#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
618#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
619#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
620#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
621#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
622#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
623#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
624#define GEN7_OACONTROL_FORMAT_SHIFT 2
625#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
626#define GEN7_OACONTROL_ENABLE (1 << 0)
627
628#define GEN8_OACTXID _MMIO(0x2364)
629
630#define GEN8_OA_DEBUG _MMIO(0x2B04)
631#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
632#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
633#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
634#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
635
636#define GEN8_OACONTROL _MMIO(0x2B00)
637#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
638#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
639#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
640#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
641#define GEN8_OA_REPORT_FORMAT_SHIFT 2
642#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
643#define GEN8_OA_COUNTER_ENABLE (1 << 0)
644
645#define GEN8_OACTXCONTROL _MMIO(0x2360)
646#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
647#define GEN8_OA_TIMER_PERIOD_SHIFT 2
648#define GEN8_OA_TIMER_ENABLE (1 << 1)
649#define GEN8_OA_COUNTER_RESUME (1 << 0)
650
651#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
652#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
653#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
654#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
655#define GEN7_OABUFFER_RESUME (1 << 0)
656
657#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
658#define GEN8_OABUFFER _MMIO(0x2b14)
659#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
660
661#define GEN7_OASTATUS1 _MMIO(0x2364)
662#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
663#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
664#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
665#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
666
667#define GEN7_OASTATUS2 _MMIO(0x2368)
668#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
669#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
670
671#define GEN8_OASTATUS _MMIO(0x2b08)
672#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
673#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
674#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
675#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
676
677#define GEN8_OAHEADPTR _MMIO(0x2B0C)
678#define GEN8_OAHEADPTR_MASK 0xffffffc0
679#define GEN8_OATAILPTR _MMIO(0x2B10)
680#define GEN8_OATAILPTR_MASK 0xffffffc0
681
682#define OABUFFER_SIZE_128K (0 << 3)
683#define OABUFFER_SIZE_256K (1 << 3)
684#define OABUFFER_SIZE_512K (2 << 3)
685#define OABUFFER_SIZE_1M (3 << 3)
686#define OABUFFER_SIZE_2M (4 << 3)
687#define OABUFFER_SIZE_4M (5 << 3)
688#define OABUFFER_SIZE_8M (6 << 3)
689#define OABUFFER_SIZE_16M (7 << 3)
690
691/*
692 * Flexible, Aggregate EU Counter Registers.
693 * Note: these aren't contiguous
694 */
695#define EU_PERF_CNTL0 _MMIO(0xe458)
696#define EU_PERF_CNTL1 _MMIO(0xe558)
697#define EU_PERF_CNTL2 _MMIO(0xe658)
698#define EU_PERF_CNTL3 _MMIO(0xe758)
699#define EU_PERF_CNTL4 _MMIO(0xe45c)
700#define EU_PERF_CNTL5 _MMIO(0xe55c)
701#define EU_PERF_CNTL6 _MMIO(0xe65c)
702
703/*
704 * OA Boolean state
705 */
706
707#define OASTARTTRIG1 _MMIO(0x2710)
708#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
709#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
710
711#define OASTARTTRIG2 _MMIO(0x2714)
712#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
713#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
714#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
715#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
716#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
717#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
718#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
719#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
720#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
721#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
722#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
723#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
724#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
725#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
726#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
727#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
728#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
729#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
730#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
731#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
732#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
733#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
734#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
735#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
736#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
737#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
738#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
739#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
740#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
741
742#define OASTARTTRIG3 _MMIO(0x2718)
743#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
744#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
745#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
746#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
747#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
748#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
749#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
750#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
751#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
752
753#define OASTARTTRIG4 _MMIO(0x271c)
754#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
755#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
756#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
757#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
758#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
759#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
760#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
761#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
762#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
763
764#define OASTARTTRIG5 _MMIO(0x2720)
765#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
766#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
767
768#define OASTARTTRIG6 _MMIO(0x2724)
769#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
770#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
771#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
772#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
773#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
774#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
775#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
776#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
777#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
778#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
779#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
780#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
781#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
782#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
783#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
784#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
785#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
786#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
787#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
788#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
789#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
790#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
791#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
792#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
793#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
794#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
795#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
796#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
797#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
798
799#define OASTARTTRIG7 _MMIO(0x2728)
800#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
801#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
802#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
803#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
804#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
805#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
806#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
807#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
808#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
809
810#define OASTARTTRIG8 _MMIO(0x272c)
811#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
812#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
813#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
814#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
815#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
816#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
817#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
818#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
819#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
820
821#define OAREPORTTRIG1 _MMIO(0x2740)
822#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
823#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
824
825#define OAREPORTTRIG2 _MMIO(0x2744)
826#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
827#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
828#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
829#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
830#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
831#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
832#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
833#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
834#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
835#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
836#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
837#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
838#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
839#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
840#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
841#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
842#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
843#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
844#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
845#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
846#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
847#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
848#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
849#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
850#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
851
852#define OAREPORTTRIG3 _MMIO(0x2748)
853#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
854#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
855#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
856#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
857#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
858#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
859#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
860#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
861#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
862
863#define OAREPORTTRIG4 _MMIO(0x274c)
864#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
865#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
866#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
867#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
868#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
869#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
870#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
871#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
872#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
873
874#define OAREPORTTRIG5 _MMIO(0x2750)
875#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
876#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
877
878#define OAREPORTTRIG6 _MMIO(0x2754)
879#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
880#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
881#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
882#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
883#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
884#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
885#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
886#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
887#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
888#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
889#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
890#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
891#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
892#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
893#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
894#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
895#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
896#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
897#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
898#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
899#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
900#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
901#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
902#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
903#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
904
905#define OAREPORTTRIG7 _MMIO(0x2758)
906#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
907#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
908#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
909#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
910#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
911#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
912#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
913#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
914#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
915
916#define OAREPORTTRIG8 _MMIO(0x275c)
917#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
918#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
919#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
920#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
921#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
922#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
923#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
924#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
925#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
926
927/* CECX_0 */
928#define OACEC_COMPARE_LESS_OR_EQUAL 6
929#define OACEC_COMPARE_NOT_EQUAL 5
930#define OACEC_COMPARE_LESS_THAN 4
931#define OACEC_COMPARE_GREATER_OR_EQUAL 3
932#define OACEC_COMPARE_EQUAL 2
933#define OACEC_COMPARE_GREATER_THAN 1
934#define OACEC_COMPARE_ANY_EQUAL 0
935
936#define OACEC_COMPARE_VALUE_MASK 0xffff
937#define OACEC_COMPARE_VALUE_SHIFT 3
938
939#define OACEC_SELECT_NOA (0 << 19)
940#define OACEC_SELECT_PREV (1 << 19)
941#define OACEC_SELECT_BOOLEAN (2 << 19)
942
943/* CECX_1 */
944#define OACEC_MASK_MASK 0xffff
945#define OACEC_CONSIDERATIONS_MASK 0xffff
946#define OACEC_CONSIDERATIONS_SHIFT 16
947
948#define OACEC0_0 _MMIO(0x2770)
949#define OACEC0_1 _MMIO(0x2774)
950#define OACEC1_0 _MMIO(0x2778)
951#define OACEC1_1 _MMIO(0x277c)
952#define OACEC2_0 _MMIO(0x2780)
953#define OACEC2_1 _MMIO(0x2784)
954#define OACEC3_0 _MMIO(0x2788)
955#define OACEC3_1 _MMIO(0x278c)
956#define OACEC4_0 _MMIO(0x2790)
957#define OACEC4_1 _MMIO(0x2794)
958#define OACEC5_0 _MMIO(0x2798)
959#define OACEC5_1 _MMIO(0x279c)
960#define OACEC6_0 _MMIO(0x27a0)
961#define OACEC6_1 _MMIO(0x27a4)
962#define OACEC7_0 _MMIO(0x27a8)
963#define OACEC7_1 _MMIO(0x27ac)
964
965/* OA perf counters */
966#define OA_PERFCNT1_LO _MMIO(0x91B8)
967#define OA_PERFCNT1_HI _MMIO(0x91BC)
968#define OA_PERFCNT2_LO _MMIO(0x91C0)
969#define OA_PERFCNT2_HI _MMIO(0x91C4)
970#define OA_PERFCNT3_LO _MMIO(0x91C8)
971#define OA_PERFCNT3_HI _MMIO(0x91CC)
972#define OA_PERFCNT4_LO _MMIO(0x91D8)
973#define OA_PERFCNT4_HI _MMIO(0x91DC)
974
975#define OA_PERFMATRIX_LO _MMIO(0x91C8)
976#define OA_PERFMATRIX_HI _MMIO(0x91CC)
977
978/* RPM unit config (Gen8+) */
979#define RPM_CONFIG0 _MMIO(0x0D00)
980#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
981#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
982#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
983#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
984#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
985#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
986#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
987#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
988#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
989#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
990#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
991#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
992
993#define RPM_CONFIG1 _MMIO(0x0D04)
994#define GEN10_GT_NOA_ENABLE (1 << 9)
995
996/* GPM unit config (Gen9+) */
997#define CTC_MODE _MMIO(0xA26C)
998#define CTC_SOURCE_PARAMETER_MASK 1
999#define CTC_SOURCE_CRYSTAL_CLOCK 0
1000#define CTC_SOURCE_DIVIDE_LOGIC 1
1001#define CTC_SHIFT_PARAMETER_SHIFT 1
1002#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1003
1004/* RCP unit config (Gen8+) */
1005#define RCP_CONFIG _MMIO(0x0D08)
1006
1007/* NOA (HSW) */
1008#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1009#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1010#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1011#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1012#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1013#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1014#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1015#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1016#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1017#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1018
1019#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1020
1021/* NOA (Gen8+) */
1022#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1023
1024#define MICRO_BP0_0 _MMIO(0x9800)
1025#define MICRO_BP0_2 _MMIO(0x9804)
1026#define MICRO_BP0_1 _MMIO(0x9808)
1027
1028#define MICRO_BP1_0 _MMIO(0x980C)
1029#define MICRO_BP1_2 _MMIO(0x9810)
1030#define MICRO_BP1_1 _MMIO(0x9814)
1031
1032#define MICRO_BP2_0 _MMIO(0x9818)
1033#define MICRO_BP2_2 _MMIO(0x981C)
1034#define MICRO_BP2_1 _MMIO(0x9820)
1035
1036#define MICRO_BP3_0 _MMIO(0x9824)
1037#define MICRO_BP3_2 _MMIO(0x9828)
1038#define MICRO_BP3_1 _MMIO(0x982C)
1039
1040#define MICRO_BP_TRIGGER _MMIO(0x9830)
1041#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1042#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1043#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1044
1045#define GDT_CHICKEN_BITS _MMIO(0x9840)
1046#define GT_NOA_ENABLE 0x00000080
1047
1048#define NOA_DATA _MMIO(0x986C)
1049#define NOA_WRITE _MMIO(0x9888)
1050#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1051
1052#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1053#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1054#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1055
1056/*
1057 * Reset registers
1058 */
1059#define DEBUG_RESET_I830 _MMIO(0x6070)
1060#define DEBUG_RESET_FULL (1 << 7)
1061#define DEBUG_RESET_RENDER (1 << 8)
1062#define DEBUG_RESET_DISPLAY (1 << 9)
1063
1064/*
1065 * IOSF sideband
1066 */
1067#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1068#define IOSF_DEVFN_SHIFT 24
1069#define IOSF_OPCODE_SHIFT 16
1070#define IOSF_PORT_SHIFT 8
1071#define IOSF_BYTE_ENABLES_SHIFT 4
1072#define IOSF_BAR_SHIFT 1
1073#define IOSF_SB_BUSY (1 << 0)
1074#define IOSF_PORT_BUNIT 0x03
1075#define IOSF_PORT_PUNIT 0x04
1076#define IOSF_PORT_NC 0x11
1077#define IOSF_PORT_DPIO 0x12
1078#define IOSF_PORT_GPIO_NC 0x13
1079#define IOSF_PORT_CCK 0x14
1080#define IOSF_PORT_DPIO_2 0x1a
1081#define IOSF_PORT_FLISDSI 0x1b
1082#define IOSF_PORT_GPIO_SC 0x48
1083#define IOSF_PORT_GPIO_SUS 0xa8
1084#define IOSF_PORT_CCU 0xa9
1085#define CHV_IOSF_PORT_GPIO_N 0x13
1086#define CHV_IOSF_PORT_GPIO_SE 0x48
1087#define CHV_IOSF_PORT_GPIO_E 0xa8
1088#define CHV_IOSF_PORT_GPIO_SW 0xb2
1089#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1090#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1091
1092/* See configdb bunit SB addr map */
1093#define BUNIT_REG_BISOC 0x11
1094
1095/* PUNIT_REG_*SSPM0 */
1096#define _SSPM0_SSC(val) ((val) << 0)
1097#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
1098#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
1099#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
1100#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
1101#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
1102#define _SSPM0_SSS(val) ((val) << 24)
1103#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
1104#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
1105#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
1106#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
1107#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
1108
1109/* PUNIT_REG_*SSPM1 */
1110#define SSPM1_FREQSTAT_SHIFT 24
1111#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
1112#define SSPM1_FREQGUAR_SHIFT 8
1113#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
1114#define SSPM1_FREQ_SHIFT 0
1115#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
1116
1117#define PUNIT_REG_VEDSSPM0 0x32
1118#define PUNIT_REG_VEDSSPM1 0x33
1119
1120#define PUNIT_REG_DSPSSPM 0x36
1121#define DSPFREQSTAT_SHIFT_CHV 24
1122#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1123#define DSPFREQGUAR_SHIFT_CHV 8
1124#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1125#define DSPFREQSTAT_SHIFT 30
1126#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1127#define DSPFREQGUAR_SHIFT 14
1128#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1129#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1130#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1131#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1132#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1133#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1134#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1135#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1136#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1137#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1138#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1139#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1140#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1141#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1142#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1143#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1144
1145#define PUNIT_REG_ISPSSPM0 0x39
1146#define PUNIT_REG_ISPSSPM1 0x3a
1147
1148#define PUNIT_REG_PWRGT_CTRL 0x60
1149#define PUNIT_REG_PWRGT_STATUS 0x61
1150#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1151#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1152#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1153#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1154#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1155
1156#define PUNIT_PWGT_IDX_RENDER 0
1157#define PUNIT_PWGT_IDX_MEDIA 1
1158#define PUNIT_PWGT_IDX_DISP2D 3
1159#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1160#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1161#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1162#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1163#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1164#define PUNIT_PWGT_IDX_DPIO_RX0 10
1165#define PUNIT_PWGT_IDX_DPIO_RX1 11
1166#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1167
1168#define PUNIT_REG_GPU_LFM 0xd3
1169#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1170#define PUNIT_REG_GPU_FREQ_STS 0xd8
1171#define GPLLENABLE (1 << 4)
1172#define GENFREQSTATUS (1 << 0)
1173#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1174#define PUNIT_REG_CZ_TIMESTAMP 0xce
1175
1176#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1177#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1178
1179#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1180#define FB_GFX_FREQ_FUSE_MASK 0xff
1181#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1182#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1183#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1184
1185#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1186#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1187
1188#define PUNIT_REG_DDR_SETUP2 0x139
1189#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1190#define FORCE_DDR_LOW_FREQ (1 << 1)
1191#define FORCE_DDR_HIGH_FREQ (1 << 0)
1192
1193#define PUNIT_GPU_STATUS_REG 0xdb
1194#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1195#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1196#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1197#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1198
1199#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1200#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1201#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1202
1203#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1204#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1205#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1206#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1207#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1208#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1209#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1210#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1211#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1212#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1213
1214#define VLV_TURBO_SOC_OVERRIDE 0x04
1215#define VLV_OVERRIDE_EN 1
1216#define VLV_SOC_TDP_EN (1 << 1)
1217#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1218#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1219
1220/* vlv2 north clock has */
1221#define CCK_FUSE_REG 0x8
1222#define CCK_FUSE_HPLL_FREQ_MASK 0x3
1223#define CCK_REG_DSI_PLL_FUSE 0x44
1224#define CCK_REG_DSI_PLL_CONTROL 0x48
1225#define DSI_PLL_VCO_EN (1 << 31)
1226#define DSI_PLL_LDO_GATE (1 << 30)
1227#define DSI_PLL_P1_POST_DIV_SHIFT 17
1228#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1229#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1230#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1231#define DSI_PLL_MUX_MASK (3 << 9)
1232#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1233#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1234#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1235#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1236#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1237#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1238#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1239#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1240#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1241#define DSI_PLL_LOCK (1 << 0)
1242#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1243#define DSI_PLL_LFSR (1 << 31)
1244#define DSI_PLL_FRACTION_EN (1 << 30)
1245#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1246#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1247#define DSI_PLL_USYNC_CNT_SHIFT 18
1248#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1249#define DSI_PLL_N1_DIV_SHIFT 16
1250#define DSI_PLL_N1_DIV_MASK (3 << 16)
1251#define DSI_PLL_M1_DIV_SHIFT 0
1252#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1253#define CCK_CZ_CLOCK_CONTROL 0x62
1254#define CCK_GPLL_CLOCK_CONTROL 0x67
1255#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1256#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1257#define CCK_TRUNK_FORCE_ON (1 << 17)
1258#define CCK_TRUNK_FORCE_OFF (1 << 16)
1259#define CCK_FREQUENCY_STATUS (0x1f << 8)
1260#define CCK_FREQUENCY_STATUS_SHIFT 8
1261#define CCK_FREQUENCY_VALUES (0x1f << 0)
1262
1263/* DPIO registers */
1264#define DPIO_DEVFN 0
1265
1266#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1267#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
1268#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
1269#define DPIO_SFR_BYPASS (1 << 1)
1270#define DPIO_CMNRST (1 << 0)
1271
1272#define DPIO_PHY(pipe) ((pipe) >> 1)
1273#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1274
1275/*
1276 * Per pipe/PLL DPIO regs
1277 */
1278#define _VLV_PLL_DW3_CH0 0x800c
1279#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1280#define DPIO_POST_DIV_DAC 0
1281#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1282#define DPIO_POST_DIV_LVDS1 2
1283#define DPIO_POST_DIV_LVDS2 3
1284#define DPIO_K_SHIFT (24) /* 4 bits */
1285#define DPIO_P1_SHIFT (21) /* 3 bits */
1286#define DPIO_P2_SHIFT (16) /* 5 bits */
1287#define DPIO_N_SHIFT (12) /* 4 bits */
1288#define DPIO_ENABLE_CALIBRATION (1 << 11)
1289#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1290#define DPIO_M2DIV_MASK 0xff
1291#define _VLV_PLL_DW3_CH1 0x802c
1292#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1293
1294#define _VLV_PLL_DW5_CH0 0x8014
1295#define DPIO_REFSEL_OVERRIDE 27
1296#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1297#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1298#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1299#define DPIO_PLL_REFCLK_SEL_MASK 3
1300#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1301#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1302#define _VLV_PLL_DW5_CH1 0x8034
1303#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1304
1305#define _VLV_PLL_DW7_CH0 0x801c
1306#define _VLV_PLL_DW7_CH1 0x803c
1307#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1308
1309#define _VLV_PLL_DW8_CH0 0x8040
1310#define _VLV_PLL_DW8_CH1 0x8060
1311#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1312
1313#define VLV_PLL_DW9_BCAST 0xc044
1314#define _VLV_PLL_DW9_CH0 0x8044
1315#define _VLV_PLL_DW9_CH1 0x8064
1316#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1317
1318#define _VLV_PLL_DW10_CH0 0x8048
1319#define _VLV_PLL_DW10_CH1 0x8068
1320#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1321
1322#define _VLV_PLL_DW11_CH0 0x804c
1323#define _VLV_PLL_DW11_CH1 0x806c
1324#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1325
1326/* Spec for ref block start counts at DW10 */
1327#define VLV_REF_DW13 0x80ac
1328
1329#define VLV_CMN_DW0 0x8100
1330
1331/*
1332 * Per DDI channel DPIO regs
1333 */
1334
1335#define _VLV_PCS_DW0_CH0 0x8200
1336#define _VLV_PCS_DW0_CH1 0x8400
1337#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1338#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1339#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1340#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1341#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1342
1343#define _VLV_PCS01_DW0_CH0 0x200
1344#define _VLV_PCS23_DW0_CH0 0x400
1345#define _VLV_PCS01_DW0_CH1 0x2600
1346#define _VLV_PCS23_DW0_CH1 0x2800
1347#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1348#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1349
1350#define _VLV_PCS_DW1_CH0 0x8204
1351#define _VLV_PCS_DW1_CH1 0x8404
1352#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1353#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1354#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1355#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1356#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1357#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1358
1359#define _VLV_PCS01_DW1_CH0 0x204
1360#define _VLV_PCS23_DW1_CH0 0x404
1361#define _VLV_PCS01_DW1_CH1 0x2604
1362#define _VLV_PCS23_DW1_CH1 0x2804
1363#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1364#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1365
1366#define _VLV_PCS_DW8_CH0 0x8220
1367#define _VLV_PCS_DW8_CH1 0x8420
1368#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1369#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1370#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1371
1372#define _VLV_PCS01_DW8_CH0 0x0220
1373#define _VLV_PCS23_DW8_CH0 0x0420
1374#define _VLV_PCS01_DW8_CH1 0x2620
1375#define _VLV_PCS23_DW8_CH1 0x2820
1376#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1377#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1378
1379#define _VLV_PCS_DW9_CH0 0x8224
1380#define _VLV_PCS_DW9_CH1 0x8424
1381#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1382#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1383#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1384#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1385#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1386#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1387#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1388
1389#define _VLV_PCS01_DW9_CH0 0x224
1390#define _VLV_PCS23_DW9_CH0 0x424
1391#define _VLV_PCS01_DW9_CH1 0x2624
1392#define _VLV_PCS23_DW9_CH1 0x2824
1393#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1394#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1395
1396#define _CHV_PCS_DW10_CH0 0x8228
1397#define _CHV_PCS_DW10_CH1 0x8428
1398#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1399#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1400#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1401#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1402#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1403#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1404#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1405#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1406#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1407
1408#define _VLV_PCS01_DW10_CH0 0x0228
1409#define _VLV_PCS23_DW10_CH0 0x0428
1410#define _VLV_PCS01_DW10_CH1 0x2628
1411#define _VLV_PCS23_DW10_CH1 0x2828
1412#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1413#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1414
1415#define _VLV_PCS_DW11_CH0 0x822c
1416#define _VLV_PCS_DW11_CH1 0x842c
1417#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1418#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1419#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1420#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1421#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1422
1423#define _VLV_PCS01_DW11_CH0 0x022c
1424#define _VLV_PCS23_DW11_CH0 0x042c
1425#define _VLV_PCS01_DW11_CH1 0x262c
1426#define _VLV_PCS23_DW11_CH1 0x282c
1427#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1428#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1429
1430#define _VLV_PCS01_DW12_CH0 0x0230
1431#define _VLV_PCS23_DW12_CH0 0x0430
1432#define _VLV_PCS01_DW12_CH1 0x2630
1433#define _VLV_PCS23_DW12_CH1 0x2830
1434#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1435#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1436
1437#define _VLV_PCS_DW12_CH0 0x8230
1438#define _VLV_PCS_DW12_CH1 0x8430
1439#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1440#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1441#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1442#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1443#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1444#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1445
1446#define _VLV_PCS_DW14_CH0 0x8238
1447#define _VLV_PCS_DW14_CH1 0x8438
1448#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1449
1450#define _VLV_PCS_DW23_CH0 0x825c
1451#define _VLV_PCS_DW23_CH1 0x845c
1452#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1453
1454#define _VLV_TX_DW2_CH0 0x8288
1455#define _VLV_TX_DW2_CH1 0x8488
1456#define DPIO_SWING_MARGIN000_SHIFT 16
1457#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1458#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1459#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1460
1461#define _VLV_TX_DW3_CH0 0x828c
1462#define _VLV_TX_DW3_CH1 0x848c
1463/* The following bit for CHV phy */
1464#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1465#define DPIO_SWING_MARGIN101_SHIFT 16
1466#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1467#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1468
1469#define _VLV_TX_DW4_CH0 0x8290
1470#define _VLV_TX_DW4_CH1 0x8490
1471#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1472#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1473#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1474#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1475#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1476
1477#define _VLV_TX3_DW4_CH0 0x690
1478#define _VLV_TX3_DW4_CH1 0x2a90
1479#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1480
1481#define _VLV_TX_DW5_CH0 0x8294
1482#define _VLV_TX_DW5_CH1 0x8494
1483#define DPIO_TX_OCALINIT_EN (1 << 31)
1484#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1485
1486#define _VLV_TX_DW11_CH0 0x82ac
1487#define _VLV_TX_DW11_CH1 0x84ac
1488#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1489
1490#define _VLV_TX_DW14_CH0 0x82b8
1491#define _VLV_TX_DW14_CH1 0x84b8
1492#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1493
1494/* CHV dpPhy registers */
1495#define _CHV_PLL_DW0_CH0 0x8000
1496#define _CHV_PLL_DW0_CH1 0x8180
1497#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1498
1499#define _CHV_PLL_DW1_CH0 0x8004
1500#define _CHV_PLL_DW1_CH1 0x8184
1501#define DPIO_CHV_N_DIV_SHIFT 8
1502#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1503#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1504
1505#define _CHV_PLL_DW2_CH0 0x8008
1506#define _CHV_PLL_DW2_CH1 0x8188
1507#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1508
1509#define _CHV_PLL_DW3_CH0 0x800c
1510#define _CHV_PLL_DW3_CH1 0x818c
1511#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1512#define DPIO_CHV_FIRST_MOD (0 << 8)
1513#define DPIO_CHV_SECOND_MOD (1 << 8)
1514#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1515#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1516#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1517
1518#define _CHV_PLL_DW6_CH0 0x8018
1519#define _CHV_PLL_DW6_CH1 0x8198
1520#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1521#define DPIO_CHV_INT_COEFF_SHIFT 8
1522#define DPIO_CHV_PROP_COEFF_SHIFT 0
1523#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1524
1525#define _CHV_PLL_DW8_CH0 0x8020
1526#define _CHV_PLL_DW8_CH1 0x81A0
1527#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1528#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1529#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1530
1531#define _CHV_PLL_DW9_CH0 0x8024
1532#define _CHV_PLL_DW9_CH1 0x81A4
1533#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1534#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1535#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1536#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1537
1538#define _CHV_CMN_DW0_CH0 0x8100
1539#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1540#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1541#define DPIO_ALLDL_POWERDOWN (1 << 1)
1542#define DPIO_ANYDL_POWERDOWN (1 << 0)
1543
1544#define _CHV_CMN_DW5_CH0 0x8114
1545#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1546#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1547#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1548#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1549#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1550#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1551#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1552#define CHV_BUFLEFTENA1_MASK (3 << 22)
1553
1554#define _CHV_CMN_DW13_CH0 0x8134
1555#define _CHV_CMN_DW0_CH1 0x8080
1556#define DPIO_CHV_S1_DIV_SHIFT 21
1557#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1558#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1559#define DPIO_CHV_K_DIV_SHIFT 4
1560#define DPIO_PLL_FREQLOCK (1 << 1)
1561#define DPIO_PLL_LOCK (1 << 0)
1562#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1563
1564#define _CHV_CMN_DW14_CH0 0x8138
1565#define _CHV_CMN_DW1_CH1 0x8084
1566#define DPIO_AFC_RECAL (1 << 14)
1567#define DPIO_DCLKP_EN (1 << 13)
1568#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1569#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1570#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1571#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1572#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1573#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1574#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1575#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1576#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1577
1578#define _CHV_CMN_DW19_CH0 0x814c
1579#define _CHV_CMN_DW6_CH1 0x8098
1580#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1581#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1582#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1583#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1584
1585#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1586
1587#define CHV_CMN_DW28 0x8170
1588#define DPIO_CL1POWERDOWNEN (1 << 23)
1589#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1590#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1591#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1592#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1593#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1594
1595#define CHV_CMN_DW30 0x8178
1596#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1597#define DPIO_LRC_BYPASS (1 << 3)
1598
1599#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1600 (lane) * 0x200 + (offset))
1601
1602#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1603#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1604#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1605#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1606#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1607#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1608#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1609#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1610#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1611#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1612#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1613#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1614#define DPIO_FRC_LATENCY_SHFIT 8
1615#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1616#define DPIO_UPAR_SHIFT 30
1617
1618/* BXT PHY registers */
1619#define _BXT_PHY0_BASE 0x6C000
1620#define _BXT_PHY1_BASE 0x162000
1621#define _BXT_PHY2_BASE 0x163000
1622#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1623 _BXT_PHY1_BASE, \
1624 _BXT_PHY2_BASE)
1625
1626#define _BXT_PHY(phy, reg) \
1627 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1628
1629#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1630 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1631 (reg_ch1) - _BXT_PHY0_BASE))
1632#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1633 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1634
1635#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1636#define MIPIO_RST_CTRL (1 << 2)
1637
1638#define _BXT_PHY_CTL_DDI_A 0x64C00
1639#define _BXT_PHY_CTL_DDI_B 0x64C10
1640#define _BXT_PHY_CTL_DDI_C 0x64C20
1641#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1642#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1643#define BXT_PHY_LANE_ENABLED (1 << 8)
1644#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1645 _BXT_PHY_CTL_DDI_B)
1646
1647#define _PHY_CTL_FAMILY_EDP 0x64C80
1648#define _PHY_CTL_FAMILY_DDI 0x64C90
1649#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1650#define COMMON_RESET_DIS (1 << 31)
1651#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1652 _PHY_CTL_FAMILY_EDP, \
1653 _PHY_CTL_FAMILY_DDI_C)
1654
1655/* BXT PHY PLL registers */
1656#define _PORT_PLL_A 0x46074
1657#define _PORT_PLL_B 0x46078
1658#define _PORT_PLL_C 0x4607c
1659#define PORT_PLL_ENABLE (1 << 31)
1660#define PORT_PLL_LOCK (1 << 30)
1661#define PORT_PLL_REF_SEL (1 << 27)
1662#define PORT_PLL_POWER_ENABLE (1 << 26)
1663#define PORT_PLL_POWER_STATE (1 << 25)
1664#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1665
1666#define _PORT_PLL_EBB_0_A 0x162034
1667#define _PORT_PLL_EBB_0_B 0x6C034
1668#define _PORT_PLL_EBB_0_C 0x6C340
1669#define PORT_PLL_P1_SHIFT 13
1670#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1671#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1672#define PORT_PLL_P2_SHIFT 8
1673#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1674#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1675#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1676 _PORT_PLL_EBB_0_B, \
1677 _PORT_PLL_EBB_0_C)
1678
1679#define _PORT_PLL_EBB_4_A 0x162038
1680#define _PORT_PLL_EBB_4_B 0x6C038
1681#define _PORT_PLL_EBB_4_C 0x6C344
1682#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1683#define PORT_PLL_RECALIBRATE (1 << 14)
1684#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1685 _PORT_PLL_EBB_4_B, \
1686 _PORT_PLL_EBB_4_C)
1687
1688#define _PORT_PLL_0_A 0x162100
1689#define _PORT_PLL_0_B 0x6C100
1690#define _PORT_PLL_0_C 0x6C380
1691/* PORT_PLL_0_A */
1692#define PORT_PLL_M2_MASK 0xFF
1693/* PORT_PLL_1_A */
1694#define PORT_PLL_N_SHIFT 8
1695#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1696#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1697/* PORT_PLL_2_A */
1698#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1699/* PORT_PLL_3_A */
1700#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1701/* PORT_PLL_6_A */
1702#define PORT_PLL_PROP_COEFF_MASK 0xF
1703#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1704#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1705#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1706#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1707/* PORT_PLL_8_A */
1708#define PORT_PLL_TARGET_CNT_MASK 0x3FF
1709/* PORT_PLL_9_A */
1710#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1711#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1712/* PORT_PLL_10_A */
1713#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1714#define PORT_PLL_DCO_AMP_DEFAULT 15
1715#define PORT_PLL_DCO_AMP_MASK 0x3c00
1716#define PORT_PLL_DCO_AMP(x) ((x) << 10)
1717#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1718 _PORT_PLL_0_B, \
1719 _PORT_PLL_0_C)
1720#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1721 (idx) * 4)
1722
1723/* BXT PHY common lane registers */
1724#define _PORT_CL1CM_DW0_A 0x162000
1725#define _PORT_CL1CM_DW0_BC 0x6C000
1726#define PHY_POWER_GOOD (1 << 16)
1727#define PHY_RESERVED (1 << 7)
1728#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1729
1730#define _PORT_CL1CM_DW9_A 0x162024
1731#define _PORT_CL1CM_DW9_BC 0x6C024
1732#define IREF0RC_OFFSET_SHIFT 8
1733#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1734#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1735
1736#define _PORT_CL1CM_DW10_A 0x162028
1737#define _PORT_CL1CM_DW10_BC 0x6C028
1738#define IREF1RC_OFFSET_SHIFT 8
1739#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1740#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1741
1742#define _PORT_CL1CM_DW28_A 0x162070
1743#define _PORT_CL1CM_DW28_BC 0x6C070
1744#define OCL1_POWER_DOWN_EN (1 << 23)
1745#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1746#define SUS_CLK_CONFIG 0x3
1747#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1748
1749#define _PORT_CL1CM_DW30_A 0x162078
1750#define _PORT_CL1CM_DW30_BC 0x6C078
1751#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1752#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1753
1754/*
1755 * CNL/ICL Port/COMBO-PHY Registers
1756 */
1757#define _ICL_COMBOPHY_A 0x162000
1758#define _ICL_COMBOPHY_B 0x6C000
1759#define _EHL_COMBOPHY_C 0x160000
1760#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
1761 _ICL_COMBOPHY_B, \
1762 _EHL_COMBOPHY_C)
1763
1764/* CNL/ICL Port CL_DW registers */
1765#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1766 4 * (dw))
1767
1768#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1769#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
1770#define CL_POWER_DOWN_ENABLE (1 << 4)
1771#define SUS_CLOCK_CONFIG (3 << 0)
1772
1773#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
1774#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1775#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1776#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1777#define PWR_UP_ALL_LANES (0x0 << 4)
1778#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1779#define PWR_DOWN_LN_3_2 (0xc << 4)
1780#define PWR_DOWN_LN_3 (0x8 << 4)
1781#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1782#define PWR_DOWN_LN_1_0 (0x3 << 4)
1783#define PWR_DOWN_LN_3_1 (0xa << 4)
1784#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1785#define PWR_DOWN_LN_MASK (0xf << 4)
1786#define PWR_DOWN_LN_SHIFT 4
1787
1788#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
1789#define ICL_LANE_ENABLE_AUX (1 << 0)
1790
1791/* CNL/ICL Port COMP_DW registers */
1792#define _ICL_PORT_COMP 0x100
1793#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1794 _ICL_PORT_COMP + 4 * (dw))
1795
1796#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1797#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
1798#define COMP_INIT (1 << 31)
1799
1800#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1801#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
1802
1803#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1804#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
1805#define PROCESS_INFO_DOT_0 (0 << 26)
1806#define PROCESS_INFO_DOT_1 (1 << 26)
1807#define PROCESS_INFO_DOT_4 (2 << 26)
1808#define PROCESS_INFO_MASK (7 << 26)
1809#define PROCESS_INFO_SHIFT 26
1810#define VOLTAGE_INFO_0_85V (0 << 24)
1811#define VOLTAGE_INFO_0_95V (1 << 24)
1812#define VOLTAGE_INFO_1_05V (2 << 24)
1813#define VOLTAGE_INFO_MASK (3 << 24)
1814#define VOLTAGE_INFO_SHIFT 24
1815
1816#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
1817#define IREFGEN (1 << 24)
1818
1819#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1820#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
1821
1822#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1823#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
1824
1825/* CNL/ICL Port PCS registers */
1826#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1827#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1828#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1829#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1830#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1831#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1832#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1833#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1834#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1835#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1836#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
1837 _CNL_PORT_PCS_DW1_GRP_AE, \
1838 _CNL_PORT_PCS_DW1_GRP_B, \
1839 _CNL_PORT_PCS_DW1_GRP_C, \
1840 _CNL_PORT_PCS_DW1_GRP_D, \
1841 _CNL_PORT_PCS_DW1_GRP_AE, \
1842 _CNL_PORT_PCS_DW1_GRP_F))
1843#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
1844 _CNL_PORT_PCS_DW1_LN0_AE, \
1845 _CNL_PORT_PCS_DW1_LN0_B, \
1846 _CNL_PORT_PCS_DW1_LN0_C, \
1847 _CNL_PORT_PCS_DW1_LN0_D, \
1848 _CNL_PORT_PCS_DW1_LN0_AE, \
1849 _CNL_PORT_PCS_DW1_LN0_F))
1850
1851#define _ICL_PORT_PCS_AUX 0x300
1852#define _ICL_PORT_PCS_GRP 0x600
1853#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1854#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1855 _ICL_PORT_PCS_AUX + 4 * (dw))
1856#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1857 _ICL_PORT_PCS_GRP + 4 * (dw))
1858#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1859 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1860#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1861#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1862#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1863#define COMMON_KEEPER_EN (1 << 26)
1864#define LATENCY_OPTIM_MASK (0x3 << 2)
1865#define LATENCY_OPTIM_VAL(x) ((x) << 2)
1866
1867/* CNL/ICL Port TX registers */
1868#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1869#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1870#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1871#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1872#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1873#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1874#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1875#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1876#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1877#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1878#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
1879 _CNL_PORT_TX_AE_GRP_OFFSET, \
1880 _CNL_PORT_TX_B_GRP_OFFSET, \
1881 _CNL_PORT_TX_B_GRP_OFFSET, \
1882 _CNL_PORT_TX_D_GRP_OFFSET, \
1883 _CNL_PORT_TX_AE_GRP_OFFSET, \
1884 _CNL_PORT_TX_F_GRP_OFFSET) + \
1885 4 * (dw))
1886#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
1887 _CNL_PORT_TX_AE_LN0_OFFSET, \
1888 _CNL_PORT_TX_B_LN0_OFFSET, \
1889 _CNL_PORT_TX_B_LN0_OFFSET, \
1890 _CNL_PORT_TX_D_LN0_OFFSET, \
1891 _CNL_PORT_TX_AE_LN0_OFFSET, \
1892 _CNL_PORT_TX_F_LN0_OFFSET) + \
1893 4 * (dw))
1894
1895#define _ICL_PORT_TX_AUX 0x380
1896#define _ICL_PORT_TX_GRP 0x680
1897#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
1898
1899#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1900 _ICL_PORT_TX_AUX + 4 * (dw))
1901#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1902 _ICL_PORT_TX_GRP + 4 * (dw))
1903#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1904 _ICL_PORT_TX_LN(ln) + 4 * (dw))
1905
1906#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1907#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1908#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
1909#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
1910#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
1911#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1912#define SWING_SEL_UPPER_MASK (1 << 15)
1913#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
1914#define SWING_SEL_LOWER_MASK (0x7 << 11)
1915#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
1916#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
1917#define RCOMP_SCALAR(x) ((x) << 0)
1918#define RCOMP_SCALAR_MASK (0xFF << 0)
1919
1920#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1921#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1922#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
1923#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
1924#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1925 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1926 _CNL_PORT_TX_DW4_LN0_AE)))
1927#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
1928#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
1929#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
1930#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
1931#define LOADGEN_SELECT (1 << 31)
1932#define POST_CURSOR_1(x) ((x) << 12)
1933#define POST_CURSOR_1_MASK (0x3F << 12)
1934#define POST_CURSOR_2(x) ((x) << 6)
1935#define POST_CURSOR_2_MASK (0x3F << 6)
1936#define CURSOR_COEFF(x) ((x) << 0)
1937#define CURSOR_COEFF_MASK (0x3F << 0)
1938
1939#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1940#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1941#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
1942#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
1943#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
1944#define TX_TRAINING_EN (1 << 31)
1945#define TAP2_DISABLE (1 << 30)
1946#define TAP3_DISABLE (1 << 29)
1947#define SCALING_MODE_SEL(x) ((x) << 18)
1948#define SCALING_MODE_SEL_MASK (0x7 << 18)
1949#define RTERM_SELECT(x) ((x) << 3)
1950#define RTERM_SELECT_MASK (0x7 << 3)
1951
1952#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
1953#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
1954#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
1955#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
1956#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
1957#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
1958#define N_SCALAR(x) ((x) << 24)
1959#define N_SCALAR_MASK (0x7F << 24)
1960
1961#define _ICL_DPHY_CHKN_REG 0x194
1962#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
1963#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
1964
1965#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
1966 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1967
1968#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1969#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1970#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1971#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1972#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1973#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1974#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1975#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1976#define MG_TX1_LINK_PARAMS(ln, port) \
1977 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1978 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1979 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1980
1981#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1982#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1983#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1984#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1985#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1986#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1987#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1988#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1989#define MG_TX2_LINK_PARAMS(ln, port) \
1990 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1991 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1992 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1993#define CRI_USE_FS32 (1 << 5)
1994
1995#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1996#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1997#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1998#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1999#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
2000#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
2001#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
2002#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
2003#define MG_TX1_PISO_READLOAD(ln, port) \
2004 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2005 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2006 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2007
2008#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
2009#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
2010#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
2011#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
2012#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
2013#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
2014#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
2015#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
2016#define MG_TX2_PISO_READLOAD(ln, port) \
2017 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2018 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2019 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2020#define CRI_CALCINIT (1 << 1)
2021
2022#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
2023#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2024#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2025#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2026#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2027#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2028#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2029#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2030#define MG_TX1_SWINGCTRL(ln, port) \
2031 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2032 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2033 MG_TX_SWINGCTRL_TX1LN1_PORT1)
2034
2035#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2036#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2037#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2038#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2039#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2040#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2041#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2042#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2043#define MG_TX2_SWINGCTRL(ln, port) \
2044 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2045 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2046 MG_TX_SWINGCTRL_TX2LN1_PORT1)
2047#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2048#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
2049
2050#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
2051#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
2052#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
2053#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
2054#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
2055#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
2056#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
2057#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
2058#define MG_TX1_DRVCTRL(ln, port) \
2059 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2060 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2061 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2062
2063#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2064#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2065#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2066#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2067#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2068#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2069#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2070#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2071#define MG_TX2_DRVCTRL(ln, port) \
2072 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2073 MG_TX_DRVCTRL_TX2LN0_PORT2, \
2074 MG_TX_DRVCTRL_TX2LN1_PORT1)
2075#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2076#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2077#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2078#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2079#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2080#define CRI_LOADGEN_SEL(x) ((x) << 12)
2081#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2082
2083#define MG_CLKHUB_LN0_PORT1 0x16839C
2084#define MG_CLKHUB_LN1_PORT1 0x16879C
2085#define MG_CLKHUB_LN0_PORT2 0x16939C
2086#define MG_CLKHUB_LN1_PORT2 0x16979C
2087#define MG_CLKHUB_LN0_PORT3 0x16A39C
2088#define MG_CLKHUB_LN1_PORT3 0x16A79C
2089#define MG_CLKHUB_LN0_PORT4 0x16B39C
2090#define MG_CLKHUB_LN1_PORT4 0x16B79C
2091#define MG_CLKHUB(ln, port) \
2092 MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
2093 MG_CLKHUB_LN0_PORT2, \
2094 MG_CLKHUB_LN1_PORT1)
2095#define CFG_LOW_RATE_LKREN_EN (1 << 11)
2096
2097#define MG_TX_DCC_TX1LN0_PORT1 0x168110
2098#define MG_TX_DCC_TX1LN1_PORT1 0x168510
2099#define MG_TX_DCC_TX1LN0_PORT2 0x169110
2100#define MG_TX_DCC_TX1LN1_PORT2 0x169510
2101#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2102#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2103#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2104#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
2105#define MG_TX1_DCC(ln, port) \
2106 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
2107 MG_TX_DCC_TX1LN0_PORT2, \
2108 MG_TX_DCC_TX1LN1_PORT1)
2109#define MG_TX_DCC_TX2LN0_PORT1 0x168090
2110#define MG_TX_DCC_TX2LN1_PORT1 0x168490
2111#define MG_TX_DCC_TX2LN0_PORT2 0x169090
2112#define MG_TX_DCC_TX2LN1_PORT2 0x169490
2113#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2114#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2115#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2116#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2117#define MG_TX2_DCC(ln, port) \
2118 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
2119 MG_TX_DCC_TX2LN0_PORT2, \
2120 MG_TX_DCC_TX2LN1_PORT1)
2121#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2122#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2123#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2124
2125#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2126#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2127#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2128#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2129#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2130#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2131#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2132#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2133#define MG_DP_MODE(ln, port) \
2134 MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
2135 MG_DP_MODE_LN0_ACU_PORT2, \
2136 MG_DP_MODE_LN1_ACU_PORT1)
2137#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2138#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2139#define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
2140#define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
2141#define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
2142#define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
2143#define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
2144
2145#define MG_MISC_SUS0_PORT1 0x168814
2146#define MG_MISC_SUS0_PORT2 0x169814
2147#define MG_MISC_SUS0_PORT3 0x16A814
2148#define MG_MISC_SUS0_PORT4 0x16B814
2149#define MG_MISC_SUS0(tc_port) \
2150 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2151#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
2152#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
2153#define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
2154#define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
2155#define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
2156#define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
2157#define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
2158#define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
2159
2160/* The spec defines this only for BXT PHY0, but lets assume that this
2161 * would exist for PHY1 too if it had a second channel.
2162 */
2163#define _PORT_CL2CM_DW6_A 0x162358
2164#define _PORT_CL2CM_DW6_BC 0x6C358
2165#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2166#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2167
2168#define FIA1_BASE 0x163000
2169#define FIA2_BASE 0x16E000
2170#define FIA3_BASE 0x16F000
2171#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2172#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
2173
2174/* ICL PHY DFLEX registers */
2175#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
2176#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2177#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2178#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2179#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2180#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2181#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2182
2183/* BXT PHY Ref registers */
2184#define _PORT_REF_DW3_A 0x16218C
2185#define _PORT_REF_DW3_BC 0x6C18C
2186#define GRC_DONE (1 << 22)
2187#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2188
2189#define _PORT_REF_DW6_A 0x162198
2190#define _PORT_REF_DW6_BC 0x6C198
2191#define GRC_CODE_SHIFT 24
2192#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2193#define GRC_CODE_FAST_SHIFT 16
2194#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2195#define GRC_CODE_SLOW_SHIFT 8
2196#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2197#define GRC_CODE_NOM_MASK 0xFF
2198#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2199
2200#define _PORT_REF_DW8_A 0x1621A0
2201#define _PORT_REF_DW8_BC 0x6C1A0
2202#define GRC_DIS (1 << 15)
2203#define GRC_RDY_OVRD (1 << 1)
2204#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2205
2206/* BXT PHY PCS registers */
2207#define _PORT_PCS_DW10_LN01_A 0x162428
2208#define _PORT_PCS_DW10_LN01_B 0x6C428
2209#define _PORT_PCS_DW10_LN01_C 0x6C828
2210#define _PORT_PCS_DW10_GRP_A 0x162C28
2211#define _PORT_PCS_DW10_GRP_B 0x6CC28
2212#define _PORT_PCS_DW10_GRP_C 0x6CE28
2213#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2214 _PORT_PCS_DW10_LN01_B, \
2215 _PORT_PCS_DW10_LN01_C)
2216#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2217 _PORT_PCS_DW10_GRP_B, \
2218 _PORT_PCS_DW10_GRP_C)
2219
2220#define TX2_SWING_CALC_INIT (1 << 31)
2221#define TX1_SWING_CALC_INIT (1 << 30)
2222
2223#define _PORT_PCS_DW12_LN01_A 0x162430
2224#define _PORT_PCS_DW12_LN01_B 0x6C430
2225#define _PORT_PCS_DW12_LN01_C 0x6C830
2226#define _PORT_PCS_DW12_LN23_A 0x162630
2227#define _PORT_PCS_DW12_LN23_B 0x6C630
2228#define _PORT_PCS_DW12_LN23_C 0x6CA30
2229#define _PORT_PCS_DW12_GRP_A 0x162c30
2230#define _PORT_PCS_DW12_GRP_B 0x6CC30
2231#define _PORT_PCS_DW12_GRP_C 0x6CE30
2232#define LANESTAGGER_STRAP_OVRD (1 << 6)
2233#define LANE_STAGGER_MASK 0x1F
2234#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2235 _PORT_PCS_DW12_LN01_B, \
2236 _PORT_PCS_DW12_LN01_C)
2237#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2238 _PORT_PCS_DW12_LN23_B, \
2239 _PORT_PCS_DW12_LN23_C)
2240#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2241 _PORT_PCS_DW12_GRP_B, \
2242 _PORT_PCS_DW12_GRP_C)
2243
2244/* BXT PHY TX registers */
2245#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2246 ((lane) & 1) * 0x80)
2247
2248#define _PORT_TX_DW2_LN0_A 0x162508
2249#define _PORT_TX_DW2_LN0_B 0x6C508
2250#define _PORT_TX_DW2_LN0_C 0x6C908
2251#define _PORT_TX_DW2_GRP_A 0x162D08
2252#define _PORT_TX_DW2_GRP_B 0x6CD08
2253#define _PORT_TX_DW2_GRP_C 0x6CF08
2254#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2255 _PORT_TX_DW2_LN0_B, \
2256 _PORT_TX_DW2_LN0_C)
2257#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2258 _PORT_TX_DW2_GRP_B, \
2259 _PORT_TX_DW2_GRP_C)
2260#define MARGIN_000_SHIFT 16
2261#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2262#define UNIQ_TRANS_SCALE_SHIFT 8
2263#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2264
2265#define _PORT_TX_DW3_LN0_A 0x16250C
2266#define _PORT_TX_DW3_LN0_B 0x6C50C
2267#define _PORT_TX_DW3_LN0_C 0x6C90C
2268#define _PORT_TX_DW3_GRP_A 0x162D0C
2269#define _PORT_TX_DW3_GRP_B 0x6CD0C
2270#define _PORT_TX_DW3_GRP_C 0x6CF0C
2271#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2272 _PORT_TX_DW3_LN0_B, \
2273 _PORT_TX_DW3_LN0_C)
2274#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2275 _PORT_TX_DW3_GRP_B, \
2276 _PORT_TX_DW3_GRP_C)
2277#define SCALE_DCOMP_METHOD (1 << 26)
2278#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2279
2280#define _PORT_TX_DW4_LN0_A 0x162510
2281#define _PORT_TX_DW4_LN0_B 0x6C510
2282#define _PORT_TX_DW4_LN0_C 0x6C910
2283#define _PORT_TX_DW4_GRP_A 0x162D10
2284#define _PORT_TX_DW4_GRP_B 0x6CD10
2285#define _PORT_TX_DW4_GRP_C 0x6CF10
2286#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2287 _PORT_TX_DW4_LN0_B, \
2288 _PORT_TX_DW4_LN0_C)
2289#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2290 _PORT_TX_DW4_GRP_B, \
2291 _PORT_TX_DW4_GRP_C)
2292#define DEEMPH_SHIFT 24
2293#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2294
2295#define _PORT_TX_DW5_LN0_A 0x162514
2296#define _PORT_TX_DW5_LN0_B 0x6C514
2297#define _PORT_TX_DW5_LN0_C 0x6C914
2298#define _PORT_TX_DW5_GRP_A 0x162D14
2299#define _PORT_TX_DW5_GRP_B 0x6CD14
2300#define _PORT_TX_DW5_GRP_C 0x6CF14
2301#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2302 _PORT_TX_DW5_LN0_B, \
2303 _PORT_TX_DW5_LN0_C)
2304#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2305 _PORT_TX_DW5_GRP_B, \
2306 _PORT_TX_DW5_GRP_C)
2307#define DCC_DELAY_RANGE_1 (1 << 9)
2308#define DCC_DELAY_RANGE_2 (1 << 8)
2309
2310#define _PORT_TX_DW14_LN0_A 0x162538
2311#define _PORT_TX_DW14_LN0_B 0x6C538
2312#define _PORT_TX_DW14_LN0_C 0x6C938
2313#define LATENCY_OPTIM_SHIFT 30
2314#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2315#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2316 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2317 _PORT_TX_DW14_LN0_C) + \
2318 _BXT_LANE_OFFSET(lane))
2319
2320/* UAIMI scratch pad register 1 */
2321#define UAIMI_SPR1 _MMIO(0x4F074)
2322/* SKL VccIO mask */
2323#define SKL_VCCIO_MASK 0x1
2324/* SKL balance leg register */
2325#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2326/* I_boost values */
2327#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2328#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2329/* Balance leg disable bits */
2330#define BALANCE_LEG_DISABLE_SHIFT 23
2331#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2332
2333/*
2334 * Fence registers
2335 * [0-7] @ 0x2000 gen2,gen3
2336 * [8-15] @ 0x3000 945,g33,pnv
2337 *
2338 * [0-15] @ 0x3000 gen4,gen5
2339 *
2340 * [0-15] @ 0x100000 gen6,vlv,chv
2341 * [0-31] @ 0x100000 gen7+
2342 */
2343#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2344#define I830_FENCE_START_MASK 0x07f80000
2345#define I830_FENCE_TILING_Y_SHIFT 12
2346#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2347#define I830_FENCE_PITCH_SHIFT 4
2348#define I830_FENCE_REG_VALID (1 << 0)
2349#define I915_FENCE_MAX_PITCH_VAL 4
2350#define I830_FENCE_MAX_PITCH_VAL 6
2351#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2352
2353#define I915_FENCE_START_MASK 0x0ff00000
2354#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2355
2356#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2357#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2358#define I965_FENCE_PITCH_SHIFT 2
2359#define I965_FENCE_TILING_Y_SHIFT 1
2360#define I965_FENCE_REG_VALID (1 << 0)
2361#define I965_FENCE_MAX_PITCH_VAL 0x0400
2362
2363#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2364#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2365#define GEN6_FENCE_PITCH_SHIFT 32
2366#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2367
2368
2369/* control register for cpu gtt access */
2370#define TILECTL _MMIO(0x101000)
2371#define TILECTL_SWZCTL (1 << 0)
2372#define TILECTL_TLBPF (1 << 1)
2373#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2374#define TILECTL_BACKSNOOP_DIS (1 << 3)
2375
2376/*
2377 * Instruction and interrupt control regs
2378 */
2379#define PGTBL_CTL _MMIO(0x02020)
2380#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2381#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2382#define PGTBL_ER _MMIO(0x02024)
2383#define PRB0_BASE (0x2030 - 0x30)
2384#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2385#define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2386#define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2387#define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2388#define SRB2_BASE (0x2120 - 0x30) /* 830 */
2389#define SRB3_BASE (0x2130 - 0x30) /* 830 */
2390#define RENDER_RING_BASE 0x02000
2391#define BSD_RING_BASE 0x04000
2392#define GEN6_BSD_RING_BASE 0x12000
2393#define GEN8_BSD2_RING_BASE 0x1c000
2394#define GEN11_BSD_RING_BASE 0x1c0000
2395#define GEN11_BSD2_RING_BASE 0x1c4000
2396#define GEN11_BSD3_RING_BASE 0x1d0000
2397#define GEN11_BSD4_RING_BASE 0x1d4000
2398#define VEBOX_RING_BASE 0x1a000
2399#define GEN11_VEBOX_RING_BASE 0x1c8000
2400#define GEN11_VEBOX2_RING_BASE 0x1d8000
2401#define BLT_RING_BASE 0x22000
2402#define RING_TAIL(base) _MMIO((base) + 0x30)
2403#define RING_HEAD(base) _MMIO((base) + 0x34)
2404#define RING_START(base) _MMIO((base) + 0x38)
2405#define RING_CTL(base) _MMIO((base) + 0x3c)
2406#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2407#define RING_SYNC_0(base) _MMIO((base) + 0x40)
2408#define RING_SYNC_1(base) _MMIO((base) + 0x44)
2409#define RING_SYNC_2(base) _MMIO((base) + 0x48)
2410#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2411#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2412#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2413#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2414#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2415#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2416#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2417#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2418#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2419#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2420#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2421#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2422#define GEN6_NOSYNC INVALID_MMIO_REG
2423#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2424#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2425#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2426#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2427#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2428#define RESET_CTL_CAT_ERROR REG_BIT(2)
2429#define RESET_CTL_READY_TO_RESET REG_BIT(1)
2430#define RESET_CTL_REQUEST_RESET REG_BIT(0)
2431
2432#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2433
2434#define HSW_GTT_CACHE_EN _MMIO(0x4024)
2435#define GTT_CACHE_EN_ALL 0xF0007FFF
2436#define GEN7_WR_WATERMARK _MMIO(0x4028)
2437#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2438#define ARB_MODE _MMIO(0x4030)
2439#define ARB_MODE_SWIZZLE_SNB (1 << 4)
2440#define ARB_MODE_SWIZZLE_IVB (1 << 5)
2441#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2442#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2443/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2444#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2445#define GEN7_LRA_LIMITS_REG_NUM 13
2446#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2447#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2448
2449#define GAMTARBMODE _MMIO(0x04a08)
2450#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2451#define ARB_MODE_SWIZZLE_BDW (1 << 1)
2452#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2453#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2454#define GEN8_RING_FAULT_REG _MMIO(0x4094)
2455#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
2456#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2457#define RING_FAULT_GTTSEL_MASK (1 << 11)
2458#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2459#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2460#define RING_FAULT_VALID (1 << 0)
2461#define DONE_REG _MMIO(0x40b0)
2462#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2463#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2464#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2465#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
2466#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2467#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2468#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2469#define RING_ACTHD(base) _MMIO((base) + 0x74)
2470#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2471#define RING_NOPID(base) _MMIO((base) + 0x94)
2472#define RING_IMR(base) _MMIO((base) + 0xa8)
2473#define RING_HWSTAM(base) _MMIO((base) + 0x98)
2474#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2475#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2476#define TAIL_ADDR 0x001FFFF8
2477#define HEAD_WRAP_COUNT 0xFFE00000
2478#define HEAD_WRAP_ONE 0x00200000
2479#define HEAD_ADDR 0x001FFFFC
2480#define RING_NR_PAGES 0x001FF000
2481#define RING_REPORT_MASK 0x00000006
2482#define RING_REPORT_64K 0x00000002
2483#define RING_REPORT_128K 0x00000004
2484#define RING_NO_REPORT 0x00000000
2485#define RING_VALID_MASK 0x00000001
2486#define RING_VALID 0x00000001
2487#define RING_INVALID 0x00000000
2488#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2489#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2490#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2491
2492#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2493#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
2494#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
2495#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
2496#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
2497#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
2498#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
2499#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
2500#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
2501#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
2502#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
2503#define RING_FORCE_TO_NONPRIV_MASK_VALID \
2504 (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2505 | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2506#define RING_MAX_NONPRIV_SLOTS 12
2507
2508#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2509
2510#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2511#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2512
2513#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2514#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2515#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2516
2517#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2518#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2519#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2520#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2521
2522#if 0
2523#define PRB0_TAIL _MMIO(0x2030)
2524#define PRB0_HEAD _MMIO(0x2034)
2525#define PRB0_START _MMIO(0x2038)
2526#define PRB0_CTL _MMIO(0x203c)
2527#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2528#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2529#define PRB1_START _MMIO(0x2048) /* 915+ only */
2530#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2531#endif
2532#define IPEIR_I965 _MMIO(0x2064)
2533#define IPEHR_I965 _MMIO(0x2068)
2534#define GEN7_SC_INSTDONE _MMIO(0x7100)
2535#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2536#define GEN7_ROW_INSTDONE _MMIO(0xe164)
2537#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2538#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2539#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2540#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2541#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2542#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2543#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2544#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2545#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2546#define RING_IPEIR(base) _MMIO((base) + 0x64)
2547#define RING_IPEHR(base) _MMIO((base) + 0x68)
2548/*
2549 * On GEN4, only the render ring INSTDONE exists and has a different
2550 * layout than the GEN7+ version.
2551 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2552 */
2553#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2554#define RING_INSTPS(base) _MMIO((base) + 0x70)
2555#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2556#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2557#define RING_INSTPM(base) _MMIO((base) + 0xc0)
2558#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2559#define INSTPS _MMIO(0x2070) /* 965+ only */
2560#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2561#define ACTHD_I965 _MMIO(0x2074)
2562#define HWS_PGA _MMIO(0x2080)
2563#define HWS_ADDRESS_MASK 0xfffff000
2564#define HWS_START_ADDRESS_SHIFT 4
2565#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2566#define PWRCTX_EN (1 << 0)
2567#define IPEIR(base) _MMIO((base) + 0x88)
2568#define IPEHR(base) _MMIO((base) + 0x8c)
2569#define GEN2_INSTDONE _MMIO(0x2090)
2570#define NOPID _MMIO(0x2094)
2571#define HWSTAM _MMIO(0x2098)
2572#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
2573#define RING_BBSTATE(base) _MMIO((base) + 0x110)
2574#define RING_BB_PPGTT (1 << 5)
2575#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2576#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2577#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2578#define RING_BBADDR(base) _MMIO((base) + 0x140)
2579#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2580#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2581#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2582#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2583#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
2584
2585#define ERROR_GEN6 _MMIO(0x40a0)
2586#define GEN7_ERR_INT _MMIO(0x44040)
2587#define ERR_INT_POISON (1 << 31)
2588#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2589#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2590#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2591#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2592#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2593#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2594#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2595#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2596#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2597
2598#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2599#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2600#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
2601#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
2602#define FAULT_VA_HIGH_BITS (0xf << 0)
2603#define FAULT_GTT_SEL (1 << 4)
2604
2605#define FPGA_DBG _MMIO(0x42300)
2606#define FPGA_DBG_RM_NOCLAIM (1 << 31)
2607
2608#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2609#define CLAIM_ER_CLR (1 << 31)
2610#define CLAIM_ER_OVERFLOW (1 << 16)
2611#define CLAIM_ER_CTR_MASK 0xffff
2612
2613#define DERRMR _MMIO(0x44050)
2614/* Note that HBLANK events are reserved on bdw+ */
2615#define DERRMR_PIPEA_SCANLINE (1 << 0)
2616#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2617#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2618#define DERRMR_PIPEA_VBLANK (1 << 3)
2619#define DERRMR_PIPEA_HBLANK (1 << 5)
2620#define DERRMR_PIPEB_SCANLINE (1 << 8)
2621#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2622#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2623#define DERRMR_PIPEB_VBLANK (1 << 11)
2624#define DERRMR_PIPEB_HBLANK (1 << 13)
2625/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2626#define DERRMR_PIPEC_SCANLINE (1 << 14)
2627#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2628#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2629#define DERRMR_PIPEC_VBLANK (1 << 21)
2630#define DERRMR_PIPEC_HBLANK (1 << 22)
2631
2632
2633/* GM45+ chicken bits -- debug workaround bits that may be required
2634 * for various sorts of correct behavior. The top 16 bits of each are
2635 * the enables for writing to the corresponding low bit.
2636 */
2637#define _3D_CHICKEN _MMIO(0x2084)
2638#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2639#define _3D_CHICKEN2 _MMIO(0x208c)
2640
2641#define FF_SLICE_CHICKEN _MMIO(0x2088)
2642#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2643
2644/* Disables pipelining of read flushes past the SF-WIZ interface.
2645 * Required on all Ironlake steppings according to the B-Spec, but the
2646 * particular danger of not doing so is not specified.
2647 */
2648# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2649#define _3D_CHICKEN3 _MMIO(0x2090)
2650#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2651#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2652#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2653#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2654#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
2655#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2656
2657#define MI_MODE _MMIO(0x209c)
2658# define VS_TIMER_DISPATCH (1 << 6)
2659# define MI_FLUSH_ENABLE (1 << 12)
2660# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2661# define MODE_IDLE (1 << 9)
2662# define STOP_RING (1 << 8)
2663
2664#define GEN6_GT_MODE _MMIO(0x20d0)
2665#define GEN7_GT_MODE _MMIO(0x7008)
2666#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2667#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2668#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2669#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2670#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2671#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2672#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2673#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2674
2675/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2676#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2677#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2678#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2679
2680/* WaClearTdlStateAckDirtyBits */
2681#define GEN8_STATE_ACK _MMIO(0x20F0)
2682#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2683#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2684#define GEN9_STATE_ACK_TDL0 (1 << 12)
2685#define GEN9_STATE_ACK_TDL1 (1 << 13)
2686#define GEN9_STATE_ACK_TDL2 (1 << 14)
2687#define GEN9_STATE_ACK_TDL3 (1 << 15)
2688#define GEN9_SUBSLICE_TDL_ACK_BITS \
2689 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2690 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2691
2692#define GFX_MODE _MMIO(0x2520)
2693#define GFX_MODE_GEN7 _MMIO(0x229c)
2694#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
2695#define GFX_RUN_LIST_ENABLE (1 << 15)
2696#define GFX_INTERRUPT_STEERING (1 << 14)
2697#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2698#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2699#define GFX_REPLAY_MODE (1 << 11)
2700#define GFX_PSMI_GRANULARITY (1 << 10)
2701#define GFX_PPGTT_ENABLE (1 << 9)
2702#define GEN8_GFX_PPGTT_48B (1 << 7)
2703
2704#define GFX_FORWARD_VBLANK_MASK (3 << 5)
2705#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2706#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2707#define GFX_FORWARD_VBLANK_COND (2 << 5)
2708
2709#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2710
2711#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2712#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2713#define SCPD0 _MMIO(0x209c) /* 915+ only */
2714#define GEN2_IER _MMIO(0x20a0)
2715#define GEN2_IIR _MMIO(0x20a4)
2716#define GEN2_IMR _MMIO(0x20a8)
2717#define GEN2_ISR _MMIO(0x20ac)
2718#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2719#define GINT_DIS (1 << 22)
2720#define GCFG_DIS (1 << 8)
2721#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2722#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2723#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2724#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2725#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2726#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2727#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2728#define VLV_PCBR_ADDR_SHIFT 12
2729
2730#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2731#define EIR _MMIO(0x20b0)
2732#define EMR _MMIO(0x20b4)
2733#define ESR _MMIO(0x20b8)
2734#define GM45_ERROR_PAGE_TABLE (1 << 5)
2735#define GM45_ERROR_MEM_PRIV (1 << 4)
2736#define I915_ERROR_PAGE_TABLE (1 << 4)
2737#define GM45_ERROR_CP_PRIV (1 << 3)
2738#define I915_ERROR_MEMORY_REFRESH (1 << 1)
2739#define I915_ERROR_INSTRUCTION (1 << 0)
2740#define INSTPM _MMIO(0x20c0)
2741#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
2742#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2743 will not assert AGPBUSY# and will only
2744 be delivered when out of C3. */
2745#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2746#define INSTPM_TLB_INVALIDATE (1 << 9)
2747#define INSTPM_SYNC_FLUSH (1 << 5)
2748#define ACTHD(base) _MMIO((base) + 0xc8)
2749#define MEM_MODE _MMIO(0x20cc)
2750#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2751#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2752#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2753#define FW_BLC _MMIO(0x20d8)
2754#define FW_BLC2 _MMIO(0x20dc)
2755#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2756#define FW_BLC_SELF_EN_MASK (1 << 31)
2757#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
2758#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
2759#define MM_BURST_LENGTH 0x00700000
2760#define MM_FIFO_WATERMARK 0x0001F000
2761#define LM_BURST_LENGTH 0x00000700
2762#define LM_FIFO_WATERMARK 0x0000001F
2763#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2764
2765#define MBUS_ABOX_CTL _MMIO(0x45038)
2766#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2767#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2768#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2769#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2770#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2771#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2772#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2773#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2774
2775#define _PIPEA_MBUS_DBOX_CTL 0x7003C
2776#define _PIPEB_MBUS_DBOX_CTL 0x7103C
2777#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2778 _PIPEB_MBUS_DBOX_CTL)
2779#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2780#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2781#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2782#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2783#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2784#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2785
2786#define MBUS_UBOX_CTL _MMIO(0x4503C)
2787#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2788#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2789
2790/* Make render/texture TLB fetches lower priorty than associated data
2791 * fetches. This is not turned on by default
2792 */
2793#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2794
2795/* Isoch request wait on GTT enable (Display A/B/C streams).
2796 * Make isoch requests stall on the TLB update. May cause
2797 * display underruns (test mode only)
2798 */
2799#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2800
2801/* Block grant count for isoch requests when block count is
2802 * set to a finite value.
2803 */
2804#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2805#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2806#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2807#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2808#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2809
2810/* Enable render writes to complete in C2/C3/C4 power states.
2811 * If this isn't enabled, render writes are prevented in low
2812 * power states. That seems bad to me.
2813 */
2814#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2815
2816/* This acknowledges an async flip immediately instead
2817 * of waiting for 2TLB fetches.
2818 */
2819#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2820
2821/* Enables non-sequential data reads through arbiter
2822 */
2823#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2824
2825/* Disable FSB snooping of cacheable write cycles from binner/render
2826 * command stream
2827 */
2828#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2829
2830/* Arbiter time slice for non-isoch streams */
2831#define MI_ARB_TIME_SLICE_MASK (7 << 5)
2832#define MI_ARB_TIME_SLICE_1 (0 << 5)
2833#define MI_ARB_TIME_SLICE_2 (1 << 5)
2834#define MI_ARB_TIME_SLICE_4 (2 << 5)
2835#define MI_ARB_TIME_SLICE_6 (3 << 5)
2836#define MI_ARB_TIME_SLICE_8 (4 << 5)
2837#define MI_ARB_TIME_SLICE_10 (5 << 5)
2838#define MI_ARB_TIME_SLICE_14 (6 << 5)
2839#define MI_ARB_TIME_SLICE_16 (7 << 5)
2840
2841/* Low priority grace period page size */
2842#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2843#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2844
2845/* Disable display A/B trickle feed */
2846#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2847
2848/* Set display plane priority */
2849#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2850#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2851
2852#define MI_STATE _MMIO(0x20e4) /* gen2 only */
2853#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2854#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2855
2856#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2857#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2858#define CM0_IZ_OPT_DISABLE (1 << 6)
2859#define CM0_ZR_OPT_DISABLE (1 << 5)
2860#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2861#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
2862#define CM0_COLOR_EVICT_DISABLE (1 << 3)
2863#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
2864#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2865#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2866#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2867#define GFX_FLSH_CNTL_EN (1 << 0)
2868#define ECOSKPD _MMIO(0x21d0)
2869#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
2870#define ECO_GATING_CX_ONLY (1 << 3)
2871#define ECO_FLIP_DONE (1 << 0)
2872
2873#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2874#define RC_OP_FLUSH_ENABLE (1 << 0)
2875#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2876#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2877#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
2878#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
2879#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
2880
2881#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2882#define GEN6_BLITTER_LOCK_SHIFT 16
2883#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
2884
2885#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2886#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2887#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2888#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
2889
2890#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2891#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2892
2893#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
2894#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
2895
2896/* Fuse readout registers for GT */
2897#define HSW_PAVP_FUSE1 _MMIO(0x911C)
2898#define HSW_F1_EU_DIS_SHIFT 16
2899#define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2900#define HSW_F1_EU_DIS_10EUS 0
2901#define HSW_F1_EU_DIS_8EUS 1
2902#define HSW_F1_EU_DIS_6EUS 2
2903
2904#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2905#define CHV_FGT_DISABLE_SS0 (1 << 10)
2906#define CHV_FGT_DISABLE_SS1 (1 << 11)
2907#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2908#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2909#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2910#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2911#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2912#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2913#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2914#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2915
2916#define GEN8_FUSE2 _MMIO(0x9120)
2917#define GEN8_F2_SS_DIS_SHIFT 21
2918#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2919#define GEN8_F2_S_ENA_SHIFT 25
2920#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2921
2922#define GEN9_F2_SS_DIS_SHIFT 20
2923#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2924
2925#define GEN10_F2_S_ENA_SHIFT 22
2926#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2927#define GEN10_F2_SS_DIS_SHIFT 18
2928#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2929
2930#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
2931#define GEN10_L3BANK_PAIR_COUNT 4
2932#define GEN10_L3BANK_MASK 0x0F
2933
2934#define GEN8_EU_DISABLE0 _MMIO(0x9134)
2935#define GEN8_EU_DIS0_S0_MASK 0xffffff
2936#define GEN8_EU_DIS0_S1_SHIFT 24
2937#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2938
2939#define GEN8_EU_DISABLE1 _MMIO(0x9138)
2940#define GEN8_EU_DIS1_S1_MASK 0xffff
2941#define GEN8_EU_DIS1_S2_SHIFT 16
2942#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2943
2944#define GEN8_EU_DISABLE2 _MMIO(0x913c)
2945#define GEN8_EU_DIS2_S2_MASK 0xff
2946
2947#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
2948
2949#define GEN10_EU_DISABLE3 _MMIO(0x9140)
2950#define GEN10_EU_DIS_SS_MASK 0xff
2951
2952#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2953#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2954#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2955#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
2956
2957#define GEN11_EU_DISABLE _MMIO(0x9134)
2958#define GEN11_EU_DIS_MASK 0xFF
2959
2960#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2961#define GEN11_GT_S_ENA_MASK 0xFF
2962
2963#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2964
2965#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2966#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2967#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2968#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2969#define GEN6_BSD_GO_INDICATOR (1 << 4)
2970
2971/* On modern GEN architectures interrupt control consists of two sets
2972 * of registers. The first set pertains to the ring generating the
2973 * interrupt. The second control is for the functional block generating the
2974 * interrupt. These are PM, GT, DE, etc.
2975 *
2976 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2977 * GT interrupt bits, so we don't need to duplicate the defines.
2978 *
2979 * These defines should cover us well from SNB->HSW with minor exceptions
2980 * it can also work on ILK.
2981 */
2982#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2983#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2984#define GT_BLT_USER_INTERRUPT (1 << 22)
2985#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2986#define GT_BSD_USER_INTERRUPT (1 << 12)
2987#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2988#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2989#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2990#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2991#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2992#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2993#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2994#define GT_RENDER_USER_INTERRUPT (1 << 0)
2995
2996#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2997#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2998
2999#define GT_PARITY_ERROR(dev_priv) \
3000 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3001 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3002
3003/* These are all the "old" interrupts */
3004#define ILK_BSD_USER_INTERRUPT (1 << 5)
3005
3006#define I915_PM_INTERRUPT (1 << 31)
3007#define I915_ISP_INTERRUPT (1 << 22)
3008#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
3009#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
3010#define I915_MIPIC_INTERRUPT (1 << 19)
3011#define I915_MIPIA_INTERRUPT (1 << 18)
3012#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
3013#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
3014#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
3015#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
3016#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
3017#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
3018#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
3019#define I915_HWB_OOM_INTERRUPT (1 << 13)
3020#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
3021#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
3022#define I915_MISC_INTERRUPT (1 << 11)
3023#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
3024#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
3025#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
3026#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
3027#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
3028#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
3029#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
3030#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
3031#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
3032#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
3033#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
3034#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
3035#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
3036#define I915_DEBUG_INTERRUPT (1 << 2)
3037#define I915_WINVALID_INTERRUPT (1 << 1)
3038#define I915_USER_INTERRUPT (1 << 1)
3039#define I915_ASLE_INTERRUPT (1 << 0)
3040#define I915_BSD_USER_INTERRUPT (1 << 25)
3041
3042#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
3043#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
3044
3045/* DisplayPort Audio w/ LPE */
3046#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3047#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
3048
3049#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
3050#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
3051#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3052#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3053 _VLV_AUD_PORT_EN_B_DBG, \
3054 _VLV_AUD_PORT_EN_C_DBG, \
3055 _VLV_AUD_PORT_EN_D_DBG)
3056#define VLV_AMP_MUTE (1 << 1)
3057
3058#define GEN6_BSD_RNCID _MMIO(0x12198)
3059
3060#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
3061#define GEN7_FF_SCHED_MASK 0x0077070
3062#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
3063#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
3064#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
3065#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3066#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
3067#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
3068#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
3069#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
3070#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
3071#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
3072#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
3073#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
3074#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
3075#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
3076
3077/*
3078 * Framebuffer compression (915+ only)
3079 */
3080
3081#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
3082#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
3083#define FBC_CONTROL _MMIO(0x3208)
3084#define FBC_CTL_EN (1 << 31)
3085#define FBC_CTL_PERIODIC (1 << 30)
3086#define FBC_CTL_INTERVAL_SHIFT (16)
3087#define FBC_CTL_UNCOMPRESSIBLE (1 << 14)
3088#define FBC_CTL_C3_IDLE (1 << 13)
3089#define FBC_CTL_STRIDE_SHIFT (5)
3090#define FBC_CTL_FENCENO_SHIFT (0)
3091#define FBC_COMMAND _MMIO(0x320c)
3092#define FBC_CMD_COMPRESS (1 << 0)
3093#define FBC_STATUS _MMIO(0x3210)
3094#define FBC_STAT_COMPRESSING (1 << 31)
3095#define FBC_STAT_COMPRESSED (1 << 30)
3096#define FBC_STAT_MODIFIED (1 << 29)
3097#define FBC_STAT_CURRENT_LINE_SHIFT (0)
3098#define FBC_CONTROL2 _MMIO(0x3214)
3099#define FBC_CTL_FENCE_DBL (0 << 4)
3100#define FBC_CTL_IDLE_IMM (0 << 2)
3101#define FBC_CTL_IDLE_FULL (1 << 2)
3102#define FBC_CTL_IDLE_LINE (2 << 2)
3103#define FBC_CTL_IDLE_DEBUG (3 << 2)
3104#define FBC_CTL_CPU_FENCE (1 << 1)
3105#define FBC_CTL_PLANE(plane) ((plane) << 0)
3106#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3107#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3108
3109#define FBC_LL_SIZE (1536)
3110
3111#define FBC_LLC_READ_CTRL _MMIO(0x9044)
3112#define FBC_LLC_FULLY_OPEN (1 << 30)
3113
3114/* Framebuffer compression for GM45+ */
3115#define DPFC_CB_BASE _MMIO(0x3200)
3116#define DPFC_CONTROL _MMIO(0x3208)
3117#define DPFC_CTL_EN (1 << 31)
3118#define DPFC_CTL_PLANE(plane) ((plane) << 30)
3119#define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
3120#define DPFC_CTL_FENCE_EN (1 << 29)
3121#define IVB_DPFC_CTL_FENCE_EN (1 << 28)
3122#define DPFC_CTL_PERSISTENT_MODE (1 << 25)
3123#define DPFC_SR_EN (1 << 10)
3124#define DPFC_CTL_LIMIT_1X (0 << 6)
3125#define DPFC_CTL_LIMIT_2X (1 << 6)
3126#define DPFC_CTL_LIMIT_4X (2 << 6)
3127#define DPFC_RECOMP_CTL _MMIO(0x320c)
3128#define DPFC_RECOMP_STALL_EN (1 << 27)
3129#define DPFC_RECOMP_STALL_WM_SHIFT (16)
3130#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3131#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3132#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3133#define DPFC_STATUS _MMIO(0x3210)
3134#define DPFC_INVAL_SEG_SHIFT (16)
3135#define DPFC_INVAL_SEG_MASK (0x07ff0000)
3136#define DPFC_COMP_SEG_SHIFT (0)
3137#define DPFC_COMP_SEG_MASK (0x000007ff)
3138#define DPFC_STATUS2 _MMIO(0x3214)
3139#define DPFC_FENCE_YOFF _MMIO(0x3218)
3140#define DPFC_CHICKEN _MMIO(0x3224)
3141#define DPFC_HT_MODIFY (1 << 31)
3142
3143/* Framebuffer compression for Ironlake */
3144#define ILK_DPFC_CB_BASE _MMIO(0x43200)
3145#define ILK_DPFC_CONTROL _MMIO(0x43208)
3146#define FBC_CTL_FALSE_COLOR (1 << 10)
3147/* The bit 28-8 is reserved */
3148#define DPFC_RESERVED (0x1FFFFF00)
3149#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3150#define ILK_DPFC_STATUS _MMIO(0x43210)
3151#define ILK_DPFC_COMP_SEG_MASK 0x7ff
3152#define IVB_FBC_STATUS2 _MMIO(0x43214)
3153#define IVB_FBC_COMP_SEG_MASK 0x7ff
3154#define BDW_FBC_COMP_SEG_MASK 0xfff
3155#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3156#define ILK_DPFC_CHICKEN _MMIO(0x43224)
3157#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3158#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
3159#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3160#define ILK_FBC_RT_BASE _MMIO(0x2128)
3161#define ILK_FBC_RT_VALID (1 << 0)
3162#define SNB_FBC_FRONT_BUFFER (1 << 1)
3163
3164#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3165#define ILK_FBCQ_DIS (1 << 22)
3166#define ILK_PABSTRETCH_DIS (1 << 21)
3167
3168
3169/*
3170 * Framebuffer compression for Sandybridge
3171 *
3172 * The following two registers are of type GTTMMADR
3173 */
3174#define SNB_DPFC_CTL_SA _MMIO(0x100100)
3175#define SNB_CPU_FENCE_ENABLE (1 << 29)
3176#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3177
3178/* Framebuffer compression for Ivybridge */
3179#define IVB_FBC_RT_BASE _MMIO(0x7020)
3180
3181#define IPS_CTL _MMIO(0x43408)
3182#define IPS_ENABLE (1 << 31)
3183
3184#define MSG_FBC_REND_STATE _MMIO(0x50380)
3185#define FBC_REND_NUKE (1 << 2)
3186#define FBC_REND_CACHE_CLEAN (1 << 1)
3187
3188/*
3189 * GPIO regs
3190 */
3191#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3192 4 * (gpio))
3193
3194# define GPIO_CLOCK_DIR_MASK (1 << 0)
3195# define GPIO_CLOCK_DIR_IN (0 << 1)
3196# define GPIO_CLOCK_DIR_OUT (1 << 1)
3197# define GPIO_CLOCK_VAL_MASK (1 << 2)
3198# define GPIO_CLOCK_VAL_OUT (1 << 3)
3199# define GPIO_CLOCK_VAL_IN (1 << 4)
3200# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3201# define GPIO_DATA_DIR_MASK (1 << 8)
3202# define GPIO_DATA_DIR_IN (0 << 9)
3203# define GPIO_DATA_DIR_OUT (1 << 9)
3204# define GPIO_DATA_VAL_MASK (1 << 10)
3205# define GPIO_DATA_VAL_OUT (1 << 11)
3206# define GPIO_DATA_VAL_IN (1 << 12)
3207# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3208
3209#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3210#define GMBUS_AKSV_SELECT (1 << 11)
3211#define GMBUS_RATE_100KHZ (0 << 8)
3212#define GMBUS_RATE_50KHZ (1 << 8)
3213#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
3214#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3215#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
3216#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3217
3218#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3219#define GMBUS_SW_CLR_INT (1 << 31)
3220#define GMBUS_SW_RDY (1 << 30)
3221#define GMBUS_ENT (1 << 29) /* enable timeout */
3222#define GMBUS_CYCLE_NONE (0 << 25)
3223#define GMBUS_CYCLE_WAIT (1 << 25)
3224#define GMBUS_CYCLE_INDEX (2 << 25)
3225#define GMBUS_CYCLE_STOP (4 << 25)
3226#define GMBUS_BYTE_COUNT_SHIFT 16
3227#define GMBUS_BYTE_COUNT_MAX 256U
3228#define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3229#define GMBUS_SLAVE_INDEX_SHIFT 8
3230#define GMBUS_SLAVE_ADDR_SHIFT 1
3231#define GMBUS_SLAVE_READ (1 << 0)
3232#define GMBUS_SLAVE_WRITE (0 << 0)
3233#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3234#define GMBUS_INUSE (1 << 15)
3235#define GMBUS_HW_WAIT_PHASE (1 << 14)
3236#define GMBUS_STALL_TIMEOUT (1 << 13)
3237#define GMBUS_INT (1 << 12)
3238#define GMBUS_HW_RDY (1 << 11)
3239#define GMBUS_SATOER (1 << 10)
3240#define GMBUS_ACTIVE (1 << 9)
3241#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3242#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3243#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3244#define GMBUS_NAK_EN (1 << 3)
3245#define GMBUS_IDLE_EN (1 << 2)
3246#define GMBUS_HW_WAIT_EN (1 << 1)
3247#define GMBUS_HW_RDY_EN (1 << 0)
3248#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3249#define GMBUS_2BYTE_INDEX_EN (1 << 31)
3250
3251/*
3252 * Clock control & power management
3253 */
3254#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3255#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3256#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3257#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3258
3259#define VGA0 _MMIO(0x6000)
3260#define VGA1 _MMIO(0x6004)
3261#define VGA_PD _MMIO(0x6010)
3262#define VGA0_PD_P2_DIV_4 (1 << 7)
3263#define VGA0_PD_P1_DIV_2 (1 << 5)
3264#define VGA0_PD_P1_SHIFT 0
3265#define VGA0_PD_P1_MASK (0x1f << 0)
3266#define VGA1_PD_P2_DIV_4 (1 << 15)
3267#define VGA1_PD_P1_DIV_2 (1 << 13)
3268#define VGA1_PD_P1_SHIFT 8
3269#define VGA1_PD_P1_MASK (0x1f << 8)
3270#define DPLL_VCO_ENABLE (1 << 31)
3271#define DPLL_SDVO_HIGH_SPEED (1 << 30)
3272#define DPLL_DVO_2X_MODE (1 << 30)
3273#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3274#define DPLL_SYNCLOCK_ENABLE (1 << 29)
3275#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3276#define DPLL_VGA_MODE_DIS (1 << 28)
3277#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3278#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3279#define DPLL_MODE_MASK (3 << 26)
3280#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3281#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3282#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3283#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3284#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3285#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3286#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3287#define DPLL_LOCK_VLV (1 << 15)
3288#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3289#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3290#define DPLL_SSC_REF_CLK_CHV (1 << 13)
3291#define DPLL_PORTC_READY_MASK (0xf << 4)
3292#define DPLL_PORTB_READY_MASK (0xf)
3293
3294#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3295
3296/* Additional CHV pll/phy registers */
3297#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3298#define DPLL_PORTD_READY_MASK (0xf)
3299#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3300#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3301#define PHY_LDO_DELAY_0NS 0x0
3302#define PHY_LDO_DELAY_200NS 0x1
3303#define PHY_LDO_DELAY_600NS 0x2
3304#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3305#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3306#define PHY_CH_SU_PSR 0x1
3307#define PHY_CH_DEEP_PSR 0x7
3308#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3309#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3310#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3311#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3312#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3313#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3314
3315/*
3316 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3317 * this field (only one bit may be set).
3318 */
3319#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3320#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3321#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3322/* i830, required in DVO non-gang */
3323#define PLL_P2_DIVIDE_BY_4 (1 << 23)
3324#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3325#define PLL_REF_INPUT_DREFCLK (0 << 13)
3326#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3327#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3328#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3329#define PLL_REF_INPUT_MASK (3 << 13)
3330#define PLL_LOAD_PULSE_PHASE_SHIFT 9
3331/* Ironlake */
3332# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3333# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3334# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3335# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3336# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3337
3338/*
3339 * Parallel to Serial Load Pulse phase selection.
3340 * Selects the phase for the 10X DPLL clock for the PCIe
3341 * digital display port. The range is 4 to 13; 10 or more
3342 * is just a flip delay. The default is 6
3343 */
3344#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3345#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3346/*
3347 * SDVO multiplier for 945G/GM. Not used on 965.
3348 */
3349#define SDVO_MULTIPLIER_MASK 0x000000ff
3350#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3351#define SDVO_MULTIPLIER_SHIFT_VGA 0
3352
3353#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3354#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3355#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3356#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3357
3358/*
3359 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3360 *
3361 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3362 */
3363#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3364#define DPLL_MD_UDI_DIVIDER_SHIFT 24
3365/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3366#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3367#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3368/*
3369 * SDVO/UDI pixel multiplier.
3370 *
3371 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3372 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3373 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3374 * dummy bytes in the datastream at an increased clock rate, with both sides of
3375 * the link knowing how many bytes are fill.
3376 *
3377 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3378 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3379 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3380 * through an SDVO command.
3381 *
3382 * This register field has values of multiplication factor minus 1, with
3383 * a maximum multiplier of 5 for SDVO.
3384 */
3385#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3386#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3387/*
3388 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3389 * This best be set to the default value (3) or the CRT won't work. No,
3390 * I don't entirely understand what this does...
3391 */
3392#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3393#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3394
3395#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3396
3397#define _FPA0 0x6040
3398#define _FPA1 0x6044
3399#define _FPB0 0x6048
3400#define _FPB1 0x604c
3401#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3402#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3403#define FP_N_DIV_MASK 0x003f0000
3404#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3405#define FP_N_DIV_SHIFT 16
3406#define FP_M1_DIV_MASK 0x00003f00
3407#define FP_M1_DIV_SHIFT 8
3408#define FP_M2_DIV_MASK 0x0000003f
3409#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3410#define FP_M2_DIV_SHIFT 0
3411#define DPLL_TEST _MMIO(0x606c)
3412#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3413#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3414#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3415#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3416#define DPLLB_TEST_N_BYPASS (1 << 19)
3417#define DPLLB_TEST_M_BYPASS (1 << 18)
3418#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3419#define DPLLA_TEST_N_BYPASS (1 << 3)
3420#define DPLLA_TEST_M_BYPASS (1 << 2)
3421#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3422#define D_STATE _MMIO(0x6104)
3423#define DSTATE_GFX_RESET_I830 (1 << 6)
3424#define DSTATE_PLL_D3_OFF (1 << 3)
3425#define DSTATE_GFX_CLOCK_GATING (1 << 1)
3426#define DSTATE_DOT_CLOCK_GATING (1 << 0)
3427#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3428# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3429# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3430# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3431# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3432# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3433# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3434# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3435# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3436# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3437# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3438# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3439# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3440# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3441# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3442# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3443# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3444# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3445# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3446# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3447# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3448# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3449# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3450# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3451# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3452# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3453# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3454# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3455# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3456# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3457/*
3458 * This bit must be set on the 830 to prevent hangs when turning off the
3459 * overlay scaler.
3460 */
3461# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3462# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3463# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3464# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3465# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3466
3467#define RENCLK_GATE_D1 _MMIO(0x6204)
3468# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3469# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3470# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3471# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3472# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3473# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3474# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3475# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3476# define MAG_CLOCK_GATE_DISABLE (1 << 5)
3477/* This bit must be unset on 855,865 */
3478# define MECI_CLOCK_GATE_DISABLE (1 << 4)
3479# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3480# define MEC_CLOCK_GATE_DISABLE (1 << 2)
3481# define MECO_CLOCK_GATE_DISABLE (1 << 1)
3482/* This bit must be set on 855,865. */
3483# define SV_CLOCK_GATE_DISABLE (1 << 0)
3484# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3485# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3486# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3487# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3488# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3489# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3490# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3491# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3492# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3493# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3494# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3495# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3496# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3497# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3498# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3499# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3500# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3501
3502# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3503/* This bit must always be set on 965G/965GM */
3504# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3505# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3506# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3507# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3508# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3509# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3510/* This bit must always be set on 965G */
3511# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3512# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3513# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3514# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3515# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3516# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3517# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3518# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3519# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3520# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3521# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3522# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3523# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3524# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3525# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3526# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3527# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3528# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3529# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3530
3531#define RENCLK_GATE_D2 _MMIO(0x6208)
3532#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3533#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3534#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3535
3536#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3537#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3538
3539#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3540#define DEUC _MMIO(0x6214) /* CRL only */
3541
3542#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3543#define FW_CSPWRDWNEN (1 << 15)
3544
3545#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3546
3547#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3548#define CDCLK_FREQ_SHIFT 4
3549#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3550#define CZCLK_FREQ_MASK 0xf
3551
3552#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3553#define PFI_CREDIT_63 (9 << 28) /* chv only */
3554#define PFI_CREDIT_31 (8 << 28) /* chv only */
3555#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3556#define PFI_CREDIT_RESEND (1 << 27)
3557#define VGA_FAST_MODE_DISABLE (1 << 14)
3558
3559#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3560
3561/*
3562 * Palette regs
3563 */
3564#define _PALETTE_A 0xa000
3565#define _PALETTE_B 0xa800
3566#define _CHV_PALETTE_C 0xc000
3567#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3568 _PICK((pipe), _PALETTE_A, \
3569 _PALETTE_B, _CHV_PALETTE_C) + \
3570 (i) * 4)
3571
3572/* MCH MMIO space */
3573
3574/*
3575 * MCHBAR mirror.
3576 *
3577 * This mirrors the MCHBAR MMIO space whose location is determined by
3578 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3579 * every way. It is not accessible from the CP register read instructions.
3580 *
3581 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3582 * just read.
3583 */
3584#define MCHBAR_MIRROR_BASE 0x10000
3585
3586#define MCHBAR_MIRROR_BASE_SNB 0x140000
3587
3588#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3589#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3590#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3591#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3592#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3593
3594/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3595#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3596
3597/* 915-945 and GM965 MCH register controlling DRAM channel access */
3598#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3599#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3600#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3601#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3602#define DCC_ADDRESSING_MODE_MASK (3 << 0)
3603#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3604#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3605#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3606#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3607
3608/* Pineview MCH register contains DDR3 setting */
3609#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3610#define CSHRDDR3CTL_DDR3 (1 << 2)
3611
3612/* 965 MCH register controlling DRAM channel configuration */
3613#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3614#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3615
3616/* snb MCH registers for reading the DRAM channel configuration */
3617#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3618#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3619#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3620#define MAD_DIMM_ECC_MASK (0x3 << 24)
3621#define MAD_DIMM_ECC_OFF (0x0 << 24)
3622#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3623#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3624#define MAD_DIMM_ECC_ON (0x3 << 24)
3625#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3626#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3627#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3628#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3629#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3630#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3631#define MAD_DIMM_A_SELECT (0x1 << 16)
3632/* DIMM sizes are in multiples of 256mb. */
3633#define MAD_DIMM_B_SIZE_SHIFT 8
3634#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3635#define MAD_DIMM_A_SIZE_SHIFT 0
3636#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3637
3638/* snb MCH registers for priority tuning */
3639#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3640#define MCH_SSKPD_WM0_MASK 0x3f
3641#define MCH_SSKPD_WM0_VAL 0xc
3642
3643#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3644
3645/* Clocking configuration register */
3646#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3647#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3648#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3649#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3650#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3651#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3652#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3653#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3654/*
3655 * Note that on at least on ELK the below value is reported for both
3656 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3657 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3658 */
3659#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3660#define CLKCFG_FSB_MASK (7 << 0)
3661#define CLKCFG_MEM_533 (1 << 4)
3662#define CLKCFG_MEM_667 (2 << 4)
3663#define CLKCFG_MEM_800 (3 << 4)
3664#define CLKCFG_MEM_MASK (7 << 4)
3665
3666#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3667#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3668
3669#define TSC1 _MMIO(0x11001)
3670#define TSE (1 << 0)
3671#define TR1 _MMIO(0x11006)
3672#define TSFS _MMIO(0x11020)
3673#define TSFS_SLOPE_MASK 0x0000ff00
3674#define TSFS_SLOPE_SHIFT 8
3675#define TSFS_INTR_MASK 0x000000ff
3676
3677#define CRSTANDVID _MMIO(0x11100)
3678#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3679#define PXVFREQ_PX_MASK 0x7f000000
3680#define PXVFREQ_PX_SHIFT 24
3681#define VIDFREQ_BASE _MMIO(0x11110)
3682#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3683#define VIDFREQ2 _MMIO(0x11114)
3684#define VIDFREQ3 _MMIO(0x11118)
3685#define VIDFREQ4 _MMIO(0x1111c)
3686#define VIDFREQ_P0_MASK 0x1f000000
3687#define VIDFREQ_P0_SHIFT 24
3688#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3689#define VIDFREQ_P0_CSCLK_SHIFT 20
3690#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3691#define VIDFREQ_P0_CRCLK_SHIFT 16
3692#define VIDFREQ_P1_MASK 0x00001f00
3693#define VIDFREQ_P1_SHIFT 8
3694#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3695#define VIDFREQ_P1_CSCLK_SHIFT 4
3696#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3697#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3698#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3699#define INTTOEXT_MAP3_SHIFT 24
3700#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3701#define INTTOEXT_MAP2_SHIFT 16
3702#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3703#define INTTOEXT_MAP1_SHIFT 8
3704#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3705#define INTTOEXT_MAP0_SHIFT 0
3706#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3707#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3708#define MEMCTL_CMD_MASK 0xe000
3709#define MEMCTL_CMD_SHIFT 13
3710#define MEMCTL_CMD_RCLK_OFF 0
3711#define MEMCTL_CMD_RCLK_ON 1
3712#define MEMCTL_CMD_CHFREQ 2
3713#define MEMCTL_CMD_CHVID 3
3714#define MEMCTL_CMD_VMMOFF 4
3715#define MEMCTL_CMD_VMMON 5
3716#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
3717 when command complete */
3718#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3719#define MEMCTL_FREQ_SHIFT 8
3720#define MEMCTL_SFCAVM (1 << 7)
3721#define MEMCTL_TGT_VID_MASK 0x007f
3722#define MEMIHYST _MMIO(0x1117c)
3723#define MEMINTREN _MMIO(0x11180) /* 16 bits */
3724#define MEMINT_RSEXIT_EN (1 << 8)
3725#define MEMINT_CX_SUPR_EN (1 << 7)
3726#define MEMINT_CONT_BUSY_EN (1 << 6)
3727#define MEMINT_AVG_BUSY_EN (1 << 5)
3728#define MEMINT_EVAL_CHG_EN (1 << 4)
3729#define MEMINT_MON_IDLE_EN (1 << 3)
3730#define MEMINT_UP_EVAL_EN (1 << 2)
3731#define MEMINT_DOWN_EVAL_EN (1 << 1)
3732#define MEMINT_SW_CMD_EN (1 << 0)
3733#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3734#define MEM_RSEXIT_MASK 0xc000
3735#define MEM_RSEXIT_SHIFT 14
3736#define MEM_CONT_BUSY_MASK 0x3000
3737#define MEM_CONT_BUSY_SHIFT 12
3738#define MEM_AVG_BUSY_MASK 0x0c00
3739#define MEM_AVG_BUSY_SHIFT 10
3740#define MEM_EVAL_CHG_MASK 0x0300
3741#define MEM_EVAL_BUSY_SHIFT 8
3742#define MEM_MON_IDLE_MASK 0x00c0
3743#define MEM_MON_IDLE_SHIFT 6
3744#define MEM_UP_EVAL_MASK 0x0030
3745#define MEM_UP_EVAL_SHIFT 4
3746#define MEM_DOWN_EVAL_MASK 0x000c
3747#define MEM_DOWN_EVAL_SHIFT 2
3748#define MEM_SW_CMD_MASK 0x0003
3749#define MEM_INT_STEER_GFX 0
3750#define MEM_INT_STEER_CMR 1
3751#define MEM_INT_STEER_SMI 2
3752#define MEM_INT_STEER_SCI 3
3753#define MEMINTRSTS _MMIO(0x11184)
3754#define MEMINT_RSEXIT (1 << 7)
3755#define MEMINT_CONT_BUSY (1 << 6)
3756#define MEMINT_AVG_BUSY (1 << 5)
3757#define MEMINT_EVAL_CHG (1 << 4)
3758#define MEMINT_MON_IDLE (1 << 3)
3759#define MEMINT_UP_EVAL (1 << 2)
3760#define MEMINT_DOWN_EVAL (1 << 1)
3761#define MEMINT_SW_CMD (1 << 0)
3762#define MEMMODECTL _MMIO(0x11190)
3763#define MEMMODE_BOOST_EN (1 << 31)
3764#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3765#define MEMMODE_BOOST_FREQ_SHIFT 24
3766#define MEMMODE_IDLE_MODE_MASK 0x00030000
3767#define MEMMODE_IDLE_MODE_SHIFT 16
3768#define MEMMODE_IDLE_MODE_EVAL 0
3769#define MEMMODE_IDLE_MODE_CONT 1
3770#define MEMMODE_HWIDLE_EN (1 << 15)
3771#define MEMMODE_SWMODE_EN (1 << 14)
3772#define MEMMODE_RCLK_GATE (1 << 13)
3773#define MEMMODE_HW_UPDATE (1 << 12)
3774#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3775#define MEMMODE_FSTART_SHIFT 8
3776#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3777#define MEMMODE_FMAX_SHIFT 4
3778#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3779#define RCBMAXAVG _MMIO(0x1119c)
3780#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3781#define SWMEMCMD_RENDER_OFF (0 << 13)
3782#define SWMEMCMD_RENDER_ON (1 << 13)
3783#define SWMEMCMD_SWFREQ (2 << 13)
3784#define SWMEMCMD_TARVID (3 << 13)
3785#define SWMEMCMD_VRM_OFF (4 << 13)
3786#define SWMEMCMD_VRM_ON (5 << 13)
3787#define CMDSTS (1 << 12)
3788#define SFCAVM (1 << 11)
3789#define SWFREQ_MASK 0x0380 /* P0-7 */
3790#define SWFREQ_SHIFT 7
3791#define TARVID_MASK 0x001f
3792#define MEMSTAT_CTG _MMIO(0x111a0)
3793#define RCBMINAVG _MMIO(0x111a0)
3794#define RCUPEI _MMIO(0x111b0)
3795#define RCDNEI _MMIO(0x111b4)
3796#define RSTDBYCTL _MMIO(0x111b8)
3797#define RS1EN (1 << 31)
3798#define RS2EN (1 << 30)
3799#define RS3EN (1 << 29)
3800#define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
3801#define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
3802#define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
3803#define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
3804#define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
3805#define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
3806#define RSX_STATUS_MASK (7 << 20)
3807#define RSX_STATUS_ON (0 << 20)
3808#define RSX_STATUS_RC1 (1 << 20)
3809#define RSX_STATUS_RC1E (2 << 20)
3810#define RSX_STATUS_RS1 (3 << 20)
3811#define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
3812#define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
3813#define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
3814#define RSX_STATUS_RSVD2 (7 << 20)
3815#define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
3816#define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
3817#define JRSC (1 << 17) /* rsx coupled to cpu c-state */
3818#define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
3819#define RS1CONTSAV_MASK (3 << 14)
3820#define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
3821#define RS1CONTSAV_RSVD (1 << 14)
3822#define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
3823#define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
3824#define NORMSLEXLAT_MASK (3 << 12)
3825#define SLOW_RS123 (0 << 12)
3826#define SLOW_RS23 (1 << 12)
3827#define SLOW_RS3 (2 << 12)
3828#define NORMAL_RS123 (3 << 12)
3829#define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
3830#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3831#define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3832#define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
3833#define RS_CSTATE_MASK (3 << 4)
3834#define RS_CSTATE_C367_RS1 (0 << 4)
3835#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3836#define RS_CSTATE_RSVD (2 << 4)
3837#define RS_CSTATE_C367_RS2 (3 << 4)
3838#define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
3839#define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
3840#define VIDCTL _MMIO(0x111c0)
3841#define VIDSTS _MMIO(0x111c8)
3842#define VIDSTART _MMIO(0x111cc) /* 8 bits */
3843#define MEMSTAT_ILK _MMIO(0x111f8)
3844#define MEMSTAT_VID_MASK 0x7f00
3845#define MEMSTAT_VID_SHIFT 8
3846#define MEMSTAT_PSTATE_MASK 0x00f8
3847#define MEMSTAT_PSTATE_SHIFT 3
3848#define MEMSTAT_MON_ACTV (1 << 2)
3849#define MEMSTAT_SRC_CTL_MASK 0x0003
3850#define MEMSTAT_SRC_CTL_CORE 0
3851#define MEMSTAT_SRC_CTL_TRB 1
3852#define MEMSTAT_SRC_CTL_THM 2
3853#define MEMSTAT_SRC_CTL_STDBY 3
3854#define RCPREVBSYTUPAVG _MMIO(0x113b8)
3855#define RCPREVBSYTDNAVG _MMIO(0x113bc)
3856#define PMMISC _MMIO(0x11214)
3857#define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
3858#define SDEW _MMIO(0x1124c)
3859#define CSIEW0 _MMIO(0x11250)
3860#define CSIEW1 _MMIO(0x11254)
3861#define CSIEW2 _MMIO(0x11258)
3862#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3863#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3864#define MCHAFE _MMIO(0x112c0)
3865#define CSIEC _MMIO(0x112e0)
3866#define DMIEC _MMIO(0x112e4)
3867#define DDREC _MMIO(0x112e8)
3868#define PEG0EC _MMIO(0x112ec)
3869#define PEG1EC _MMIO(0x112f0)
3870#define GFXEC _MMIO(0x112f4)
3871#define RPPREVBSYTUPAVG _MMIO(0x113b8)
3872#define RPPREVBSYTDNAVG _MMIO(0x113bc)
3873#define ECR _MMIO(0x11600)
3874#define ECR_GPFE (1 << 31)
3875#define ECR_IMONE (1 << 30)
3876#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3877#define OGW0 _MMIO(0x11608)
3878#define OGW1 _MMIO(0x1160c)
3879#define EG0 _MMIO(0x11610)
3880#define EG1 _MMIO(0x11614)
3881#define EG2 _MMIO(0x11618)
3882#define EG3 _MMIO(0x1161c)
3883#define EG4 _MMIO(0x11620)
3884#define EG5 _MMIO(0x11624)
3885#define EG6 _MMIO(0x11628)
3886#define EG7 _MMIO(0x1162c)
3887#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3888#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3889#define LCFUSE02 _MMIO(0x116c0)
3890#define LCFUSE_HIV_MASK 0x000000ff
3891#define CSIPLL0 _MMIO(0x12c10)
3892#define DDRMPLL1 _MMIO(0X12c20)
3893#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3894
3895#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3896#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3897
3898#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3899#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3900#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3901#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3902#define BXT_RP_STATE_CAP _MMIO(0x138170)
3903
3904/*
3905 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3906 * 8300) freezing up around GPU hangs. Looks as if even
3907 * scheduling/timer interrupts start misbehaving if the RPS
3908 * EI/thresholds are "bad", leading to a very sluggish or even
3909 * frozen machine.
3910 */
3911#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3912#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3913#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3914#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3915 (IS_GEN9_LP(dev_priv) ? \
3916 INTERVAL_0_833_US(us) : \
3917 INTERVAL_1_33_US(us)) : \
3918 INTERVAL_1_28_US(us))
3919
3920#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3921#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3922#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3923#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3924 (IS_GEN9_LP(dev_priv) ? \
3925 INTERVAL_0_833_TO_US(interval) : \
3926 INTERVAL_1_33_TO_US(interval)) : \
3927 INTERVAL_1_28_TO_US(interval))
3928
3929/*
3930 * Logical Context regs
3931 */
3932#define CCID(base) _MMIO((base) + 0x180)
3933#define CCID_EN BIT(0)
3934#define CCID_EXTENDED_STATE_RESTORE BIT(2)
3935#define CCID_EXTENDED_STATE_SAVE BIT(3)
3936/*
3937 * Notes on SNB/IVB/VLV context size:
3938 * - Power context is saved elsewhere (LLC or stolen)
3939 * - Ring/execlist context is saved on SNB, not on IVB
3940 * - Extended context size already includes render context size
3941 * - We always need to follow the extended context size.
3942 * SNB BSpec has comments indicating that we should use the
3943 * render context size instead if execlists are disabled, but
3944 * based on empirical testing that's just nonsense.
3945 * - Pipelined/VF state is saved on SNB/IVB respectively
3946 * - GT1 size just indicates how much of render context
3947 * doesn't need saving on GT1
3948 */
3949#define CXT_SIZE _MMIO(0x21a0)
3950#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3951#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3952#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3953#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3954#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3955#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3956 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3957 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3958#define GEN7_CXT_SIZE _MMIO(0x21a8)
3959#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3960#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3961#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3962#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3963#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3964#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3965#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3966 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3967
3968enum {
3969 INTEL_ADVANCED_CONTEXT = 0,
3970 INTEL_LEGACY_32B_CONTEXT,
3971 INTEL_ADVANCED_AD_CONTEXT,
3972 INTEL_LEGACY_64B_CONTEXT
3973};
3974
3975enum {
3976 FAULT_AND_HANG = 0,
3977 FAULT_AND_HALT, /* Debug only */
3978 FAULT_AND_STREAM,
3979 FAULT_AND_CONTINUE /* Unsupported */
3980};
3981
3982#define GEN8_CTX_VALID (1 << 0)
3983#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
3984#define GEN8_CTX_FORCE_RESTORE (1 << 2)
3985#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
3986#define GEN8_CTX_PRIVILEGE (1 << 8)
3987#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3988
3989#define GEN8_CTX_ID_SHIFT 32
3990#define GEN8_CTX_ID_WIDTH 21
3991#define GEN11_SW_CTX_ID_SHIFT 37
3992#define GEN11_SW_CTX_ID_WIDTH 11
3993#define GEN11_ENGINE_CLASS_SHIFT 61
3994#define GEN11_ENGINE_CLASS_WIDTH 3
3995#define GEN11_ENGINE_INSTANCE_SHIFT 48
3996#define GEN11_ENGINE_INSTANCE_WIDTH 6
3997
3998#define CHV_CLK_CTL1 _MMIO(0x101100)
3999#define VLV_CLK_CTL2 _MMIO(0x101104)
4000#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
4001
4002/*
4003 * Overlay regs
4004 */
4005
4006#define OVADD _MMIO(0x30000)
4007#define DOVSTA _MMIO(0x30008)
4008#define OC_BUF (0x3 << 20)
4009#define OGAMC5 _MMIO(0x30010)
4010#define OGAMC4 _MMIO(0x30014)
4011#define OGAMC3 _MMIO(0x30018)
4012#define OGAMC2 _MMIO(0x3001c)
4013#define OGAMC1 _MMIO(0x30020)
4014#define OGAMC0 _MMIO(0x30024)
4015
4016/*
4017 * GEN9 clock gating regs
4018 */
4019#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
4020#define DARBF_GATING_DIS (1 << 27)
4021#define PWM2_GATING_DIS (1 << 14)
4022#define PWM1_GATING_DIS (1 << 13)
4023
4024#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
4025#define BXT_GMBUS_GATING_DIS (1 << 14)
4026
4027#define _CLKGATE_DIS_PSL_A 0x46520
4028#define _CLKGATE_DIS_PSL_B 0x46524
4029#define _CLKGATE_DIS_PSL_C 0x46528
4030#define DUPS1_GATING_DIS (1 << 15)
4031#define DUPS2_GATING_DIS (1 << 19)
4032#define DUPS3_GATING_DIS (1 << 23)
4033#define DPF_GATING_DIS (1 << 10)
4034#define DPF_RAM_GATING_DIS (1 << 9)
4035#define DPFR_GATING_DIS (1 << 8)
4036
4037#define CLKGATE_DIS_PSL(pipe) \
4038 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4039
4040/*
4041 * GEN10 clock gating regs
4042 */
4043#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
4044#define SARBUNIT_CLKGATE_DIS (1 << 5)
4045#define RCCUNIT_CLKGATE_DIS (1 << 7)
4046#define MSCUNIT_CLKGATE_DIS (1 << 10)
4047
4048#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
4049#define GWUNIT_CLKGATE_DIS (1 << 16)
4050
4051#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
4052#define VFUNIT_CLKGATE_DIS (1 << 20)
4053
4054#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
4055#define CGPSF_CLKGATE_DIS (1 << 3)
4056
4057/*
4058 * Display engine regs
4059 */
4060
4061/* Pipe A CRC regs */
4062#define _PIPE_CRC_CTL_A 0x60050
4063#define PIPE_CRC_ENABLE (1 << 31)
4064/* skl+ source selection */
4065#define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
4066#define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
4067#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
4068#define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
4069#define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
4070#define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
4071#define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
4072#define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
4073/* ivb+ source selection */
4074#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
4075#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
4076#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
4077/* ilk+ source selection */
4078#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
4079#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
4080#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
4081/* embedded DP port on the north display block, reserved on ivb */
4082#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
4083#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
4084/* vlv source selection */
4085#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
4086#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
4087#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
4088/* with DP port the pipe source is invalid */
4089#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
4090#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
4091#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
4092/* gen3+ source selection */
4093#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
4094#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
4095#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
4096/* with DP/TV port the pipe source is invalid */
4097#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4098#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4099#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4100#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4101#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4102/* gen2 doesn't have source selection bits */
4103#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4104
4105#define _PIPE_CRC_RES_1_A_IVB 0x60064
4106#define _PIPE_CRC_RES_2_A_IVB 0x60068
4107#define _PIPE_CRC_RES_3_A_IVB 0x6006c
4108#define _PIPE_CRC_RES_4_A_IVB 0x60070
4109#define _PIPE_CRC_RES_5_A_IVB 0x60074
4110
4111#define _PIPE_CRC_RES_RED_A 0x60060
4112#define _PIPE_CRC_RES_GREEN_A 0x60064
4113#define _PIPE_CRC_RES_BLUE_A 0x60068
4114#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4115#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4116
4117/* Pipe B CRC regs */
4118#define _PIPE_CRC_RES_1_B_IVB 0x61064
4119#define _PIPE_CRC_RES_2_B_IVB 0x61068
4120#define _PIPE_CRC_RES_3_B_IVB 0x6106c
4121#define _PIPE_CRC_RES_4_B_IVB 0x61070
4122#define _PIPE_CRC_RES_5_B_IVB 0x61074
4123
4124#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4125#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4126#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4127#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4128#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4129#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4130
4131#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4132#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4133#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4134#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4135#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4136
4137/* Pipe A timing regs */
4138#define _HTOTAL_A 0x60000
4139#define _HBLANK_A 0x60004
4140#define _HSYNC_A 0x60008
4141#define _VTOTAL_A 0x6000c
4142#define _VBLANK_A 0x60010
4143#define _VSYNC_A 0x60014
4144#define _PIPEASRC 0x6001c
4145#define _BCLRPAT_A 0x60020
4146#define _VSYNCSHIFT_A 0x60028
4147#define _PIPE_MULT_A 0x6002c
4148
4149/* Pipe B timing regs */
4150#define _HTOTAL_B 0x61000
4151#define _HBLANK_B 0x61004
4152#define _HSYNC_B 0x61008
4153#define _VTOTAL_B 0x6100c
4154#define _VBLANK_B 0x61010
4155#define _VSYNC_B 0x61014
4156#define _PIPEBSRC 0x6101c
4157#define _BCLRPAT_B 0x61020
4158#define _VSYNCSHIFT_B 0x61028
4159#define _PIPE_MULT_B 0x6102c
4160
4161/* DSI 0 timing regs */
4162#define _HTOTAL_DSI0 0x6b000
4163#define _HSYNC_DSI0 0x6b008
4164#define _VTOTAL_DSI0 0x6b00c
4165#define _VSYNC_DSI0 0x6b014
4166#define _VSYNCSHIFT_DSI0 0x6b028
4167
4168/* DSI 1 timing regs */
4169#define _HTOTAL_DSI1 0x6b800
4170#define _HSYNC_DSI1 0x6b808
4171#define _VTOTAL_DSI1 0x6b80c
4172#define _VSYNC_DSI1 0x6b814
4173#define _VSYNCSHIFT_DSI1 0x6b828
4174
4175#define TRANSCODER_A_OFFSET 0x60000
4176#define TRANSCODER_B_OFFSET 0x61000
4177#define TRANSCODER_C_OFFSET 0x62000
4178#define CHV_TRANSCODER_C_OFFSET 0x63000
4179#define TRANSCODER_D_OFFSET 0x63000
4180#define TRANSCODER_EDP_OFFSET 0x6f000
4181#define TRANSCODER_DSI0_OFFSET 0x6b000
4182#define TRANSCODER_DSI1_OFFSET 0x6b800
4183
4184#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4185#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4186#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4187#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4188#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4189#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4190#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4191#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4192#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4193#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4194
4195/* HSW+ eDP PSR registers */
4196#define HSW_EDP_PSR_BASE 0x64800
4197#define BDW_EDP_PSR_BASE 0x6f800
4198#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4199#define EDP_PSR_ENABLE (1 << 31)
4200#define BDW_PSR_SINGLE_FRAME (1 << 30)
4201#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
4202#define EDP_PSR_LINK_STANDBY (1 << 27)
4203#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4204#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4205#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4206#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4207#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4208#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4209#define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4210#define EDP_PSR_TP1_TP2_SEL (0 << 11)
4211#define EDP_PSR_TP1_TP3_SEL (1 << 11)
4212#define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
4213#define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4214#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4215#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4216#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4217#define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
4218#define EDP_PSR_TP1_TIME_500us (0 << 4)
4219#define EDP_PSR_TP1_TIME_100us (1 << 4)
4220#define EDP_PSR_TP1_TIME_2500us (2 << 4)
4221#define EDP_PSR_TP1_TIME_0us (3 << 4)
4222#define EDP_PSR_IDLE_FRAME_SHIFT 0
4223
4224/* Bspec claims those aren't shifted but stay at 0x64800 */
4225#define EDP_PSR_IMR _MMIO(0x64834)
4226#define EDP_PSR_IIR _MMIO(0x64838)
4227#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
4228#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
4229#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
4230#define EDP_PSR_TRANSCODER_C_SHIFT 24
4231#define EDP_PSR_TRANSCODER_B_SHIFT 16
4232#define EDP_PSR_TRANSCODER_A_SHIFT 8
4233#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
4234
4235#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4236#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4237#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4238#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4239#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4240#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4241
4242#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4243
4244#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4245#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4246#define EDP_PSR_STATUS_STATE_SHIFT 29
4247#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4248#define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4249#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4250#define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4251#define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4252#define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4253#define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4254#define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4255#define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4256#define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4257#define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4258#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4259#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4260#define EDP_PSR_STATUS_COUNT_SHIFT 16
4261#define EDP_PSR_STATUS_COUNT_MASK 0xf
4262#define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4263#define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4264#define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4265#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4266#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4267#define EDP_PSR_STATUS_IDLE_MASK 0xf
4268
4269#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4270#define EDP_PSR_PERF_CNT_MASK 0xffffff
4271
4272#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
4273#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4274#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4275#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4276#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4277#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4278#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4279
4280#define EDP_PSR2_CTL _MMIO(0x6f900)
4281#define EDP_PSR2_ENABLE (1 << 31)
4282#define EDP_SU_TRACK_ENABLE (1 << 30)
4283#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
4284#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
4285#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4286#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4287#define EDP_PSR2_TP2_TIME_500us (0 << 8)
4288#define EDP_PSR2_TP2_TIME_100us (1 << 8)
4289#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4290#define EDP_PSR2_TP2_TIME_50us (3 << 8)
4291#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4292#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4293#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4294#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4295#define EDP_PSR2_IDLE_FRAME_MASK 0xf
4296#define EDP_PSR2_IDLE_FRAME_SHIFT 0
4297
4298#define _PSR_EVENT_TRANS_A 0x60848
4299#define _PSR_EVENT_TRANS_B 0x61848
4300#define _PSR_EVENT_TRANS_C 0x62848
4301#define _PSR_EVENT_TRANS_D 0x63848
4302#define _PSR_EVENT_TRANS_EDP 0x6F848
4303#define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4304#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4305#define PSR_EVENT_PSR2_DISABLED (1 << 16)
4306#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4307#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4308#define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4309#define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4310#define PSR_EVENT_MEMORY_UP (1 << 10)
4311#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4312#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4313#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4314#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4315#define PSR_EVENT_HDCP_ENABLE (1 << 4)
4316#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4317#define PSR_EVENT_VBI_ENABLE (1 << 2)
4318#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4319#define PSR_EVENT_PSR_DISABLE (1 << 0)
4320
4321#define EDP_PSR2_STATUS _MMIO(0x6f940)
4322#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4323#define EDP_PSR2_STATUS_STATE_SHIFT 28
4324
4325#define _PSR2_SU_STATUS_0 0x6F914
4326#define _PSR2_SU_STATUS_1 0x6F918
4327#define _PSR2_SU_STATUS_2 0x6F91C
4328#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
4329#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
4330#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
4331#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4332#define PSR2_SU_STATUS_FRAMES 8
4333
4334/* VGA port control */
4335#define ADPA _MMIO(0x61100)
4336#define PCH_ADPA _MMIO(0xe1100)
4337#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4338
4339#define ADPA_DAC_ENABLE (1 << 31)
4340#define ADPA_DAC_DISABLE 0
4341#define ADPA_PIPE_SEL_SHIFT 30
4342#define ADPA_PIPE_SEL_MASK (1 << 30)
4343#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4344#define ADPA_PIPE_SEL_SHIFT_CPT 29
4345#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4346#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4347#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4348#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4349#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4350#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4351#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4352#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4353#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4354#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4355#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4356#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4357#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4358#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4359#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4360#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4361#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4362#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4363#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4364#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4365#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4366#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4367#define ADPA_SETS_HVPOLARITY 0
4368#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4369#define ADPA_VSYNC_CNTL_ENABLE 0
4370#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4371#define ADPA_HSYNC_CNTL_ENABLE 0
4372#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4373#define ADPA_VSYNC_ACTIVE_LOW 0
4374#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4375#define ADPA_HSYNC_ACTIVE_LOW 0
4376#define ADPA_DPMS_MASK (~(3 << 10))
4377#define ADPA_DPMS_ON (0 << 10)
4378#define ADPA_DPMS_SUSPEND (1 << 10)
4379#define ADPA_DPMS_STANDBY (2 << 10)
4380#define ADPA_DPMS_OFF (3 << 10)
4381
4382
4383/* Hotplug control (945+ only) */
4384#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4385#define PORTB_HOTPLUG_INT_EN (1 << 29)
4386#define PORTC_HOTPLUG_INT_EN (1 << 28)
4387#define PORTD_HOTPLUG_INT_EN (1 << 27)
4388#define SDVOB_HOTPLUG_INT_EN (1 << 26)
4389#define SDVOC_HOTPLUG_INT_EN (1 << 25)
4390#define TV_HOTPLUG_INT_EN (1 << 18)
4391#define CRT_HOTPLUG_INT_EN (1 << 9)
4392#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4393 PORTC_HOTPLUG_INT_EN | \
4394 PORTD_HOTPLUG_INT_EN | \
4395 SDVOC_HOTPLUG_INT_EN | \
4396 SDVOB_HOTPLUG_INT_EN | \
4397 CRT_HOTPLUG_INT_EN)
4398#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4399#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4400/* must use period 64 on GM45 according to docs */
4401#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4402#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4403#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4404#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4405#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4406#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4407#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4408#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4409#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4410#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4411#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4412#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4413
4414#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4415/*
4416 * HDMI/DP bits are g4x+
4417 *
4418 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4419 * Please check the detailed lore in the commit message for for experimental
4420 * evidence.
4421 */
4422/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4423#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4424#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4425#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4426/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4427#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4428#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4429#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4430#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4431#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4432#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4433#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4434#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4435#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4436#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4437#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4438#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4439/* CRT/TV common between gen3+ */
4440#define CRT_HOTPLUG_INT_STATUS (1 << 11)
4441#define TV_HOTPLUG_INT_STATUS (1 << 10)
4442#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4443#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4444#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4445#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4446#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4447#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4448#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4449#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4450
4451/* SDVO is different across gen3/4 */
4452#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4453#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4454/*
4455 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4456 * since reality corrobates that they're the same as on gen3. But keep these
4457 * bits here (and the comment!) to help any other lost wanderers back onto the
4458 * right tracks.
4459 */
4460#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4461#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4462#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4463#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4464#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4465 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4466 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4467 PORTB_HOTPLUG_INT_STATUS | \
4468 PORTC_HOTPLUG_INT_STATUS | \
4469 PORTD_HOTPLUG_INT_STATUS)
4470
4471#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4472 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4473 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4474 PORTB_HOTPLUG_INT_STATUS | \
4475 PORTC_HOTPLUG_INT_STATUS | \
4476 PORTD_HOTPLUG_INT_STATUS)
4477
4478/* SDVO and HDMI port control.
4479 * The same register may be used for SDVO or HDMI */
4480#define _GEN3_SDVOB 0x61140
4481#define _GEN3_SDVOC 0x61160
4482#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4483#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4484#define GEN4_HDMIB GEN3_SDVOB
4485#define GEN4_HDMIC GEN3_SDVOC
4486#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4487#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4488#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4489#define PCH_SDVOB _MMIO(0xe1140)
4490#define PCH_HDMIB PCH_SDVOB
4491#define PCH_HDMIC _MMIO(0xe1150)
4492#define PCH_HDMID _MMIO(0xe1160)
4493
4494#define PORT_DFT_I9XX _MMIO(0x61150)
4495#define DC_BALANCE_RESET (1 << 25)
4496#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4497#define DC_BALANCE_RESET_VLV (1 << 31)
4498#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4499#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4500#define PIPE_B_SCRAMBLE_RESET (1 << 1)
4501#define PIPE_A_SCRAMBLE_RESET (1 << 0)
4502
4503/* Gen 3 SDVO bits: */
4504#define SDVO_ENABLE (1 << 31)
4505#define SDVO_PIPE_SEL_SHIFT 30
4506#define SDVO_PIPE_SEL_MASK (1 << 30)
4507#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4508#define SDVO_STALL_SELECT (1 << 29)
4509#define SDVO_INTERRUPT_ENABLE (1 << 26)
4510/*
4511 * 915G/GM SDVO pixel multiplier.
4512 * Programmed value is multiplier - 1, up to 5x.
4513 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4514 */
4515#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4516#define SDVO_PORT_MULTIPLY_SHIFT 23
4517#define SDVO_PHASE_SELECT_MASK (15 << 19)
4518#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4519#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4520#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4521#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4522#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4523#define SDVO_DETECTED (1 << 2)
4524/* Bits to be preserved when writing */
4525#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4526 SDVO_INTERRUPT_ENABLE)
4527#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4528
4529/* Gen 4 SDVO/HDMI bits: */
4530#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4531#define SDVO_COLOR_FORMAT_MASK (7 << 26)
4532#define SDVO_ENCODING_SDVO (0 << 10)
4533#define SDVO_ENCODING_HDMI (2 << 10)
4534#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4535#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4536#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4537#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
4538/* VSYNC/HSYNC bits new with 965, default is to be set */
4539#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4540#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4541
4542/* Gen 5 (IBX) SDVO/HDMI bits: */
4543#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4544#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4545
4546/* Gen 6 (CPT) SDVO/HDMI bits: */
4547#define SDVO_PIPE_SEL_SHIFT_CPT 29
4548#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4549#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4550
4551/* CHV SDVO/HDMI bits: */
4552#define SDVO_PIPE_SEL_SHIFT_CHV 24
4553#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4554#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4555
4556
4557/* DVO port control */
4558#define _DVOA 0x61120
4559#define DVOA _MMIO(_DVOA)
4560#define _DVOB 0x61140
4561#define DVOB _MMIO(_DVOB)
4562#define _DVOC 0x61160
4563#define DVOC _MMIO(_DVOC)
4564#define DVO_ENABLE (1 << 31)
4565#define DVO_PIPE_SEL_SHIFT 30
4566#define DVO_PIPE_SEL_MASK (1 << 30)
4567#define DVO_PIPE_SEL(pipe) ((pipe) << 30)
4568#define DVO_PIPE_STALL_UNUSED (0 << 28)
4569#define DVO_PIPE_STALL (1 << 28)
4570#define DVO_PIPE_STALL_TV (2 << 28)
4571#define DVO_PIPE_STALL_MASK (3 << 28)
4572#define DVO_USE_VGA_SYNC (1 << 15)
4573#define DVO_DATA_ORDER_I740 (0 << 14)
4574#define DVO_DATA_ORDER_FP (1 << 14)
4575#define DVO_VSYNC_DISABLE (1 << 11)
4576#define DVO_HSYNC_DISABLE (1 << 10)
4577#define DVO_VSYNC_TRISTATE (1 << 9)
4578#define DVO_HSYNC_TRISTATE (1 << 8)
4579#define DVO_BORDER_ENABLE (1 << 7)
4580#define DVO_DATA_ORDER_GBRG (1 << 6)
4581#define DVO_DATA_ORDER_RGGB (0 << 6)
4582#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4583#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4584#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4585#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4586#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4587#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4588#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4589#define DVO_PRESERVE_MASK (0x7 << 24)
4590#define DVOA_SRCDIM _MMIO(0x61124)
4591#define DVOB_SRCDIM _MMIO(0x61144)
4592#define DVOC_SRCDIM _MMIO(0x61164)
4593#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4594#define DVO_SRCDIM_VERTICAL_SHIFT 0
4595
4596/* LVDS port control */
4597#define LVDS _MMIO(0x61180)
4598/*
4599 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4600 * the DPLL semantics change when the LVDS is assigned to that pipe.
4601 */
4602#define LVDS_PORT_EN (1 << 31)
4603/* Selects pipe B for LVDS data. Must be set on pre-965. */
4604#define LVDS_PIPE_SEL_SHIFT 30
4605#define LVDS_PIPE_SEL_MASK (1 << 30)
4606#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
4607#define LVDS_PIPE_SEL_SHIFT_CPT 29
4608#define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
4609#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4610/* LVDS dithering flag on 965/g4x platform */
4611#define LVDS_ENABLE_DITHER (1 << 25)
4612/* LVDS sync polarity flags. Set to invert (i.e. negative) */
4613#define LVDS_VSYNC_POLARITY (1 << 21)
4614#define LVDS_HSYNC_POLARITY (1 << 20)
4615
4616/* Enable border for unscaled (or aspect-scaled) display */
4617#define LVDS_BORDER_ENABLE (1 << 15)
4618/*
4619 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4620 * pixel.
4621 */
4622#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4623#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4624#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4625/*
4626 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4627 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4628 * on.
4629 */
4630#define LVDS_A3_POWER_MASK (3 << 6)
4631#define LVDS_A3_POWER_DOWN (0 << 6)
4632#define LVDS_A3_POWER_UP (3 << 6)
4633/*
4634 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4635 * is set.
4636 */
4637#define LVDS_CLKB_POWER_MASK (3 << 4)
4638#define LVDS_CLKB_POWER_DOWN (0 << 4)
4639#define LVDS_CLKB_POWER_UP (3 << 4)
4640/*
4641 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4642 * setting for whether we are in dual-channel mode. The B3 pair will
4643 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4644 */
4645#define LVDS_B0B3_POWER_MASK (3 << 2)
4646#define LVDS_B0B3_POWER_DOWN (0 << 2)
4647#define LVDS_B0B3_POWER_UP (3 << 2)
4648
4649/* Video Data Island Packet control */
4650#define VIDEO_DIP_DATA _MMIO(0x61178)
4651/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4652 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4653 * of the infoframe structure specified by CEA-861. */
4654#define VIDEO_DIP_DATA_SIZE 32
4655#define VIDEO_DIP_VSC_DATA_SIZE 36
4656#define VIDEO_DIP_PPS_DATA_SIZE 132
4657#define VIDEO_DIP_CTL _MMIO(0x61170)
4658/* Pre HSW: */
4659#define VIDEO_DIP_ENABLE (1 << 31)
4660#define VIDEO_DIP_PORT(port) ((port) << 29)
4661#define VIDEO_DIP_PORT_MASK (3 << 29)
4662#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
4663#define VIDEO_DIP_ENABLE_AVI (1 << 21)
4664#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4665#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
4666#define VIDEO_DIP_ENABLE_SPD (8 << 21)
4667#define VIDEO_DIP_SELECT_AVI (0 << 19)
4668#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4669#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
4670#define VIDEO_DIP_SELECT_SPD (3 << 19)
4671#define VIDEO_DIP_SELECT_MASK (3 << 19)
4672#define VIDEO_DIP_FREQ_ONCE (0 << 16)
4673#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4674#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4675#define VIDEO_DIP_FREQ_MASK (3 << 16)
4676/* HSW and later: */
4677#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
4678#define PSR_VSC_BIT_7_SET (1 << 27)
4679#define VSC_SELECT_MASK (0x3 << 25)
4680#define VSC_SELECT_SHIFT 25
4681#define VSC_DIP_HW_HEA_DATA (0 << 25)
4682#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4683#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4684#define VSC_DIP_SW_HEA_DATA (3 << 25)
4685#define VDIP_ENABLE_PPS (1 << 24)
4686#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4687#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4688#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4689#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4690#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4691#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4692
4693/* Panel power sequencing */
4694#define PPS_BASE 0x61200
4695#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4696#define PCH_PPS_BASE 0xC7200
4697
4698#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4699 PPS_BASE + (reg) + \
4700 (pps_idx) * 0x100)
4701
4702#define _PP_STATUS 0x61200
4703#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4704#define PP_ON REG_BIT(31)
4705
4706#define _PP_CONTROL_1 0xc7204
4707#define _PP_CONTROL_2 0xc7304
4708#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
4709 _PP_CONTROL_2)
4710#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
4711#define VDD_OVERRIDE_FORCE REG_BIT(3)
4712#define BACKLIGHT_ENABLE REG_BIT(2)
4713#define PWR_DOWN_ON_RESET REG_BIT(1)
4714#define PWR_STATE_TARGET REG_BIT(0)
4715/*
4716 * Indicates that all dependencies of the panel are on:
4717 *
4718 * - PLL enabled
4719 * - pipe enabled
4720 * - LVDS/DVOB/DVOC on
4721 */
4722#define PP_READY REG_BIT(30)
4723#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
4724#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4725#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4726#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4727#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
4728#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
4729#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4730#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4731#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4732#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4733#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4734#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
4735#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
4736#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
4737#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
4738
4739#define _PP_CONTROL 0x61204
4740#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4741#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
4742#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
4743#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
4744#define EDP_FORCE_VDD REG_BIT(3)
4745#define EDP_BLC_ENABLE REG_BIT(2)
4746#define PANEL_POWER_RESET REG_BIT(1)
4747#define PANEL_POWER_ON REG_BIT(0)
4748
4749#define _PP_ON_DELAYS 0x61208
4750#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4751#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
4752#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
4753#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
4754#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
4755#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
4756#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
4757#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
4758#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
4759
4760#define _PP_OFF_DELAYS 0x6120C
4761#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4762#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
4763#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
4764
4765#define _PP_DIVISOR 0x61210
4766#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4767#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
4768#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
4769
4770/* Panel fitting */
4771#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4772#define PFIT_ENABLE (1 << 31)
4773#define PFIT_PIPE_MASK (3 << 29)
4774#define PFIT_PIPE_SHIFT 29
4775#define VERT_INTERP_DISABLE (0 << 10)
4776#define VERT_INTERP_BILINEAR (1 << 10)
4777#define VERT_INTERP_MASK (3 << 10)
4778#define VERT_AUTO_SCALE (1 << 9)
4779#define HORIZ_INTERP_DISABLE (0 << 6)
4780#define HORIZ_INTERP_BILINEAR (1 << 6)
4781#define HORIZ_INTERP_MASK (3 << 6)
4782#define HORIZ_AUTO_SCALE (1 << 5)
4783#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4784#define PFIT_FILTER_FUZZY (0 << 24)
4785#define PFIT_SCALING_AUTO (0 << 26)
4786#define PFIT_SCALING_PROGRAMMED (1 << 26)
4787#define PFIT_SCALING_PILLAR (2 << 26)
4788#define PFIT_SCALING_LETTER (3 << 26)
4789#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4790/* Pre-965 */
4791#define PFIT_VERT_SCALE_SHIFT 20
4792#define PFIT_VERT_SCALE_MASK 0xfff00000
4793#define PFIT_HORIZ_SCALE_SHIFT 4
4794#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4795/* 965+ */
4796#define PFIT_VERT_SCALE_SHIFT_965 16
4797#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4798#define PFIT_HORIZ_SCALE_SHIFT_965 0
4799#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4800
4801#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4802
4803#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
4804#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4805#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4806 _VLV_BLC_PWM_CTL2_B)
4807
4808#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4809#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4810#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4811 _VLV_BLC_PWM_CTL_B)
4812
4813#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4814#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4815#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4816 _VLV_BLC_HIST_CTL_B)
4817
4818/* Backlight control */
4819#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4820#define BLM_PWM_ENABLE (1 << 31)
4821#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4822#define BLM_PIPE_SELECT (1 << 29)
4823#define BLM_PIPE_SELECT_IVB (3 << 29)
4824#define BLM_PIPE_A (0 << 29)
4825#define BLM_PIPE_B (1 << 29)
4826#define BLM_PIPE_C (2 << 29) /* ivb + */
4827#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4828#define BLM_TRANSCODER_B BLM_PIPE_B
4829#define BLM_TRANSCODER_C BLM_PIPE_C
4830#define BLM_TRANSCODER_EDP (3 << 29)
4831#define BLM_PIPE(pipe) ((pipe) << 29)
4832#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4833#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4834#define BLM_PHASE_IN_ENABLE (1 << 25)
4835#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4836#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4837#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4838#define BLM_PHASE_IN_COUNT_SHIFT (8)
4839#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4840#define BLM_PHASE_IN_INCR_SHIFT (0)
4841#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4842#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4843/*
4844 * This is the most significant 15 bits of the number of backlight cycles in a
4845 * complete cycle of the modulated backlight control.
4846 *
4847 * The actual value is this field multiplied by two.
4848 */
4849#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4850#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4851#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4852/*
4853 * This is the number of cycles out of the backlight modulation cycle for which
4854 * the backlight is on.
4855 *
4856 * This field must be no greater than the number of cycles in the complete
4857 * backlight modulation cycle.
4858 */
4859#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4860#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4861#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4862#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4863
4864#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4865#define BLM_HISTOGRAM_ENABLE (1 << 31)
4866
4867/* New registers for PCH-split platforms. Safe where new bits show up, the
4868 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4869#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4870#define BLC_PWM_CPU_CTL _MMIO(0x48254)
4871
4872#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4873
4874/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4875 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4876#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4877#define BLM_PCH_PWM_ENABLE (1 << 31)
4878#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4879#define BLM_PCH_POLARITY (1 << 29)
4880#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4881
4882#define UTIL_PIN_CTL _MMIO(0x48400)
4883#define UTIL_PIN_ENABLE (1 << 31)
4884
4885#define UTIL_PIN_PIPE(x) ((x) << 29)
4886#define UTIL_PIN_PIPE_MASK (3 << 29)
4887#define UTIL_PIN_MODE_PWM (1 << 24)
4888#define UTIL_PIN_MODE_MASK (0xf << 24)
4889#define UTIL_PIN_POLARITY (1 << 22)
4890
4891/* BXT backlight register definition. */
4892#define _BXT_BLC_PWM_CTL1 0xC8250
4893#define BXT_BLC_PWM_ENABLE (1 << 31)
4894#define BXT_BLC_PWM_POLARITY (1 << 29)
4895#define _BXT_BLC_PWM_FREQ1 0xC8254
4896#define _BXT_BLC_PWM_DUTY1 0xC8258
4897
4898#define _BXT_BLC_PWM_CTL2 0xC8350
4899#define _BXT_BLC_PWM_FREQ2 0xC8354
4900#define _BXT_BLC_PWM_DUTY2 0xC8358
4901
4902#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4903 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4904#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4905 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4906#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4907 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4908
4909#define PCH_GTC_CTL _MMIO(0xe7000)
4910#define PCH_GTC_ENABLE (1 << 31)
4911
4912/* TV port control */
4913#define TV_CTL _MMIO(0x68000)
4914/* Enables the TV encoder */
4915# define TV_ENC_ENABLE (1 << 31)
4916/* Sources the TV encoder input from pipe B instead of A. */
4917# define TV_ENC_PIPE_SEL_SHIFT 30
4918# define TV_ENC_PIPE_SEL_MASK (1 << 30)
4919# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
4920/* Outputs composite video (DAC A only) */
4921# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4922/* Outputs SVideo video (DAC B/C) */
4923# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4924/* Outputs Component video (DAC A/B/C) */
4925# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4926/* Outputs Composite and SVideo (DAC A/B/C) */
4927# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4928# define TV_TRILEVEL_SYNC (1 << 21)
4929/* Enables slow sync generation (945GM only) */
4930# define TV_SLOW_SYNC (1 << 20)
4931/* Selects 4x oversampling for 480i and 576p */
4932# define TV_OVERSAMPLE_4X (0 << 18)
4933/* Selects 2x oversampling for 720p and 1080i */
4934# define TV_OVERSAMPLE_2X (1 << 18)
4935/* Selects no oversampling for 1080p */
4936# define TV_OVERSAMPLE_NONE (2 << 18)
4937/* Selects 8x oversampling */
4938# define TV_OVERSAMPLE_8X (3 << 18)
4939# define TV_OVERSAMPLE_MASK (3 << 18)
4940/* Selects progressive mode rather than interlaced */
4941# define TV_PROGRESSIVE (1 << 17)
4942/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
4943# define TV_PAL_BURST (1 << 16)
4944/* Field for setting delay of Y compared to C */
4945# define TV_YC_SKEW_MASK (7 << 12)
4946/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4947# define TV_ENC_SDP_FIX (1 << 11)
4948/*
4949 * Enables a fix for the 915GM only.
4950 *
4951 * Not sure what it does.
4952 */
4953# define TV_ENC_C0_FIX (1 << 10)
4954/* Bits that must be preserved by software */
4955# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4956# define TV_FUSE_STATE_MASK (3 << 4)
4957/* Read-only state that reports all features enabled */
4958# define TV_FUSE_STATE_ENABLED (0 << 4)
4959/* Read-only state that reports that Macrovision is disabled in hardware*/
4960# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4961/* Read-only state that reports that TV-out is disabled in hardware. */
4962# define TV_FUSE_STATE_DISABLED (2 << 4)
4963/* Normal operation */
4964# define TV_TEST_MODE_NORMAL (0 << 0)
4965/* Encoder test pattern 1 - combo pattern */
4966# define TV_TEST_MODE_PATTERN_1 (1 << 0)
4967/* Encoder test pattern 2 - full screen vertical 75% color bars */
4968# define TV_TEST_MODE_PATTERN_2 (2 << 0)
4969/* Encoder test pattern 3 - full screen horizontal 75% color bars */
4970# define TV_TEST_MODE_PATTERN_3 (3 << 0)
4971/* Encoder test pattern 4 - random noise */
4972# define TV_TEST_MODE_PATTERN_4 (4 << 0)
4973/* Encoder test pattern 5 - linear color ramps */
4974# define TV_TEST_MODE_PATTERN_5 (5 << 0)
4975/*
4976 * This test mode forces the DACs to 50% of full output.
4977 *
4978 * This is used for load detection in combination with TVDAC_SENSE_MASK
4979 */
4980# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4981# define TV_TEST_MODE_MASK (7 << 0)
4982
4983#define TV_DAC _MMIO(0x68004)
4984# define TV_DAC_SAVE 0x00ffff00
4985/*
4986 * Reports that DAC state change logic has reported change (RO).
4987 *
4988 * This gets cleared when TV_DAC_STATE_EN is cleared
4989*/
4990# define TVDAC_STATE_CHG (1 << 31)
4991# define TVDAC_SENSE_MASK (7 << 28)
4992/* Reports that DAC A voltage is above the detect threshold */
4993# define TVDAC_A_SENSE (1 << 30)
4994/* Reports that DAC B voltage is above the detect threshold */
4995# define TVDAC_B_SENSE (1 << 29)
4996/* Reports that DAC C voltage is above the detect threshold */
4997# define TVDAC_C_SENSE (1 << 28)
4998/*
4999 * Enables DAC state detection logic, for load-based TV detection.
5000 *
5001 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5002 * to off, for load detection to work.
5003 */
5004# define TVDAC_STATE_CHG_EN (1 << 27)
5005/* Sets the DAC A sense value to high */
5006# define TVDAC_A_SENSE_CTL (1 << 26)
5007/* Sets the DAC B sense value to high */
5008# define TVDAC_B_SENSE_CTL (1 << 25)
5009/* Sets the DAC C sense value to high */
5010# define TVDAC_C_SENSE_CTL (1 << 24)
5011/* Overrides the ENC_ENABLE and DAC voltage levels */
5012# define DAC_CTL_OVERRIDE (1 << 7)
5013/* Sets the slew rate. Must be preserved in software */
5014# define ENC_TVDAC_SLEW_FAST (1 << 6)
5015# define DAC_A_1_3_V (0 << 4)
5016# define DAC_A_1_1_V (1 << 4)
5017# define DAC_A_0_7_V (2 << 4)
5018# define DAC_A_MASK (3 << 4)
5019# define DAC_B_1_3_V (0 << 2)
5020# define DAC_B_1_1_V (1 << 2)
5021# define DAC_B_0_7_V (2 << 2)
5022# define DAC_B_MASK (3 << 2)
5023# define DAC_C_1_3_V (0 << 0)
5024# define DAC_C_1_1_V (1 << 0)
5025# define DAC_C_0_7_V (2 << 0)
5026# define DAC_C_MASK (3 << 0)
5027
5028/*
5029 * CSC coefficients are stored in a floating point format with 9 bits of
5030 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5031 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5032 * -1 (0x3) being the only legal negative value.
5033 */
5034#define TV_CSC_Y _MMIO(0x68010)
5035# define TV_RY_MASK 0x07ff0000
5036# define TV_RY_SHIFT 16
5037# define TV_GY_MASK 0x00000fff
5038# define TV_GY_SHIFT 0
5039
5040#define TV_CSC_Y2 _MMIO(0x68014)
5041# define TV_BY_MASK 0x07ff0000
5042# define TV_BY_SHIFT 16
5043/*
5044 * Y attenuation for component video.
5045 *
5046 * Stored in 1.9 fixed point.
5047 */
5048# define TV_AY_MASK 0x000003ff
5049# define TV_AY_SHIFT 0
5050
5051#define TV_CSC_U _MMIO(0x68018)
5052# define TV_RU_MASK 0x07ff0000
5053# define TV_RU_SHIFT 16
5054# define TV_GU_MASK 0x000007ff
5055# define TV_GU_SHIFT 0
5056
5057#define TV_CSC_U2 _MMIO(0x6801c)
5058# define TV_BU_MASK 0x07ff0000
5059# define TV_BU_SHIFT 16
5060/*
5061 * U attenuation for component video.
5062 *
5063 * Stored in 1.9 fixed point.
5064 */
5065# define TV_AU_MASK 0x000003ff
5066# define TV_AU_SHIFT 0
5067
5068#define TV_CSC_V _MMIO(0x68020)
5069# define TV_RV_MASK 0x0fff0000
5070# define TV_RV_SHIFT 16
5071# define TV_GV_MASK 0x000007ff
5072# define TV_GV_SHIFT 0
5073
5074#define TV_CSC_V2 _MMIO(0x68024)
5075# define TV_BV_MASK 0x07ff0000
5076# define TV_BV_SHIFT 16
5077/*
5078 * V attenuation for component video.
5079 *
5080 * Stored in 1.9 fixed point.
5081 */
5082# define TV_AV_MASK 0x000007ff
5083# define TV_AV_SHIFT 0
5084
5085#define TV_CLR_KNOBS _MMIO(0x68028)
5086/* 2s-complement brightness adjustment */
5087# define TV_BRIGHTNESS_MASK 0xff000000
5088# define TV_BRIGHTNESS_SHIFT 24
5089/* Contrast adjustment, as a 2.6 unsigned floating point number */
5090# define TV_CONTRAST_MASK 0x00ff0000
5091# define TV_CONTRAST_SHIFT 16
5092/* Saturation adjustment, as a 2.6 unsigned floating point number */
5093# define TV_SATURATION_MASK 0x0000ff00
5094# define TV_SATURATION_SHIFT 8
5095/* Hue adjustment, as an integer phase angle in degrees */
5096# define TV_HUE_MASK 0x000000ff
5097# define TV_HUE_SHIFT 0
5098
5099#define TV_CLR_LEVEL _MMIO(0x6802c)
5100/* Controls the DAC level for black */
5101# define TV_BLACK_LEVEL_MASK 0x01ff0000
5102# define TV_BLACK_LEVEL_SHIFT 16
5103/* Controls the DAC level for blanking */
5104# define TV_BLANK_LEVEL_MASK 0x000001ff
5105# define TV_BLANK_LEVEL_SHIFT 0
5106
5107#define TV_H_CTL_1 _MMIO(0x68030)
5108/* Number of pixels in the hsync. */
5109# define TV_HSYNC_END_MASK 0x1fff0000
5110# define TV_HSYNC_END_SHIFT 16
5111/* Total number of pixels minus one in the line (display and blanking). */
5112# define TV_HTOTAL_MASK 0x00001fff
5113# define TV_HTOTAL_SHIFT 0
5114
5115#define TV_H_CTL_2 _MMIO(0x68034)
5116/* Enables the colorburst (needed for non-component color) */
5117# define TV_BURST_ENA (1 << 31)
5118/* Offset of the colorburst from the start of hsync, in pixels minus one. */
5119# define TV_HBURST_START_SHIFT 16
5120# define TV_HBURST_START_MASK 0x1fff0000
5121/* Length of the colorburst */
5122# define TV_HBURST_LEN_SHIFT 0
5123# define TV_HBURST_LEN_MASK 0x0001fff
5124
5125#define TV_H_CTL_3 _MMIO(0x68038)
5126/* End of hblank, measured in pixels minus one from start of hsync */
5127# define TV_HBLANK_END_SHIFT 16
5128# define TV_HBLANK_END_MASK 0x1fff0000
5129/* Start of hblank, measured in pixels minus one from start of hsync */
5130# define TV_HBLANK_START_SHIFT 0
5131# define TV_HBLANK_START_MASK 0x0001fff
5132
5133#define TV_V_CTL_1 _MMIO(0x6803c)
5134/* XXX */
5135# define TV_NBR_END_SHIFT 16
5136# define TV_NBR_END_MASK 0x07ff0000
5137/* XXX */
5138# define TV_VI_END_F1_SHIFT 8
5139# define TV_VI_END_F1_MASK 0x00003f00
5140/* XXX */
5141# define TV_VI_END_F2_SHIFT 0
5142# define TV_VI_END_F2_MASK 0x0000003f
5143
5144#define TV_V_CTL_2 _MMIO(0x68040)
5145/* Length of vsync, in half lines */
5146# define TV_VSYNC_LEN_MASK 0x07ff0000
5147# define TV_VSYNC_LEN_SHIFT 16
5148/* Offset of the start of vsync in field 1, measured in one less than the
5149 * number of half lines.
5150 */
5151# define TV_VSYNC_START_F1_MASK 0x00007f00
5152# define TV_VSYNC_START_F1_SHIFT 8
5153/*
5154 * Offset of the start of vsync in field 2, measured in one less than the
5155 * number of half lines.
5156 */
5157# define TV_VSYNC_START_F2_MASK 0x0000007f
5158# define TV_VSYNC_START_F2_SHIFT 0
5159
5160#define TV_V_CTL_3 _MMIO(0x68044)
5161/* Enables generation of the equalization signal */
5162# define TV_EQUAL_ENA (1 << 31)
5163/* Length of vsync, in half lines */
5164# define TV_VEQ_LEN_MASK 0x007f0000
5165# define TV_VEQ_LEN_SHIFT 16
5166/* Offset of the start of equalization in field 1, measured in one less than
5167 * the number of half lines.
5168 */
5169# define TV_VEQ_START_F1_MASK 0x0007f00
5170# define TV_VEQ_START_F1_SHIFT 8
5171/*
5172 * Offset of the start of equalization in field 2, measured in one less than
5173 * the number of half lines.
5174 */
5175# define TV_VEQ_START_F2_MASK 0x000007f
5176# define TV_VEQ_START_F2_SHIFT 0
5177
5178#define TV_V_CTL_4 _MMIO(0x68048)
5179/*
5180 * Offset to start of vertical colorburst, measured in one less than the
5181 * number of lines from vertical start.
5182 */
5183# define TV_VBURST_START_F1_MASK 0x003f0000
5184# define TV_VBURST_START_F1_SHIFT 16
5185/*
5186 * Offset to the end of vertical colorburst, measured in one less than the
5187 * number of lines from the start of NBR.
5188 */
5189# define TV_VBURST_END_F1_MASK 0x000000ff
5190# define TV_VBURST_END_F1_SHIFT 0
5191
5192#define TV_V_CTL_5 _MMIO(0x6804c)
5193/*
5194 * Offset to start of vertical colorburst, measured in one less than the
5195 * number of lines from vertical start.
5196 */
5197# define TV_VBURST_START_F2_MASK 0x003f0000
5198# define TV_VBURST_START_F2_SHIFT 16
5199/*
5200 * Offset to the end of vertical colorburst, measured in one less than the
5201 * number of lines from the start of NBR.
5202 */
5203# define TV_VBURST_END_F2_MASK 0x000000ff
5204# define TV_VBURST_END_F2_SHIFT 0
5205
5206#define TV_V_CTL_6 _MMIO(0x68050)
5207/*
5208 * Offset to start of vertical colorburst, measured in one less than the
5209 * number of lines from vertical start.
5210 */
5211# define TV_VBURST_START_F3_MASK 0x003f0000
5212# define TV_VBURST_START_F3_SHIFT 16
5213/*
5214 * Offset to the end of vertical colorburst, measured in one less than the
5215 * number of lines from the start of NBR.
5216 */
5217# define TV_VBURST_END_F3_MASK 0x000000ff
5218# define TV_VBURST_END_F3_SHIFT 0
5219
5220#define TV_V_CTL_7 _MMIO(0x68054)
5221/*
5222 * Offset to start of vertical colorburst, measured in one less than the
5223 * number of lines from vertical start.
5224 */
5225# define TV_VBURST_START_F4_MASK 0x003f0000
5226# define TV_VBURST_START_F4_SHIFT 16
5227/*
5228 * Offset to the end of vertical colorburst, measured in one less than the
5229 * number of lines from the start of NBR.
5230 */
5231# define TV_VBURST_END_F4_MASK 0x000000ff
5232# define TV_VBURST_END_F4_SHIFT 0
5233
5234#define TV_SC_CTL_1 _MMIO(0x68060)
5235/* Turns on the first subcarrier phase generation DDA */
5236# define TV_SC_DDA1_EN (1 << 31)
5237/* Turns on the first subcarrier phase generation DDA */
5238# define TV_SC_DDA2_EN (1 << 30)
5239/* Turns on the first subcarrier phase generation DDA */
5240# define TV_SC_DDA3_EN (1 << 29)
5241/* Sets the subcarrier DDA to reset frequency every other field */
5242# define TV_SC_RESET_EVERY_2 (0 << 24)
5243/* Sets the subcarrier DDA to reset frequency every fourth field */
5244# define TV_SC_RESET_EVERY_4 (1 << 24)
5245/* Sets the subcarrier DDA to reset frequency every eighth field */
5246# define TV_SC_RESET_EVERY_8 (2 << 24)
5247/* Sets the subcarrier DDA to never reset the frequency */
5248# define TV_SC_RESET_NEVER (3 << 24)
5249/* Sets the peak amplitude of the colorburst.*/
5250# define TV_BURST_LEVEL_MASK 0x00ff0000
5251# define TV_BURST_LEVEL_SHIFT 16
5252/* Sets the increment of the first subcarrier phase generation DDA */
5253# define TV_SCDDA1_INC_MASK 0x00000fff
5254# define TV_SCDDA1_INC_SHIFT 0
5255
5256#define TV_SC_CTL_2 _MMIO(0x68064)
5257/* Sets the rollover for the second subcarrier phase generation DDA */
5258# define TV_SCDDA2_SIZE_MASK 0x7fff0000
5259# define TV_SCDDA2_SIZE_SHIFT 16
5260/* Sets the increent of the second subcarrier phase generation DDA */
5261# define TV_SCDDA2_INC_MASK 0x00007fff
5262# define TV_SCDDA2_INC_SHIFT 0
5263
5264#define TV_SC_CTL_3 _MMIO(0x68068)
5265/* Sets the rollover for the third subcarrier phase generation DDA */
5266# define TV_SCDDA3_SIZE_MASK 0x7fff0000
5267# define TV_SCDDA3_SIZE_SHIFT 16
5268/* Sets the increent of the third subcarrier phase generation DDA */
5269# define TV_SCDDA3_INC_MASK 0x00007fff
5270# define TV_SCDDA3_INC_SHIFT 0
5271
5272#define TV_WIN_POS _MMIO(0x68070)
5273/* X coordinate of the display from the start of horizontal active */
5274# define TV_XPOS_MASK 0x1fff0000
5275# define TV_XPOS_SHIFT 16
5276/* Y coordinate of the display from the start of vertical active (NBR) */
5277# define TV_YPOS_MASK 0x00000fff
5278# define TV_YPOS_SHIFT 0
5279
5280#define TV_WIN_SIZE _MMIO(0x68074)
5281/* Horizontal size of the display window, measured in pixels*/
5282# define TV_XSIZE_MASK 0x1fff0000
5283# define TV_XSIZE_SHIFT 16
5284/*
5285 * Vertical size of the display window, measured in pixels.
5286 *
5287 * Must be even for interlaced modes.
5288 */
5289# define TV_YSIZE_MASK 0x00000fff
5290# define TV_YSIZE_SHIFT 0
5291
5292#define TV_FILTER_CTL_1 _MMIO(0x68080)
5293/*
5294 * Enables automatic scaling calculation.
5295 *
5296 * If set, the rest of the registers are ignored, and the calculated values can
5297 * be read back from the register.
5298 */
5299# define TV_AUTO_SCALE (1 << 31)
5300/*
5301 * Disables the vertical filter.
5302 *
5303 * This is required on modes more than 1024 pixels wide */
5304# define TV_V_FILTER_BYPASS (1 << 29)
5305/* Enables adaptive vertical filtering */
5306# define TV_VADAPT (1 << 28)
5307# define TV_VADAPT_MODE_MASK (3 << 26)
5308/* Selects the least adaptive vertical filtering mode */
5309# define TV_VADAPT_MODE_LEAST (0 << 26)
5310/* Selects the moderately adaptive vertical filtering mode */
5311# define TV_VADAPT_MODE_MODERATE (1 << 26)
5312/* Selects the most adaptive vertical filtering mode */
5313# define TV_VADAPT_MODE_MOST (3 << 26)
5314/*
5315 * Sets the horizontal scaling factor.
5316 *
5317 * This should be the fractional part of the horizontal scaling factor divided
5318 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5319 *
5320 * (src width - 1) / ((oversample * dest width) - 1)
5321 */
5322# define TV_HSCALE_FRAC_MASK 0x00003fff
5323# define TV_HSCALE_FRAC_SHIFT 0
5324
5325#define TV_FILTER_CTL_2 _MMIO(0x68084)
5326/*
5327 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5328 *
5329 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5330 */
5331# define TV_VSCALE_INT_MASK 0x00038000
5332# define TV_VSCALE_INT_SHIFT 15
5333/*
5334 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5335 *
5336 * \sa TV_VSCALE_INT_MASK
5337 */
5338# define TV_VSCALE_FRAC_MASK 0x00007fff
5339# define TV_VSCALE_FRAC_SHIFT 0
5340
5341#define TV_FILTER_CTL_3 _MMIO(0x68088)
5342/*
5343 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5344 *
5345 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5346 *
5347 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5348 */
5349# define TV_VSCALE_IP_INT_MASK 0x00038000
5350# define TV_VSCALE_IP_INT_SHIFT 15
5351/*
5352 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5353 *
5354 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5355 *
5356 * \sa TV_VSCALE_IP_INT_MASK
5357 */
5358# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5359# define TV_VSCALE_IP_FRAC_SHIFT 0
5360
5361#define TV_CC_CONTROL _MMIO(0x68090)
5362# define TV_CC_ENABLE (1 << 31)
5363/*
5364 * Specifies which field to send the CC data in.
5365 *
5366 * CC data is usually sent in field 0.
5367 */
5368# define TV_CC_FID_MASK (1 << 27)
5369# define TV_CC_FID_SHIFT 27
5370/* Sets the horizontal position of the CC data. Usually 135. */
5371# define TV_CC_HOFF_MASK 0x03ff0000
5372# define TV_CC_HOFF_SHIFT 16
5373/* Sets the vertical position of the CC data. Usually 21 */
5374# define TV_CC_LINE_MASK 0x0000003f
5375# define TV_CC_LINE_SHIFT 0
5376
5377#define TV_CC_DATA _MMIO(0x68094)
5378# define TV_CC_RDY (1 << 31)
5379/* Second word of CC data to be transmitted. */
5380# define TV_CC_DATA_2_MASK 0x007f0000
5381# define TV_CC_DATA_2_SHIFT 16
5382/* First word of CC data to be transmitted. */
5383# define TV_CC_DATA_1_MASK 0x0000007f
5384# define TV_CC_DATA_1_SHIFT 0
5385
5386#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5387#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5388#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5389#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5390
5391/* Display Port */
5392#define DP_A _MMIO(0x64000) /* eDP */
5393#define DP_B _MMIO(0x64100)
5394#define DP_C _MMIO(0x64200)
5395#define DP_D _MMIO(0x64300)
5396
5397#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5398#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5399#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5400
5401#define DP_PORT_EN (1 << 31)
5402#define DP_PIPE_SEL_SHIFT 30
5403#define DP_PIPE_SEL_MASK (1 << 30)
5404#define DP_PIPE_SEL(pipe) ((pipe) << 30)
5405#define DP_PIPE_SEL_SHIFT_IVB 29
5406#define DP_PIPE_SEL_MASK_IVB (3 << 29)
5407#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5408#define DP_PIPE_SEL_SHIFT_CHV 16
5409#define DP_PIPE_SEL_MASK_CHV (3 << 16)
5410#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
5411
5412/* Link training mode - select a suitable mode for each stage */
5413#define DP_LINK_TRAIN_PAT_1 (0 << 28)
5414#define DP_LINK_TRAIN_PAT_2 (1 << 28)
5415#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5416#define DP_LINK_TRAIN_OFF (3 << 28)
5417#define DP_LINK_TRAIN_MASK (3 << 28)
5418#define DP_LINK_TRAIN_SHIFT 28
5419
5420/* CPT Link training mode */
5421#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5422#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5423#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5424#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5425#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5426#define DP_LINK_TRAIN_SHIFT_CPT 8
5427
5428/* Signal voltages. These are mostly controlled by the other end */
5429#define DP_VOLTAGE_0_4 (0 << 25)
5430#define DP_VOLTAGE_0_6 (1 << 25)
5431#define DP_VOLTAGE_0_8 (2 << 25)
5432#define DP_VOLTAGE_1_2 (3 << 25)
5433#define DP_VOLTAGE_MASK (7 << 25)
5434#define DP_VOLTAGE_SHIFT 25
5435
5436/* Signal pre-emphasis levels, like voltages, the other end tells us what
5437 * they want
5438 */
5439#define DP_PRE_EMPHASIS_0 (0 << 22)
5440#define DP_PRE_EMPHASIS_3_5 (1 << 22)
5441#define DP_PRE_EMPHASIS_6 (2 << 22)
5442#define DP_PRE_EMPHASIS_9_5 (3 << 22)
5443#define DP_PRE_EMPHASIS_MASK (7 << 22)
5444#define DP_PRE_EMPHASIS_SHIFT 22
5445
5446/* How many wires to use. I guess 3 was too hard */
5447#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5448#define DP_PORT_WIDTH_MASK (7 << 19)
5449#define DP_PORT_WIDTH_SHIFT 19
5450
5451/* Mystic DPCD version 1.1 special mode */
5452#define DP_ENHANCED_FRAMING (1 << 18)
5453
5454/* eDP */
5455#define DP_PLL_FREQ_270MHZ (0 << 16)
5456#define DP_PLL_FREQ_162MHZ (1 << 16)
5457#define DP_PLL_FREQ_MASK (3 << 16)
5458
5459/* locked once port is enabled */
5460#define DP_PORT_REVERSAL (1 << 15)
5461
5462/* eDP */
5463#define DP_PLL_ENABLE (1 << 14)
5464
5465/* sends the clock on lane 15 of the PEG for debug */
5466#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5467
5468#define DP_SCRAMBLING_DISABLE (1 << 12)
5469#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5470
5471/* limit RGB values to avoid confusing TVs */
5472#define DP_COLOR_RANGE_16_235 (1 << 8)
5473
5474/* Turn on the audio link */
5475#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5476
5477/* vs and hs sync polarity */
5478#define DP_SYNC_VS_HIGH (1 << 4)
5479#define DP_SYNC_HS_HIGH (1 << 3)
5480
5481/* A fantasy */
5482#define DP_DETECTED (1 << 2)
5483
5484/* The aux channel provides a way to talk to the
5485 * signal sink for DDC etc. Max packet size supported
5486 * is 20 bytes in each direction, hence the 5 fixed
5487 * data registers
5488 */
5489#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5490#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5491#define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
5492#define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
5493#define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
5494#define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
5495
5496#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5497#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5498#define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
5499#define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
5500#define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
5501#define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
5502
5503#define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
5504#define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
5505#define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
5506#define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
5507#define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
5508#define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
5509
5510#define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
5511#define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
5512#define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
5513#define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
5514#define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
5515#define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
5516
5517#define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
5518#define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
5519#define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
5520#define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
5521#define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
5522#define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
5523
5524#define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
5525#define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
5526#define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
5527#define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
5528#define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
5529#define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
5530
5531#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5532#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5533
5534#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5535#define DP_AUX_CH_CTL_DONE (1 << 30)
5536#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5537#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5538#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5539#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5540#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5541#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5542#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5543#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5544#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5545#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5546#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5547#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5548#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5549#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5550#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5551#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5552#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5553#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5554#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5555#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5556#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5557#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5558#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5559#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5560#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5561#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5562
5563/*
5564 * Computing GMCH M and N values for the Display Port link
5565 *
5566 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5567 *
5568 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5569 *
5570 * The GMCH value is used internally
5571 *
5572 * bytes_per_pixel is the number of bytes coming out of the plane,
5573 * which is after the LUTs, so we want the bytes for our color format.
5574 * For our current usage, this is always 3, one byte for R, G and B.
5575 */
5576#define _PIPEA_DATA_M_G4X 0x70050
5577#define _PIPEB_DATA_M_G4X 0x71050
5578
5579/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5580#define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
5581#define TU_SIZE_SHIFT 25
5582#define TU_SIZE_MASK (0x3f << 25)
5583
5584#define DATA_LINK_M_N_MASK (0xffffff)
5585#define DATA_LINK_N_MAX (0x800000)
5586
5587#define _PIPEA_DATA_N_G4X 0x70054
5588#define _PIPEB_DATA_N_G4X 0x71054
5589#define PIPE_GMCH_DATA_N_MASK (0xffffff)
5590
5591/*
5592 * Computing Link M and N values for the Display Port link
5593 *
5594 * Link M / N = pixel_clock / ls_clk
5595 *
5596 * (the DP spec calls pixel_clock the 'strm_clk')
5597 *
5598 * The Link value is transmitted in the Main Stream
5599 * Attributes and VB-ID.
5600 */
5601
5602#define _PIPEA_LINK_M_G4X 0x70060
5603#define _PIPEB_LINK_M_G4X 0x71060
5604#define PIPEA_DP_LINK_M_MASK (0xffffff)
5605
5606#define _PIPEA_LINK_N_G4X 0x70064
5607#define _PIPEB_LINK_N_G4X 0x71064
5608#define PIPEA_DP_LINK_N_MASK (0xffffff)
5609
5610#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5611#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5612#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5613#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5614
5615/* Display & cursor control */
5616
5617/* Pipe A */
5618#define _PIPEADSL 0x70000
5619#define DSL_LINEMASK_GEN2 0x00000fff
5620#define DSL_LINEMASK_GEN3 0x00001fff
5621#define _PIPEACONF 0x70008
5622#define PIPECONF_ENABLE (1 << 31)
5623#define PIPECONF_DISABLE 0
5624#define PIPECONF_DOUBLE_WIDE (1 << 30)
5625#define I965_PIPECONF_ACTIVE (1 << 30)
5626#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
5627#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5628#define PIPECONF_SINGLE_WIDE 0
5629#define PIPECONF_PIPE_UNLOCKED 0
5630#define PIPECONF_PIPE_LOCKED (1 << 25)
5631#define PIPECONF_FORCE_BORDER (1 << 25)
5632#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
5633#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
5634#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
5635#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
5636#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
5637#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
5638#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
5639#define PIPECONF_GAMMA_MODE_SHIFT 24
5640#define PIPECONF_INTERLACE_MASK (7 << 21)
5641#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5642/* Note that pre-gen3 does not support interlaced display directly. Panel
5643 * fitting must be disabled on pre-ilk for interlaced. */
5644#define PIPECONF_PROGRESSIVE (0 << 21)
5645#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5646#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5647#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5648#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5649/* Ironlake and later have a complete new set of values for interlaced. PFIT
5650 * means panel fitter required, PF means progressive fetch, DBL means power
5651 * saving pixel doubling. */
5652#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5653#define PIPECONF_INTERLACED_ILK (3 << 21)
5654#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5655#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5656#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5657#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5658#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
5659#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5660#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5661#define PIPECONF_BPC_MASK (0x7 << 5)
5662#define PIPECONF_8BPC (0 << 5)
5663#define PIPECONF_10BPC (1 << 5)
5664#define PIPECONF_6BPC (2 << 5)
5665#define PIPECONF_12BPC (3 << 5)
5666#define PIPECONF_DITHER_EN (1 << 4)
5667#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5668#define PIPECONF_DITHER_TYPE_SP (0 << 2)
5669#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5670#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5671#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5672#define _PIPEASTAT 0x70024
5673#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
5674#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
5675#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
5676#define PIPE_CRC_DONE_ENABLE (1UL << 28)
5677#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
5678#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
5679#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
5680#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
5681#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
5682#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
5683#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
5684#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
5685#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
5686#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
5687#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
5688#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
5689#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
5690#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
5691#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
5692#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
5693#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
5694#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
5695#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
5696#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
5697#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
5698#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
5699#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
5700#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
5701#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
5702#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
5703#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
5704#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
5705#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
5706#define PIPE_DPST_EVENT_STATUS (1UL << 7)
5707#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
5708#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
5709#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
5710#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
5711#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
5712#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
5713#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
5714#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
5715#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
5716#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
5717#define PIPE_HBLANK_INT_STATUS (1UL << 0)
5718#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
5719
5720#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5721#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5722
5723#define PIPE_A_OFFSET 0x70000
5724#define PIPE_B_OFFSET 0x71000
5725#define PIPE_C_OFFSET 0x72000
5726#define PIPE_D_OFFSET 0x73000
5727#define CHV_PIPE_C_OFFSET 0x74000
5728/*
5729 * There's actually no pipe EDP. Some pipe registers have
5730 * simply shifted from the pipe to the transcoder, while
5731 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5732 * to access such registers in transcoder EDP.
5733 */
5734#define PIPE_EDP_OFFSET 0x7f000
5735
5736/* ICL DSI 0 and 1 */
5737#define PIPE_DSI0_OFFSET 0x7b000
5738#define PIPE_DSI1_OFFSET 0x7b800
5739
5740#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5741#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5742#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5743#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5744#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5745
5746#define _PIPEAGCMAX 0x70010
5747#define _PIPEBGCMAX 0x71010
5748#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
5749
5750#define _PIPE_MISC_A 0x70030
5751#define _PIPE_MISC_B 0x71030
5752#define PIPEMISC_YUV420_ENABLE (1 << 27)
5753#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5754#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
5755#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
5756#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
5757#define PIPEMISC_DITHER_8_BPC (0 << 5)
5758#define PIPEMISC_DITHER_10_BPC (1 << 5)
5759#define PIPEMISC_DITHER_6_BPC (2 << 5)
5760#define PIPEMISC_DITHER_12_BPC (3 << 5)
5761#define PIPEMISC_DITHER_ENABLE (1 << 4)
5762#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
5763#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
5764#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5765
5766/* Skylake+ pipe bottom (background) color */
5767#define _SKL_BOTTOM_COLOR_A 0x70034
5768#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
5769#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
5770#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5771
5772#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5773#define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
5774#define PIPEB_HLINE_INT_EN (1 << 28)
5775#define PIPEB_VBLANK_INT_EN (1 << 27)
5776#define SPRITED_FLIP_DONE_INT_EN (1 << 26)
5777#define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
5778#define PLANEB_FLIP_DONE_INT_EN (1 << 24)
5779#define PIPE_PSR_INT_EN (1 << 22)
5780#define PIPEA_LINE_COMPARE_INT_EN (1 << 21)
5781#define PIPEA_HLINE_INT_EN (1 << 20)
5782#define PIPEA_VBLANK_INT_EN (1 << 19)
5783#define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
5784#define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
5785#define PLANEA_FLIPDONE_INT_EN (1 << 16)
5786#define PIPEC_LINE_COMPARE_INT_EN (1 << 13)
5787#define PIPEC_HLINE_INT_EN (1 << 12)
5788#define PIPEC_VBLANK_INT_EN (1 << 11)
5789#define SPRITEF_FLIPDONE_INT_EN (1 << 10)
5790#define SPRITEE_FLIPDONE_INT_EN (1 << 9)
5791#define PLANEC_FLIPDONE_INT_EN (1 << 8)
5792
5793#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5794#define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
5795#define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
5796#define PLANEC_INVALID_GTT_INT_EN (1 << 25)
5797#define CURSORC_INVALID_GTT_INT_EN (1 << 24)
5798#define CURSORB_INVALID_GTT_INT_EN (1 << 23)
5799#define CURSORA_INVALID_GTT_INT_EN (1 << 22)
5800#define SPRITED_INVALID_GTT_INT_EN (1 << 21)
5801#define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
5802#define PLANEB_INVALID_GTT_INT_EN (1 << 19)
5803#define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
5804#define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
5805#define PLANEA_INVALID_GTT_INT_EN (1 << 16)
5806#define DPINVGTT_EN_MASK 0xff0000
5807#define DPINVGTT_EN_MASK_CHV 0xfff0000
5808#define SPRITEF_INVALID_GTT_STATUS (1 << 11)
5809#define SPRITEE_INVALID_GTT_STATUS (1 << 10)
5810#define PLANEC_INVALID_GTT_STATUS (1 << 9)
5811#define CURSORC_INVALID_GTT_STATUS (1 << 8)
5812#define CURSORB_INVALID_GTT_STATUS (1 << 7)
5813#define CURSORA_INVALID_GTT_STATUS (1 << 6)
5814#define SPRITED_INVALID_GTT_STATUS (1 << 5)
5815#define SPRITEC_INVALID_GTT_STATUS (1 << 4)
5816#define PLANEB_INVALID_GTT_STATUS (1 << 3)
5817#define SPRITEB_INVALID_GTT_STATUS (1 << 2)
5818#define SPRITEA_INVALID_GTT_STATUS (1 << 1)
5819#define PLANEA_INVALID_GTT_STATUS (1 << 0)
5820#define DPINVGTT_STATUS_MASK 0xff
5821#define DPINVGTT_STATUS_MASK_CHV 0xfff
5822
5823#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5824#define DSPARB_CSTART_MASK (0x7f << 7)
5825#define DSPARB_CSTART_SHIFT 7
5826#define DSPARB_BSTART_MASK (0x7f)
5827#define DSPARB_BSTART_SHIFT 0
5828#define DSPARB_BEND_SHIFT 9 /* on 855 */
5829#define DSPARB_AEND_SHIFT 0
5830#define DSPARB_SPRITEA_SHIFT_VLV 0
5831#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5832#define DSPARB_SPRITEB_SHIFT_VLV 8
5833#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5834#define DSPARB_SPRITEC_SHIFT_VLV 16
5835#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5836#define DSPARB_SPRITED_SHIFT_VLV 24
5837#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5838#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5839#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5840#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5841#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5842#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5843#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5844#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5845#define DSPARB_SPRITED_HI_SHIFT_VLV 12
5846#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5847#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5848#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5849#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5850#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5851#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5852#define DSPARB_SPRITEE_SHIFT_VLV 0
5853#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5854#define DSPARB_SPRITEF_SHIFT_VLV 8
5855#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5856
5857/* pnv/gen4/g4x/vlv/chv */
5858#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5859#define DSPFW_SR_SHIFT 23
5860#define DSPFW_SR_MASK (0x1ff << 23)
5861#define DSPFW_CURSORB_SHIFT 16
5862#define DSPFW_CURSORB_MASK (0x3f << 16)
5863#define DSPFW_PLANEB_SHIFT 8
5864#define DSPFW_PLANEB_MASK (0x7f << 8)
5865#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
5866#define DSPFW_PLANEA_SHIFT 0
5867#define DSPFW_PLANEA_MASK (0x7f << 0)
5868#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
5869#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5870#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
5871#define DSPFW_FBC_SR_SHIFT 28
5872#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
5873#define DSPFW_FBC_HPLL_SR_SHIFT 24
5874#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
5875#define DSPFW_SPRITEB_SHIFT (16)
5876#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
5877#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
5878#define DSPFW_CURSORA_SHIFT 8
5879#define DSPFW_CURSORA_MASK (0x3f << 8)
5880#define DSPFW_PLANEC_OLD_SHIFT 0
5881#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
5882#define DSPFW_SPRITEA_SHIFT 0
5883#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
5884#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
5885#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
5886#define DSPFW_HPLL_SR_EN (1 << 31)
5887#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
5888#define DSPFW_CURSOR_SR_SHIFT 24
5889#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
5890#define DSPFW_HPLL_CURSOR_SHIFT 16
5891#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
5892#define DSPFW_HPLL_SR_SHIFT 0
5893#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
5894
5895/* vlv/chv */
5896#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5897#define DSPFW_SPRITEB_WM1_SHIFT 16
5898#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
5899#define DSPFW_CURSORA_WM1_SHIFT 8
5900#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
5901#define DSPFW_SPRITEA_WM1_SHIFT 0
5902#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
5903#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5904#define DSPFW_PLANEB_WM1_SHIFT 24
5905#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
5906#define DSPFW_PLANEA_WM1_SHIFT 16
5907#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
5908#define DSPFW_CURSORB_WM1_SHIFT 8
5909#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
5910#define DSPFW_CURSOR_SR_WM1_SHIFT 0
5911#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
5912#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5913#define DSPFW_SR_WM1_SHIFT 0
5914#define DSPFW_SR_WM1_MASK (0x1ff << 0)
5915#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5916#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5917#define DSPFW_SPRITED_WM1_SHIFT 24
5918#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
5919#define DSPFW_SPRITED_SHIFT 16
5920#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
5921#define DSPFW_SPRITEC_WM1_SHIFT 8
5922#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
5923#define DSPFW_SPRITEC_SHIFT 0
5924#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
5925#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5926#define DSPFW_SPRITEF_WM1_SHIFT 24
5927#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
5928#define DSPFW_SPRITEF_SHIFT 16
5929#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
5930#define DSPFW_SPRITEE_WM1_SHIFT 8
5931#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
5932#define DSPFW_SPRITEE_SHIFT 0
5933#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
5934#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5935#define DSPFW_PLANEC_WM1_SHIFT 24
5936#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
5937#define DSPFW_PLANEC_SHIFT 16
5938#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
5939#define DSPFW_CURSORC_WM1_SHIFT 8
5940#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
5941#define DSPFW_CURSORC_SHIFT 0
5942#define DSPFW_CURSORC_MASK (0x3f << 0)
5943
5944/* vlv/chv high order bits */
5945#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5946#define DSPFW_SR_HI_SHIFT 24
5947#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
5948#define DSPFW_SPRITEF_HI_SHIFT 23
5949#define DSPFW_SPRITEF_HI_MASK (1 << 23)
5950#define DSPFW_SPRITEE_HI_SHIFT 22
5951#define DSPFW_SPRITEE_HI_MASK (1 << 22)
5952#define DSPFW_PLANEC_HI_SHIFT 21
5953#define DSPFW_PLANEC_HI_MASK (1 << 21)
5954#define DSPFW_SPRITED_HI_SHIFT 20
5955#define DSPFW_SPRITED_HI_MASK (1 << 20)
5956#define DSPFW_SPRITEC_HI_SHIFT 16
5957#define DSPFW_SPRITEC_HI_MASK (1 << 16)
5958#define DSPFW_PLANEB_HI_SHIFT 12
5959#define DSPFW_PLANEB_HI_MASK (1 << 12)
5960#define DSPFW_SPRITEB_HI_SHIFT 8
5961#define DSPFW_SPRITEB_HI_MASK (1 << 8)
5962#define DSPFW_SPRITEA_HI_SHIFT 4
5963#define DSPFW_SPRITEA_HI_MASK (1 << 4)
5964#define DSPFW_PLANEA_HI_SHIFT 0
5965#define DSPFW_PLANEA_HI_MASK (1 << 0)
5966#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5967#define DSPFW_SR_WM1_HI_SHIFT 24
5968#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
5969#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5970#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
5971#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5972#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
5973#define DSPFW_PLANEC_WM1_HI_SHIFT 21
5974#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
5975#define DSPFW_SPRITED_WM1_HI_SHIFT 20
5976#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
5977#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5978#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
5979#define DSPFW_PLANEB_WM1_HI_SHIFT 12
5980#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
5981#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5982#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
5983#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5984#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
5985#define DSPFW_PLANEA_WM1_HI_SHIFT 0
5986#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
5987
5988/* drain latency register values*/
5989#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5990#define DDL_CURSOR_SHIFT 24
5991#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
5992#define DDL_PLANE_SHIFT 0
5993#define DDL_PRECISION_HIGH (1 << 7)
5994#define DDL_PRECISION_LOW (0 << 7)
5995#define DRAIN_LATENCY_MASK 0x7f
5996
5997#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5998#define CBR_PND_DEADLINE_DISABLE (1 << 31)
5999#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
6000
6001#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
6002#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
6003
6004/* FIFO watermark sizes etc */
6005#define G4X_FIFO_LINE_SIZE 64
6006#define I915_FIFO_LINE_SIZE 64
6007#define I830_FIFO_LINE_SIZE 32
6008
6009#define VALLEYVIEW_FIFO_SIZE 255
6010#define G4X_FIFO_SIZE 127
6011#define I965_FIFO_SIZE 512
6012#define I945_FIFO_SIZE 127
6013#define I915_FIFO_SIZE 95
6014#define I855GM_FIFO_SIZE 127 /* In cachelines */
6015#define I830_FIFO_SIZE 95
6016
6017#define VALLEYVIEW_MAX_WM 0xff
6018#define G4X_MAX_WM 0x3f
6019#define I915_MAX_WM 0x3f
6020
6021#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
6022#define PINEVIEW_FIFO_LINE_SIZE 64
6023#define PINEVIEW_MAX_WM 0x1ff
6024#define PINEVIEW_DFT_WM 0x3f
6025#define PINEVIEW_DFT_HPLLOFF_WM 0
6026#define PINEVIEW_GUARD_WM 10
6027#define PINEVIEW_CURSOR_FIFO 64
6028#define PINEVIEW_CURSOR_MAX_WM 0x3f
6029#define PINEVIEW_CURSOR_DFT_WM 0
6030#define PINEVIEW_CURSOR_GUARD_WM 5
6031
6032#define VALLEYVIEW_CURSOR_MAX_WM 64
6033#define I965_CURSOR_FIFO 64
6034#define I965_CURSOR_MAX_WM 32
6035#define I965_CURSOR_DFT_WM 8
6036
6037/* Watermark register definitions for SKL */
6038#define _CUR_WM_A_0 0x70140
6039#define _CUR_WM_B_0 0x71140
6040#define _PLANE_WM_1_A_0 0x70240
6041#define _PLANE_WM_1_B_0 0x71240
6042#define _PLANE_WM_2_A_0 0x70340
6043#define _PLANE_WM_2_B_0 0x71340
6044#define _PLANE_WM_TRANS_1_A_0 0x70268
6045#define _PLANE_WM_TRANS_1_B_0 0x71268
6046#define _PLANE_WM_TRANS_2_A_0 0x70368
6047#define _PLANE_WM_TRANS_2_B_0 0x71368
6048#define _CUR_WM_TRANS_A_0 0x70168
6049#define _CUR_WM_TRANS_B_0 0x71168
6050#define PLANE_WM_EN (1 << 31)
6051#define PLANE_WM_IGNORE_LINES (1 << 30)
6052#define PLANE_WM_LINES_SHIFT 14
6053#define PLANE_WM_LINES_MASK 0x1f
6054#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
6055
6056#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6057#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6058#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6059
6060#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6061#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6062#define _PLANE_WM_BASE(pipe, plane) \
6063 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6064#define PLANE_WM(pipe, plane, level) \
6065 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6066#define _PLANE_WM_TRANS_1(pipe) \
6067 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6068#define _PLANE_WM_TRANS_2(pipe) \
6069 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6070#define PLANE_WM_TRANS(pipe, plane) \
6071 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6072
6073/* define the Watermark register on Ironlake */
6074#define WM0_PIPEA_ILK _MMIO(0x45100)
6075#define WM0_PIPE_PLANE_MASK (0xffff << 16)
6076#define WM0_PIPE_PLANE_SHIFT 16
6077#define WM0_PIPE_SPRITE_MASK (0xff << 8)
6078#define WM0_PIPE_SPRITE_SHIFT 8
6079#define WM0_PIPE_CURSOR_MASK (0xff)
6080
6081#define WM0_PIPEB_ILK _MMIO(0x45104)
6082#define WM0_PIPEC_IVB _MMIO(0x45200)
6083#define WM1_LP_ILK _MMIO(0x45108)
6084#define WM1_LP_SR_EN (1 << 31)
6085#define WM1_LP_LATENCY_SHIFT 24
6086#define WM1_LP_LATENCY_MASK (0x7f << 24)
6087#define WM1_LP_FBC_MASK (0xf << 20)
6088#define WM1_LP_FBC_SHIFT 20
6089#define WM1_LP_FBC_SHIFT_BDW 19
6090#define WM1_LP_SR_MASK (0x7ff << 8)
6091#define WM1_LP_SR_SHIFT 8
6092#define WM1_LP_CURSOR_MASK (0xff)
6093#define WM2_LP_ILK _MMIO(0x4510c)
6094#define WM2_LP_EN (1 << 31)
6095#define WM3_LP_ILK _MMIO(0x45110)
6096#define WM3_LP_EN (1 << 31)
6097#define WM1S_LP_ILK _MMIO(0x45120)
6098#define WM2S_LP_IVB _MMIO(0x45124)
6099#define WM3S_LP_IVB _MMIO(0x45128)
6100#define WM1S_LP_EN (1 << 31)
6101
6102#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6103 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6104 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6105
6106/* Memory latency timer register */
6107#define MLTR_ILK _MMIO(0x11222)
6108#define MLTR_WM1_SHIFT 0
6109#define MLTR_WM2_SHIFT 8
6110/* the unit of memory self-refresh latency time is 0.5us */
6111#define ILK_SRLT_MASK 0x3f
6112
6113
6114/* the address where we get all kinds of latency value */
6115#define SSKPD _MMIO(0x5d10)
6116#define SSKPD_WM_MASK 0x3f
6117#define SSKPD_WM0_SHIFT 0
6118#define SSKPD_WM1_SHIFT 8
6119#define SSKPD_WM2_SHIFT 16
6120#define SSKPD_WM3_SHIFT 24
6121
6122/*
6123 * The two pipe frame counter registers are not synchronized, so
6124 * reading a stable value is somewhat tricky. The following code
6125 * should work:
6126 *
6127 * do {
6128 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6129 * PIPE_FRAME_HIGH_SHIFT;
6130 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6131 * PIPE_FRAME_LOW_SHIFT);
6132 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6133 * PIPE_FRAME_HIGH_SHIFT);
6134 * } while (high1 != high2);
6135 * frame = (high1 << 8) | low1;
6136 */
6137#define _PIPEAFRAMEHIGH 0x70040
6138#define PIPE_FRAME_HIGH_MASK 0x0000ffff
6139#define PIPE_FRAME_HIGH_SHIFT 0
6140#define _PIPEAFRAMEPIXEL 0x70044
6141#define PIPE_FRAME_LOW_MASK 0xff000000
6142#define PIPE_FRAME_LOW_SHIFT 24
6143#define PIPE_PIXEL_MASK 0x00ffffff
6144#define PIPE_PIXEL_SHIFT 0
6145/* GM45+ just has to be different */
6146#define _PIPEA_FRMCOUNT_G4X 0x70040
6147#define _PIPEA_FLIPCOUNT_G4X 0x70044
6148#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6149#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6150
6151/* Cursor A & B regs */
6152#define _CURACNTR 0x70080
6153/* Old style CUR*CNTR flags (desktop 8xx) */
6154#define CURSOR_ENABLE 0x80000000
6155#define CURSOR_GAMMA_ENABLE 0x40000000
6156#define CURSOR_STRIDE_SHIFT 28
6157#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6158#define CURSOR_FORMAT_SHIFT 24
6159#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6160#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6161#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6162#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6163#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6164#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6165/* New style CUR*CNTR flags */
6166#define MCURSOR_MODE 0x27
6167#define MCURSOR_MODE_DISABLE 0x00
6168#define MCURSOR_MODE_128_32B_AX 0x02
6169#define MCURSOR_MODE_256_32B_AX 0x03
6170#define MCURSOR_MODE_64_32B_AX 0x07
6171#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6172#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6173#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6174#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6175#define MCURSOR_PIPE_SELECT_SHIFT 28
6176#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6177#define MCURSOR_GAMMA_ENABLE (1 << 26)
6178#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6179#define MCURSOR_ROTATE_180 (1 << 15)
6180#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6181#define _CURABASE 0x70084
6182#define _CURAPOS 0x70088
6183#define CURSOR_POS_MASK 0x007FF
6184#define CURSOR_POS_SIGN 0x8000
6185#define CURSOR_X_SHIFT 0
6186#define CURSOR_Y_SHIFT 16
6187#define CURSIZE _MMIO(0x700a0) /* 845/865 */
6188#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6189#define CUR_FBC_CTL_EN (1 << 31)
6190#define _CURASURFLIVE 0x700ac /* g4x+ */
6191#define _CURBCNTR 0x700c0
6192#define _CURBBASE 0x700c4
6193#define _CURBPOS 0x700c8
6194
6195#define _CURBCNTR_IVB 0x71080
6196#define _CURBBASE_IVB 0x71084
6197#define _CURBPOS_IVB 0x71088
6198
6199#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6200#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6201#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6202#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6203#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6204
6205#define CURSOR_A_OFFSET 0x70080
6206#define CURSOR_B_OFFSET 0x700c0
6207#define CHV_CURSOR_C_OFFSET 0x700e0
6208#define IVB_CURSOR_B_OFFSET 0x71080
6209#define IVB_CURSOR_C_OFFSET 0x72080
6210
6211/* Display A control */
6212#define _DSPACNTR 0x70180
6213#define DISPLAY_PLANE_ENABLE (1 << 31)
6214#define DISPLAY_PLANE_DISABLE 0
6215#define DISPPLANE_GAMMA_ENABLE (1 << 30)
6216#define DISPPLANE_GAMMA_DISABLE 0
6217#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6218#define DISPPLANE_YUV422 (0x0 << 26)
6219#define DISPPLANE_8BPP (0x2 << 26)
6220#define DISPPLANE_BGRA555 (0x3 << 26)
6221#define DISPPLANE_BGRX555 (0x4 << 26)
6222#define DISPPLANE_BGRX565 (0x5 << 26)
6223#define DISPPLANE_BGRX888 (0x6 << 26)
6224#define DISPPLANE_BGRA888 (0x7 << 26)
6225#define DISPPLANE_RGBX101010 (0x8 << 26)
6226#define DISPPLANE_RGBA101010 (0x9 << 26)
6227#define DISPPLANE_BGRX101010 (0xa << 26)
6228#define DISPPLANE_RGBX161616 (0xc << 26)
6229#define DISPPLANE_RGBX888 (0xe << 26)
6230#define DISPPLANE_RGBA888 (0xf << 26)
6231#define DISPPLANE_STEREO_ENABLE (1 << 25)
6232#define DISPPLANE_STEREO_DISABLE 0
6233#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6234#define DISPPLANE_SEL_PIPE_SHIFT 24
6235#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6236#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6237#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6238#define DISPPLANE_SRC_KEY_DISABLE 0
6239#define DISPPLANE_LINE_DOUBLE (1 << 20)
6240#define DISPPLANE_NO_LINE_DOUBLE 0
6241#define DISPPLANE_STEREO_POLARITY_FIRST 0
6242#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6243#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6244#define DISPPLANE_ROTATE_180 (1 << 15)
6245#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6246#define DISPPLANE_TILED (1 << 10)
6247#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
6248#define _DSPAADDR 0x70184
6249#define _DSPASTRIDE 0x70188
6250#define _DSPAPOS 0x7018C /* reserved */
6251#define _DSPASIZE 0x70190
6252#define _DSPASURF 0x7019C /* 965+ only */
6253#define _DSPATILEOFF 0x701A4 /* 965+ only */
6254#define _DSPAOFFSET 0x701A4 /* HSW */
6255#define _DSPASURFLIVE 0x701AC
6256#define _DSPAGAMC 0x701E0
6257
6258#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6259#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6260#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6261#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6262#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6263#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6264#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6265#define DSPLINOFF(plane) DSPADDR(plane)
6266#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6267#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6268#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6269
6270/* CHV pipe B blender and primary plane */
6271#define _CHV_BLEND_A 0x60a00
6272#define CHV_BLEND_LEGACY (0 << 30)
6273#define CHV_BLEND_ANDROID (1 << 30)
6274#define CHV_BLEND_MPO (2 << 30)
6275#define CHV_BLEND_MASK (3 << 30)
6276#define _CHV_CANVAS_A 0x60a04
6277#define _PRIMPOS_A 0x60a08
6278#define _PRIMSIZE_A 0x60a0c
6279#define _PRIMCNSTALPHA_A 0x60a10
6280#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6281
6282#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6283#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6284#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6285#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6286#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6287
6288/* Display/Sprite base address macros */
6289#define DISP_BASEADDR_MASK (0xfffff000)
6290#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6291#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6292
6293/*
6294 * VBIOS flags
6295 * gen2:
6296 * [00:06] alm,mgm
6297 * [10:16] all
6298 * [30:32] alm,mgm
6299 * gen3+:
6300 * [00:0f] all
6301 * [10:1f] all
6302 * [30:32] all
6303 */
6304#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6305#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6306#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6307#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6308
6309/* Pipe B */
6310#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6311#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6312#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6313#define _PIPEBFRAMEHIGH 0x71040
6314#define _PIPEBFRAMEPIXEL 0x71044
6315#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6316#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6317
6318
6319/* Display B control */
6320#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6321#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6322#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6323#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6324#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6325#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6326#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6327#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6328#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6329#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6330#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6331#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6332#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6333
6334/* ICL DSI 0 and 1 */
6335#define _PIPEDSI0CONF 0x7b008
6336#define _PIPEDSI1CONF 0x7b808
6337
6338/* Sprite A control */
6339#define _DVSACNTR 0x72180
6340#define DVS_ENABLE (1 << 31)
6341#define DVS_GAMMA_ENABLE (1 << 30)
6342#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6343#define DVS_PIXFORMAT_MASK (3 << 25)
6344#define DVS_FORMAT_YUV422 (0 << 25)
6345#define DVS_FORMAT_RGBX101010 (1 << 25)
6346#define DVS_FORMAT_RGBX888 (2 << 25)
6347#define DVS_FORMAT_RGBX161616 (3 << 25)
6348#define DVS_PIPE_CSC_ENABLE (1 << 24)
6349#define DVS_SOURCE_KEY (1 << 22)
6350#define DVS_RGB_ORDER_XBGR (1 << 20)
6351#define DVS_YUV_FORMAT_BT709 (1 << 18)
6352#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6353#define DVS_YUV_ORDER_YUYV (0 << 16)
6354#define DVS_YUV_ORDER_UYVY (1 << 16)
6355#define DVS_YUV_ORDER_YVYU (2 << 16)
6356#define DVS_YUV_ORDER_VYUY (3 << 16)
6357#define DVS_ROTATE_180 (1 << 15)
6358#define DVS_DEST_KEY (1 << 2)
6359#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6360#define DVS_TILED (1 << 10)
6361#define _DVSALINOFF 0x72184
6362#define _DVSASTRIDE 0x72188
6363#define _DVSAPOS 0x7218c
6364#define _DVSASIZE 0x72190
6365#define _DVSAKEYVAL 0x72194
6366#define _DVSAKEYMSK 0x72198
6367#define _DVSASURF 0x7219c
6368#define _DVSAKEYMAXVAL 0x721a0
6369#define _DVSATILEOFF 0x721a4
6370#define _DVSASURFLIVE 0x721ac
6371#define _DVSAGAMC_G4X 0x721e0 /* g4x */
6372#define _DVSASCALE 0x72204
6373#define DVS_SCALE_ENABLE (1 << 31)
6374#define DVS_FILTER_MASK (3 << 29)
6375#define DVS_FILTER_MEDIUM (0 << 29)
6376#define DVS_FILTER_ENHANCING (1 << 29)
6377#define DVS_FILTER_SOFTENING (2 << 29)
6378#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6379#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6380#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
6381#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
6382
6383#define _DVSBCNTR 0x73180
6384#define _DVSBLINOFF 0x73184
6385#define _DVSBSTRIDE 0x73188
6386#define _DVSBPOS 0x7318c
6387#define _DVSBSIZE 0x73190
6388#define _DVSBKEYVAL 0x73194
6389#define _DVSBKEYMSK 0x73198
6390#define _DVSBSURF 0x7319c
6391#define _DVSBKEYMAXVAL 0x731a0
6392#define _DVSBTILEOFF 0x731a4
6393#define _DVSBSURFLIVE 0x731ac
6394#define _DVSBGAMC_G4X 0x731e0 /* g4x */
6395#define _DVSBSCALE 0x73204
6396#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
6397#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
6398
6399#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6400#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6401#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6402#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6403#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6404#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6405#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6406#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6407#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6408#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6409#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6410#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6411#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6412#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6413#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6414
6415#define _SPRA_CTL 0x70280
6416#define SPRITE_ENABLE (1 << 31)
6417#define SPRITE_GAMMA_ENABLE (1 << 30)
6418#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6419#define SPRITE_PIXFORMAT_MASK (7 << 25)
6420#define SPRITE_FORMAT_YUV422 (0 << 25)
6421#define SPRITE_FORMAT_RGBX101010 (1 << 25)
6422#define SPRITE_FORMAT_RGBX888 (2 << 25)
6423#define SPRITE_FORMAT_RGBX161616 (3 << 25)
6424#define SPRITE_FORMAT_YUV444 (4 << 25)
6425#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
6426#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
6427#define SPRITE_SOURCE_KEY (1 << 22)
6428#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
6429#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6430#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
6431#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
6432#define SPRITE_YUV_ORDER_YUYV (0 << 16)
6433#define SPRITE_YUV_ORDER_UYVY (1 << 16)
6434#define SPRITE_YUV_ORDER_YVYU (2 << 16)
6435#define SPRITE_YUV_ORDER_VYUY (3 << 16)
6436#define SPRITE_ROTATE_180 (1 << 15)
6437#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6438#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
6439#define SPRITE_TILED (1 << 10)
6440#define SPRITE_DEST_KEY (1 << 2)
6441#define _SPRA_LINOFF 0x70284
6442#define _SPRA_STRIDE 0x70288
6443#define _SPRA_POS 0x7028c
6444#define _SPRA_SIZE 0x70290
6445#define _SPRA_KEYVAL 0x70294
6446#define _SPRA_KEYMSK 0x70298
6447#define _SPRA_SURF 0x7029c
6448#define _SPRA_KEYMAX 0x702a0
6449#define _SPRA_TILEOFF 0x702a4
6450#define _SPRA_OFFSET 0x702a4
6451#define _SPRA_SURFLIVE 0x702ac
6452#define _SPRA_SCALE 0x70304
6453#define SPRITE_SCALE_ENABLE (1 << 31)
6454#define SPRITE_FILTER_MASK (3 << 29)
6455#define SPRITE_FILTER_MEDIUM (0 << 29)
6456#define SPRITE_FILTER_ENHANCING (1 << 29)
6457#define SPRITE_FILTER_SOFTENING (2 << 29)
6458#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6459#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6460#define _SPRA_GAMC 0x70400
6461#define _SPRA_GAMC16 0x70440
6462#define _SPRA_GAMC17 0x7044c
6463
6464#define _SPRB_CTL 0x71280
6465#define _SPRB_LINOFF 0x71284
6466#define _SPRB_STRIDE 0x71288
6467#define _SPRB_POS 0x7128c
6468#define _SPRB_SIZE 0x71290
6469#define _SPRB_KEYVAL 0x71294
6470#define _SPRB_KEYMSK 0x71298
6471#define _SPRB_SURF 0x7129c
6472#define _SPRB_KEYMAX 0x712a0
6473#define _SPRB_TILEOFF 0x712a4
6474#define _SPRB_OFFSET 0x712a4
6475#define _SPRB_SURFLIVE 0x712ac
6476#define _SPRB_SCALE 0x71304
6477#define _SPRB_GAMC 0x71400
6478#define _SPRB_GAMC16 0x71440
6479#define _SPRB_GAMC17 0x7144c
6480
6481#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6482#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6483#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6484#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6485#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6486#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6487#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6488#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6489#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6490#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6491#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6492#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6493#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6494#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6495#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6496#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6497
6498#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6499#define SP_ENABLE (1 << 31)
6500#define SP_GAMMA_ENABLE (1 << 30)
6501#define SP_PIXFORMAT_MASK (0xf << 26)
6502#define SP_FORMAT_YUV422 (0 << 26)
6503#define SP_FORMAT_BGR565 (5 << 26)
6504#define SP_FORMAT_BGRX8888 (6 << 26)
6505#define SP_FORMAT_BGRA8888 (7 << 26)
6506#define SP_FORMAT_RGBX1010102 (8 << 26)
6507#define SP_FORMAT_RGBA1010102 (9 << 26)
6508#define SP_FORMAT_RGBX8888 (0xe << 26)
6509#define SP_FORMAT_RGBA8888 (0xf << 26)
6510#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
6511#define SP_SOURCE_KEY (1 << 22)
6512#define SP_YUV_FORMAT_BT709 (1 << 18)
6513#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
6514#define SP_YUV_ORDER_YUYV (0 << 16)
6515#define SP_YUV_ORDER_UYVY (1 << 16)
6516#define SP_YUV_ORDER_YVYU (2 << 16)
6517#define SP_YUV_ORDER_VYUY (3 << 16)
6518#define SP_ROTATE_180 (1 << 15)
6519#define SP_TILED (1 << 10)
6520#define SP_MIRROR (1 << 8) /* CHV pipe B */
6521#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6522#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6523#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6524#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6525#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6526#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6527#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6528#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6529#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6530#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6531#define SP_CONST_ALPHA_ENABLE (1 << 31)
6532#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6533#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
6534#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
6535#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6536#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6537#define SP_SH_COS(x) (x) /* u3.7 */
6538#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
6539
6540#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6541#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6542#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6543#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6544#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6545#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6546#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6547#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6548#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6549#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6550#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6551#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6552#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6553#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
6554
6555#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6556 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6557#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6558 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6559
6560#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6561#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6562#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6563#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6564#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6565#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6566#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6567#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6568#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6569#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6570#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6571#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6572#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6573#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6574
6575/*
6576 * CHV pipe B sprite CSC
6577 *
6578 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6579 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6580 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6581 */
6582#define _MMIO_CHV_SPCSC(plane_id, reg) \
6583 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6584
6585#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6586#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6587#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6588#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6589#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6590
6591#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6592#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6593#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6594#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6595#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6596#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6597#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6598
6599#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6600#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6601#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6602#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6603#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6604
6605#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6606#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6607#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6608#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6609#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6610
6611/* Skylake plane registers */
6612
6613#define _PLANE_CTL_1_A 0x70180
6614#define _PLANE_CTL_2_A 0x70280
6615#define _PLANE_CTL_3_A 0x70380
6616#define PLANE_CTL_ENABLE (1 << 31)
6617#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6618#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6619/*
6620 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6621 * expanded to include bit 23 as well. However, the shift-24 based values
6622 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6623 */
6624#define PLANE_CTL_FORMAT_MASK (0xf << 24)
6625#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6626#define PLANE_CTL_FORMAT_NV12 (1 << 24)
6627#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
6628#define PLANE_CTL_FORMAT_P010 (3 << 24)
6629#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
6630#define PLANE_CTL_FORMAT_P012 (5 << 24)
6631#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
6632#define PLANE_CTL_FORMAT_P016 (7 << 24)
6633#define PLANE_CTL_FORMAT_AYUV (8 << 24)
6634#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
6635#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
6636#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6637#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6638#define PLANE_CTL_FORMAT_Y210 (1 << 23)
6639#define PLANE_CTL_FORMAT_Y212 (3 << 23)
6640#define PLANE_CTL_FORMAT_Y216 (5 << 23)
6641#define PLANE_CTL_FORMAT_Y410 (7 << 23)
6642#define PLANE_CTL_FORMAT_Y412 (9 << 23)
6643#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
6644#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6645#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
6646#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6647#define PLANE_CTL_ORDER_BGRX (0 << 20)
6648#define PLANE_CTL_ORDER_RGBX (1 << 20)
6649#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
6650#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6651#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6652#define PLANE_CTL_YUV422_YUYV (0 << 16)
6653#define PLANE_CTL_YUV422_UYVY (1 << 16)
6654#define PLANE_CTL_YUV422_YVYU (2 << 16)
6655#define PLANE_CTL_YUV422_VYUY (3 << 16)
6656#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6657#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6658#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6659#define PLANE_CTL_TILED_MASK (0x7 << 10)
6660#define PLANE_CTL_TILED_LINEAR (0 << 10)
6661#define PLANE_CTL_TILED_X (1 << 10)
6662#define PLANE_CTL_TILED_Y (4 << 10)
6663#define PLANE_CTL_TILED_YF (5 << 10)
6664#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
6665#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6666#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
6667#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
6668#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
6669#define PLANE_CTL_ROTATE_MASK 0x3
6670#define PLANE_CTL_ROTATE_0 0x0
6671#define PLANE_CTL_ROTATE_90 0x1
6672#define PLANE_CTL_ROTATE_180 0x2
6673#define PLANE_CTL_ROTATE_270 0x3
6674#define _PLANE_STRIDE_1_A 0x70188
6675#define _PLANE_STRIDE_2_A 0x70288
6676#define _PLANE_STRIDE_3_A 0x70388
6677#define _PLANE_POS_1_A 0x7018c
6678#define _PLANE_POS_2_A 0x7028c
6679#define _PLANE_POS_3_A 0x7038c
6680#define _PLANE_SIZE_1_A 0x70190
6681#define _PLANE_SIZE_2_A 0x70290
6682#define _PLANE_SIZE_3_A 0x70390
6683#define _PLANE_SURF_1_A 0x7019c
6684#define _PLANE_SURF_2_A 0x7029c
6685#define _PLANE_SURF_3_A 0x7039c
6686#define _PLANE_OFFSET_1_A 0x701a4
6687#define _PLANE_OFFSET_2_A 0x702a4
6688#define _PLANE_OFFSET_3_A 0x703a4
6689#define _PLANE_KEYVAL_1_A 0x70194
6690#define _PLANE_KEYVAL_2_A 0x70294
6691#define _PLANE_KEYMSK_1_A 0x70198
6692#define _PLANE_KEYMSK_2_A 0x70298
6693#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
6694#define _PLANE_KEYMAX_1_A 0x701a0
6695#define _PLANE_KEYMAX_2_A 0x702a0
6696#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
6697#define _PLANE_AUX_DIST_1_A 0x701c0
6698#define _PLANE_AUX_DIST_2_A 0x702c0
6699#define _PLANE_AUX_OFFSET_1_A 0x701c4
6700#define _PLANE_AUX_OFFSET_2_A 0x702c4
6701#define _PLANE_CUS_CTL_1_A 0x701c8
6702#define _PLANE_CUS_CTL_2_A 0x702c8
6703#define PLANE_CUS_ENABLE (1 << 31)
6704#define PLANE_CUS_PLANE_6 (0 << 30)
6705#define PLANE_CUS_PLANE_7 (1 << 30)
6706#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
6707#define PLANE_CUS_HPHASE_0 (0 << 16)
6708#define PLANE_CUS_HPHASE_0_25 (1 << 16)
6709#define PLANE_CUS_HPHASE_0_5 (2 << 16)
6710#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
6711#define PLANE_CUS_VPHASE_0 (0 << 12)
6712#define PLANE_CUS_VPHASE_0_25 (1 << 12)
6713#define PLANE_CUS_VPHASE_0_5 (2 << 12)
6714#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6715#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6716#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6717#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6718#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6719#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
6720#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
6721#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6722#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
6723#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6724#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6725#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
6726#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6727#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6728#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6729#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6730#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6731#define _PLANE_BUF_CFG_1_A 0x7027c
6732#define _PLANE_BUF_CFG_2_A 0x7037c
6733#define _PLANE_NV12_BUF_CFG_1_A 0x70278
6734#define _PLANE_NV12_BUF_CFG_2_A 0x70378
6735
6736/* Input CSC Register Definitions */
6737#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
6738#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
6739
6740#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
6741#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
6742
6743#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
6744 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6745 _PLANE_INPUT_CSC_RY_GY_1_B)
6746#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
6747 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6748 _PLANE_INPUT_CSC_RY_GY_2_B)
6749
6750#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
6751 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
6752 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6753
6754#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
6755#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
6756
6757#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
6758#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
6759
6760#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
6761 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6762 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6763#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
6764 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6765 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6766#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
6767 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6768 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6769
6770#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
6771#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
6772
6773#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
6774#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
6775
6776#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
6777 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6778 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6779#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
6780 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6781 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6782#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
6783 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6784 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6785
6786#define _PLANE_CTL_1_B 0x71180
6787#define _PLANE_CTL_2_B 0x71280
6788#define _PLANE_CTL_3_B 0x71380
6789#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6790#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6791#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6792#define PLANE_CTL(pipe, plane) \
6793 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6794
6795#define _PLANE_STRIDE_1_B 0x71188
6796#define _PLANE_STRIDE_2_B 0x71288
6797#define _PLANE_STRIDE_3_B 0x71388
6798#define _PLANE_STRIDE_1(pipe) \
6799 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6800#define _PLANE_STRIDE_2(pipe) \
6801 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6802#define _PLANE_STRIDE_3(pipe) \
6803 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6804#define PLANE_STRIDE(pipe, plane) \
6805 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6806
6807#define _PLANE_POS_1_B 0x7118c
6808#define _PLANE_POS_2_B 0x7128c
6809#define _PLANE_POS_3_B 0x7138c
6810#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6811#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6812#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6813#define PLANE_POS(pipe, plane) \
6814 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6815
6816#define _PLANE_SIZE_1_B 0x71190
6817#define _PLANE_SIZE_2_B 0x71290
6818#define _PLANE_SIZE_3_B 0x71390
6819#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6820#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6821#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6822#define PLANE_SIZE(pipe, plane) \
6823 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6824
6825#define _PLANE_SURF_1_B 0x7119c
6826#define _PLANE_SURF_2_B 0x7129c
6827#define _PLANE_SURF_3_B 0x7139c
6828#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6829#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6830#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6831#define PLANE_SURF(pipe, plane) \
6832 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6833
6834#define _PLANE_OFFSET_1_B 0x711a4
6835#define _PLANE_OFFSET_2_B 0x712a4
6836#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6837#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6838#define PLANE_OFFSET(pipe, plane) \
6839 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6840
6841#define _PLANE_KEYVAL_1_B 0x71194
6842#define _PLANE_KEYVAL_2_B 0x71294
6843#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6844#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6845#define PLANE_KEYVAL(pipe, plane) \
6846 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6847
6848#define _PLANE_KEYMSK_1_B 0x71198
6849#define _PLANE_KEYMSK_2_B 0x71298
6850#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6851#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6852#define PLANE_KEYMSK(pipe, plane) \
6853 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6854
6855#define _PLANE_KEYMAX_1_B 0x711a0
6856#define _PLANE_KEYMAX_2_B 0x712a0
6857#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6858#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6859#define PLANE_KEYMAX(pipe, plane) \
6860 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6861
6862#define _PLANE_BUF_CFG_1_B 0x7127c
6863#define _PLANE_BUF_CFG_2_B 0x7137c
6864#define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */
6865#define DDB_ENTRY_END_SHIFT 16
6866#define _PLANE_BUF_CFG_1(pipe) \
6867 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6868#define _PLANE_BUF_CFG_2(pipe) \
6869 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6870#define PLANE_BUF_CFG(pipe, plane) \
6871 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6872
6873#define _PLANE_NV12_BUF_CFG_1_B 0x71278
6874#define _PLANE_NV12_BUF_CFG_2_B 0x71378
6875#define _PLANE_NV12_BUF_CFG_1(pipe) \
6876 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6877#define _PLANE_NV12_BUF_CFG_2(pipe) \
6878 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6879#define PLANE_NV12_BUF_CFG(pipe, plane) \
6880 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6881
6882#define _PLANE_AUX_DIST_1_B 0x711c0
6883#define _PLANE_AUX_DIST_2_B 0x712c0
6884#define _PLANE_AUX_DIST_1(pipe) \
6885 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6886#define _PLANE_AUX_DIST_2(pipe) \
6887 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6888#define PLANE_AUX_DIST(pipe, plane) \
6889 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6890
6891#define _PLANE_AUX_OFFSET_1_B 0x711c4
6892#define _PLANE_AUX_OFFSET_2_B 0x712c4
6893#define _PLANE_AUX_OFFSET_1(pipe) \
6894 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6895#define _PLANE_AUX_OFFSET_2(pipe) \
6896 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6897#define PLANE_AUX_OFFSET(pipe, plane) \
6898 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6899
6900#define _PLANE_CUS_CTL_1_B 0x711c8
6901#define _PLANE_CUS_CTL_2_B 0x712c8
6902#define _PLANE_CUS_CTL_1(pipe) \
6903 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
6904#define _PLANE_CUS_CTL_2(pipe) \
6905 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
6906#define PLANE_CUS_CTL(pipe, plane) \
6907 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
6908
6909#define _PLANE_COLOR_CTL_1_B 0x711CC
6910#define _PLANE_COLOR_CTL_2_B 0x712CC
6911#define _PLANE_COLOR_CTL_3_B 0x713CC
6912#define _PLANE_COLOR_CTL_1(pipe) \
6913 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6914#define _PLANE_COLOR_CTL_2(pipe) \
6915 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6916#define PLANE_COLOR_CTL(pipe, plane) \
6917 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6918
6919#/* SKL new cursor registers */
6920#define _CUR_BUF_CFG_A 0x7017c
6921#define _CUR_BUF_CFG_B 0x7117c
6922#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6923
6924/* VBIOS regs */
6925#define VGACNTRL _MMIO(0x71400)
6926# define VGA_DISP_DISABLE (1 << 31)
6927# define VGA_2X_MODE (1 << 30)
6928# define VGA_PIPE_B_SELECT (1 << 29)
6929
6930#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6931
6932/* Ironlake */
6933
6934#define CPU_VGACNTRL _MMIO(0x41000)
6935
6936#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6937#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6938#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6939#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6940#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6941#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6942#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6943#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6944#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6945#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6946#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6947
6948/* refresh rate hardware control */
6949#define RR_HW_CTL _MMIO(0x45300)
6950#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6951#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6952
6953#define FDI_PLL_BIOS_0 _MMIO(0x46000)
6954#define FDI_PLL_FB_CLOCK_MASK 0xff
6955#define FDI_PLL_BIOS_1 _MMIO(0x46004)
6956#define FDI_PLL_BIOS_2 _MMIO(0x46008)
6957#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6958#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6959#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6960
6961#define PCH_3DCGDIS0 _MMIO(0x46020)
6962# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6963# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6964
6965#define PCH_3DCGDIS1 _MMIO(0x46024)
6966# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6967
6968#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6969#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
6970#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6971#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6972
6973
6974#define _PIPEA_DATA_M1 0x60030
6975#define PIPE_DATA_M1_OFFSET 0
6976#define _PIPEA_DATA_N1 0x60034
6977#define PIPE_DATA_N1_OFFSET 0
6978
6979#define _PIPEA_DATA_M2 0x60038
6980#define PIPE_DATA_M2_OFFSET 0
6981#define _PIPEA_DATA_N2 0x6003c
6982#define PIPE_DATA_N2_OFFSET 0
6983
6984#define _PIPEA_LINK_M1 0x60040
6985#define PIPE_LINK_M1_OFFSET 0
6986#define _PIPEA_LINK_N1 0x60044
6987#define PIPE_LINK_N1_OFFSET 0
6988
6989#define _PIPEA_LINK_M2 0x60048
6990#define PIPE_LINK_M2_OFFSET 0
6991#define _PIPEA_LINK_N2 0x6004c
6992#define PIPE_LINK_N2_OFFSET 0
6993
6994/* PIPEB timing regs are same start from 0x61000 */
6995
6996#define _PIPEB_DATA_M1 0x61030
6997#define _PIPEB_DATA_N1 0x61034
6998#define _PIPEB_DATA_M2 0x61038
6999#define _PIPEB_DATA_N2 0x6103c
7000#define _PIPEB_LINK_M1 0x61040
7001#define _PIPEB_LINK_N1 0x61044
7002#define _PIPEB_LINK_M2 0x61048
7003#define _PIPEB_LINK_N2 0x6104c
7004
7005#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7006#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7007#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7008#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7009#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7010#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7011#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7012#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7013
7014/* CPU panel fitter */
7015/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7016#define _PFA_CTL_1 0x68080
7017#define _PFB_CTL_1 0x68880
7018#define PF_ENABLE (1 << 31)
7019#define PF_PIPE_SEL_MASK_IVB (3 << 29)
7020#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
7021#define PF_FILTER_MASK (3 << 23)
7022#define PF_FILTER_PROGRAMMED (0 << 23)
7023#define PF_FILTER_MED_3x3 (1 << 23)
7024#define PF_FILTER_EDGE_ENHANCE (2 << 23)
7025#define PF_FILTER_EDGE_SOFTEN (3 << 23)
7026#define _PFA_WIN_SZ 0x68074
7027#define _PFB_WIN_SZ 0x68874
7028#define _PFA_WIN_POS 0x68070
7029#define _PFB_WIN_POS 0x68870
7030#define _PFA_VSCALE 0x68084
7031#define _PFB_VSCALE 0x68884
7032#define _PFA_HSCALE 0x68090
7033#define _PFB_HSCALE 0x68890
7034
7035#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7036#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7037#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7038#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7039#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7040
7041#define _PSA_CTL 0x68180
7042#define _PSB_CTL 0x68980
7043#define PS_ENABLE (1 << 31)
7044#define _PSA_WIN_SZ 0x68174
7045#define _PSB_WIN_SZ 0x68974
7046#define _PSA_WIN_POS 0x68170
7047#define _PSB_WIN_POS 0x68970
7048
7049#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7050#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7051#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7052
7053/*
7054 * Skylake scalers
7055 */
7056#define _PS_1A_CTRL 0x68180
7057#define _PS_2A_CTRL 0x68280
7058#define _PS_1B_CTRL 0x68980
7059#define _PS_2B_CTRL 0x68A80
7060#define _PS_1C_CTRL 0x69180
7061#define PS_SCALER_EN (1 << 31)
7062#define SKL_PS_SCALER_MODE_MASK (3 << 28)
7063#define SKL_PS_SCALER_MODE_DYN (0 << 28)
7064#define SKL_PS_SCALER_MODE_HQ (1 << 28)
7065#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7066#define PS_SCALER_MODE_PLANAR (1 << 29)
7067#define PS_SCALER_MODE_NORMAL (0 << 29)
7068#define PS_PLANE_SEL_MASK (7 << 25)
7069#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7070#define PS_FILTER_MASK (3 << 23)
7071#define PS_FILTER_MEDIUM (0 << 23)
7072#define PS_FILTER_EDGE_ENHANCE (2 << 23)
7073#define PS_FILTER_BILINEAR (3 << 23)
7074#define PS_VERT3TAP (1 << 21)
7075#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7076#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7077#define PS_PWRUP_PROGRESS (1 << 17)
7078#define PS_V_FILTER_BYPASS (1 << 8)
7079#define PS_VADAPT_EN (1 << 7)
7080#define PS_VADAPT_MODE_MASK (3 << 5)
7081#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7082#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
7083#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
7084#define PS_PLANE_Y_SEL_MASK (7 << 5)
7085#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7086
7087#define _PS_PWR_GATE_1A 0x68160
7088#define _PS_PWR_GATE_2A 0x68260
7089#define _PS_PWR_GATE_1B 0x68960
7090#define _PS_PWR_GATE_2B 0x68A60
7091#define _PS_PWR_GATE_1C 0x69160
7092#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
7093#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
7094#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
7095#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
7096#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
7097#define PS_PWR_GATE_SLPEN_8 0
7098#define PS_PWR_GATE_SLPEN_16 1
7099#define PS_PWR_GATE_SLPEN_24 2
7100#define PS_PWR_GATE_SLPEN_32 3
7101
7102#define _PS_WIN_POS_1A 0x68170
7103#define _PS_WIN_POS_2A 0x68270
7104#define _PS_WIN_POS_1B 0x68970
7105#define _PS_WIN_POS_2B 0x68A70
7106#define _PS_WIN_POS_1C 0x69170
7107
7108#define _PS_WIN_SZ_1A 0x68174
7109#define _PS_WIN_SZ_2A 0x68274
7110#define _PS_WIN_SZ_1B 0x68974
7111#define _PS_WIN_SZ_2B 0x68A74
7112#define _PS_WIN_SZ_1C 0x69174
7113
7114#define _PS_VSCALE_1A 0x68184
7115#define _PS_VSCALE_2A 0x68284
7116#define _PS_VSCALE_1B 0x68984
7117#define _PS_VSCALE_2B 0x68A84
7118#define _PS_VSCALE_1C 0x69184
7119
7120#define _PS_HSCALE_1A 0x68190
7121#define _PS_HSCALE_2A 0x68290
7122#define _PS_HSCALE_1B 0x68990
7123#define _PS_HSCALE_2B 0x68A90
7124#define _PS_HSCALE_1C 0x69190
7125
7126#define _PS_VPHASE_1A 0x68188
7127#define _PS_VPHASE_2A 0x68288
7128#define _PS_VPHASE_1B 0x68988
7129#define _PS_VPHASE_2B 0x68A88
7130#define _PS_VPHASE_1C 0x69188
7131#define PS_Y_PHASE(x) ((x) << 16)
7132#define PS_UV_RGB_PHASE(x) ((x) << 0)
7133#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7134#define PS_PHASE_TRIP (1 << 0)
7135
7136#define _PS_HPHASE_1A 0x68194
7137#define _PS_HPHASE_2A 0x68294
7138#define _PS_HPHASE_1B 0x68994
7139#define _PS_HPHASE_2B 0x68A94
7140#define _PS_HPHASE_1C 0x69194
7141
7142#define _PS_ECC_STAT_1A 0x681D0
7143#define _PS_ECC_STAT_2A 0x682D0
7144#define _PS_ECC_STAT_1B 0x689D0
7145#define _PS_ECC_STAT_2B 0x68AD0
7146#define _PS_ECC_STAT_1C 0x691D0
7147
7148#define _ID(id, a, b) _PICK_EVEN(id, a, b)
7149#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
7150 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
7151 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7152#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
7153 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7154 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7155#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
7156 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7157 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7158#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
7159 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
7160 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7161#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
7162 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
7163 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7164#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
7165 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
7166 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7167#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
7168 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
7169 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7170#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
7171 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
7172 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7173#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
7174 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
7175 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7176
7177/* legacy palette */
7178#define _LGC_PALETTE_A 0x4a000
7179#define _LGC_PALETTE_B 0x4a800
7180#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7181
7182/* ilk/snb precision palette */
7183#define _PREC_PALETTE_A 0x4b000
7184#define _PREC_PALETTE_B 0x4c000
7185#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7186
7187#define _PREC_PIPEAGCMAX 0x4d000
7188#define _PREC_PIPEBGCMAX 0x4d010
7189#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7190
7191#define _GAMMA_MODE_A 0x4a480
7192#define _GAMMA_MODE_B 0x4ac80
7193#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7194#define PRE_CSC_GAMMA_ENABLE (1 << 31)
7195#define POST_CSC_GAMMA_ENABLE (1 << 30)
7196#define GAMMA_MODE_MODE_MASK (3 << 0)
7197#define GAMMA_MODE_MODE_8BIT (0 << 0)
7198#define GAMMA_MODE_MODE_10BIT (1 << 0)
7199#define GAMMA_MODE_MODE_12BIT (2 << 0)
7200#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
7201#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
7202
7203/* DMC/CSR */
7204#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
7205#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
7206#define CSR_HTP_ADDR_SKL 0x00500034
7207#define CSR_SSP_BASE _MMIO(0x8F074)
7208#define CSR_HTP_SKL _MMIO(0x8F004)
7209#define CSR_LAST_WRITE _MMIO(0x8F034)
7210#define CSR_LAST_WRITE_VALUE 0xc003b400
7211/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7212#define CSR_MMIO_START_RANGE 0x80000
7213#define CSR_MMIO_END_RANGE 0x8FFFF
7214#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
7215#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
7216#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
7217#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7218#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
7219
7220/* Display Internal Timeout Register */
7221#define RM_TIMEOUT _MMIO(0x42060)
7222#define MMIO_TIMEOUT_US(us) ((us) << 0)
7223
7224/* interrupts */
7225#define DE_MASTER_IRQ_CONTROL (1 << 31)
7226#define DE_SPRITEB_FLIP_DONE (1 << 29)
7227#define DE_SPRITEA_FLIP_DONE (1 << 28)
7228#define DE_PLANEB_FLIP_DONE (1 << 27)
7229#define DE_PLANEA_FLIP_DONE (1 << 26)
7230#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7231#define DE_PCU_EVENT (1 << 25)
7232#define DE_GTT_FAULT (1 << 24)
7233#define DE_POISON (1 << 23)
7234#define DE_PERFORM_COUNTER (1 << 22)
7235#define DE_PCH_EVENT (1 << 21)
7236#define DE_AUX_CHANNEL_A (1 << 20)
7237#define DE_DP_A_HOTPLUG (1 << 19)
7238#define DE_GSE (1 << 18)
7239#define DE_PIPEB_VBLANK (1 << 15)
7240#define DE_PIPEB_EVEN_FIELD (1 << 14)
7241#define DE_PIPEB_ODD_FIELD (1 << 13)
7242#define DE_PIPEB_LINE_COMPARE (1 << 12)
7243#define DE_PIPEB_VSYNC (1 << 11)
7244#define DE_PIPEB_CRC_DONE (1 << 10)
7245#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7246#define DE_PIPEA_VBLANK (1 << 7)
7247#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7248#define DE_PIPEA_EVEN_FIELD (1 << 6)
7249#define DE_PIPEA_ODD_FIELD (1 << 5)
7250#define DE_PIPEA_LINE_COMPARE (1 << 4)
7251#define DE_PIPEA_VSYNC (1 << 3)
7252#define DE_PIPEA_CRC_DONE (1 << 2)
7253#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7254#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7255#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7256
7257/* More Ivybridge lolz */
7258#define DE_ERR_INT_IVB (1 << 30)
7259#define DE_GSE_IVB (1 << 29)
7260#define DE_PCH_EVENT_IVB (1 << 28)
7261#define DE_DP_A_HOTPLUG_IVB (1 << 27)
7262#define DE_AUX_CHANNEL_A_IVB (1 << 26)
7263#define DE_EDP_PSR_INT_HSW (1 << 19)
7264#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7265#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7266#define DE_PIPEC_VBLANK_IVB (1 << 10)
7267#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7268#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7269#define DE_PIPEB_VBLANK_IVB (1 << 5)
7270#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
7271#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
7272#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
7273#define DE_PIPEA_VBLANK_IVB (1 << 0)
7274#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
7275
7276#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
7277#define MASTER_INTERRUPT_ENABLE (1 << 31)
7278
7279#define DEISR _MMIO(0x44000)
7280#define DEIMR _MMIO(0x44004)
7281#define DEIIR _MMIO(0x44008)
7282#define DEIER _MMIO(0x4400c)
7283
7284#define GTISR _MMIO(0x44010)
7285#define GTIMR _MMIO(0x44014)
7286#define GTIIR _MMIO(0x44018)
7287#define GTIER _MMIO(0x4401c)
7288
7289#define GEN8_MASTER_IRQ _MMIO(0x44200)
7290#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
7291#define GEN8_PCU_IRQ (1 << 30)
7292#define GEN8_DE_PCH_IRQ (1 << 23)
7293#define GEN8_DE_MISC_IRQ (1 << 22)
7294#define GEN8_DE_PORT_IRQ (1 << 20)
7295#define GEN8_DE_PIPE_C_IRQ (1 << 18)
7296#define GEN8_DE_PIPE_B_IRQ (1 << 17)
7297#define GEN8_DE_PIPE_A_IRQ (1 << 16)
7298#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
7299#define GEN8_GT_VECS_IRQ (1 << 6)
7300#define GEN8_GT_GUC_IRQ (1 << 5)
7301#define GEN8_GT_PM_IRQ (1 << 4)
7302#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
7303#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
7304#define GEN8_GT_BCS_IRQ (1 << 1)
7305#define GEN8_GT_RCS_IRQ (1 << 0)
7306
7307#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7308#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7309#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7310#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7311
7312#define GEN8_RCS_IRQ_SHIFT 0
7313#define GEN8_BCS_IRQ_SHIFT 16
7314#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
7315#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7316#define GEN8_VECS_IRQ_SHIFT 0
7317#define GEN8_WD_IRQ_SHIFT 16
7318
7319#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7320#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7321#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7322#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7323#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7324#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7325#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7326#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7327#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7328#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7329#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7330#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7331#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7332#define GEN8_PIPE_VSYNC (1 << 1)
7333#define GEN8_PIPE_VBLANK (1 << 0)
7334#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7335#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7336#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7337#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7338#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7339#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7340#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7341#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7342#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7343#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7344#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7345 (GEN8_PIPE_CURSOR_FAULT | \
7346 GEN8_PIPE_SPRITE_FAULT | \
7347 GEN8_PIPE_PRIMARY_FAULT)
7348#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7349 (GEN9_PIPE_CURSOR_FAULT | \
7350 GEN9_PIPE_PLANE4_FAULT | \
7351 GEN9_PIPE_PLANE3_FAULT | \
7352 GEN9_PIPE_PLANE2_FAULT | \
7353 GEN9_PIPE_PLANE1_FAULT)
7354
7355#define GEN8_DE_PORT_ISR _MMIO(0x44440)
7356#define GEN8_DE_PORT_IMR _MMIO(0x44444)
7357#define GEN8_DE_PORT_IIR _MMIO(0x44448)
7358#define GEN8_DE_PORT_IER _MMIO(0x4444c)
7359#define ICL_AUX_CHANNEL_E (1 << 29)
7360#define CNL_AUX_CHANNEL_F (1 << 28)
7361#define GEN9_AUX_CHANNEL_D (1 << 27)
7362#define GEN9_AUX_CHANNEL_C (1 << 26)
7363#define GEN9_AUX_CHANNEL_B (1 << 25)
7364#define BXT_DE_PORT_HP_DDIC (1 << 5)
7365#define BXT_DE_PORT_HP_DDIB (1 << 4)
7366#define BXT_DE_PORT_HP_DDIA (1 << 3)
7367#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7368 BXT_DE_PORT_HP_DDIB | \
7369 BXT_DE_PORT_HP_DDIC)
7370#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7371#define BXT_DE_PORT_GMBUS (1 << 1)
7372#define GEN8_AUX_CHANNEL_A (1 << 0)
7373#define TGL_DE_PORT_AUX_DDIC (1 << 2)
7374#define TGL_DE_PORT_AUX_DDIB (1 << 1)
7375#define TGL_DE_PORT_AUX_DDIA (1 << 0)
7376
7377#define GEN8_DE_MISC_ISR _MMIO(0x44460)
7378#define GEN8_DE_MISC_IMR _MMIO(0x44464)
7379#define GEN8_DE_MISC_IIR _MMIO(0x44468)
7380#define GEN8_DE_MISC_IER _MMIO(0x4446c)
7381#define GEN8_DE_MISC_GSE (1 << 27)
7382#define GEN8_DE_EDP_PSR (1 << 19)
7383
7384#define GEN8_PCU_ISR _MMIO(0x444e0)
7385#define GEN8_PCU_IMR _MMIO(0x444e4)
7386#define GEN8_PCU_IIR _MMIO(0x444e8)
7387#define GEN8_PCU_IER _MMIO(0x444ec)
7388
7389#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
7390#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
7391#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
7392#define GEN11_GU_MISC_IER _MMIO(0x444fc)
7393#define GEN11_GU_MISC_GSE (1 << 27)
7394
7395#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7396#define GEN11_MASTER_IRQ (1 << 31)
7397#define GEN11_PCU_IRQ (1 << 30)
7398#define GEN11_GU_MISC_IRQ (1 << 29)
7399#define GEN11_DISPLAY_IRQ (1 << 16)
7400#define GEN11_GT_DW_IRQ(x) (1 << (x))
7401#define GEN11_GT_DW1_IRQ (1 << 1)
7402#define GEN11_GT_DW0_IRQ (1 << 0)
7403
7404#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7405#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7406#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7407#define GEN11_DE_PCH_IRQ (1 << 23)
7408#define GEN11_DE_MISC_IRQ (1 << 22)
7409#define GEN11_DE_HPD_IRQ (1 << 21)
7410#define GEN11_DE_PORT_IRQ (1 << 20)
7411#define GEN11_DE_PIPE_C (1 << 18)
7412#define GEN11_DE_PIPE_B (1 << 17)
7413#define GEN11_DE_PIPE_A (1 << 16)
7414
7415#define GEN11_DE_HPD_ISR _MMIO(0x44470)
7416#define GEN11_DE_HPD_IMR _MMIO(0x44474)
7417#define GEN11_DE_HPD_IIR _MMIO(0x44478)
7418#define GEN11_DE_HPD_IER _MMIO(0x4447c)
7419#define GEN12_TC6_HOTPLUG (1 << 21)
7420#define GEN12_TC5_HOTPLUG (1 << 20)
7421#define GEN11_TC4_HOTPLUG (1 << 19)
7422#define GEN11_TC3_HOTPLUG (1 << 18)
7423#define GEN11_TC2_HOTPLUG (1 << 17)
7424#define GEN11_TC1_HOTPLUG (1 << 16)
7425#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
7426#define GEN11_DE_TC_HOTPLUG_MASK (GEN12_TC6_HOTPLUG | \
7427 GEN12_TC5_HOTPLUG | \
7428 GEN11_TC4_HOTPLUG | \
7429 GEN11_TC3_HOTPLUG | \
7430 GEN11_TC2_HOTPLUG | \
7431 GEN11_TC1_HOTPLUG)
7432#define GEN12_TBT6_HOTPLUG (1 << 5)
7433#define GEN12_TBT5_HOTPLUG (1 << 4)
7434#define GEN11_TBT4_HOTPLUG (1 << 3)
7435#define GEN11_TBT3_HOTPLUG (1 << 2)
7436#define GEN11_TBT2_HOTPLUG (1 << 1)
7437#define GEN11_TBT1_HOTPLUG (1 << 0)
7438#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
7439#define GEN11_DE_TBT_HOTPLUG_MASK (GEN12_TBT6_HOTPLUG | \
7440 GEN12_TBT5_HOTPLUG | \
7441 GEN11_TBT4_HOTPLUG | \
7442 GEN11_TBT3_HOTPLUG | \
7443 GEN11_TBT2_HOTPLUG | \
7444 GEN11_TBT1_HOTPLUG)
7445
7446#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7447#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
7448#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
7449#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7450#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7451#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
7452
7453#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7454#define GEN11_CSME (31)
7455#define GEN11_GUNIT (28)
7456#define GEN11_GUC (25)
7457#define GEN11_WDPERF (20)
7458#define GEN11_KCR (19)
7459#define GEN11_GTPM (16)
7460#define GEN11_BCS (15)
7461#define GEN11_RCS0 (0)
7462
7463#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7464#define GEN11_VECS(x) (31 - (x))
7465#define GEN11_VCS(x) (x)
7466
7467#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
7468
7469#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7470#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7471#define GEN11_INTR_DATA_VALID (1 << 31)
7472#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7473#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7474#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
7475/* irq instances for OTHER_CLASS */
7476#define OTHER_GUC_INSTANCE 0
7477#define OTHER_GTPM_INSTANCE 1
7478
7479#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7480
7481#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7482#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7483
7484#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
7485
7486#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7487#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7488#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7489#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7490#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7491#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7492
7493#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7494#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7495#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7496#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7497#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7498#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7499#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7500#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7501#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7502
7503#define ENGINE1_MASK REG_GENMASK(31, 16)
7504#define ENGINE0_MASK REG_GENMASK(15, 0)
7505
7506#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7507/* Required on all Ironlake and Sandybridge according to the B-Spec. */
7508#define ILK_ELPIN_409_SELECT (1 << 25)
7509#define ILK_DPARB_GATE (1 << 22)
7510#define ILK_VSDPFD_FULL (1 << 21)
7511#define FUSE_STRAP _MMIO(0x42014)
7512#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7513#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7514#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7515#define IVB_PIPE_C_DISABLE (1 << 28)
7516#define ILK_HDCP_DISABLE (1 << 25)
7517#define ILK_eDP_A_DISABLE (1 << 24)
7518#define HSW_CDCLK_LIMIT (1 << 24)
7519#define ILK_DESKTOP (1 << 23)
7520#define HSW_CPU_SSC_ENABLE (1 << 21)
7521
7522#define FUSE_STRAP3 _MMIO(0x42020)
7523#define HSW_REF_CLK_SELECT (1 << 1)
7524
7525#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7526#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7527#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7528#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7529#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7530#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7531
7532#define IVB_CHICKEN3 _MMIO(0x4200c)
7533# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7534# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7535
7536#define CHICKEN_PAR1_1 _MMIO(0x42080)
7537#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7538#define DPA_MASK_VBLANK_SRD (1 << 15)
7539#define FORCE_ARB_IDLE_PLANES (1 << 14)
7540#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7541
7542#define CHICKEN_PAR2_1 _MMIO(0x42090)
7543#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7544
7545#define CHICKEN_MISC_2 _MMIO(0x42084)
7546#define CNL_COMP_PWR_DOWN (1 << 23)
7547#define GLK_CL2_PWR_DOWN (1 << 12)
7548#define GLK_CL1_PWR_DOWN (1 << 11)
7549#define GLK_CL0_PWR_DOWN (1 << 10)
7550
7551#define CHICKEN_MISC_4 _MMIO(0x4208c)
7552#define FBC_STRIDE_OVERRIDE (1 << 13)
7553#define FBC_STRIDE_MASK 0x1FFF
7554
7555#define _CHICKEN_PIPESL_1_A 0x420b0
7556#define _CHICKEN_PIPESL_1_B 0x420b4
7557#define HSW_FBCQ_DIS (1 << 22)
7558#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7559#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7560
7561#define CHICKEN_TRANS_A _MMIO(0x420c0)
7562#define CHICKEN_TRANS_B _MMIO(0x420c4)
7563#define CHICKEN_TRANS_C _MMIO(0x420c8)
7564#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
7565#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
7566#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7567#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
7568#define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */
7569#define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */
7570#define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
7571#define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
7572
7573#define DISP_ARB_CTL _MMIO(0x45000)
7574#define DISP_FBC_MEMORY_WAKE (1 << 31)
7575#define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
7576#define DISP_FBC_WM_DIS (1 << 15)
7577#define DISP_ARB_CTL2 _MMIO(0x45004)
7578#define DISP_DATA_PARTITION_5_6 (1 << 6)
7579#define DISP_IPC_ENABLE (1 << 3)
7580#define DBUF_CTL _MMIO(0x45008)
7581#define DBUF_CTL_S1 _MMIO(0x45008)
7582#define DBUF_CTL_S2 _MMIO(0x44FE8)
7583#define DBUF_POWER_REQUEST (1 << 31)
7584#define DBUF_POWER_STATE (1 << 30)
7585#define GEN7_MSG_CTL _MMIO(0x45010)
7586#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
7587#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
7588#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7589#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
7590
7591#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7592#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7593#define MASK_WAKEMEM (1 << 13)
7594#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7595
7596#define SKL_DFSM _MMIO(0x51000)
7597#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7598#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7599#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7600#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7601#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7602#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7603#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7604#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7605#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
7606
7607#define SKL_DSSM _MMIO(0x51004)
7608#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7609#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7610#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7611#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7612#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7613
7614#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7615#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7616
7617#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7618#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
7619#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
7620
7621#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7622#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7623#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7624#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
7625#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7626#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7627#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7628#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7629#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7630
7631/* GEN7 chicken */
7632#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7633 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
7634 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
7635
7636#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7637 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
7638 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
7639 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
7640 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
7641
7642#define GEN8_L3CNTLREG _MMIO(0x7034)
7643 #define GEN8_ERRDETBCTRL (1 << 9)
7644
7645#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
7646 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
7647
7648#define HIZ_CHICKEN _MMIO(0x7018)
7649# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
7650# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
7651
7652#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7653#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
7654
7655#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7656#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
7657
7658#define GEN7_SARCHKMD _MMIO(0xB000)
7659#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
7660#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
7661
7662#define GEN7_L3SQCREG1 _MMIO(0xB010)
7663#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7664
7665#define GEN8_L3SQCREG1 _MMIO(0xB100)
7666/*
7667 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7668 * Using the formula in BSpec leads to a hang, while the formula here works
7669 * fine and matches the formulas for all other platforms. A BSpec change
7670 * request has been filed to clarify this.
7671 */
7672#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7673#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7674#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7675
7676#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7677#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7678#define GEN7_L3AGDIS (1 << 19)
7679#define GEN7_L3CNTLREG2 _MMIO(0xB020)
7680#define GEN7_L3CNTLREG3 _MMIO(0xB024)
7681
7682#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7683#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7684#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
7685#define GEN11_I2M_WRITE_DISABLE (1 << 28)
7686
7687#define GEN7_L3SQCREG4 _MMIO(0xb034)
7688#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
7689
7690#define GEN11_SCRATCH2 _MMIO(0xb140)
7691#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
7692
7693#define GEN8_L3SQCREG4 _MMIO(0xb118)
7694#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
7695#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
7696#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
7697
7698/* GEN8 chicken */
7699#define HDC_CHICKEN0 _MMIO(0x7300)
7700#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7701#define ICL_HDC_MODE _MMIO(0xE5F4)
7702#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7703#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
7704#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
7705#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
7706#define HDC_FORCE_NON_COHERENT (1 << 4)
7707#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
7708
7709#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7710
7711/* GEN9 chicken */
7712#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7713#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7714
7715#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
7716#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
7717
7718/* WaCatErrorRejectionIssue */
7719#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7720#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
7721
7722#define HSW_SCRATCH1 _MMIO(0xb038)
7723#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
7724
7725#define BDW_SCRATCH1 _MMIO(0xb11c)
7726#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
7727
7728/*GEN11 chicken */
7729#define _PIPEA_CHICKEN 0x70038
7730#define _PIPEB_CHICKEN 0x71038
7731#define _PIPEC_CHICKEN 0x72038
7732#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7733 _PIPEB_CHICKEN)
7734#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
7735#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
7736
7737/* PCH */
7738
7739#define PCH_DISPLAY_BASE 0xc0000u
7740
7741/* south display engine interrupt: IBX */
7742#define SDE_AUDIO_POWER_D (1 << 27)
7743#define SDE_AUDIO_POWER_C (1 << 26)
7744#define SDE_AUDIO_POWER_B (1 << 25)
7745#define SDE_AUDIO_POWER_SHIFT (25)
7746#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7747#define SDE_GMBUS (1 << 24)
7748#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7749#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7750#define SDE_AUDIO_HDCP_MASK (3 << 22)
7751#define SDE_AUDIO_TRANSB (1 << 21)
7752#define SDE_AUDIO_TRANSA (1 << 20)
7753#define SDE_AUDIO_TRANS_MASK (3 << 20)
7754#define SDE_POISON (1 << 19)
7755/* 18 reserved */
7756#define SDE_FDI_RXB (1 << 17)
7757#define SDE_FDI_RXA (1 << 16)
7758#define SDE_FDI_MASK (3 << 16)
7759#define SDE_AUXD (1 << 15)
7760#define SDE_AUXC (1 << 14)
7761#define SDE_AUXB (1 << 13)
7762#define SDE_AUX_MASK (7 << 13)
7763/* 12 reserved */
7764#define SDE_CRT_HOTPLUG (1 << 11)
7765#define SDE_PORTD_HOTPLUG (1 << 10)
7766#define SDE_PORTC_HOTPLUG (1 << 9)
7767#define SDE_PORTB_HOTPLUG (1 << 8)
7768#define SDE_SDVOB_HOTPLUG (1 << 6)
7769#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7770 SDE_SDVOB_HOTPLUG | \
7771 SDE_PORTB_HOTPLUG | \
7772 SDE_PORTC_HOTPLUG | \
7773 SDE_PORTD_HOTPLUG)
7774#define SDE_TRANSB_CRC_DONE (1 << 5)
7775#define SDE_TRANSB_CRC_ERR (1 << 4)
7776#define SDE_TRANSB_FIFO_UNDER (1 << 3)
7777#define SDE_TRANSA_CRC_DONE (1 << 2)
7778#define SDE_TRANSA_CRC_ERR (1 << 1)
7779#define SDE_TRANSA_FIFO_UNDER (1 << 0)
7780#define SDE_TRANS_MASK (0x3f)
7781
7782/* south display engine interrupt: CPT - CNP */
7783#define SDE_AUDIO_POWER_D_CPT (1 << 31)
7784#define SDE_AUDIO_POWER_C_CPT (1 << 30)
7785#define SDE_AUDIO_POWER_B_CPT (1 << 29)
7786#define SDE_AUDIO_POWER_SHIFT_CPT 29
7787#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7788#define SDE_AUXD_CPT (1 << 27)
7789#define SDE_AUXC_CPT (1 << 26)
7790#define SDE_AUXB_CPT (1 << 25)
7791#define SDE_AUX_MASK_CPT (7 << 25)
7792#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7793#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7794#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7795#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7796#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7797#define SDE_CRT_HOTPLUG_CPT (1 << 19)
7798#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7799#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7800 SDE_SDVOB_HOTPLUG_CPT | \
7801 SDE_PORTD_HOTPLUG_CPT | \
7802 SDE_PORTC_HOTPLUG_CPT | \
7803 SDE_PORTB_HOTPLUG_CPT)
7804#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7805 SDE_PORTD_HOTPLUG_CPT | \
7806 SDE_PORTC_HOTPLUG_CPT | \
7807 SDE_PORTB_HOTPLUG_CPT | \
7808 SDE_PORTA_HOTPLUG_SPT)
7809#define SDE_GMBUS_CPT (1 << 17)
7810#define SDE_ERROR_CPT (1 << 16)
7811#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7812#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7813#define SDE_FDI_RXC_CPT (1 << 8)
7814#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7815#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7816#define SDE_FDI_RXB_CPT (1 << 4)
7817#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7818#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7819#define SDE_FDI_RXA_CPT (1 << 0)
7820#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7821 SDE_AUDIO_CP_REQ_B_CPT | \
7822 SDE_AUDIO_CP_REQ_A_CPT)
7823#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7824 SDE_AUDIO_CP_CHG_B_CPT | \
7825 SDE_AUDIO_CP_CHG_A_CPT)
7826#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7827 SDE_FDI_RXB_CPT | \
7828 SDE_FDI_RXA_CPT)
7829
7830/* south display engine interrupt: ICP/TGP */
7831#define SDE_TC6_HOTPLUG_TGP (1 << 29)
7832#define SDE_TC5_HOTPLUG_TGP (1 << 28)
7833#define SDE_TC4_HOTPLUG_ICP (1 << 27)
7834#define SDE_TC3_HOTPLUG_ICP (1 << 26)
7835#define SDE_TC2_HOTPLUG_ICP (1 << 25)
7836#define SDE_TC1_HOTPLUG_ICP (1 << 24)
7837#define SDE_GMBUS_ICP (1 << 23)
7838#define SDE_DDIC_HOTPLUG_TGP (1 << 18)
7839#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
7840#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7841#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
7842#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
7843#define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
7844 SDE_DDIA_HOTPLUG_ICP)
7845#define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
7846 SDE_TC3_HOTPLUG_ICP | \
7847 SDE_TC2_HOTPLUG_ICP | \
7848 SDE_TC1_HOTPLUG_ICP)
7849#define SDE_DDI_MASK_TGP (SDE_DDIC_HOTPLUG_TGP | \
7850 SDE_DDI_MASK_ICP)
7851#define SDE_TC_MASK_TGP (SDE_TC6_HOTPLUG_TGP | \
7852 SDE_TC5_HOTPLUG_TGP | \
7853 SDE_TC_MASK_ICP)
7854
7855#define SDEISR _MMIO(0xc4000)
7856#define SDEIMR _MMIO(0xc4004)
7857#define SDEIIR _MMIO(0xc4008)
7858#define SDEIER _MMIO(0xc400c)
7859
7860#define SERR_INT _MMIO(0xc4040)
7861#define SERR_INT_POISON (1 << 31)
7862#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
7863
7864/* digital port hotplug */
7865#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7866#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7867#define BXT_DDIA_HPD_INVERT (1 << 27)
7868#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7869#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7870#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7871#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7872#define PORTD_HOTPLUG_ENABLE (1 << 20)
7873#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7874#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7875#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7876#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7877#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7878#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7879#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7880#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7881#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7882#define PORTC_HOTPLUG_ENABLE (1 << 12)
7883#define BXT_DDIC_HPD_INVERT (1 << 11)
7884#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7885#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7886#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7887#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7888#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7889#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7890#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7891#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7892#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7893#define PORTB_HOTPLUG_ENABLE (1 << 4)
7894#define BXT_DDIB_HPD_INVERT (1 << 3)
7895#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7896#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7897#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7898#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7899#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7900#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7901#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7902#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7903#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7904#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7905 BXT_DDIB_HPD_INVERT | \
7906 BXT_DDIC_HPD_INVERT)
7907
7908#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7909#define PORTE_HOTPLUG_ENABLE (1 << 4)
7910#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7911#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7912#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7913#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7914
7915/* This register is a reuse of PCH_PORT_HOTPLUG register. The
7916 * functionality covered in PCH_PORT_HOTPLUG is split into
7917 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7918 */
7919
7920#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
7921#define TGP_DDIC_HPD_ENABLE (1 << 11)
7922#define TGP_DDIC_HPD_STATUS_MASK (3 << 8)
7923#define TGP_DDIC_HPD_NO_DETECT (0 << 8)
7924#define TGP_DDIC_HPD_SHORT_DETECT (1 << 8)
7925#define TGP_DDIC_HPD_LONG_DETECT (2 << 8)
7926#define TGP_DDIC_HPD_SHORT_LONG_DETECT (3 << 8)
7927#define ICP_DDIB_HPD_ENABLE (1 << 7)
7928#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
7929#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
7930#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
7931#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
7932#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
7933#define ICP_DDIA_HPD_ENABLE (1 << 3)
7934#define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
7935#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
7936#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
7937#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
7938#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
7939#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
7940
7941#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
7942#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
7943/* Icelake DSC Rate Control Range Parameter Registers */
7944#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
7945#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
7946#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
7947#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
7948#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
7949#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
7950#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
7951#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
7952#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
7953#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
7954#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
7955#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
7956#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7957 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
7958 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
7959#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7960 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
7961 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
7962#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7963 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
7964 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
7965#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7966 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
7967 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
7968#define RC_BPG_OFFSET_SHIFT 10
7969#define RC_MAX_QP_SHIFT 5
7970#define RC_MIN_QP_SHIFT 0
7971
7972#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
7973#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
7974#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
7975#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
7976#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
7977#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
7978#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
7979#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
7980#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
7981#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
7982#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
7983#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
7984#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7985 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
7986 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
7987#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7988 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
7989 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
7990#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7991 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
7992 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
7993#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7994 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
7995 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
7996
7997#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
7998#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
7999#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
8000#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
8001#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
8002#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
8003#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
8004#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
8005#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
8006#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
8007#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
8008#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
8009#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8010 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
8011 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
8012#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8013 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
8014 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
8015#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8016 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
8017 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
8018#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8019 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
8020 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
8021
8022#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
8023#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
8024#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
8025#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
8026#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
8027#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
8028#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
8029#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
8030#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
8031#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
8032#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
8033#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
8034#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8035 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
8036 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
8037#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8038 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
8039 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
8040#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8041 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
8042 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
8043#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8044 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
8045 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
8046
8047#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
8048#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
8049
8050#define ICP_DDI_HPD_ENABLE_MASK (ICP_DDIB_HPD_ENABLE | \
8051 ICP_DDIA_HPD_ENABLE)
8052#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
8053 ICP_TC_HPD_ENABLE(PORT_TC3) | \
8054 ICP_TC_HPD_ENABLE(PORT_TC2) | \
8055 ICP_TC_HPD_ENABLE(PORT_TC1))
8056#define TGP_DDI_HPD_ENABLE_MASK (TGP_DDIC_HPD_ENABLE | \
8057 ICP_DDI_HPD_ENABLE_MASK)
8058#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
8059 ICP_TC_HPD_ENABLE(PORT_TC5) | \
8060 ICP_TC_HPD_ENABLE_MASK)
8061
8062#define _PCH_DPLL_A 0xc6014
8063#define _PCH_DPLL_B 0xc6018
8064#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8065
8066#define _PCH_FPA0 0xc6040
8067#define FP_CB_TUNE (0x3 << 22)
8068#define _PCH_FPA1 0xc6044
8069#define _PCH_FPB0 0xc6048
8070#define _PCH_FPB1 0xc604c
8071#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8072#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8073
8074#define PCH_DPLL_TEST _MMIO(0xc606c)
8075
8076#define PCH_DREF_CONTROL _MMIO(0xC6200)
8077#define DREF_CONTROL_MASK 0x7fc3
8078#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
8079#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
8080#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
8081#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
8082#define DREF_SSC_SOURCE_DISABLE (0 << 11)
8083#define DREF_SSC_SOURCE_ENABLE (2 << 11)
8084#define DREF_SSC_SOURCE_MASK (3 << 11)
8085#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
8086#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
8087#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
8088#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
8089#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
8090#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
8091#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
8092#define DREF_SSC4_DOWNSPREAD (0 << 6)
8093#define DREF_SSC4_CENTERSPREAD (1 << 6)
8094#define DREF_SSC1_DISABLE (0 << 1)
8095#define DREF_SSC1_ENABLE (1 << 1)
8096#define DREF_SSC4_DISABLE (0)
8097#define DREF_SSC4_ENABLE (1)
8098
8099#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
8100#define FDL_TP1_TIMER_SHIFT 12
8101#define FDL_TP1_TIMER_MASK (3 << 12)
8102#define FDL_TP2_TIMER_SHIFT 10
8103#define FDL_TP2_TIMER_MASK (3 << 10)
8104#define RAWCLK_FREQ_MASK 0x3ff
8105#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
8106#define CNP_RAWCLK_DIV(div) ((div) << 16)
8107#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
8108#define CNP_RAWCLK_DEN(den) ((den) << 26)
8109#define ICP_RAWCLK_NUM(num) ((num) << 11)
8110
8111#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
8112
8113#define PCH_SSC4_PARMS _MMIO(0xc6210)
8114#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
8115
8116#define PCH_DPLL_SEL _MMIO(0xc7000)
8117#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
8118#define TRANS_DPLLA_SEL(pipe) 0
8119#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
8120
8121/* transcoder */
8122
8123#define _PCH_TRANS_HTOTAL_A 0xe0000
8124#define TRANS_HTOTAL_SHIFT 16
8125#define TRANS_HACTIVE_SHIFT 0
8126#define _PCH_TRANS_HBLANK_A 0xe0004
8127#define TRANS_HBLANK_END_SHIFT 16
8128#define TRANS_HBLANK_START_SHIFT 0
8129#define _PCH_TRANS_HSYNC_A 0xe0008
8130#define TRANS_HSYNC_END_SHIFT 16
8131#define TRANS_HSYNC_START_SHIFT 0
8132#define _PCH_TRANS_VTOTAL_A 0xe000c
8133#define TRANS_VTOTAL_SHIFT 16
8134#define TRANS_VACTIVE_SHIFT 0
8135#define _PCH_TRANS_VBLANK_A 0xe0010
8136#define TRANS_VBLANK_END_SHIFT 16
8137#define TRANS_VBLANK_START_SHIFT 0
8138#define _PCH_TRANS_VSYNC_A 0xe0014
8139#define TRANS_VSYNC_END_SHIFT 16
8140#define TRANS_VSYNC_START_SHIFT 0
8141#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
8142
8143#define _PCH_TRANSA_DATA_M1 0xe0030
8144#define _PCH_TRANSA_DATA_N1 0xe0034
8145#define _PCH_TRANSA_DATA_M2 0xe0038
8146#define _PCH_TRANSA_DATA_N2 0xe003c
8147#define _PCH_TRANSA_LINK_M1 0xe0040
8148#define _PCH_TRANSA_LINK_N1 0xe0044
8149#define _PCH_TRANSA_LINK_M2 0xe0048
8150#define _PCH_TRANSA_LINK_N2 0xe004c
8151
8152/* Per-transcoder DIP controls (PCH) */
8153#define _VIDEO_DIP_CTL_A 0xe0200
8154#define _VIDEO_DIP_DATA_A 0xe0208
8155#define _VIDEO_DIP_GCP_A 0xe0210
8156#define GCP_COLOR_INDICATION (1 << 2)
8157#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
8158#define GCP_AV_MUTE (1 << 0)
8159
8160#define _VIDEO_DIP_CTL_B 0xe1200
8161#define _VIDEO_DIP_DATA_B 0xe1208
8162#define _VIDEO_DIP_GCP_B 0xe1210
8163
8164#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8165#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8166#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8167
8168/* Per-transcoder DIP controls (VLV) */
8169#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8170#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8171#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
8172
8173#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8174#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8175#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
8176
8177#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8178#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8179#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8180
8181#define VLV_TVIDEO_DIP_CTL(pipe) \
8182 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8183 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8184#define VLV_TVIDEO_DIP_DATA(pipe) \
8185 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8186 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8187#define VLV_TVIDEO_DIP_GCP(pipe) \
8188 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8189 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8190
8191/* Haswell DIP controls */
8192
8193#define _HSW_VIDEO_DIP_CTL_A 0x60200
8194#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
8195#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
8196#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
8197#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
8198#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
8199#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
8200#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
8201#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
8202#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
8203#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
8204#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
8205#define _HSW_VIDEO_DIP_GCP_A 0x60210
8206
8207#define _HSW_VIDEO_DIP_CTL_B 0x61200
8208#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
8209#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
8210#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
8211#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
8212#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
8213#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
8214#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
8215#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
8216#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
8217#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
8218#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
8219#define _HSW_VIDEO_DIP_GCP_B 0x61210
8220
8221/* Icelake PPS_DATA and _ECC DIP Registers.
8222 * These are available for transcoders B,C and eDP.
8223 * Adding the _A so as to reuse the _MMIO_TRANS2
8224 * definition, with which it offsets to the right location.
8225 */
8226
8227#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
8228#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
8229#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
8230#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
8231
8232#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8233#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8234#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8235#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8236#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8237#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8238#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8239#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8240#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8241#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8242
8243#define _HSW_STEREO_3D_CTL_A 0x70020
8244#define S3D_ENABLE (1 << 31)
8245#define _HSW_STEREO_3D_CTL_B 0x71020
8246
8247#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8248
8249#define _PCH_TRANS_HTOTAL_B 0xe1000
8250#define _PCH_TRANS_HBLANK_B 0xe1004
8251#define _PCH_TRANS_HSYNC_B 0xe1008
8252#define _PCH_TRANS_VTOTAL_B 0xe100c
8253#define _PCH_TRANS_VBLANK_B 0xe1010
8254#define _PCH_TRANS_VSYNC_B 0xe1014
8255#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8256
8257#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8258#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8259#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8260#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8261#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8262#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8263#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8264
8265#define _PCH_TRANSB_DATA_M1 0xe1030
8266#define _PCH_TRANSB_DATA_N1 0xe1034
8267#define _PCH_TRANSB_DATA_M2 0xe1038
8268#define _PCH_TRANSB_DATA_N2 0xe103c
8269#define _PCH_TRANSB_LINK_M1 0xe1040
8270#define _PCH_TRANSB_LINK_N1 0xe1044
8271#define _PCH_TRANSB_LINK_M2 0xe1048
8272#define _PCH_TRANSB_LINK_N2 0xe104c
8273
8274#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8275#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8276#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8277#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8278#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8279#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8280#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8281#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8282
8283#define _PCH_TRANSACONF 0xf0008
8284#define _PCH_TRANSBCONF 0xf1008
8285#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8286#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8287#define TRANS_DISABLE (0 << 31)
8288#define TRANS_ENABLE (1 << 31)
8289#define TRANS_STATE_MASK (1 << 30)
8290#define TRANS_STATE_DISABLE (0 << 30)
8291#define TRANS_STATE_ENABLE (1 << 30)
8292#define TRANS_FSYNC_DELAY_HB1 (0 << 27)
8293#define TRANS_FSYNC_DELAY_HB2 (1 << 27)
8294#define TRANS_FSYNC_DELAY_HB3 (2 << 27)
8295#define TRANS_FSYNC_DELAY_HB4 (3 << 27)
8296#define TRANS_INTERLACE_MASK (7 << 21)
8297#define TRANS_PROGRESSIVE (0 << 21)
8298#define TRANS_INTERLACED (3 << 21)
8299#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8300#define TRANS_8BPC (0 << 5)
8301#define TRANS_10BPC (1 << 5)
8302#define TRANS_6BPC (2 << 5)
8303#define TRANS_12BPC (3 << 5)
8304
8305#define _TRANSA_CHICKEN1 0xf0060
8306#define _TRANSB_CHICKEN1 0xf1060
8307#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8308#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
8309#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
8310#define _TRANSA_CHICKEN2 0xf0064
8311#define _TRANSB_CHICKEN2 0xf1064
8312#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8313#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8314#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8315#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
8316#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8317#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8318
8319#define SOUTH_CHICKEN1 _MMIO(0xc2000)
8320#define FDIA_PHASE_SYNC_SHIFT_OVR 19
8321#define FDIA_PHASE_SYNC_SHIFT_EN 18
8322#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8323#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8324#define FDI_BC_BIFURCATION_SELECT (1 << 12)
8325#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8326#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
8327#define SPT_PWM_GRANULARITY (1 << 0)
8328#define SOUTH_CHICKEN2 _MMIO(0xc2004)
8329#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
8330#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
8331#define LPT_PWM_GRANULARITY (1 << 5)
8332#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
8333
8334#define _FDI_RXA_CHICKEN 0xc200c
8335#define _FDI_RXB_CHICKEN 0xc2010
8336#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
8337#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
8338#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8339
8340#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
8341#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8342#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8343#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8344#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8345#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8346#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
8347
8348/* CPU: FDI_TX */
8349#define _FDI_TXA_CTL 0x60100
8350#define _FDI_TXB_CTL 0x61100
8351#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8352#define FDI_TX_DISABLE (0 << 31)
8353#define FDI_TX_ENABLE (1 << 31)
8354#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
8355#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
8356#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
8357#define FDI_LINK_TRAIN_NONE (3 << 28)
8358#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
8359#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
8360#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
8361#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
8362#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8363#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8364#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
8365#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
8366/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8367 SNB has different settings. */
8368/* SNB A-stepping */
8369#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8370#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8371#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8372#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8373/* SNB B-stepping */
8374#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
8375#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
8376#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
8377#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
8378#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
8379#define FDI_DP_PORT_WIDTH_SHIFT 19
8380#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
8381#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8382#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
8383/* Ironlake: hardwired to 1 */
8384#define FDI_TX_PLL_ENABLE (1 << 14)
8385
8386/* Ivybridge has different bits for lolz */
8387#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
8388#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
8389#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
8390#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
8391
8392/* both Tx and Rx */
8393#define FDI_COMPOSITE_SYNC (1 << 11)
8394#define FDI_LINK_TRAIN_AUTO (1 << 10)
8395#define FDI_SCRAMBLING_ENABLE (0 << 7)
8396#define FDI_SCRAMBLING_DISABLE (1 << 7)
8397
8398/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8399#define _FDI_RXA_CTL 0xf000c
8400#define _FDI_RXB_CTL 0xf100c
8401#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8402#define FDI_RX_ENABLE (1 << 31)
8403/* train, dp width same as FDI_TX */
8404#define FDI_FS_ERRC_ENABLE (1 << 27)
8405#define FDI_FE_ERRC_ENABLE (1 << 26)
8406#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
8407#define FDI_8BPC (0 << 16)
8408#define FDI_10BPC (1 << 16)
8409#define FDI_6BPC (2 << 16)
8410#define FDI_12BPC (3 << 16)
8411#define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
8412#define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
8413#define FDI_RX_PLL_ENABLE (1 << 13)
8414#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
8415#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
8416#define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
8417#define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
8418#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
8419#define FDI_PCDCLK (1 << 4)
8420/* CPT */
8421#define FDI_AUTO_TRAINING (1 << 10)
8422#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
8423#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
8424#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
8425#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
8426#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
8427
8428#define _FDI_RXA_MISC 0xf0010
8429#define _FDI_RXB_MISC 0xf1010
8430#define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
8431#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
8432#define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
8433#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
8434#define FDI_RX_TP1_TO_TP2_48 (2 << 20)
8435#define FDI_RX_TP1_TO_TP2_64 (3 << 20)
8436#define FDI_RX_FDI_DELAY_90 (0x90 << 0)
8437#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8438
8439#define _FDI_RXA_TUSIZE1 0xf0030
8440#define _FDI_RXA_TUSIZE2 0xf0038
8441#define _FDI_RXB_TUSIZE1 0xf1030
8442#define _FDI_RXB_TUSIZE2 0xf1038
8443#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8444#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8445
8446/* FDI_RX interrupt register format */
8447#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
8448#define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
8449#define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
8450#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
8451#define FDI_RX_FS_CODE_ERR (1 << 6)
8452#define FDI_RX_FE_CODE_ERR (1 << 5)
8453#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
8454#define FDI_RX_HDCP_LINK_FAIL (1 << 3)
8455#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
8456#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
8457#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
8458
8459#define _FDI_RXA_IIR 0xf0014
8460#define _FDI_RXA_IMR 0xf0018
8461#define _FDI_RXB_IIR 0xf1014
8462#define _FDI_RXB_IMR 0xf1018
8463#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8464#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8465
8466#define FDI_PLL_CTL_1 _MMIO(0xfe000)
8467#define FDI_PLL_CTL_2 _MMIO(0xfe004)
8468
8469#define PCH_LVDS _MMIO(0xe1180)
8470#define LVDS_DETECTED (1 << 1)
8471
8472#define _PCH_DP_B 0xe4100
8473#define PCH_DP_B _MMIO(_PCH_DP_B)
8474#define _PCH_DPB_AUX_CH_CTL 0xe4110
8475#define _PCH_DPB_AUX_CH_DATA1 0xe4114
8476#define _PCH_DPB_AUX_CH_DATA2 0xe4118
8477#define _PCH_DPB_AUX_CH_DATA3 0xe411c
8478#define _PCH_DPB_AUX_CH_DATA4 0xe4120
8479#define _PCH_DPB_AUX_CH_DATA5 0xe4124
8480
8481#define _PCH_DP_C 0xe4200
8482#define PCH_DP_C _MMIO(_PCH_DP_C)
8483#define _PCH_DPC_AUX_CH_CTL 0xe4210
8484#define _PCH_DPC_AUX_CH_DATA1 0xe4214
8485#define _PCH_DPC_AUX_CH_DATA2 0xe4218
8486#define _PCH_DPC_AUX_CH_DATA3 0xe421c
8487#define _PCH_DPC_AUX_CH_DATA4 0xe4220
8488#define _PCH_DPC_AUX_CH_DATA5 0xe4224
8489
8490#define _PCH_DP_D 0xe4300
8491#define PCH_DP_D _MMIO(_PCH_DP_D)
8492#define _PCH_DPD_AUX_CH_CTL 0xe4310
8493#define _PCH_DPD_AUX_CH_DATA1 0xe4314
8494#define _PCH_DPD_AUX_CH_DATA2 0xe4318
8495#define _PCH_DPD_AUX_CH_DATA3 0xe431c
8496#define _PCH_DPD_AUX_CH_DATA4 0xe4320
8497#define _PCH_DPD_AUX_CH_DATA5 0xe4324
8498
8499#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8500#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8501
8502/* CPT */
8503#define _TRANS_DP_CTL_A 0xe0300
8504#define _TRANS_DP_CTL_B 0xe1300
8505#define _TRANS_DP_CTL_C 0xe2300
8506#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8507#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
8508#define TRANS_DP_PORT_SEL_MASK (3 << 29)
8509#define TRANS_DP_PORT_SEL_NONE (3 << 29)
8510#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8511#define TRANS_DP_AUDIO_ONLY (1 << 26)
8512#define TRANS_DP_ENH_FRAMING (1 << 18)
8513#define TRANS_DP_8BPC (0 << 9)
8514#define TRANS_DP_10BPC (1 << 9)
8515#define TRANS_DP_6BPC (2 << 9)
8516#define TRANS_DP_12BPC (3 << 9)
8517#define TRANS_DP_BPC_MASK (3 << 9)
8518#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
8519#define TRANS_DP_VSYNC_ACTIVE_LOW 0
8520#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
8521#define TRANS_DP_HSYNC_ACTIVE_LOW 0
8522#define TRANS_DP_SYNC_MASK (3 << 3)
8523
8524/* SNB eDP training params */
8525/* SNB A-stepping */
8526#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8527#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8528#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8529#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8530/* SNB B-stepping */
8531#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
8532#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
8533#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
8534#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
8535#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
8536#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
8537
8538/* IVB */
8539#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
8540#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
8541#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
8542#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
8543#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
8544#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
8545#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
8546
8547/* legacy values */
8548#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
8549#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
8550#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
8551#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
8552#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
8553
8554#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
8555
8556#define VLV_PMWGICZ _MMIO(0x1300a4)
8557
8558#define RC6_LOCATION _MMIO(0xD40)
8559#define RC6_CTX_IN_DRAM (1 << 0)
8560#define RC6_CTX_BASE _MMIO(0xD48)
8561#define RC6_CTX_BASE_MASK 0xFFFFFFF0
8562#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8563#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8564#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8565#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8566#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8567#define IDLE_TIME_MASK 0xFFFFF
8568#define FORCEWAKE _MMIO(0xA18C)
8569#define FORCEWAKE_VLV _MMIO(0x1300b0)
8570#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8571#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8572#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8573#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8574#define FORCEWAKE_ACK _MMIO(0x130090)
8575#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8576#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8577#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8578#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8579
8580#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8581#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8582#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8583#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8584#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8585#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
8586#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8587#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8588#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8589#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8590#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
8591#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8592#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8593#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8594#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8595#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
8596#define FORCEWAKE_KERNEL BIT(0)
8597#define FORCEWAKE_USER BIT(1)
8598#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8599#define FORCEWAKE_MT_ACK _MMIO(0x130040)
8600#define ECOBUS _MMIO(0xa180)
8601#define FORCEWAKE_MT_ENABLE (1 << 5)
8602#define VLV_SPAREG2H _MMIO(0xA194)
8603#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8604#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8605#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8606
8607#define GTFIFODBG _MMIO(0x120000)
8608#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8609#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8610#define GT_FIFO_SBDROPERR (1 << 6)
8611#define GT_FIFO_BLOBDROPERR (1 << 5)
8612#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
8613#define GT_FIFO_DROPERR (1 << 3)
8614#define GT_FIFO_OVFERR (1 << 2)
8615#define GT_FIFO_IAWRERR (1 << 1)
8616#define GT_FIFO_IARDERR (1 << 0)
8617
8618#define GTFIFOCTL _MMIO(0x120008)
8619#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8620#define GT_FIFO_NUM_RESERVED_ENTRIES 20
8621#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8622#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8623
8624#define HSW_IDICR _MMIO(0x9008)
8625#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8626#define HSW_EDRAM_CAP _MMIO(0x120010)
8627#define EDRAM_ENABLED 0x1
8628#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8629#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8630#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8631
8632#define GEN6_UCGCTL1 _MMIO(0x9400)
8633# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8634# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8635# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8636# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8637
8638#define GEN6_UCGCTL2 _MMIO(0x9404)
8639# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8640# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8641# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8642# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8643# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8644# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8645
8646#define GEN6_UCGCTL3 _MMIO(0x9408)
8647# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8648
8649#define GEN7_UCGCTL4 _MMIO(0x940c)
8650#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
8651#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
8652
8653#define GEN6_RCGCTL1 _MMIO(0x9410)
8654#define GEN6_RCGCTL2 _MMIO(0x9414)
8655#define GEN6_RSTCTL _MMIO(0x9420)
8656
8657#define GEN8_UCGCTL6 _MMIO(0x9430)
8658#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
8659#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
8660#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8661
8662#define GEN6_GFXPAUSE _MMIO(0xA000)
8663#define GEN6_RPNSWREQ _MMIO(0xA008)
8664#define GEN6_TURBO_DISABLE (1 << 31)
8665#define GEN6_FREQUENCY(x) ((x) << 25)
8666#define HSW_FREQUENCY(x) ((x) << 24)
8667#define GEN9_FREQUENCY(x) ((x) << 23)
8668#define GEN6_OFFSET(x) ((x) << 19)
8669#define GEN6_AGGRESSIVE_TURBO (0 << 15)
8670#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8671#define GEN6_RC_CONTROL _MMIO(0xA090)
8672#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
8673#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
8674#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
8675#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
8676#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
8677#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
8678#define GEN7_RC_CTL_TO_MODE (1 << 28)
8679#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
8680#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
8681#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8682#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8683#define GEN6_RPSTAT1 _MMIO(0xA01C)
8684#define GEN6_CAGF_SHIFT 8
8685#define HSW_CAGF_SHIFT 7
8686#define GEN9_CAGF_SHIFT 23
8687#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8688#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8689#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8690#define GEN6_RP_CONTROL _MMIO(0xA024)
8691#define GEN6_RP_MEDIA_TURBO (1 << 11)
8692#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
8693#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
8694#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
8695#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
8696#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
8697#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
8698#define GEN6_RP_ENABLE (1 << 7)
8699#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
8700#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
8701#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
8702#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
8703#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
8704#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8705#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8706#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8707#define GEN6_RP_EI_MASK 0xffffff
8708#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8709#define GEN6_RP_CUR_UP _MMIO(0xA054)
8710#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8711#define GEN6_RP_PREV_UP _MMIO(0xA058)
8712#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8713#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8714#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8715#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8716#define GEN6_RP_UP_EI _MMIO(0xA068)
8717#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8718#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8719#define GEN6_RPDEUHWTC _MMIO(0xA080)
8720#define GEN6_RPDEUC _MMIO(0xA084)
8721#define GEN6_RPDEUCSW _MMIO(0xA088)
8722#define GEN6_RC_STATE _MMIO(0xA094)
8723#define RC_SW_TARGET_STATE_SHIFT 16
8724#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8725#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8726#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8727#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8728#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8729#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8730#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8731#define GEN6_RC_SLEEP _MMIO(0xA0B0)
8732#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8733#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8734#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8735#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8736#define VLV_RCEDATA _MMIO(0xA0BC)
8737#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8738#define GEN6_PMINTRMSK _MMIO(0xA168)
8739#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
8740#define ARAT_EXPIRED_INTRMSK (1 << 9)
8741#define GEN8_MISC_CTRL0 _MMIO(0xA180)
8742#define VLV_PWRDWNUPCTL _MMIO(0xA294)
8743#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8744#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8745#define GEN9_PG_ENABLE _MMIO(0xA210)
8746#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
8747#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
8748#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
8749#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8750#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8751#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8752
8753#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8754#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8755#define PIXEL_OVERLAP_CNT_SHIFT 30
8756
8757#define GEN6_PMISR _MMIO(0x44020)
8758#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8759#define GEN6_PMIIR _MMIO(0x44028)
8760#define GEN6_PMIER _MMIO(0x4402C)
8761#define GEN6_PM_MBOX_EVENT (1 << 25)
8762#define GEN6_PM_THERMAL_EVENT (1 << 24)
8763
8764/*
8765 * For Gen11 these are in the upper word of the GPM_WGBOXPERF
8766 * registers. Shifting is handled on accessing the imr and ier.
8767 */
8768#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
8769#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
8770#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
8771#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
8772#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8773#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
8774 GEN6_PM_RP_UP_THRESHOLD | \
8775 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8776 GEN6_PM_RP_DOWN_THRESHOLD | \
8777 GEN6_PM_RP_DOWN_TIMEOUT)
8778
8779#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8780#define GEN7_GT_SCRATCH_REG_NUM 8
8781
8782#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8783#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
8784#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
8785
8786#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8787#define VLV_COUNTER_CONTROL _MMIO(0x138104)
8788#define VLV_COUNT_RANGE_HIGH (1 << 15)
8789#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
8790#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
8791#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
8792#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
8793#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8794#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8795#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8796
8797#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8798#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8799#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8800#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8801
8802#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8803#define GEN6_PCODE_READY (1 << 31)
8804#define GEN6_PCODE_ERROR_MASK 0xFF
8805#define GEN6_PCODE_SUCCESS 0x0
8806#define GEN6_PCODE_ILLEGAL_CMD 0x1
8807#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8808#define GEN6_PCODE_TIMEOUT 0x3
8809#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8810#define GEN7_PCODE_TIMEOUT 0x2
8811#define GEN7_PCODE_ILLEGAL_DATA 0x3
8812#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8813#define GEN6_PCODE_WRITE_RC6VIDS 0x4
8814#define GEN6_PCODE_READ_RC6VIDS 0x5
8815#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8816#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8817#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8818#define GEN9_PCODE_READ_MEM_LATENCY 0x6
8819#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8820#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8821#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8822#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8823#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8824#define SKL_PCODE_CDCLK_CONTROL 0x7
8825#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8826#define SKL_CDCLK_READY_FOR_CHANGE 0x1
8827#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8828#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8829#define GEN6_READ_OC_PARAMS 0xc
8830#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
8831#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
8832#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
8833#define GEN6_PCODE_READ_D_COMP 0x10
8834#define GEN6_PCODE_WRITE_D_COMP 0x11
8835#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8836#define DISPLAY_IPS_CONTROL 0x19
8837 /* See also IPS_CTL */
8838#define IPS_PCODE_CONTROL (1 << 30)
8839#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8840#define GEN9_PCODE_SAGV_CONTROL 0x21
8841#define GEN9_SAGV_DISABLE 0x0
8842#define GEN9_SAGV_IS_DISABLED 0x1
8843#define GEN9_SAGV_ENABLE 0x3
8844#define GEN6_PCODE_DATA _MMIO(0x138128)
8845#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8846#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8847#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8848
8849#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8850#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
8851#define GEN6_RCn_MASK 7
8852#define GEN6_RC0 0
8853#define GEN6_RC3 2
8854#define GEN6_RC6 3
8855#define GEN6_RC7 4
8856
8857#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8858#define GEN8_LSLICESTAT_MASK 0x7
8859
8860#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8861#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8862#define CHV_SS_PG_ENABLE (1 << 1)
8863#define CHV_EU08_PG_ENABLE (1 << 9)
8864#define CHV_EU19_PG_ENABLE (1 << 17)
8865#define CHV_EU210_PG_ENABLE (1 << 25)
8866
8867#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8868#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8869#define CHV_EU311_PG_ENABLE (1 << 1)
8870
8871#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
8872#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8873 ((slice) % 3) * 0x4)
8874#define GEN9_PGCTL_SLICE_ACK (1 << 0)
8875#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
8876#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8877
8878#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
8879#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8880 ((slice) % 3) * 0x8)
8881#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
8882#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8883 ((slice) % 3) * 0x8)
8884#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8885#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8886#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8887#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8888#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8889#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8890#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8891#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8892
8893#define GEN7_MISCCPCTL _MMIO(0x9424)
8894#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
8895#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
8896#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
8897#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
8898
8899#define GEN8_GARBCNTL _MMIO(0xB004)
8900#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
8901#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
8902#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
8903#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
8904
8905#define GEN11_GLBLINVL _MMIO(0xB404)
8906#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
8907#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
8908
8909#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
8910#define DFR_DISABLE (1 << 9)
8911
8912#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
8913#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
8914#define GEN11_HASH_CTRL_BIT0 (1 << 0)
8915#define GEN11_HASH_CTRL_BIT4 (1 << 12)
8916
8917#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
8918#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8919#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8920
8921#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
8922#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
8923
8924/* IVYBRIDGE DPF */
8925#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8926#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
8927#define GEN7_PARITY_ERROR_VALID (1 << 13)
8928#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
8929#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
8930#define GEN7_PARITY_ERROR_ROW(reg) \
8931 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8932#define GEN7_PARITY_ERROR_BANK(reg) \
8933 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8934#define GEN7_PARITY_ERROR_SUBBANK(reg) \
8935 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8936#define GEN7_L3CDERRST1_ENABLE (1 << 7)
8937
8938#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8939#define GEN7_L3LOG_SIZE 0x80
8940
8941#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8942#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8943#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
8944#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
8945#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
8946#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
8947
8948#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8949#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
8950#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
8951
8952#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8953#define FLOW_CONTROL_ENABLE (1 << 15)
8954#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
8955#define STALL_DOP_GATING_DISABLE (1 << 5)
8956#define THROTTLE_12_5 (7 << 2)
8957#define DISABLE_EARLY_EOT (1 << 1)
8958
8959#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8960#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8961#define DOP_CLOCK_GATING_DISABLE (1 << 0)
8962#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
8963#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
8964
8965#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8966#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8967
8968#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8969#define GEN8_ST_PO_DISABLE (1 << 13)
8970
8971#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8972#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
8973#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
8974#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
8975#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
8976#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
8977
8978#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8979#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8)
8980#define GEN9_ENABLE_YV12_BUGFIX (1 << 4)
8981#define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
8982
8983/* Audio */
8984#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
8985#define INTEL_AUDIO_DEVCL 0x808629FB
8986#define INTEL_AUDIO_DEVBLC 0x80862801
8987#define INTEL_AUDIO_DEVCTG 0x80862802
8988
8989#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8990#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8991#define G4X_ELDV_DEVCTG (1 << 14)
8992#define G4X_ELD_ADDR_MASK (0xf << 5)
8993#define G4X_ELD_ACK (1 << 4)
8994#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8995
8996#define _IBX_HDMIW_HDMIEDID_A 0xE2050
8997#define _IBX_HDMIW_HDMIEDID_B 0xE2150
8998#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8999 _IBX_HDMIW_HDMIEDID_B)
9000#define _IBX_AUD_CNTL_ST_A 0xE20B4
9001#define _IBX_AUD_CNTL_ST_B 0xE21B4
9002#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9003 _IBX_AUD_CNTL_ST_B)
9004#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
9005#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
9006#define IBX_ELD_ACK (1 << 4)
9007#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
9008#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9009#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
9010
9011#define _CPT_HDMIW_HDMIEDID_A 0xE5050
9012#define _CPT_HDMIW_HDMIEDID_B 0xE5150
9013#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9014#define _CPT_AUD_CNTL_ST_A 0xE50B4
9015#define _CPT_AUD_CNTL_ST_B 0xE51B4
9016#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9017#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
9018
9019#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
9020#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
9021#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9022#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
9023#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
9024#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9025#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9026
9027/* These are the 4 32-bit write offset registers for each stream
9028 * output buffer. It determines the offset from the
9029 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9030 */
9031#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
9032
9033#define _IBX_AUD_CONFIG_A 0xe2000
9034#define _IBX_AUD_CONFIG_B 0xe2100
9035#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9036#define _CPT_AUD_CONFIG_A 0xe5000
9037#define _CPT_AUD_CONFIG_B 0xe5100
9038#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9039#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
9040#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
9041#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9042
9043#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
9044#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
9045#define AUD_CONFIG_UPPER_N_SHIFT 20
9046#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
9047#define AUD_CONFIG_LOWER_N_SHIFT 4
9048#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
9049#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9050#define AUD_CONFIG_N(n) \
9051 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
9052 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9053#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
9054#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
9055#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
9056#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
9057#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
9058#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
9059#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
9060#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
9061#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
9062#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
9063#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
9064#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
9065#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
9066
9067/* HSW Audio */
9068#define _HSW_AUD_CONFIG_A 0x65000
9069#define _HSW_AUD_CONFIG_B 0x65100
9070#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9071
9072#define _HSW_AUD_MISC_CTRL_A 0x65010
9073#define _HSW_AUD_MISC_CTRL_B 0x65110
9074#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9075
9076#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
9077#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
9078#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9079#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
9080#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
9081#define AUD_CONFIG_M_MASK 0xfffff
9082
9083#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
9084#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
9085#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9086
9087/* Audio Digital Converter */
9088#define _HSW_AUD_DIG_CNVT_1 0x65080
9089#define _HSW_AUD_DIG_CNVT_2 0x65180
9090#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9091#define DIP_PORT_SEL_MASK 0x3
9092
9093#define _HSW_AUD_EDID_DATA_A 0x65050
9094#define _HSW_AUD_EDID_DATA_B 0x65150
9095#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9096
9097#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
9098#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
9099#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
9100#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
9101#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
9102#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
9103
9104#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
9105#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
9106
9107/*
9108 * HSW - ICL power wells
9109 *
9110 * Platforms have up to 3 power well control register sets, each set
9111 * controlling up to 16 power wells via a request/status HW flag tuple:
9112 * - main (HSW_PWR_WELL_CTL[1-4])
9113 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9114 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9115 * Each control register set consists of up to 4 registers used by different
9116 * sources that can request a power well to be enabled:
9117 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9118 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9119 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9120 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9121 */
9122#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
9123#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
9124#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
9125#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
9126#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
9127#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
9128
9129/* HSW/BDW power well */
9130#define HSW_PW_CTL_IDX_GLOBAL 15
9131
9132/* SKL/BXT/GLK/CNL power wells */
9133#define SKL_PW_CTL_IDX_PW_2 15
9134#define SKL_PW_CTL_IDX_PW_1 14
9135#define CNL_PW_CTL_IDX_AUX_F 12
9136#define CNL_PW_CTL_IDX_AUX_D 11
9137#define GLK_PW_CTL_IDX_AUX_C 10
9138#define GLK_PW_CTL_IDX_AUX_B 9
9139#define GLK_PW_CTL_IDX_AUX_A 8
9140#define CNL_PW_CTL_IDX_DDI_F 6
9141#define SKL_PW_CTL_IDX_DDI_D 4
9142#define SKL_PW_CTL_IDX_DDI_C 3
9143#define SKL_PW_CTL_IDX_DDI_B 2
9144#define SKL_PW_CTL_IDX_DDI_A_E 1
9145#define GLK_PW_CTL_IDX_DDI_A 1
9146#define SKL_PW_CTL_IDX_MISC_IO 0
9147
9148/* ICL/TGL - power wells */
9149#define TGL_PW_CTL_IDX_PW_5 4
9150#define ICL_PW_CTL_IDX_PW_4 3
9151#define ICL_PW_CTL_IDX_PW_3 2
9152#define ICL_PW_CTL_IDX_PW_2 1
9153#define ICL_PW_CTL_IDX_PW_1 0
9154
9155#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
9156#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
9157#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
9158#define TGL_PW_CTL_IDX_AUX_TBT6 14
9159#define TGL_PW_CTL_IDX_AUX_TBT5 13
9160#define TGL_PW_CTL_IDX_AUX_TBT4 12
9161#define ICL_PW_CTL_IDX_AUX_TBT4 11
9162#define TGL_PW_CTL_IDX_AUX_TBT3 11
9163#define ICL_PW_CTL_IDX_AUX_TBT3 10
9164#define TGL_PW_CTL_IDX_AUX_TBT2 10
9165#define ICL_PW_CTL_IDX_AUX_TBT2 9
9166#define TGL_PW_CTL_IDX_AUX_TBT1 9
9167#define ICL_PW_CTL_IDX_AUX_TBT1 8
9168#define TGL_PW_CTL_IDX_AUX_TC6 8
9169#define TGL_PW_CTL_IDX_AUX_TC5 7
9170#define TGL_PW_CTL_IDX_AUX_TC4 6
9171#define ICL_PW_CTL_IDX_AUX_F 5
9172#define TGL_PW_CTL_IDX_AUX_TC3 5
9173#define ICL_PW_CTL_IDX_AUX_E 4
9174#define TGL_PW_CTL_IDX_AUX_TC2 4
9175#define ICL_PW_CTL_IDX_AUX_D 3
9176#define TGL_PW_CTL_IDX_AUX_TC1 3
9177#define ICL_PW_CTL_IDX_AUX_C 2
9178#define ICL_PW_CTL_IDX_AUX_B 1
9179#define ICL_PW_CTL_IDX_AUX_A 0
9180
9181#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
9182#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
9183#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
9184#define TGL_PW_CTL_IDX_DDI_TC6 8
9185#define TGL_PW_CTL_IDX_DDI_TC5 7
9186#define TGL_PW_CTL_IDX_DDI_TC4 6
9187#define ICL_PW_CTL_IDX_DDI_F 5
9188#define TGL_PW_CTL_IDX_DDI_TC3 5
9189#define ICL_PW_CTL_IDX_DDI_E 4
9190#define TGL_PW_CTL_IDX_DDI_TC2 4
9191#define ICL_PW_CTL_IDX_DDI_D 3
9192#define TGL_PW_CTL_IDX_DDI_TC1 3
9193#define ICL_PW_CTL_IDX_DDI_C 2
9194#define ICL_PW_CTL_IDX_DDI_B 1
9195#define ICL_PW_CTL_IDX_DDI_A 0
9196
9197/* HSW - power well misc debug registers */
9198#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
9199#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
9200#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
9201#define HSW_PWR_WELL_FORCE_ON (1 << 19)
9202#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
9203
9204/* SKL Fuse Status */
9205enum skl_power_gate {
9206 SKL_PG0,
9207 SKL_PG1,
9208 SKL_PG2,
9209 ICL_PG3,
9210 ICL_PG4,
9211};
9212
9213#define SKL_FUSE_STATUS _MMIO(0x42000)
9214#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
9215/*
9216 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9217 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9218 */
9219#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
9220 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9221/*
9222 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9223 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9224 */
9225#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
9226 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9227#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
9228
9229#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9230#define _CNL_AUX_ANAOVRD1_B 0x162250
9231#define _CNL_AUX_ANAOVRD1_C 0x162210
9232#define _CNL_AUX_ANAOVRD1_D 0x1622D0
9233#define _CNL_AUX_ANAOVRD1_F 0x162A90
9234#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9235 _CNL_AUX_ANAOVRD1_B, \
9236 _CNL_AUX_ANAOVRD1_C, \
9237 _CNL_AUX_ANAOVRD1_D, \
9238 _CNL_AUX_ANAOVRD1_F))
9239#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
9240#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
9241
9242#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9243#define _ICL_AUX_ANAOVRD1_A 0x162398
9244#define _ICL_AUX_ANAOVRD1_B 0x6C398
9245#define _TGL_AUX_ANAOVRD1_C 0x160398
9246#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9247 _ICL_AUX_ANAOVRD1_A, \
9248 _ICL_AUX_ANAOVRD1_B, \
9249 _TGL_AUX_ANAOVRD1_C))
9250#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
9251#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
9252
9253/* HDCP Key Registers */
9254#define HDCP_KEY_CONF _MMIO(0x66c00)
9255#define HDCP_AKSV_SEND_TRIGGER BIT(31)
9256#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
9257#define HDCP_KEY_LOAD_TRIGGER BIT(8)
9258#define HDCP_KEY_STATUS _MMIO(0x66c04)
9259#define HDCP_FUSE_IN_PROGRESS BIT(7)
9260#define HDCP_FUSE_ERROR BIT(6)
9261#define HDCP_FUSE_DONE BIT(5)
9262#define HDCP_KEY_LOAD_STATUS BIT(1)
9263#define HDCP_KEY_LOAD_DONE BIT(0)
9264#define HDCP_AKSV_LO _MMIO(0x66c10)
9265#define HDCP_AKSV_HI _MMIO(0x66c14)
9266
9267/* HDCP Repeater Registers */
9268#define HDCP_REP_CTL _MMIO(0x66d00)
9269#define HDCP_DDIB_REP_PRESENT BIT(30)
9270#define HDCP_DDIA_REP_PRESENT BIT(29)
9271#define HDCP_DDIC_REP_PRESENT BIT(28)
9272#define HDCP_DDID_REP_PRESENT BIT(27)
9273#define HDCP_DDIF_REP_PRESENT BIT(26)
9274#define HDCP_DDIE_REP_PRESENT BIT(25)
9275#define HDCP_DDIB_SHA1_M0 (1 << 20)
9276#define HDCP_DDIA_SHA1_M0 (2 << 20)
9277#define HDCP_DDIC_SHA1_M0 (3 << 20)
9278#define HDCP_DDID_SHA1_M0 (4 << 20)
9279#define HDCP_DDIF_SHA1_M0 (5 << 20)
9280#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
9281#define HDCP_SHA1_BUSY BIT(16)
9282#define HDCP_SHA1_READY BIT(17)
9283#define HDCP_SHA1_COMPLETE BIT(18)
9284#define HDCP_SHA1_V_MATCH BIT(19)
9285#define HDCP_SHA1_TEXT_32 (1 << 1)
9286#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
9287#define HDCP_SHA1_TEXT_24 (4 << 1)
9288#define HDCP_SHA1_TEXT_16 (5 << 1)
9289#define HDCP_SHA1_TEXT_8 (6 << 1)
9290#define HDCP_SHA1_TEXT_0 (7 << 1)
9291#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
9292#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
9293#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
9294#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
9295#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
9296#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
9297#define HDCP_SHA_TEXT _MMIO(0x66d18)
9298
9299/* HDCP Auth Registers */
9300#define _PORTA_HDCP_AUTHENC 0x66800
9301#define _PORTB_HDCP_AUTHENC 0x66500
9302#define _PORTC_HDCP_AUTHENC 0x66600
9303#define _PORTD_HDCP_AUTHENC 0x66700
9304#define _PORTE_HDCP_AUTHENC 0x66A00
9305#define _PORTF_HDCP_AUTHENC 0x66900
9306#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
9307 _PORTA_HDCP_AUTHENC, \
9308 _PORTB_HDCP_AUTHENC, \
9309 _PORTC_HDCP_AUTHENC, \
9310 _PORTD_HDCP_AUTHENC, \
9311 _PORTE_HDCP_AUTHENC, \
9312 _PORTF_HDCP_AUTHENC) + (x))
9313#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
9314#define HDCP_CONF_CAPTURE_AN BIT(0)
9315#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
9316#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
9317#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
9318#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
9319#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
9320#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
9321#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
9322#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
9323#define HDCP_STATUS_STREAM_A_ENC BIT(31)
9324#define HDCP_STATUS_STREAM_B_ENC BIT(30)
9325#define HDCP_STATUS_STREAM_C_ENC BIT(29)
9326#define HDCP_STATUS_STREAM_D_ENC BIT(28)
9327#define HDCP_STATUS_AUTH BIT(21)
9328#define HDCP_STATUS_ENC BIT(20)
9329#define HDCP_STATUS_RI_MATCH BIT(19)
9330#define HDCP_STATUS_R0_READY BIT(18)
9331#define HDCP_STATUS_AN_READY BIT(17)
9332#define HDCP_STATUS_CIPHER BIT(16)
9333#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9334
9335/* HDCP2.2 Registers */
9336#define _PORTA_HDCP2_BASE 0x66800
9337#define _PORTB_HDCP2_BASE 0x66500
9338#define _PORTC_HDCP2_BASE 0x66600
9339#define _PORTD_HDCP2_BASE 0x66700
9340#define _PORTE_HDCP2_BASE 0x66A00
9341#define _PORTF_HDCP2_BASE 0x66900
9342#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
9343 _PORTA_HDCP2_BASE, \
9344 _PORTB_HDCP2_BASE, \
9345 _PORTC_HDCP2_BASE, \
9346 _PORTD_HDCP2_BASE, \
9347 _PORTE_HDCP2_BASE, \
9348 _PORTF_HDCP2_BASE) + (x))
9349
9350#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
9351#define AUTH_LINK_AUTHENTICATED BIT(31)
9352#define AUTH_LINK_TYPE BIT(30)
9353#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
9354#define AUTH_CLR_KEYS BIT(18)
9355
9356#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
9357#define CTL_LINK_ENCRYPTION_REQ BIT(31)
9358
9359#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
9360#define STREAM_ENCRYPTION_STATUS_A BIT(31)
9361#define STREAM_ENCRYPTION_STATUS_B BIT(30)
9362#define STREAM_ENCRYPTION_STATUS_C BIT(29)
9363#define LINK_TYPE_STATUS BIT(22)
9364#define LINK_AUTH_STATUS BIT(21)
9365#define LINK_ENCRYPTION_STATUS BIT(20)
9366
9367/* Per-pipe DDI Function Control */
9368#define _TRANS_DDI_FUNC_CTL_A 0x60400
9369#define _TRANS_DDI_FUNC_CTL_B 0x61400
9370#define _TRANS_DDI_FUNC_CTL_C 0x62400
9371#define _TRANS_DDI_FUNC_CTL_D 0x63400
9372#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9373#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
9374#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
9375#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9376
9377#define TRANS_DDI_FUNC_ENABLE (1 << 31)
9378/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9379#define TRANS_DDI_PORT_SHIFT 28
9380#define TGL_TRANS_DDI_PORT_SHIFT 27
9381#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
9382#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
9383#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
9384#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
9385#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
9386#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9387#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9388#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9389#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
9390#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
9391#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
9392#define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
9393#define TRANS_DDI_BPC_MASK (7 << 20)
9394#define TRANS_DDI_BPC_8 (0 << 20)
9395#define TRANS_DDI_BPC_10 (1 << 20)
9396#define TRANS_DDI_BPC_6 (2 << 20)
9397#define TRANS_DDI_BPC_12 (3 << 20)
9398#define TRANS_DDI_PVSYNC (1 << 17)
9399#define TRANS_DDI_PHSYNC (1 << 16)
9400#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9401#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9402#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9403#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9404#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9405#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9406#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9407#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9408#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9409#define TRANS_DDI_BFI_ENABLE (1 << 4)
9410#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
9411#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
9412#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9413 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9414 | TRANS_DDI_HDMI_SCRAMBLING)
9415
9416#define _TRANS_DDI_FUNC_CTL2_A 0x60404
9417#define _TRANS_DDI_FUNC_CTL2_B 0x61404
9418#define _TRANS_DDI_FUNC_CTL2_C 0x62404
9419#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
9420#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
9421#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
9422#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
9423 _TRANS_DDI_FUNC_CTL2_A)
9424#define PORT_SYNC_MODE_ENABLE (1 << 4)
9425#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0)
9426#define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
9427#define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
9428
9429/* DisplayPort Transport Control */
9430#define _DP_TP_CTL_A 0x64040
9431#define _DP_TP_CTL_B 0x64140
9432#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9433#define DP_TP_CTL_ENABLE (1 << 31)
9434#define DP_TP_CTL_FEC_ENABLE (1 << 30)
9435#define DP_TP_CTL_MODE_SST (0 << 27)
9436#define DP_TP_CTL_MODE_MST (1 << 27)
9437#define DP_TP_CTL_FORCE_ACT (1 << 25)
9438#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
9439#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
9440#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
9441#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
9442#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
9443#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
9444#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
9445#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
9446#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
9447#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
9448
9449/* DisplayPort Transport Status */
9450#define _DP_TP_STATUS_A 0x64044
9451#define _DP_TP_STATUS_B 0x64144
9452#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9453#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
9454#define DP_TP_STATUS_IDLE_DONE (1 << 25)
9455#define DP_TP_STATUS_ACT_SENT (1 << 24)
9456#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
9457#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
9458#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
9459#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
9460#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
9461
9462/* DDI Buffer Control */
9463#define _DDI_BUF_CTL_A 0x64000
9464#define _DDI_BUF_CTL_B 0x64100
9465#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9466#define DDI_BUF_CTL_ENABLE (1 << 31)
9467#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
9468#define DDI_BUF_EMP_MASK (0xf << 24)
9469#define DDI_BUF_PORT_REVERSAL (1 << 16)
9470#define DDI_BUF_IS_IDLE (1 << 7)
9471#define DDI_A_4_LANES (1 << 4)
9472#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
9473#define DDI_PORT_WIDTH_MASK (7 << 1)
9474#define DDI_PORT_WIDTH_SHIFT 1
9475#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
9476
9477/* DDI Buffer Translations */
9478#define _DDI_BUF_TRANS_A 0x64E00
9479#define _DDI_BUF_TRANS_B 0x64E60
9480#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9481#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
9482#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9483
9484/* Sideband Interface (SBI) is programmed indirectly, via
9485 * SBI_ADDR, which contains the register offset; and SBI_DATA,
9486 * which contains the payload */
9487#define SBI_ADDR _MMIO(0xC6000)
9488#define SBI_DATA _MMIO(0xC6004)
9489#define SBI_CTL_STAT _MMIO(0xC6008)
9490#define SBI_CTL_DEST_ICLK (0x0 << 16)
9491#define SBI_CTL_DEST_MPHY (0x1 << 16)
9492#define SBI_CTL_OP_IORD (0x2 << 8)
9493#define SBI_CTL_OP_IOWR (0x3 << 8)
9494#define SBI_CTL_OP_CRRD (0x6 << 8)
9495#define SBI_CTL_OP_CRWR (0x7 << 8)
9496#define SBI_RESPONSE_FAIL (0x1 << 1)
9497#define SBI_RESPONSE_SUCCESS (0x0 << 1)
9498#define SBI_BUSY (0x1 << 0)
9499#define SBI_READY (0x0 << 0)
9500
9501/* SBI offsets */
9502#define SBI_SSCDIVINTPHASE 0x0200
9503#define SBI_SSCDIVINTPHASE6 0x0600
9504#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
9505#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
9506#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
9507#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
9508#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
9509#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
9510#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
9511#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
9512#define SBI_SSCDITHPHASE 0x0204
9513#define SBI_SSCCTL 0x020c
9514#define SBI_SSCCTL6 0x060C
9515#define SBI_SSCCTL_PATHALT (1 << 3)
9516#define SBI_SSCCTL_DISABLE (1 << 0)
9517#define SBI_SSCAUXDIV6 0x0610
9518#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
9519#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
9520#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
9521#define SBI_DBUFF0 0x2a00
9522#define SBI_GEN0 0x1f00
9523#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
9524
9525/* LPT PIXCLK_GATE */
9526#define PIXCLK_GATE _MMIO(0xC6020)
9527#define PIXCLK_GATE_UNGATE (1 << 0)
9528#define PIXCLK_GATE_GATE (0 << 0)
9529
9530/* SPLL */
9531#define SPLL_CTL _MMIO(0x46020)
9532#define SPLL_PLL_ENABLE (1 << 31)
9533#define SPLL_REF_BCLK (0 << 28)
9534#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9535#define SPLL_REF_NON_SSC_HSW (2 << 28)
9536#define SPLL_REF_PCH_SSC_BDW (2 << 28)
9537#define SPLL_REF_LCPLL (3 << 28)
9538#define SPLL_REF_MASK (3 << 28)
9539#define SPLL_FREQ_810MHz (0 << 26)
9540#define SPLL_FREQ_1350MHz (1 << 26)
9541#define SPLL_FREQ_2700MHz (2 << 26)
9542#define SPLL_FREQ_MASK (3 << 26)
9543
9544/* WRPLL */
9545#define _WRPLL_CTL1 0x46040
9546#define _WRPLL_CTL2 0x46060
9547#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9548#define WRPLL_PLL_ENABLE (1 << 31)
9549#define WRPLL_REF_BCLK (0 << 28)
9550#define WRPLL_REF_PCH_SSC (1 << 28)
9551#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9552#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
9553#define WRPLL_REF_LCPLL (3 << 28)
9554#define WRPLL_REF_MASK (3 << 28)
9555/* WRPLL divider programming */
9556#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
9557#define WRPLL_DIVIDER_REF_MASK (0xff)
9558#define WRPLL_DIVIDER_POST(x) ((x) << 8)
9559#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
9560#define WRPLL_DIVIDER_POST_SHIFT 8
9561#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
9562#define WRPLL_DIVIDER_FB_SHIFT 16
9563#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
9564
9565/* Port clock selection */
9566#define _PORT_CLK_SEL_A 0x46100
9567#define _PORT_CLK_SEL_B 0x46104
9568#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9569#define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
9570#define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
9571#define PORT_CLK_SEL_LCPLL_810 (2 << 29)
9572#define PORT_CLK_SEL_SPLL (3 << 29)
9573#define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
9574#define PORT_CLK_SEL_WRPLL1 (4 << 29)
9575#define PORT_CLK_SEL_WRPLL2 (5 << 29)
9576#define PORT_CLK_SEL_NONE (7 << 29)
9577#define PORT_CLK_SEL_MASK (7 << 29)
9578
9579/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9580#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
9581#define DDI_CLK_SEL_NONE (0x0 << 28)
9582#define DDI_CLK_SEL_MG (0x8 << 28)
9583#define DDI_CLK_SEL_TBT_162 (0xC << 28)
9584#define DDI_CLK_SEL_TBT_270 (0xD << 28)
9585#define DDI_CLK_SEL_TBT_540 (0xE << 28)
9586#define DDI_CLK_SEL_TBT_810 (0xF << 28)
9587#define DDI_CLK_SEL_MASK (0xF << 28)
9588
9589/* Transcoder clock selection */
9590#define _TRANS_CLK_SEL_A 0x46140
9591#define _TRANS_CLK_SEL_B 0x46144
9592#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9593/* For each transcoder, we need to select the corresponding port clock */
9594#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
9595#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
9596#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
9597#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
9598
9599
9600#define CDCLK_FREQ _MMIO(0x46200)
9601
9602#define _TRANSA_MSA_MISC 0x60410
9603#define _TRANSB_MSA_MISC 0x61410
9604#define _TRANSC_MSA_MISC 0x62410
9605#define _TRANS_EDP_MSA_MISC 0x6f410
9606#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9607
9608#define TRANS_MSA_SYNC_CLK (1 << 0)
9609#define TRANS_MSA_SAMPLING_444 (2 << 1)
9610#define TRANS_MSA_CLRSP_YCBCR (2 << 3)
9611#define TRANS_MSA_6_BPC (0 << 5)
9612#define TRANS_MSA_8_BPC (1 << 5)
9613#define TRANS_MSA_10_BPC (2 << 5)
9614#define TRANS_MSA_12_BPC (3 << 5)
9615#define TRANS_MSA_16_BPC (4 << 5)
9616#define TRANS_MSA_CEA_RANGE (1 << 3)
9617#define TRANS_MSA_USE_VSC_SDP (1 << 14)
9618
9619/* LCPLL Control */
9620#define LCPLL_CTL _MMIO(0x130040)
9621#define LCPLL_PLL_DISABLE (1 << 31)
9622#define LCPLL_PLL_LOCK (1 << 30)
9623#define LCPLL_REF_NON_SSC (0 << 28)
9624#define LCPLL_REF_BCLK (2 << 28)
9625#define LCPLL_REF_PCH_SSC (3 << 28)
9626#define LCPLL_REF_MASK (3 << 28)
9627#define LCPLL_CLK_FREQ_MASK (3 << 26)
9628#define LCPLL_CLK_FREQ_450 (0 << 26)
9629#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
9630#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
9631#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
9632#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
9633#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
9634#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
9635#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
9636#define LCPLL_CD_SOURCE_FCLK (1 << 21)
9637#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
9638
9639/*
9640 * SKL Clocks
9641 */
9642
9643/* CDCLK_CTL */
9644#define CDCLK_CTL _MMIO(0x46000)
9645#define CDCLK_FREQ_SEL_MASK (3 << 26)
9646#define CDCLK_FREQ_450_432 (0 << 26)
9647#define CDCLK_FREQ_540 (1 << 26)
9648#define CDCLK_FREQ_337_308 (2 << 26)
9649#define CDCLK_FREQ_675_617 (3 << 26)
9650#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
9651#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
9652#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
9653#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
9654#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
9655#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
9656#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
9657#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
9658#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
9659#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9660#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
9661
9662/* LCPLL_CTL */
9663#define LCPLL1_CTL _MMIO(0x46010)
9664#define LCPLL2_CTL _MMIO(0x46014)
9665#define LCPLL_PLL_ENABLE (1 << 31)
9666
9667/* DPLL control1 */
9668#define DPLL_CTRL1 _MMIO(0x6C058)
9669#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
9670#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
9671#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
9672#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
9673#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
9674#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
9675#define DPLL_CTRL1_LINK_RATE_2700 0
9676#define DPLL_CTRL1_LINK_RATE_1350 1
9677#define DPLL_CTRL1_LINK_RATE_810 2
9678#define DPLL_CTRL1_LINK_RATE_1620 3
9679#define DPLL_CTRL1_LINK_RATE_1080 4
9680#define DPLL_CTRL1_LINK_RATE_2160 5
9681
9682/* DPLL control2 */
9683#define DPLL_CTRL2 _MMIO(0x6C05C)
9684#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
9685#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
9686#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
9687#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
9688#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
9689
9690/* DPLL Status */
9691#define DPLL_STATUS _MMIO(0x6C060)
9692#define DPLL_LOCK(id) (1 << ((id) * 8))
9693
9694/* DPLL cfg */
9695#define _DPLL1_CFGCR1 0x6C040
9696#define _DPLL2_CFGCR1 0x6C048
9697#define _DPLL3_CFGCR1 0x6C050
9698#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
9699#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
9700#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
9701#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
9702
9703#define _DPLL1_CFGCR2 0x6C044
9704#define _DPLL2_CFGCR2 0x6C04C
9705#define _DPLL3_CFGCR2 0x6C054
9706#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
9707#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
9708#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
9709#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
9710#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
9711#define DPLL_CFGCR2_KDIV_5 (0 << 5)
9712#define DPLL_CFGCR2_KDIV_2 (1 << 5)
9713#define DPLL_CFGCR2_KDIV_3 (2 << 5)
9714#define DPLL_CFGCR2_KDIV_1 (3 << 5)
9715#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
9716#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
9717#define DPLL_CFGCR2_PDIV_1 (0 << 2)
9718#define DPLL_CFGCR2_PDIV_2 (1 << 2)
9719#define DPLL_CFGCR2_PDIV_3 (2 << 2)
9720#define DPLL_CFGCR2_PDIV_7 (4 << 2)
9721#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
9722
9723#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9724#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9725
9726/*
9727 * CNL Clocks
9728 */
9729#define DPCLKA_CFGCR0 _MMIO(0x6C200)
9730#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9731 (port) + 10))
9732#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9733 (port) * 2)
9734#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9735#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9736
9737#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
9738#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
9739#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
9740 (tc_port) + 12 : \
9741 (tc_port) - PORT_TC4 + 21))
9742#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
9743#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9744#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9745
9746/* CNL PLL */
9747#define DPLL0_ENABLE 0x46010
9748#define DPLL1_ENABLE 0x46014
9749#define PLL_ENABLE (1 << 31)
9750#define PLL_LOCK (1 << 30)
9751#define PLL_POWER_ENABLE (1 << 27)
9752#define PLL_POWER_STATE (1 << 26)
9753#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9754
9755#define TBT_PLL_ENABLE _MMIO(0x46020)
9756
9757#define _MG_PLL1_ENABLE 0x46030
9758#define _MG_PLL2_ENABLE 0x46034
9759#define _MG_PLL3_ENABLE 0x46038
9760#define _MG_PLL4_ENABLE 0x4603C
9761/* Bits are the same as DPLL0_ENABLE */
9762#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
9763 _MG_PLL2_ENABLE)
9764
9765#define _MG_REFCLKIN_CTL_PORT1 0x16892C
9766#define _MG_REFCLKIN_CTL_PORT2 0x16992C
9767#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
9768#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
9769#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
9770#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
9771#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
9772 _MG_REFCLKIN_CTL_PORT1, \
9773 _MG_REFCLKIN_CTL_PORT2)
9774
9775#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
9776#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
9777#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
9778#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
9779#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
9780#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
9781#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
9782#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
9783#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
9784 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9785 _MG_CLKTOP2_CORECLKCTL1_PORT2)
9786
9787#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
9788#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
9789#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
9790#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
9791#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
9792#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
9793#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
9794#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9795#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
9796#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
9797#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
9798#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
9799#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
9800#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
9801#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
9802#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
9803#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
9804 _MG_CLKTOP2_HSCLKCTL_PORT1, \
9805 _MG_CLKTOP2_HSCLKCTL_PORT2)
9806
9807#define _MG_PLL_DIV0_PORT1 0x168A00
9808#define _MG_PLL_DIV0_PORT2 0x169A00
9809#define _MG_PLL_DIV0_PORT3 0x16AA00
9810#define _MG_PLL_DIV0_PORT4 0x16BA00
9811#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
9812#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
9813#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
9814#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
9815#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
9816#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
9817#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
9818 _MG_PLL_DIV0_PORT2)
9819
9820#define _MG_PLL_DIV1_PORT1 0x168A04
9821#define _MG_PLL_DIV1_PORT2 0x169A04
9822#define _MG_PLL_DIV1_PORT3 0x16AA04
9823#define _MG_PLL_DIV1_PORT4 0x16BA04
9824#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
9825#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
9826#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
9827#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
9828#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
9829#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
9830#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
9831#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
9832#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
9833 _MG_PLL_DIV1_PORT2)
9834
9835#define _MG_PLL_LF_PORT1 0x168A08
9836#define _MG_PLL_LF_PORT2 0x169A08
9837#define _MG_PLL_LF_PORT3 0x16AA08
9838#define _MG_PLL_LF_PORT4 0x16BA08
9839#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
9840#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
9841#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
9842#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
9843#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
9844#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
9845#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
9846 _MG_PLL_LF_PORT2)
9847
9848#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
9849#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
9850#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
9851#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
9852#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
9853#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
9854#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
9855#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
9856#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
9857#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
9858#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
9859 _MG_PLL_FRAC_LOCK_PORT1, \
9860 _MG_PLL_FRAC_LOCK_PORT2)
9861
9862#define _MG_PLL_SSC_PORT1 0x168A10
9863#define _MG_PLL_SSC_PORT2 0x169A10
9864#define _MG_PLL_SSC_PORT3 0x16AA10
9865#define _MG_PLL_SSC_PORT4 0x16BA10
9866#define MG_PLL_SSC_EN (1 << 28)
9867#define MG_PLL_SSC_TYPE(x) ((x) << 26)
9868#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
9869#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
9870#define MG_PLL_SSC_FLLEN (1 << 9)
9871#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
9872#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
9873 _MG_PLL_SSC_PORT2)
9874
9875#define _MG_PLL_BIAS_PORT1 0x168A14
9876#define _MG_PLL_BIAS_PORT2 0x169A14
9877#define _MG_PLL_BIAS_PORT3 0x16AA14
9878#define _MG_PLL_BIAS_PORT4 0x16BA14
9879#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
9880#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
9881#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
9882#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
9883#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
9884#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
9885#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
9886#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
9887#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
9888#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
9889#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
9890#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
9891#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
9892#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
9893 _MG_PLL_BIAS_PORT2)
9894
9895#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
9896#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
9897#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
9898#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
9899#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
9900#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
9901#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
9902#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
9903#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
9904#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
9905 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9906 _MG_PLL_TDC_COLDST_BIAS_PORT2)
9907
9908#define _CNL_DPLL0_CFGCR0 0x6C000
9909#define _CNL_DPLL1_CFGCR0 0x6C080
9910#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
9911#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
9912#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
9913#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
9914#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
9915#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
9916#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
9917#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
9918#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
9919#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
9920#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
9921#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
9922#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
9923#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9924#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
9925#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
9926#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9927
9928#define _CNL_DPLL0_CFGCR1 0x6C004
9929#define _CNL_DPLL1_CFGCR1 0x6C084
9930#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
9931#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
9932#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
9933#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
9934#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
9935#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
9936#define DPLL_CFGCR1_KDIV_SHIFT (6)
9937#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9938#define DPLL_CFGCR1_KDIV_1 (1 << 6)
9939#define DPLL_CFGCR1_KDIV_2 (2 << 6)
9940#define DPLL_CFGCR1_KDIV_3 (4 << 6)
9941#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9942#define DPLL_CFGCR1_PDIV_SHIFT (2)
9943#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
9944#define DPLL_CFGCR1_PDIV_2 (1 << 2)
9945#define DPLL_CFGCR1_PDIV_3 (2 << 2)
9946#define DPLL_CFGCR1_PDIV_5 (4 << 2)
9947#define DPLL_CFGCR1_PDIV_7 (8 << 2)
9948#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9949#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
9950#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
9951#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9952
9953#define _ICL_DPLL0_CFGCR0 0x164000
9954#define _ICL_DPLL1_CFGCR0 0x164080
9955#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
9956 _ICL_DPLL1_CFGCR0)
9957
9958#define _ICL_DPLL0_CFGCR1 0x164004
9959#define _ICL_DPLL1_CFGCR1 0x164084
9960#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9961 _ICL_DPLL1_CFGCR1)
9962
9963#define _TGL_DPLL0_CFGCR0 0x164284
9964#define _TGL_DPLL1_CFGCR0 0x16428C
9965/* TODO: add DPLL4 */
9966#define _TGL_TBTPLL_CFGCR0 0x16429C
9967#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
9968 _TGL_DPLL1_CFGCR0, \
9969 _TGL_TBTPLL_CFGCR0)
9970
9971#define _TGL_DPLL0_CFGCR1 0x164288
9972#define _TGL_DPLL1_CFGCR1 0x164290
9973/* TODO: add DPLL4 */
9974#define _TGL_TBTPLL_CFGCR1 0x1642A0
9975#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
9976 _TGL_DPLL1_CFGCR1, \
9977 _TGL_TBTPLL_CFGCR1)
9978
9979/* BXT display engine PLL */
9980#define BXT_DE_PLL_CTL _MMIO(0x6d000)
9981#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
9982#define BXT_DE_PLL_RATIO_MASK 0xff
9983
9984#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
9985#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
9986#define BXT_DE_PLL_LOCK (1 << 30)
9987#define CNL_CDCLK_PLL_RATIO(x) (x)
9988#define CNL_CDCLK_PLL_RATIO_MASK 0xff
9989
9990/* GEN9 DC */
9991#define DC_STATE_EN _MMIO(0x45504)
9992#define DC_STATE_DISABLE 0
9993#define DC_STATE_EN_UPTO_DC5 (1 << 0)
9994#define DC_STATE_EN_DC9 (1 << 3)
9995#define DC_STATE_EN_UPTO_DC6 (2 << 0)
9996#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
9997
9998#define DC_STATE_DEBUG _MMIO(0x45520)
9999#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
10000#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
10001
10002#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10003#define BXT_REQ_DATA_MASK 0x3F
10004#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
10005#define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
10006#define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
10007
10008#define BXT_D_CR_DRP0_DUNIT8 0x1000
10009#define BXT_D_CR_DRP0_DUNIT9 0x1200
10010#define BXT_D_CR_DRP0_DUNIT_START 8
10011#define BXT_D_CR_DRP0_DUNIT_END 11
10012#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
10013 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10014 BXT_D_CR_DRP0_DUNIT9))
10015#define BXT_DRAM_RANK_MASK 0x3
10016#define BXT_DRAM_RANK_SINGLE 0x1
10017#define BXT_DRAM_RANK_DUAL 0x3
10018#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
10019#define BXT_DRAM_WIDTH_SHIFT 4
10020#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
10021#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
10022#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
10023#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
10024#define BXT_DRAM_SIZE_MASK (0x7 << 6)
10025#define BXT_DRAM_SIZE_SHIFT 6
10026#define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
10027#define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
10028#define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
10029#define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
10030#define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
10031#define BXT_DRAM_TYPE_MASK (0x7 << 22)
10032#define BXT_DRAM_TYPE_SHIFT 22
10033#define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
10034#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
10035#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
10036#define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
10037
10038#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
10039#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10040#define SKL_REQ_DATA_MASK (0xF << 0)
10041
10042#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10043#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
10044#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
10045#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
10046#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
10047#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
10048
10049#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10050#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10051#define SKL_DRAM_S_SHIFT 16
10052#define SKL_DRAM_SIZE_MASK 0x3F
10053#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
10054#define SKL_DRAM_WIDTH_SHIFT 8
10055#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
10056#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
10057#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
10058#define SKL_DRAM_RANK_MASK (0x1 << 10)
10059#define SKL_DRAM_RANK_SHIFT 10
10060#define SKL_DRAM_RANK_1 (0x0 << 10)
10061#define SKL_DRAM_RANK_2 (0x1 << 10)
10062#define SKL_DRAM_RANK_MASK (0x1 << 10)
10063#define CNL_DRAM_SIZE_MASK 0x7F
10064#define CNL_DRAM_WIDTH_MASK (0x3 << 7)
10065#define CNL_DRAM_WIDTH_SHIFT 7
10066#define CNL_DRAM_WIDTH_X8 (0x0 << 7)
10067#define CNL_DRAM_WIDTH_X16 (0x1 << 7)
10068#define CNL_DRAM_WIDTH_X32 (0x2 << 7)
10069#define CNL_DRAM_RANK_MASK (0x3 << 9)
10070#define CNL_DRAM_RANK_SHIFT 9
10071#define CNL_DRAM_RANK_1 (0x0 << 9)
10072#define CNL_DRAM_RANK_2 (0x1 << 9)
10073#define CNL_DRAM_RANK_3 (0x2 << 9)
10074#define CNL_DRAM_RANK_4 (0x3 << 9)
10075
10076/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10077 * since on HSW we can't write to it using I915_WRITE. */
10078#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10079#define D_COMP_BDW _MMIO(0x138144)
10080#define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
10081#define D_COMP_COMP_FORCE (1 << 8)
10082#define D_COMP_COMP_DISABLE (1 << 0)
10083
10084/* Pipe WM_LINETIME - watermark line time */
10085#define _PIPE_WM_LINETIME_A 0x45270
10086#define _PIPE_WM_LINETIME_B 0x45274
10087#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
10088#define PIPE_WM_LINETIME_MASK (0x1ff)
10089#define PIPE_WM_LINETIME_TIME(x) ((x))
10090#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
10091#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
10092
10093/* SFUSE_STRAP */
10094#define SFUSE_STRAP _MMIO(0xc2014)
10095#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
10096#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
10097#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
10098#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
10099#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
10100#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
10101#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
10102#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
10103
10104#define WM_MISC _MMIO(0x45260)
10105#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
10106
10107#define WM_DBG _MMIO(0x45280)
10108#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
10109#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
10110#define WM_DBG_DISALLOW_SPRITE (1 << 2)
10111
10112/* pipe CSC */
10113#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
10114#define _PIPE_A_CSC_COEFF_BY 0x49014
10115#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
10116#define _PIPE_A_CSC_COEFF_BU 0x4901c
10117#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
10118#define _PIPE_A_CSC_COEFF_BV 0x49024
10119
10120#define _PIPE_A_CSC_MODE 0x49028
10121#define ICL_CSC_ENABLE (1 << 31)
10122#define ICL_OUTPUT_CSC_ENABLE (1 << 30)
10123#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
10124#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
10125#define CSC_MODE_YUV_TO_RGB (1 << 0)
10126
10127#define _PIPE_A_CSC_PREOFF_HI 0x49030
10128#define _PIPE_A_CSC_PREOFF_ME 0x49034
10129#define _PIPE_A_CSC_PREOFF_LO 0x49038
10130#define _PIPE_A_CSC_POSTOFF_HI 0x49040
10131#define _PIPE_A_CSC_POSTOFF_ME 0x49044
10132#define _PIPE_A_CSC_POSTOFF_LO 0x49048
10133
10134#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
10135#define _PIPE_B_CSC_COEFF_BY 0x49114
10136#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
10137#define _PIPE_B_CSC_COEFF_BU 0x4911c
10138#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
10139#define _PIPE_B_CSC_COEFF_BV 0x49124
10140#define _PIPE_B_CSC_MODE 0x49128
10141#define _PIPE_B_CSC_PREOFF_HI 0x49130
10142#define _PIPE_B_CSC_PREOFF_ME 0x49134
10143#define _PIPE_B_CSC_PREOFF_LO 0x49138
10144#define _PIPE_B_CSC_POSTOFF_HI 0x49140
10145#define _PIPE_B_CSC_POSTOFF_ME 0x49144
10146#define _PIPE_B_CSC_POSTOFF_LO 0x49148
10147
10148#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
10149#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
10150#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
10151#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
10152#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
10153#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
10154#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
10155#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
10156#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
10157#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
10158#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
10159#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
10160#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
10161
10162/* Pipe Output CSC */
10163#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
10164#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
10165#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
10166#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
10167#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
10168#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
10169#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
10170#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
10171#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
10172#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
10173#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
10174#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
10175
10176#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
10177#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
10178#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
10179#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
10180#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
10181#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
10182#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
10183#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
10184#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
10185#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
10186#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
10187#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
10188
10189#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
10190 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
10191 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
10192#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
10193 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
10194 _PIPE_B_OUTPUT_CSC_COEFF_BY)
10195#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
10196 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
10197 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
10198#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
10199 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
10200 _PIPE_B_OUTPUT_CSC_COEFF_BU)
10201#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
10202 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
10203 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
10204#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
10205 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
10206 _PIPE_B_OUTPUT_CSC_COEFF_BV)
10207#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
10208 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
10209 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
10210#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
10211 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
10212 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
10213#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
10214 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
10215 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
10216#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
10217 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
10218 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
10219#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
10220 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
10221 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
10222#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
10223 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
10224 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
10225
10226/* pipe degamma/gamma LUTs on IVB+ */
10227#define _PAL_PREC_INDEX_A 0x4A400
10228#define _PAL_PREC_INDEX_B 0x4AC00
10229#define _PAL_PREC_INDEX_C 0x4B400
10230#define PAL_PREC_10_12_BIT (0 << 31)
10231#define PAL_PREC_SPLIT_MODE (1 << 31)
10232#define PAL_PREC_AUTO_INCREMENT (1 << 15)
10233#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
10234#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
10235#define _PAL_PREC_DATA_A 0x4A404
10236#define _PAL_PREC_DATA_B 0x4AC04
10237#define _PAL_PREC_DATA_C 0x4B404
10238#define _PAL_PREC_GC_MAX_A 0x4A410
10239#define _PAL_PREC_GC_MAX_B 0x4AC10
10240#define _PAL_PREC_GC_MAX_C 0x4B410
10241#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
10242#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
10243#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
10244#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
10245#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
10246#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
10247
10248#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
10249#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
10250#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
10251#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
10252#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
10253
10254#define _PRE_CSC_GAMC_INDEX_A 0x4A484
10255#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
10256#define _PRE_CSC_GAMC_INDEX_C 0x4B484
10257#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
10258#define _PRE_CSC_GAMC_DATA_A 0x4A488
10259#define _PRE_CSC_GAMC_DATA_B 0x4AC88
10260#define _PRE_CSC_GAMC_DATA_C 0x4B488
10261
10262#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
10263#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
10264
10265/* ICL Multi segmented gamma */
10266#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
10267#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
10268#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
10269#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
10270
10271#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
10272#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
10273
10274#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
10275 _PAL_PREC_MULTI_SEG_INDEX_A, \
10276 _PAL_PREC_MULTI_SEG_INDEX_B)
10277#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
10278 _PAL_PREC_MULTI_SEG_DATA_A, \
10279 _PAL_PREC_MULTI_SEG_DATA_B)
10280
10281/* pipe CSC & degamma/gamma LUTs on CHV */
10282#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
10283#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
10284#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
10285#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
10286#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
10287#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
10288#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
10289#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
10290#define CGM_PIPE_MODE_GAMMA (1 << 2)
10291#define CGM_PIPE_MODE_CSC (1 << 1)
10292#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
10293
10294#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
10295#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
10296#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
10297#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
10298#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
10299#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
10300#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
10301#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
10302
10303#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
10304#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
10305#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
10306#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
10307#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
10308#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
10309#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
10310#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
10311
10312/* MIPI DSI registers */
10313
10314#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
10315#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
10316
10317/* Gen11 DSI */
10318#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
10319 dsi0, dsi1)
10320
10321#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
10322#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
10323#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
10324#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
10325
10326#define _ICL_DSI_ESC_CLK_DIV0 0x6b090
10327#define _ICL_DSI_ESC_CLK_DIV1 0x6b890
10328#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
10329 _ICL_DSI_ESC_CLK_DIV0, \
10330 _ICL_DSI_ESC_CLK_DIV1)
10331#define _ICL_DPHY_ESC_CLK_DIV0 0x162190
10332#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
10333#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
10334 _ICL_DPHY_ESC_CLK_DIV0, \
10335 _ICL_DPHY_ESC_CLK_DIV1)
10336#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
10337#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
10338#define ICL_ESC_CLK_DIV_MASK 0x1ff
10339#define ICL_ESC_CLK_DIV_SHIFT 0
10340#define DSI_MAX_ESC_CLK 20000 /* in KHz */
10341
10342/* Gen4+ Timestamp and Pipe Frame time stamp registers */
10343#define GEN4_TIMESTAMP _MMIO(0x2358)
10344#define ILK_TIMESTAMP_HI _MMIO(0x70070)
10345#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
10346
10347#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
10348#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
10349#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
10350#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
10351#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
10352
10353#define _PIPE_FRMTMSTMP_A 0x70048
10354#define PIPE_FRMTMSTMP(pipe) \
10355 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
10356
10357/* BXT MIPI clock controls */
10358#define BXT_MAX_VAR_OUTPUT_KHZ 39500
10359
10360#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
10361#define BXT_MIPI1_DIV_SHIFT 26
10362#define BXT_MIPI2_DIV_SHIFT 10
10363#define BXT_MIPI_DIV_SHIFT(port) \
10364 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10365 BXT_MIPI2_DIV_SHIFT)
10366
10367/* TX control divider to select actual TX clock output from (8x/var) */
10368#define BXT_MIPI1_TX_ESCLK_SHIFT 26
10369#define BXT_MIPI2_TX_ESCLK_SHIFT 10
10370#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
10371 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10372 BXT_MIPI2_TX_ESCLK_SHIFT)
10373#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
10374#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
10375#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
10376 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10377 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10378#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
10379 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10380/* RX upper control divider to select actual RX clock output from 8x */
10381#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
10382#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
10383#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
10384 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10385 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10386#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
10387#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
10388#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
10389 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10390 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10391#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
10392 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10393/* 8/3X divider to select the actual 8/3X clock output from 8x */
10394#define BXT_MIPI1_8X_BY3_SHIFT 19
10395#define BXT_MIPI2_8X_BY3_SHIFT 3
10396#define BXT_MIPI_8X_BY3_SHIFT(port) \
10397 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10398 BXT_MIPI2_8X_BY3_SHIFT)
10399#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
10400#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
10401#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
10402 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10403 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10404#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
10405 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10406/* RX lower control divider to select actual RX clock output from 8x */
10407#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
10408#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
10409#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
10410 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10411 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10412#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
10413#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
10414#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
10415 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10416 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10417#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
10418 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10419
10420#define RX_DIVIDER_BIT_1_2 0x3
10421#define RX_DIVIDER_BIT_3_4 0xC
10422
10423/* BXT MIPI mode configure */
10424#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
10425#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
10426#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
10427 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10428
10429#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
10430#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
10431#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
10432 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10433
10434#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
10435#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
10436#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
10437 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10438
10439#define BXT_DSI_PLL_CTL _MMIO(0x161000)
10440#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
10441#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10442#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10443#define BXT_DSIC_16X_BY1 (0 << 10)
10444#define BXT_DSIC_16X_BY2 (1 << 10)
10445#define BXT_DSIC_16X_BY3 (2 << 10)
10446#define BXT_DSIC_16X_BY4 (3 << 10)
10447#define BXT_DSIC_16X_MASK (3 << 10)
10448#define BXT_DSIA_16X_BY1 (0 << 8)
10449#define BXT_DSIA_16X_BY2 (1 << 8)
10450#define BXT_DSIA_16X_BY3 (2 << 8)
10451#define BXT_DSIA_16X_BY4 (3 << 8)
10452#define BXT_DSIA_16X_MASK (3 << 8)
10453#define BXT_DSI_FREQ_SEL_SHIFT 8
10454#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
10455
10456#define BXT_DSI_PLL_RATIO_MAX 0x7D
10457#define BXT_DSI_PLL_RATIO_MIN 0x22
10458#define GLK_DSI_PLL_RATIO_MAX 0x6F
10459#define GLK_DSI_PLL_RATIO_MIN 0x22
10460#define BXT_DSI_PLL_RATIO_MASK 0xFF
10461#define BXT_REF_CLOCK_KHZ 19200
10462
10463#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
10464#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
10465#define BXT_DSI_PLL_LOCKED (1 << 30)
10466
10467#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
10468#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
10469#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10470
10471 /* BXT port control */
10472#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
10473#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
10474#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
10475
10476/* ICL DSI MODE control */
10477#define _ICL_DSI_IO_MODECTL_0 0x6B094
10478#define _ICL_DSI_IO_MODECTL_1 0x6B894
10479#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
10480 _ICL_DSI_IO_MODECTL_0, \
10481 _ICL_DSI_IO_MODECTL_1)
10482#define COMBO_PHY_MODE_DSI (1 << 0)
10483
10484/* Display Stream Splitter Control */
10485#define DSS_CTL1 _MMIO(0x67400)
10486#define SPLITTER_ENABLE (1 << 31)
10487#define JOINER_ENABLE (1 << 30)
10488#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
10489#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
10490#define OVERLAP_PIXELS_MASK (0xf << 16)
10491#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
10492#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10493#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10494#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
10495
10496#define DSS_CTL2 _MMIO(0x67404)
10497#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
10498#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
10499#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10500#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10501
10502#define _ICL_PIPE_DSS_CTL1_PB 0x78200
10503#define _ICL_PIPE_DSS_CTL1_PC 0x78400
10504#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10505 _ICL_PIPE_DSS_CTL1_PB, \
10506 _ICL_PIPE_DSS_CTL1_PC)
10507#define BIG_JOINER_ENABLE (1 << 29)
10508#define MASTER_BIG_JOINER_ENABLE (1 << 28)
10509#define VGA_CENTERING_ENABLE (1 << 27)
10510
10511#define _ICL_PIPE_DSS_CTL2_PB 0x78204
10512#define _ICL_PIPE_DSS_CTL2_PC 0x78404
10513#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10514 _ICL_PIPE_DSS_CTL2_PB, \
10515 _ICL_PIPE_DSS_CTL2_PC)
10516
10517#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
10518#define STAP_SELECT (1 << 0)
10519
10520#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
10521#define HS_IO_CTRL_SELECT (1 << 0)
10522
10523#define DPI_ENABLE (1 << 31) /* A + C */
10524#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
10525#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
10526#define DUAL_LINK_MODE_SHIFT 26
10527#define DUAL_LINK_MODE_MASK (1 << 26)
10528#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
10529#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
10530#define DITHERING_ENABLE (1 << 25) /* A + C */
10531#define FLOPPED_HSTX (1 << 23)
10532#define DE_INVERT (1 << 19) /* XXX */
10533#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
10534#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
10535#define AFE_LATCHOUT (1 << 17)
10536#define LP_OUTPUT_HOLD (1 << 16)
10537#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
10538#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
10539#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
10540#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
10541#define CSB_SHIFT 9
10542#define CSB_MASK (3 << 9)
10543#define CSB_20MHZ (0 << 9)
10544#define CSB_10MHZ (1 << 9)
10545#define CSB_40MHZ (2 << 9)
10546#define BANDGAP_MASK (1 << 8)
10547#define BANDGAP_PNW_CIRCUIT (0 << 8)
10548#define BANDGAP_LNC_CIRCUIT (1 << 8)
10549#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
10550#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
10551#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
10552#define TEARING_EFFECT_SHIFT 2 /* A + C */
10553#define TEARING_EFFECT_MASK (3 << 2)
10554#define TEARING_EFFECT_OFF (0 << 2)
10555#define TEARING_EFFECT_DSI (1 << 2)
10556#define TEARING_EFFECT_GPIO (2 << 2)
10557#define LANE_CONFIGURATION_SHIFT 0
10558#define LANE_CONFIGURATION_MASK (3 << 0)
10559#define LANE_CONFIGURATION_4LANE (0 << 0)
10560#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
10561#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
10562
10563#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
10564#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
10565#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10566#define TEARING_EFFECT_DELAY_SHIFT 0
10567#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
10568
10569/* XXX: all bits reserved */
10570#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
10571
10572/* MIPI DSI Controller and D-PHY registers */
10573
10574#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
10575#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
10576#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10577#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
10578#define ULPS_STATE_MASK (3 << 1)
10579#define ULPS_STATE_ENTER (2 << 1)
10580#define ULPS_STATE_EXIT (1 << 1)
10581#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
10582#define DEVICE_READY (1 << 0)
10583
10584#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
10585#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
10586#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10587#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
10588#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
10589#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10590#define TEARING_EFFECT (1 << 31)
10591#define SPL_PKT_SENT_INTERRUPT (1 << 30)
10592#define GEN_READ_DATA_AVAIL (1 << 29)
10593#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
10594#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
10595#define RX_PROT_VIOLATION (1 << 26)
10596#define RX_INVALID_TX_LENGTH (1 << 25)
10597#define ACK_WITH_NO_ERROR (1 << 24)
10598#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
10599#define LP_RX_TIMEOUT (1 << 22)
10600#define HS_TX_TIMEOUT (1 << 21)
10601#define DPI_FIFO_UNDERRUN (1 << 20)
10602#define LOW_CONTENTION (1 << 19)
10603#define HIGH_CONTENTION (1 << 18)
10604#define TXDSI_VC_ID_INVALID (1 << 17)
10605#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
10606#define TXCHECKSUM_ERROR (1 << 15)
10607#define TXECC_MULTIBIT_ERROR (1 << 14)
10608#define TXECC_SINGLE_BIT_ERROR (1 << 13)
10609#define TXFALSE_CONTROL_ERROR (1 << 12)
10610#define RXDSI_VC_ID_INVALID (1 << 11)
10611#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
10612#define RXCHECKSUM_ERROR (1 << 9)
10613#define RXECC_MULTIBIT_ERROR (1 << 8)
10614#define RXECC_SINGLE_BIT_ERROR (1 << 7)
10615#define RXFALSE_CONTROL_ERROR (1 << 6)
10616#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
10617#define RX_LP_TX_SYNC_ERROR (1 << 4)
10618#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
10619#define RXEOT_SYNC_ERROR (1 << 2)
10620#define RXSOT_SYNC_ERROR (1 << 1)
10621#define RXSOT_ERROR (1 << 0)
10622
10623#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
10624#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
10625#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10626#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
10627#define CMD_MODE_NOT_SUPPORTED (0 << 13)
10628#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
10629#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
10630#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
10631#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
10632#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
10633#define VID_MODE_FORMAT_MASK (0xf << 7)
10634#define VID_MODE_NOT_SUPPORTED (0 << 7)
10635#define VID_MODE_FORMAT_RGB565 (1 << 7)
10636#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
10637#define VID_MODE_FORMAT_RGB666 (3 << 7)
10638#define VID_MODE_FORMAT_RGB888 (4 << 7)
10639#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
10640#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
10641#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
10642#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
10643#define DATA_LANES_PRG_REG_SHIFT 0
10644#define DATA_LANES_PRG_REG_MASK (7 << 0)
10645
10646#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
10647#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
10648#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10649#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
10650
10651#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
10652#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
10653#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10654#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
10655
10656#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
10657#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
10658#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10659#define TURN_AROUND_TIMEOUT_MASK 0x3f
10660
10661#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
10662#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
10663#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10664#define DEVICE_RESET_TIMER_MASK 0xffff
10665
10666#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
10667#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
10668#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10669#define VERTICAL_ADDRESS_SHIFT 16
10670#define VERTICAL_ADDRESS_MASK (0xffff << 16)
10671#define HORIZONTAL_ADDRESS_SHIFT 0
10672#define HORIZONTAL_ADDRESS_MASK 0xffff
10673
10674#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
10675#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
10676#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10677#define DBI_FIFO_EMPTY_HALF (0 << 0)
10678#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
10679#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
10680
10681/* regs below are bits 15:0 */
10682#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
10683#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
10684#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10685
10686#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
10687#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
10688#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10689
10690#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
10691#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
10692#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10693
10694#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
10695#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
10696#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10697
10698#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
10699#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
10700#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10701
10702#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
10703#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
10704#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10705
10706#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
10707#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
10708#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10709
10710#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
10711#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
10712#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10713
10714/* regs above are bits 15:0 */
10715
10716#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
10717#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
10718#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10719#define DPI_LP_MODE (1 << 6)
10720#define BACKLIGHT_OFF (1 << 5)
10721#define BACKLIGHT_ON (1 << 4)
10722#define COLOR_MODE_OFF (1 << 3)
10723#define COLOR_MODE_ON (1 << 2)
10724#define TURN_ON (1 << 1)
10725#define SHUTDOWN (1 << 0)
10726
10727#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
10728#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
10729#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10730#define COMMAND_BYTE_SHIFT 0
10731#define COMMAND_BYTE_MASK (0x3f << 0)
10732
10733#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
10734#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
10735#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10736#define MASTER_INIT_TIMER_SHIFT 0
10737#define MASTER_INIT_TIMER_MASK (0xffff << 0)
10738
10739#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
10740#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
10741#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
10742 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10743#define MAX_RETURN_PKT_SIZE_SHIFT 0
10744#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
10745
10746#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
10747#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
10748#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10749#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
10750#define DISABLE_VIDEO_BTA (1 << 3)
10751#define IP_TG_CONFIG (1 << 2)
10752#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
10753#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
10754#define VIDEO_MODE_BURST (3 << 0)
10755
10756#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
10757#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
10758#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10759#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
10760#define BXT_DPHY_DEFEATURE_EN (1 << 8)
10761#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
10762#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
10763#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
10764#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
10765#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10766#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
10767#define CLOCKSTOP (1 << 1)
10768#define EOT_DISABLE (1 << 0)
10769
10770#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
10771#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
10772#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10773#define LP_BYTECLK_SHIFT 0
10774#define LP_BYTECLK_MASK (0xffff << 0)
10775
10776#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
10777#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
10778#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10779
10780#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
10781#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
10782#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10783
10784/* bits 31:0 */
10785#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
10786#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
10787#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10788
10789/* bits 31:0 */
10790#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
10791#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
10792#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10793
10794#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
10795#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
10796#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10797#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
10798#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
10799#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10800#define LONG_PACKET_WORD_COUNT_SHIFT 8
10801#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
10802#define SHORT_PACKET_PARAM_SHIFT 8
10803#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
10804#define VIRTUAL_CHANNEL_SHIFT 6
10805#define VIRTUAL_CHANNEL_MASK (3 << 6)
10806#define DATA_TYPE_SHIFT 0
10807#define DATA_TYPE_MASK (0x3f << 0)
10808/* data type values, see include/video/mipi_display.h */
10809
10810#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
10811#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
10812#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10813#define DPI_FIFO_EMPTY (1 << 28)
10814#define DBI_FIFO_EMPTY (1 << 27)
10815#define LP_CTRL_FIFO_EMPTY (1 << 26)
10816#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
10817#define LP_CTRL_FIFO_FULL (1 << 24)
10818#define HS_CTRL_FIFO_EMPTY (1 << 18)
10819#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
10820#define HS_CTRL_FIFO_FULL (1 << 16)
10821#define LP_DATA_FIFO_EMPTY (1 << 10)
10822#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
10823#define LP_DATA_FIFO_FULL (1 << 8)
10824#define HS_DATA_FIFO_EMPTY (1 << 2)
10825#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
10826#define HS_DATA_FIFO_FULL (1 << 0)
10827
10828#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
10829#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
10830#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10831#define DBI_HS_LP_MODE_MASK (1 << 0)
10832#define DBI_LP_MODE (1 << 0)
10833#define DBI_HS_MODE (0 << 0)
10834
10835#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
10836#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
10837#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10838#define EXIT_ZERO_COUNT_SHIFT 24
10839#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
10840#define TRAIL_COUNT_SHIFT 16
10841#define TRAIL_COUNT_MASK (0x1f << 16)
10842#define CLK_ZERO_COUNT_SHIFT 8
10843#define CLK_ZERO_COUNT_MASK (0xff << 8)
10844#define PREPARE_COUNT_SHIFT 0
10845#define PREPARE_COUNT_MASK (0x3f << 0)
10846
10847#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
10848#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
10849#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
10850 _ICL_DSI_T_INIT_MASTER_0,\
10851 _ICL_DSI_T_INIT_MASTER_1)
10852
10853#define _DPHY_CLK_TIMING_PARAM_0 0x162180
10854#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
10855#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10856 _DPHY_CLK_TIMING_PARAM_0,\
10857 _DPHY_CLK_TIMING_PARAM_1)
10858#define _DSI_CLK_TIMING_PARAM_0 0x6b080
10859#define _DSI_CLK_TIMING_PARAM_1 0x6b880
10860#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10861 _DSI_CLK_TIMING_PARAM_0,\
10862 _DSI_CLK_TIMING_PARAM_1)
10863#define CLK_PREPARE_OVERRIDE (1 << 31)
10864#define CLK_PREPARE(x) ((x) << 28)
10865#define CLK_PREPARE_MASK (0x7 << 28)
10866#define CLK_PREPARE_SHIFT 28
10867#define CLK_ZERO_OVERRIDE (1 << 27)
10868#define CLK_ZERO(x) ((x) << 20)
10869#define CLK_ZERO_MASK (0xf << 20)
10870#define CLK_ZERO_SHIFT 20
10871#define CLK_PRE_OVERRIDE (1 << 19)
10872#define CLK_PRE(x) ((x) << 16)
10873#define CLK_PRE_MASK (0x3 << 16)
10874#define CLK_PRE_SHIFT 16
10875#define CLK_POST_OVERRIDE (1 << 15)
10876#define CLK_POST(x) ((x) << 8)
10877#define CLK_POST_MASK (0x7 << 8)
10878#define CLK_POST_SHIFT 8
10879#define CLK_TRAIL_OVERRIDE (1 << 7)
10880#define CLK_TRAIL(x) ((x) << 0)
10881#define CLK_TRAIL_MASK (0xf << 0)
10882#define CLK_TRAIL_SHIFT 0
10883
10884#define _DPHY_DATA_TIMING_PARAM_0 0x162184
10885#define _DPHY_DATA_TIMING_PARAM_1 0x6c184
10886#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10887 _DPHY_DATA_TIMING_PARAM_0,\
10888 _DPHY_DATA_TIMING_PARAM_1)
10889#define _DSI_DATA_TIMING_PARAM_0 0x6B084
10890#define _DSI_DATA_TIMING_PARAM_1 0x6B884
10891#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10892 _DSI_DATA_TIMING_PARAM_0,\
10893 _DSI_DATA_TIMING_PARAM_1)
10894#define HS_PREPARE_OVERRIDE (1 << 31)
10895#define HS_PREPARE(x) ((x) << 24)
10896#define HS_PREPARE_MASK (0x7 << 24)
10897#define HS_PREPARE_SHIFT 24
10898#define HS_ZERO_OVERRIDE (1 << 23)
10899#define HS_ZERO(x) ((x) << 16)
10900#define HS_ZERO_MASK (0xf << 16)
10901#define HS_ZERO_SHIFT 16
10902#define HS_TRAIL_OVERRIDE (1 << 15)
10903#define HS_TRAIL(x) ((x) << 8)
10904#define HS_TRAIL_MASK (0x7 << 8)
10905#define HS_TRAIL_SHIFT 8
10906#define HS_EXIT_OVERRIDE (1 << 7)
10907#define HS_EXIT(x) ((x) << 0)
10908#define HS_EXIT_MASK (0x7 << 0)
10909#define HS_EXIT_SHIFT 0
10910
10911#define _DPHY_TA_TIMING_PARAM_0 0x162188
10912#define _DPHY_TA_TIMING_PARAM_1 0x6c188
10913#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10914 _DPHY_TA_TIMING_PARAM_0,\
10915 _DPHY_TA_TIMING_PARAM_1)
10916#define _DSI_TA_TIMING_PARAM_0 0x6b098
10917#define _DSI_TA_TIMING_PARAM_1 0x6b898
10918#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10919 _DSI_TA_TIMING_PARAM_0,\
10920 _DSI_TA_TIMING_PARAM_1)
10921#define TA_SURE_OVERRIDE (1 << 31)
10922#define TA_SURE(x) ((x) << 16)
10923#define TA_SURE_MASK (0x1f << 16)
10924#define TA_SURE_SHIFT 16
10925#define TA_GO_OVERRIDE (1 << 15)
10926#define TA_GO(x) ((x) << 8)
10927#define TA_GO_MASK (0xf << 8)
10928#define TA_GO_SHIFT 8
10929#define TA_GET_OVERRIDE (1 << 7)
10930#define TA_GET(x) ((x) << 0)
10931#define TA_GET_MASK (0xf << 0)
10932#define TA_GET_SHIFT 0
10933
10934/* DSI transcoder configuration */
10935#define _DSI_TRANS_FUNC_CONF_0 0x6b030
10936#define _DSI_TRANS_FUNC_CONF_1 0x6b830
10937#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
10938 _DSI_TRANS_FUNC_CONF_0,\
10939 _DSI_TRANS_FUNC_CONF_1)
10940#define OP_MODE_MASK (0x3 << 28)
10941#define OP_MODE_SHIFT 28
10942#define CMD_MODE_NO_GATE (0x0 << 28)
10943#define CMD_MODE_TE_GATE (0x1 << 28)
10944#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
10945#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
10946#define LINK_READY (1 << 20)
10947#define PIX_FMT_MASK (0x3 << 16)
10948#define PIX_FMT_SHIFT 16
10949#define PIX_FMT_RGB565 (0x0 << 16)
10950#define PIX_FMT_RGB666_PACKED (0x1 << 16)
10951#define PIX_FMT_RGB666_LOOSE (0x2 << 16)
10952#define PIX_FMT_RGB888 (0x3 << 16)
10953#define PIX_FMT_RGB101010 (0x4 << 16)
10954#define PIX_FMT_RGB121212 (0x5 << 16)
10955#define PIX_FMT_COMPRESSED (0x6 << 16)
10956#define BGR_TRANSMISSION (1 << 15)
10957#define PIX_VIRT_CHAN(x) ((x) << 12)
10958#define PIX_VIRT_CHAN_MASK (0x3 << 12)
10959#define PIX_VIRT_CHAN_SHIFT 12
10960#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
10961#define PIX_BUF_THRESHOLD_SHIFT 10
10962#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
10963#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
10964#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
10965#define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
10966#define CONTINUOUS_CLK_MASK (0x3 << 8)
10967#define CONTINUOUS_CLK_SHIFT 8
10968#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
10969#define CLK_HS_OR_LP (0x2 << 8)
10970#define CLK_HS_CONTINUOUS (0x3 << 8)
10971#define LINK_CALIBRATION_MASK (0x3 << 4)
10972#define LINK_CALIBRATION_SHIFT 4
10973#define CALIBRATION_DISABLED (0x0 << 4)
10974#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
10975#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
10976#define BLANKING_PACKET_ENABLE (1 << 2)
10977#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
10978#define EOTP_DISABLED (1 << 0)
10979
10980#define _DSI_CMD_RXCTL_0 0x6b0d4
10981#define _DSI_CMD_RXCTL_1 0x6b8d4
10982#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
10983 _DSI_CMD_RXCTL_0,\
10984 _DSI_CMD_RXCTL_1)
10985#define READ_UNLOADS_DW (1 << 16)
10986#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
10987#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
10988#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
10989#define RECEIVED_RESET_TRIGGER (1 << 12)
10990#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
10991#define RECEIVED_CRC_WAS_LOST (1 << 10)
10992#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
10993#define NUMBER_RX_PLOAD_DW_SHIFT 0
10994
10995#define _DSI_CMD_TXCTL_0 0x6b0d0
10996#define _DSI_CMD_TXCTL_1 0x6b8d0
10997#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
10998 _DSI_CMD_TXCTL_0,\
10999 _DSI_CMD_TXCTL_1)
11000#define KEEP_LINK_IN_HS (1 << 24)
11001#define FREE_HEADER_CREDIT_MASK (0x1f << 8)
11002#define FREE_HEADER_CREDIT_SHIFT 0x8
11003#define FREE_PLOAD_CREDIT_MASK (0xff << 0)
11004#define FREE_PLOAD_CREDIT_SHIFT 0
11005#define MAX_HEADER_CREDIT 0x10
11006#define MAX_PLOAD_CREDIT 0x40
11007
11008#define _DSI_CMD_TXHDR_0 0x6b100
11009#define _DSI_CMD_TXHDR_1 0x6b900
11010#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
11011 _DSI_CMD_TXHDR_0,\
11012 _DSI_CMD_TXHDR_1)
11013#define PAYLOAD_PRESENT (1 << 31)
11014#define LP_DATA_TRANSFER (1 << 30)
11015#define VBLANK_FENCE (1 << 29)
11016#define PARAM_WC_MASK (0xffff << 8)
11017#define PARAM_WC_LOWER_SHIFT 8
11018#define PARAM_WC_UPPER_SHIFT 16
11019#define VC_MASK (0x3 << 6)
11020#define VC_SHIFT 6
11021#define DT_MASK (0x3f << 0)
11022#define DT_SHIFT 0
11023
11024#define _DSI_CMD_TXPYLD_0 0x6b104
11025#define _DSI_CMD_TXPYLD_1 0x6b904
11026#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
11027 _DSI_CMD_TXPYLD_0,\
11028 _DSI_CMD_TXPYLD_1)
11029
11030#define _DSI_LP_MSG_0 0x6b0d8
11031#define _DSI_LP_MSG_1 0x6b8d8
11032#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
11033 _DSI_LP_MSG_0,\
11034 _DSI_LP_MSG_1)
11035#define LPTX_IN_PROGRESS (1 << 17)
11036#define LINK_IN_ULPS (1 << 16)
11037#define LINK_ULPS_TYPE_LP11 (1 << 8)
11038#define LINK_ENTER_ULPS (1 << 0)
11039
11040/* DSI timeout registers */
11041#define _DSI_HSTX_TO_0 0x6b044
11042#define _DSI_HSTX_TO_1 0x6b844
11043#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
11044 _DSI_HSTX_TO_0,\
11045 _DSI_HSTX_TO_1)
11046#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
11047#define HSTX_TIMEOUT_VALUE_SHIFT 16
11048#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
11049#define HSTX_TIMED_OUT (1 << 0)
11050
11051#define _DSI_LPRX_HOST_TO_0 0x6b048
11052#define _DSI_LPRX_HOST_TO_1 0x6b848
11053#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
11054 _DSI_LPRX_HOST_TO_0,\
11055 _DSI_LPRX_HOST_TO_1)
11056#define LPRX_TIMED_OUT (1 << 16)
11057#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
11058#define LPRX_TIMEOUT_VALUE_SHIFT 0
11059#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
11060
11061#define _DSI_PWAIT_TO_0 0x6b040
11062#define _DSI_PWAIT_TO_1 0x6b840
11063#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
11064 _DSI_PWAIT_TO_0,\
11065 _DSI_PWAIT_TO_1)
11066#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
11067#define PRESET_TIMEOUT_VALUE_SHIFT 16
11068#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
11069#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
11070#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
11071#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
11072
11073#define _DSI_TA_TO_0 0x6b04c
11074#define _DSI_TA_TO_1 0x6b84c
11075#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
11076 _DSI_TA_TO_0,\
11077 _DSI_TA_TO_1)
11078#define TA_TIMED_OUT (1 << 16)
11079#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
11080#define TA_TIMEOUT_VALUE_SHIFT 0
11081#define TA_TIMEOUT_VALUE(x) ((x) << 0)
11082
11083/* bits 31:0 */
11084#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
11085#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
11086#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
11087
11088#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
11089#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
11090#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
11091#define LP_HS_SSW_CNT_SHIFT 16
11092#define LP_HS_SSW_CNT_MASK (0xffff << 16)
11093#define HS_LP_PWR_SW_CNT_SHIFT 0
11094#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
11095
11096#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
11097#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
11098#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
11099#define STOP_STATE_STALL_COUNTER_SHIFT 0
11100#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
11101
11102#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
11103#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
11104#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
11105#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
11106#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
11107#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
11108#define RX_CONTENTION_DETECTED (1 << 0)
11109
11110/* XXX: only pipe A ?!? */
11111#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
11112#define DBI_TYPEC_ENABLE (1 << 31)
11113#define DBI_TYPEC_WIP (1 << 30)
11114#define DBI_TYPEC_OPTION_SHIFT 28
11115#define DBI_TYPEC_OPTION_MASK (3 << 28)
11116#define DBI_TYPEC_FREQ_SHIFT 24
11117#define DBI_TYPEC_FREQ_MASK (0xf << 24)
11118#define DBI_TYPEC_OVERRIDE (1 << 8)
11119#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
11120#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
11121
11122
11123/* MIPI adapter registers */
11124
11125#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
11126#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
11127#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
11128#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
11129#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
11130#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
11131#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
11132#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
11133#define READ_REQUEST_PRIORITY_SHIFT 3
11134#define READ_REQUEST_PRIORITY_MASK (3 << 3)
11135#define READ_REQUEST_PRIORITY_LOW (0 << 3)
11136#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
11137#define RGB_FLIP_TO_BGR (1 << 2)
11138
11139#define BXT_PIPE_SELECT_SHIFT 7
11140#define BXT_PIPE_SELECT_MASK (7 << 7)
11141#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
11142#define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
11143#define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
11144#define GLK_MIPIIO_RESET_RELEASED (1 << 28)
11145#define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
11146#define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
11147#define GLK_LP_WAKE (1 << 22)
11148#define GLK_LP11_LOW_PWR_MODE (1 << 21)
11149#define GLK_LP00_LOW_PWR_MODE (1 << 20)
11150#define GLK_FIREWALL_ENABLE (1 << 16)
11151#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
11152#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
11153#define BXT_DSC_ENABLE (1 << 3)
11154#define BXT_RGB_FLIP (1 << 2)
11155#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
11156#define GLK_MIPIIO_ENABLE (1 << 0)
11157
11158#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
11159#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
11160#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
11161#define DATA_MEM_ADDRESS_SHIFT 5
11162#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
11163#define DATA_VALID (1 << 0)
11164
11165#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
11166#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
11167#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
11168#define DATA_LENGTH_SHIFT 0
11169#define DATA_LENGTH_MASK (0xfffff << 0)
11170
11171#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
11172#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
11173#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
11174#define COMMAND_MEM_ADDRESS_SHIFT 5
11175#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
11176#define AUTO_PWG_ENABLE (1 << 2)
11177#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
11178#define COMMAND_VALID (1 << 0)
11179
11180#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
11181#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
11182#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
11183#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
11184#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
11185
11186#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
11187#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
11188#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
11189
11190#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
11191#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
11192#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
11193#define READ_DATA_VALID(n) (1 << (n))
11194
11195/* MOCS (Memory Object Control State) registers */
11196#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
11197
11198#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
11199#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
11200#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
11201#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
11202#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
11203/* Media decoder 2 MOCS registers */
11204#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
11205
11206#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
11207#define PMFLUSHDONE_LNICRSDROP (1 << 20)
11208#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
11209#define PMFLUSHDONE_LNEBLK (1 << 22)
11210
11211#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
11212
11213/* gamt regs */
11214#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
11215#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
11216#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
11217#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
11218#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
11219
11220#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
11221#define MMCD_PCLA (1 << 31)
11222#define MMCD_HOTSPOT_EN (1 << 27)
11223
11224#define _ICL_PHY_MISC_A 0x64C00
11225#define _ICL_PHY_MISC_B 0x64C04
11226#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
11227 _ICL_PHY_MISC_B)
11228#define ICL_PHY_MISC_MUX_DDID (1 << 28)
11229#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
11230
11231/* Icelake Display Stream Compression Registers */
11232#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
11233#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
11234#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
11235#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
11236#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
11237#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
11238#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11239 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
11240 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
11241#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11242 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
11243 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
11244#define DSC_VBR_ENABLE (1 << 19)
11245#define DSC_422_ENABLE (1 << 18)
11246#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
11247#define DSC_BLOCK_PREDICTION (1 << 16)
11248#define DSC_LINE_BUF_DEPTH_SHIFT 12
11249#define DSC_BPC_SHIFT 8
11250#define DSC_VER_MIN_SHIFT 4
11251#define DSC_VER_MAJ (0x1 << 0)
11252
11253#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
11254#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
11255#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
11256#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
11257#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
11258#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
11259#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11260 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
11261 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
11262#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11263 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
11264 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
11265#define DSC_BPP(bpp) ((bpp) << 0)
11266
11267#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
11268#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
11269#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
11270#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
11271#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
11272#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
11273#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11274 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
11275 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
11276#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11277 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
11278 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
11279#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
11280#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
11281
11282#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
11283#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
11284#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
11285#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
11286#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
11287#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
11288#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11289 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
11290 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
11291#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11292 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
11293 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
11294#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
11295#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
11296
11297#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
11298#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
11299#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
11300#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
11301#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
11302#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
11303#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11304 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
11305 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
11306#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11307 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
11308 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
11309#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
11310#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
11311
11312#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
11313#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
11314#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
11315#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
11316#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
11317#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
11318#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11319 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
11320 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
11321#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11322 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
11323 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
11324#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
11325#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
11326
11327#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
11328#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
11329#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
11330#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
11331#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
11332#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
11333#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11334 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
11335 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
11336#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11337 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
11338 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
11339#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
11340#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
11341#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
11342#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
11343
11344#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
11345#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
11346#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
11347#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
11348#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
11349#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
11350#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11351 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
11352 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
11353#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11354 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
11355 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
11356#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
11357#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
11358
11359#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
11360#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
11361#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
11362#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
11363#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
11364#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
11365#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11366 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11367 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11368#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11369 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11370 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11371#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
11372#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
11373
11374#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
11375#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
11376#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
11377#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
11378#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
11379#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
11380#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11381 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11382 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11383#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11384 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11385 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11386#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
11387#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
11388
11389#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
11390#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
11391#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
11392#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
11393#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
11394#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
11395#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11396 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11397 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11398#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11399 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11400 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11401#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
11402#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
11403#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
11404#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
11405
11406#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
11407#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
11408#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
11409#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
11410#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
11411#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
11412#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11413 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11414 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11415#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11416 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11417 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11418
11419#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
11420#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
11421#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
11422#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
11423#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
11424#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
11425#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11426 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11427 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11428#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11429 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11430 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11431
11432#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
11433#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
11434#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
11435#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
11436#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
11437#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
11438#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11439 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11440 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11441#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11442 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11443 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11444
11445#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
11446#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
11447#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
11448#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
11449#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
11450#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
11451#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11452 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11453 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11454#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11455 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11456 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11457
11458#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
11459#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
11460#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
11461#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
11462#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
11463#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
11464#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11465 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11466 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11467#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11468 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
11469 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
11470
11471#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
11472#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
11473#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
11474#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
11475#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
11476#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
11477#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11478 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
11479 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
11480#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11481 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
11482 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11483#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
11484#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
11485#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
11486
11487/* Icelake Rate Control Buffer Threshold Registers */
11488#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
11489#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
11490#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
11491#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
11492#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
11493#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
11494#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
11495#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
11496#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
11497#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
11498#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
11499#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
11500#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11501 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
11502 _ICL_DSC0_RC_BUF_THRESH_0_PC)
11503#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11504 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
11505 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
11506#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11507 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
11508 _ICL_DSC1_RC_BUF_THRESH_0_PC)
11509#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11510 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
11511 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
11512
11513#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
11514#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
11515#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
11516#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
11517#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
11518#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
11519#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
11520#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
11521#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
11522#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
11523#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
11524#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
11525#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11526 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
11527 _ICL_DSC0_RC_BUF_THRESH_1_PC)
11528#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11529 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
11530 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
11531#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11532 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
11533 _ICL_DSC1_RC_BUF_THRESH_1_PC)
11534#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11535 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
11536 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
11537
11538#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
11539#define MODULAR_FIA_MASK (1 << 4)
11540#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
11541#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
11542#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
11543#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
11544#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
11545
11546#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
11547#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
11548
11549#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
11550#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
11551
11552#endif /* _I915_REG_H_ */
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
30/*
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
35 */
36#define INTEL_GMCH_CTRL 0x52
37#define INTEL_GMCH_VGA_DISABLE (1 << 1)
38
39/* PCI config space */
40
41#define HPLLCC 0xc0 /* 855 only */
42#define GC_CLOCK_CONTROL_MASK (0xf << 0)
43#define GC_CLOCK_133_200 (0 << 0)
44#define GC_CLOCK_100_200 (1 << 0)
45#define GC_CLOCK_100_133 (2 << 0)
46#define GC_CLOCK_166_250 (3 << 0)
47#define GCFGC2 0xda
48#define GCFGC 0xf0 /* 915+ only */
49#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52#define GC_DISPLAY_CLOCK_MASK (7 << 4)
53#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
72#define LBB 0xf4
73
74/* Graphics reset regs */
75#define I965_GDRST 0xc0 /* PCI config register */
76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
80
81#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82#define GEN6_MBC_SNPCR_SHIFT 21
83#define GEN6_MBC_SNPCR_MASK (3<<21)
84#define GEN6_MBC_SNPCR_MAX (0<<21)
85#define GEN6_MBC_SNPCR_MED (1<<21)
86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
89#define GEN6_GDRST 0x941c
90#define GEN6_GRDOM_FULL (1 << 0)
91#define GEN6_GRDOM_RENDER (1 << 1)
92#define GEN6_GRDOM_MEDIA (1 << 2)
93#define GEN6_GRDOM_BLT (1 << 3)
94
95/* VGA stuff */
96
97#define VGA_ST01_MDA 0x3ba
98#define VGA_ST01_CGA 0x3da
99
100#define VGA_MSR_WRITE 0x3c2
101#define VGA_MSR_READ 0x3cc
102#define VGA_MSR_MEM_EN (1<<1)
103#define VGA_MSR_CGA_MODE (1<<0)
104
105#define VGA_SR_INDEX 0x3c4
106#define VGA_SR_DATA 0x3c5
107
108#define VGA_AR_INDEX 0x3c0
109#define VGA_AR_VID_EN (1<<5)
110#define VGA_AR_DATA_WRITE 0x3c0
111#define VGA_AR_DATA_READ 0x3c1
112
113#define VGA_GR_INDEX 0x3ce
114#define VGA_GR_DATA 0x3cf
115/* GR05 */
116#define VGA_GR_MEM_READ_MODE_SHIFT 3
117#define VGA_GR_MEM_READ_MODE_PLANE 1
118/* GR06 */
119#define VGA_GR_MEM_MODE_MASK 0xc
120#define VGA_GR_MEM_MODE_SHIFT 2
121#define VGA_GR_MEM_A0000_AFFFF 0
122#define VGA_GR_MEM_A0000_BFFFF 1
123#define VGA_GR_MEM_B0000_B7FFF 2
124#define VGA_GR_MEM_B0000_BFFFF 3
125
126#define VGA_DACMASK 0x3c6
127#define VGA_DACRX 0x3c7
128#define VGA_DACWX 0x3c8
129#define VGA_DACDATA 0x3c9
130
131#define VGA_CR_INDEX_MDA 0x3b4
132#define VGA_CR_DATA_MDA 0x3b5
133#define VGA_CR_INDEX_CGA 0x3d4
134#define VGA_CR_DATA_CGA 0x3d5
135
136/*
137 * Memory interface instructions used by the kernel
138 */
139#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
140
141#define MI_NOOP MI_INSTR(0, 0)
142#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
143#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
144#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
145#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
146#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
147#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
148#define MI_FLUSH MI_INSTR(0x04, 0)
149#define MI_READ_FLUSH (1 << 0)
150#define MI_EXE_FLUSH (1 << 1)
151#define MI_NO_WRITE_FLUSH (1 << 2)
152#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
153#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
154#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
155#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
157#define MI_SUSPEND_FLUSH_EN (1<<0)
158#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
159#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
160#define MI_OVERLAY_CONTINUE (0x0<<21)
161#define MI_OVERLAY_ON (0x1<<21)
162#define MI_OVERLAY_OFF (0x2<<21)
163#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
164#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
165#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
166#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
167#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
168#define MI_MM_SPACE_GTT (1<<8)
169#define MI_MM_SPACE_PHYSICAL (0<<8)
170#define MI_SAVE_EXT_STATE_EN (1<<3)
171#define MI_RESTORE_EXT_STATE_EN (1<<2)
172#define MI_FORCE_RESTORE (1<<1)
173#define MI_RESTORE_INHIBIT (1<<0)
174#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
175#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
176#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
177#define MI_STORE_DWORD_INDEX_SHIFT 2
178/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
180 * simply ignores the register load under certain conditions.
181 * - One can actually load arbitrary many arbitrary registers: Simply issue x
182 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
183 */
184#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
185#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
186#define MI_INVALIDATE_TLB (1<<18)
187#define MI_INVALIDATE_BSD (1<<7)
188#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
189#define MI_BATCH_NON_SECURE (1)
190#define MI_BATCH_NON_SECURE_I965 (1<<8)
191#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
192#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
193#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
194#define MI_SEMAPHORE_UPDATE (1<<21)
195#define MI_SEMAPHORE_COMPARE (1<<20)
196#define MI_SEMAPHORE_REGISTER (1<<18)
197/*
198 * 3D instructions used by the kernel
199 */
200#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201
202#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
203#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
204#define SC_UPDATE_SCISSOR (0x1<<1)
205#define SC_ENABLE_MASK (0x1<<0)
206#define SC_ENABLE (0x1<<0)
207#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
208#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
209#define SCI_YMIN_MASK (0xffff<<16)
210#define SCI_XMIN_MASK (0xffff<<0)
211#define SCI_YMAX_MASK (0xffff<<16)
212#define SCI_XMAX_MASK (0xffff<<0)
213#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
214#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
215#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
216#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
217#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
218#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
219#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
220#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
221#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
222#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
223#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
224#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
225#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
226#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
227#define BLT_DEPTH_8 (0<<24)
228#define BLT_DEPTH_16_565 (1<<24)
229#define BLT_DEPTH_16_1555 (2<<24)
230#define BLT_DEPTH_32 (3<<24)
231#define BLT_ROP_GXCOPY (0xcc<<16)
232#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
233#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
234#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
235#define ASYNC_FLIP (1<<22)
236#define DISPLAY_PLANE_A (0<<20)
237#define DISPLAY_PLANE_B (1<<20)
238#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
239#define PIPE_CONTROL_QW_WRITE (1<<14)
240#define PIPE_CONTROL_DEPTH_STALL (1<<13)
241#define PIPE_CONTROL_WC_FLUSH (1<<12)
242#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
243#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
244#define PIPE_CONTROL_ISP_DIS (1<<9)
245#define PIPE_CONTROL_NOTIFY (1<<8)
246#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
247#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
248
249
250/*
251 * Reset registers
252 */
253#define DEBUG_RESET_I830 0x6070
254#define DEBUG_RESET_FULL (1<<7)
255#define DEBUG_RESET_RENDER (1<<8)
256#define DEBUG_RESET_DISPLAY (1<<9)
257
258
259/*
260 * Fence registers
261 */
262#define FENCE_REG_830_0 0x2000
263#define FENCE_REG_945_8 0x3000
264#define I830_FENCE_START_MASK 0x07f80000
265#define I830_FENCE_TILING_Y_SHIFT 12
266#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
267#define I830_FENCE_PITCH_SHIFT 4
268#define I830_FENCE_REG_VALID (1<<0)
269#define I915_FENCE_MAX_PITCH_VAL 4
270#define I830_FENCE_MAX_PITCH_VAL 6
271#define I830_FENCE_MAX_SIZE_VAL (1<<8)
272
273#define I915_FENCE_START_MASK 0x0ff00000
274#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
275
276#define FENCE_REG_965_0 0x03000
277#define I965_FENCE_PITCH_SHIFT 2
278#define I965_FENCE_TILING_Y_SHIFT 1
279#define I965_FENCE_REG_VALID (1<<0)
280#define I965_FENCE_MAX_PITCH_VAL 0x0400
281
282#define FENCE_REG_SANDYBRIDGE_0 0x100000
283#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
284
285/*
286 * Instruction and interrupt control regs
287 */
288#define PGTBL_ER 0x02024
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define BLT_RING_BASE 0x22000
293#define RING_TAIL(base) ((base)+0x30)
294#define RING_HEAD(base) ((base)+0x34)
295#define RING_START(base) ((base)+0x38)
296#define RING_CTL(base) ((base)+0x3c)
297#define RING_SYNC_0(base) ((base)+0x40)
298#define RING_SYNC_1(base) ((base)+0x44)
299#define RING_MAX_IDLE(base) ((base)+0x54)
300#define RING_HWS_PGA(base) ((base)+0x80)
301#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
302#define RENDER_HWS_PGA_GEN7 (0x04080)
303#define BSD_HWS_PGA_GEN7 (0x04180)
304#define BLT_HWS_PGA_GEN7 (0x04280)
305#define RING_ACTHD(base) ((base)+0x74)
306#define RING_NOPID(base) ((base)+0x94)
307#define RING_IMR(base) ((base)+0xa8)
308#define TAIL_ADDR 0x001FFFF8
309#define HEAD_WRAP_COUNT 0xFFE00000
310#define HEAD_WRAP_ONE 0x00200000
311#define HEAD_ADDR 0x001FFFFC
312#define RING_NR_PAGES 0x001FF000
313#define RING_REPORT_MASK 0x00000006
314#define RING_REPORT_64K 0x00000002
315#define RING_REPORT_128K 0x00000004
316#define RING_NO_REPORT 0x00000000
317#define RING_VALID_MASK 0x00000001
318#define RING_VALID 0x00000001
319#define RING_INVALID 0x00000000
320#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
321#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
322#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
323#if 0
324#define PRB0_TAIL 0x02030
325#define PRB0_HEAD 0x02034
326#define PRB0_START 0x02038
327#define PRB0_CTL 0x0203c
328#define PRB1_TAIL 0x02040 /* 915+ only */
329#define PRB1_HEAD 0x02044 /* 915+ only */
330#define PRB1_START 0x02048 /* 915+ only */
331#define PRB1_CTL 0x0204c /* 915+ only */
332#endif
333#define IPEIR_I965 0x02064
334#define IPEHR_I965 0x02068
335#define INSTDONE_I965 0x0206c
336#define INSTPS 0x02070 /* 965+ only */
337#define INSTDONE1 0x0207c /* 965+ only */
338#define ACTHD_I965 0x02074
339#define HWS_PGA 0x02080
340#define HWS_ADDRESS_MASK 0xfffff000
341#define HWS_START_ADDRESS_SHIFT 4
342#define PWRCTXA 0x2088 /* 965GM+ only */
343#define PWRCTX_EN (1<<0)
344#define IPEIR 0x02088
345#define IPEHR 0x0208c
346#define INSTDONE 0x02090
347#define NOPID 0x02094
348#define HWSTAM 0x02098
349#define VCS_INSTDONE 0x1206C
350#define VCS_IPEIR 0x12064
351#define VCS_IPEHR 0x12068
352#define VCS_ACTHD 0x12074
353#define BCS_INSTDONE 0x2206C
354#define BCS_IPEIR 0x22064
355#define BCS_IPEHR 0x22068
356#define BCS_ACTHD 0x22074
357
358#define ERROR_GEN6 0x040a0
359
360/* GM45+ chicken bits -- debug workaround bits that may be required
361 * for various sorts of correct behavior. The top 16 bits of each are
362 * the enables for writing to the corresponding low bit.
363 */
364#define _3D_CHICKEN 0x02084
365#define _3D_CHICKEN2 0x0208c
366/* Disables pipelining of read flushes past the SF-WIZ interface.
367 * Required on all Ironlake steppings according to the B-Spec, but the
368 * particular danger of not doing so is not specified.
369 */
370# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
371#define _3D_CHICKEN3 0x02090
372
373#define MI_MODE 0x0209c
374# define VS_TIMER_DISPATCH (1 << 6)
375# define MI_FLUSH_ENABLE (1 << 11)
376
377#define GFX_MODE 0x02520
378#define GFX_MODE_GEN7 0x0229c
379#define GFX_RUN_LIST_ENABLE (1<<15)
380#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
381#define GFX_SURFACE_FAULT_ENABLE (1<<12)
382#define GFX_REPLAY_MODE (1<<11)
383#define GFX_PSMI_GRANULARITY (1<<10)
384#define GFX_PPGTT_ENABLE (1<<9)
385
386#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
387#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
388
389#define SCPD0 0x0209c /* 915+ only */
390#define IER 0x020a0
391#define IIR 0x020a4
392#define IMR 0x020a8
393#define ISR 0x020ac
394#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
395#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
396#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
397#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
398#define I915_HWB_OOM_INTERRUPT (1<<13)
399#define I915_SYNC_STATUS_INTERRUPT (1<<12)
400#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
401#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
402#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
403#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
404#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
405#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
406#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
407#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
408#define I915_DEBUG_INTERRUPT (1<<2)
409#define I915_USER_INTERRUPT (1<<1)
410#define I915_ASLE_INTERRUPT (1<<0)
411#define I915_BSD_USER_INTERRUPT (1<<25)
412#define EIR 0x020b0
413#define EMR 0x020b4
414#define ESR 0x020b8
415#define GM45_ERROR_PAGE_TABLE (1<<5)
416#define GM45_ERROR_MEM_PRIV (1<<4)
417#define I915_ERROR_PAGE_TABLE (1<<4)
418#define GM45_ERROR_CP_PRIV (1<<3)
419#define I915_ERROR_MEMORY_REFRESH (1<<1)
420#define I915_ERROR_INSTRUCTION (1<<0)
421#define INSTPM 0x020c0
422#define INSTPM_SELF_EN (1<<12) /* 915GM only */
423#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
424 will not assert AGPBUSY# and will only
425 be delivered when out of C3. */
426#define ACTHD 0x020c8
427#define FW_BLC 0x020d8
428#define FW_BLC2 0x020dc
429#define FW_BLC_SELF 0x020e0 /* 915+ only */
430#define FW_BLC_SELF_EN_MASK (1<<31)
431#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
432#define FW_BLC_SELF_EN (1<<15) /* 945 only */
433#define MM_BURST_LENGTH 0x00700000
434#define MM_FIFO_WATERMARK 0x0001F000
435#define LM_BURST_LENGTH 0x00000700
436#define LM_FIFO_WATERMARK 0x0000001F
437#define MI_ARB_STATE 0x020e4 /* 915+ only */
438#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
439
440/* Make render/texture TLB fetches lower priorty than associated data
441 * fetches. This is not turned on by default
442 */
443#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
444
445/* Isoch request wait on GTT enable (Display A/B/C streams).
446 * Make isoch requests stall on the TLB update. May cause
447 * display underruns (test mode only)
448 */
449#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
450
451/* Block grant count for isoch requests when block count is
452 * set to a finite value.
453 */
454#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
455#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
456#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
457#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
458#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
459
460/* Enable render writes to complete in C2/C3/C4 power states.
461 * If this isn't enabled, render writes are prevented in low
462 * power states. That seems bad to me.
463 */
464#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
465
466/* This acknowledges an async flip immediately instead
467 * of waiting for 2TLB fetches.
468 */
469#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
470
471/* Enables non-sequential data reads through arbiter
472 */
473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
474
475/* Disable FSB snooping of cacheable write cycles from binner/render
476 * command stream
477 */
478#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
479
480/* Arbiter time slice for non-isoch streams */
481#define MI_ARB_TIME_SLICE_MASK (7 << 5)
482#define MI_ARB_TIME_SLICE_1 (0 << 5)
483#define MI_ARB_TIME_SLICE_2 (1 << 5)
484#define MI_ARB_TIME_SLICE_4 (2 << 5)
485#define MI_ARB_TIME_SLICE_6 (3 << 5)
486#define MI_ARB_TIME_SLICE_8 (4 << 5)
487#define MI_ARB_TIME_SLICE_10 (5 << 5)
488#define MI_ARB_TIME_SLICE_14 (6 << 5)
489#define MI_ARB_TIME_SLICE_16 (7 << 5)
490
491/* Low priority grace period page size */
492#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
493#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
494
495/* Disable display A/B trickle feed */
496#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
497
498/* Set display plane priority */
499#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
500#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
501
502#define CACHE_MODE_0 0x02120 /* 915+ only */
503#define CM0_MASK_SHIFT 16
504#define CM0_IZ_OPT_DISABLE (1<<6)
505#define CM0_ZR_OPT_DISABLE (1<<5)
506#define CM0_DEPTH_EVICT_DISABLE (1<<4)
507#define CM0_COLOR_EVICT_DISABLE (1<<3)
508#define CM0_DEPTH_WRITE_DISABLE (1<<1)
509#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
510#define BB_ADDR 0x02140 /* 8 bytes */
511#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
512#define ECOSKPD 0x021d0
513#define ECO_GATING_CX_ONLY (1<<3)
514#define ECO_FLIP_DONE (1<<0)
515
516/* GEN6 interrupt control */
517#define GEN6_RENDER_HWSTAM 0x2098
518#define GEN6_RENDER_IMR 0x20a8
519#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
520#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
521#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
522#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
523#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
524#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
525#define GEN6_RENDER_SYNC_STATUS (1 << 2)
526#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
527#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
528
529#define GEN6_BLITTER_HWSTAM 0x22098
530#define GEN6_BLITTER_IMR 0x220a8
531#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
532#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
533#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
534#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
535
536#define GEN6_BLITTER_ECOSKPD 0x221d0
537#define GEN6_BLITTER_LOCK_SHIFT 16
538#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
539
540#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
541#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
542#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
543#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
544#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
545
546#define GEN6_BSD_HWSTAM 0x12098
547#define GEN6_BSD_IMR 0x120a8
548#define GEN6_BSD_USER_INTERRUPT (1 << 12)
549
550#define GEN6_BSD_RNCID 0x12198
551
552/*
553 * Framebuffer compression (915+ only)
554 */
555
556#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
557#define FBC_LL_BASE 0x03204 /* 4k page aligned */
558#define FBC_CONTROL 0x03208
559#define FBC_CTL_EN (1<<31)
560#define FBC_CTL_PERIODIC (1<<30)
561#define FBC_CTL_INTERVAL_SHIFT (16)
562#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
563#define FBC_CTL_C3_IDLE (1<<13)
564#define FBC_CTL_STRIDE_SHIFT (5)
565#define FBC_CTL_FENCENO (1<<0)
566#define FBC_COMMAND 0x0320c
567#define FBC_CMD_COMPRESS (1<<0)
568#define FBC_STATUS 0x03210
569#define FBC_STAT_COMPRESSING (1<<31)
570#define FBC_STAT_COMPRESSED (1<<30)
571#define FBC_STAT_MODIFIED (1<<29)
572#define FBC_STAT_CURRENT_LINE (1<<0)
573#define FBC_CONTROL2 0x03214
574#define FBC_CTL_FENCE_DBL (0<<4)
575#define FBC_CTL_IDLE_IMM (0<<2)
576#define FBC_CTL_IDLE_FULL (1<<2)
577#define FBC_CTL_IDLE_LINE (2<<2)
578#define FBC_CTL_IDLE_DEBUG (3<<2)
579#define FBC_CTL_CPU_FENCE (1<<1)
580#define FBC_CTL_PLANEA (0<<0)
581#define FBC_CTL_PLANEB (1<<0)
582#define FBC_FENCE_OFF 0x0321b
583#define FBC_TAG 0x03300
584
585#define FBC_LL_SIZE (1536)
586
587/* Framebuffer compression for GM45+ */
588#define DPFC_CB_BASE 0x3200
589#define DPFC_CONTROL 0x3208
590#define DPFC_CTL_EN (1<<31)
591#define DPFC_CTL_PLANEA (0<<30)
592#define DPFC_CTL_PLANEB (1<<30)
593#define DPFC_CTL_FENCE_EN (1<<29)
594#define DPFC_CTL_PERSISTENT_MODE (1<<25)
595#define DPFC_SR_EN (1<<10)
596#define DPFC_CTL_LIMIT_1X (0<<6)
597#define DPFC_CTL_LIMIT_2X (1<<6)
598#define DPFC_CTL_LIMIT_4X (2<<6)
599#define DPFC_RECOMP_CTL 0x320c
600#define DPFC_RECOMP_STALL_EN (1<<27)
601#define DPFC_RECOMP_STALL_WM_SHIFT (16)
602#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
603#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
604#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
605#define DPFC_STATUS 0x3210
606#define DPFC_INVAL_SEG_SHIFT (16)
607#define DPFC_INVAL_SEG_MASK (0x07ff0000)
608#define DPFC_COMP_SEG_SHIFT (0)
609#define DPFC_COMP_SEG_MASK (0x000003ff)
610#define DPFC_STATUS2 0x3214
611#define DPFC_FENCE_YOFF 0x3218
612#define DPFC_CHICKEN 0x3224
613#define DPFC_HT_MODIFY (1<<31)
614
615/* Framebuffer compression for Ironlake */
616#define ILK_DPFC_CB_BASE 0x43200
617#define ILK_DPFC_CONTROL 0x43208
618/* The bit 28-8 is reserved */
619#define DPFC_RESERVED (0x1FFFFF00)
620#define ILK_DPFC_RECOMP_CTL 0x4320c
621#define ILK_DPFC_STATUS 0x43210
622#define ILK_DPFC_FENCE_YOFF 0x43218
623#define ILK_DPFC_CHICKEN 0x43224
624#define ILK_FBC_RT_BASE 0x2128
625#define ILK_FBC_RT_VALID (1<<0)
626
627#define ILK_DISPLAY_CHICKEN1 0x42000
628#define ILK_FBCQ_DIS (1<<22)
629#define ILK_PABSTRETCH_DIS (1<<21)
630
631
632/*
633 * Framebuffer compression for Sandybridge
634 *
635 * The following two registers are of type GTTMMADR
636 */
637#define SNB_DPFC_CTL_SA 0x100100
638#define SNB_CPU_FENCE_ENABLE (1<<29)
639#define DPFC_CPU_FENCE_OFFSET 0x100104
640
641
642/*
643 * GPIO regs
644 */
645#define GPIOA 0x5010
646#define GPIOB 0x5014
647#define GPIOC 0x5018
648#define GPIOD 0x501c
649#define GPIOE 0x5020
650#define GPIOF 0x5024
651#define GPIOG 0x5028
652#define GPIOH 0x502c
653# define GPIO_CLOCK_DIR_MASK (1 << 0)
654# define GPIO_CLOCK_DIR_IN (0 << 1)
655# define GPIO_CLOCK_DIR_OUT (1 << 1)
656# define GPIO_CLOCK_VAL_MASK (1 << 2)
657# define GPIO_CLOCK_VAL_OUT (1 << 3)
658# define GPIO_CLOCK_VAL_IN (1 << 4)
659# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
660# define GPIO_DATA_DIR_MASK (1 << 8)
661# define GPIO_DATA_DIR_IN (0 << 9)
662# define GPIO_DATA_DIR_OUT (1 << 9)
663# define GPIO_DATA_VAL_MASK (1 << 10)
664# define GPIO_DATA_VAL_OUT (1 << 11)
665# define GPIO_DATA_VAL_IN (1 << 12)
666# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
667
668#define GMBUS0 0x5100 /* clock/port select */
669#define GMBUS_RATE_100KHZ (0<<8)
670#define GMBUS_RATE_50KHZ (1<<8)
671#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
672#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
673#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
674#define GMBUS_PORT_DISABLED 0
675#define GMBUS_PORT_SSC 1
676#define GMBUS_PORT_VGADDC 2
677#define GMBUS_PORT_PANEL 3
678#define GMBUS_PORT_DPC 4 /* HDMIC */
679#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
680 /* 6 reserved */
681#define GMBUS_PORT_DPD 7 /* HDMID */
682#define GMBUS_NUM_PORTS 8
683#define GMBUS1 0x5104 /* command/status */
684#define GMBUS_SW_CLR_INT (1<<31)
685#define GMBUS_SW_RDY (1<<30)
686#define GMBUS_ENT (1<<29) /* enable timeout */
687#define GMBUS_CYCLE_NONE (0<<25)
688#define GMBUS_CYCLE_WAIT (1<<25)
689#define GMBUS_CYCLE_INDEX (2<<25)
690#define GMBUS_CYCLE_STOP (4<<25)
691#define GMBUS_BYTE_COUNT_SHIFT 16
692#define GMBUS_SLAVE_INDEX_SHIFT 8
693#define GMBUS_SLAVE_ADDR_SHIFT 1
694#define GMBUS_SLAVE_READ (1<<0)
695#define GMBUS_SLAVE_WRITE (0<<0)
696#define GMBUS2 0x5108 /* status */
697#define GMBUS_INUSE (1<<15)
698#define GMBUS_HW_WAIT_PHASE (1<<14)
699#define GMBUS_STALL_TIMEOUT (1<<13)
700#define GMBUS_INT (1<<12)
701#define GMBUS_HW_RDY (1<<11)
702#define GMBUS_SATOER (1<<10)
703#define GMBUS_ACTIVE (1<<9)
704#define GMBUS3 0x510c /* data buffer bytes 3-0 */
705#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
706#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
707#define GMBUS_NAK_EN (1<<3)
708#define GMBUS_IDLE_EN (1<<2)
709#define GMBUS_HW_WAIT_EN (1<<1)
710#define GMBUS_HW_RDY_EN (1<<0)
711#define GMBUS5 0x5120 /* byte index */
712#define GMBUS_2BYTE_INDEX_EN (1<<31)
713
714/*
715 * Clock control & power management
716 */
717
718#define VGA0 0x6000
719#define VGA1 0x6004
720#define VGA_PD 0x6010
721#define VGA0_PD_P2_DIV_4 (1 << 7)
722#define VGA0_PD_P1_DIV_2 (1 << 5)
723#define VGA0_PD_P1_SHIFT 0
724#define VGA0_PD_P1_MASK (0x1f << 0)
725#define VGA1_PD_P2_DIV_4 (1 << 15)
726#define VGA1_PD_P1_DIV_2 (1 << 13)
727#define VGA1_PD_P1_SHIFT 8
728#define VGA1_PD_P1_MASK (0x1f << 8)
729#define _DPLL_A 0x06014
730#define _DPLL_B 0x06018
731#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
732#define DPLL_VCO_ENABLE (1 << 31)
733#define DPLL_DVO_HIGH_SPEED (1 << 30)
734#define DPLL_SYNCLOCK_ENABLE (1 << 29)
735#define DPLL_VGA_MODE_DIS (1 << 28)
736#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
737#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
738#define DPLL_MODE_MASK (3 << 26)
739#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
740#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
741#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
742#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
743#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
744#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
745#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
746
747#define SRX_INDEX 0x3c4
748#define SRX_DATA 0x3c5
749#define SR01 1
750#define SR01_SCREEN_OFF (1<<5)
751
752#define PPCR 0x61204
753#define PPCR_ON (1<<0)
754
755#define DVOB 0x61140
756#define DVOB_ON (1<<31)
757#define DVOC 0x61160
758#define DVOC_ON (1<<31)
759#define LVDS 0x61180
760#define LVDS_ON (1<<31)
761
762/* Scratch pad debug 0 reg:
763 */
764#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
765/*
766 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
767 * this field (only one bit may be set).
768 */
769#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
770#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
771#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
772/* i830, required in DVO non-gang */
773#define PLL_P2_DIVIDE_BY_4 (1 << 23)
774#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
775#define PLL_REF_INPUT_DREFCLK (0 << 13)
776#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
777#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
778#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
779#define PLL_REF_INPUT_MASK (3 << 13)
780#define PLL_LOAD_PULSE_PHASE_SHIFT 9
781/* Ironlake */
782# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
783# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
784# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
785# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
786# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
787
788/*
789 * Parallel to Serial Load Pulse phase selection.
790 * Selects the phase for the 10X DPLL clock for the PCIe
791 * digital display port. The range is 4 to 13; 10 or more
792 * is just a flip delay. The default is 6
793 */
794#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
795#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
796/*
797 * SDVO multiplier for 945G/GM. Not used on 965.
798 */
799#define SDVO_MULTIPLIER_MASK 0x000000ff
800#define SDVO_MULTIPLIER_SHIFT_HIRES 4
801#define SDVO_MULTIPLIER_SHIFT_VGA 0
802#define _DPLL_A_MD 0x0601c /* 965+ only */
803/*
804 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
805 *
806 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
807 */
808#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
809#define DPLL_MD_UDI_DIVIDER_SHIFT 24
810/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
811#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
812#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
813/*
814 * SDVO/UDI pixel multiplier.
815 *
816 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
817 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
818 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
819 * dummy bytes in the datastream at an increased clock rate, with both sides of
820 * the link knowing how many bytes are fill.
821 *
822 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
823 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
824 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
825 * through an SDVO command.
826 *
827 * This register field has values of multiplication factor minus 1, with
828 * a maximum multiplier of 5 for SDVO.
829 */
830#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
831#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
832/*
833 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
834 * This best be set to the default value (3) or the CRT won't work. No,
835 * I don't entirely understand what this does...
836 */
837#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
838#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
839#define _DPLL_B_MD 0x06020 /* 965+ only */
840#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
841#define _FPA0 0x06040
842#define _FPA1 0x06044
843#define _FPB0 0x06048
844#define _FPB1 0x0604c
845#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
846#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
847#define FP_N_DIV_MASK 0x003f0000
848#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
849#define FP_N_DIV_SHIFT 16
850#define FP_M1_DIV_MASK 0x00003f00
851#define FP_M1_DIV_SHIFT 8
852#define FP_M2_DIV_MASK 0x0000003f
853#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
854#define FP_M2_DIV_SHIFT 0
855#define DPLL_TEST 0x606c
856#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
857#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
858#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
859#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
860#define DPLLB_TEST_N_BYPASS (1 << 19)
861#define DPLLB_TEST_M_BYPASS (1 << 18)
862#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
863#define DPLLA_TEST_N_BYPASS (1 << 3)
864#define DPLLA_TEST_M_BYPASS (1 << 2)
865#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
866#define D_STATE 0x6104
867#define DSTATE_GFX_RESET_I830 (1<<6)
868#define DSTATE_PLL_D3_OFF (1<<3)
869#define DSTATE_GFX_CLOCK_GATING (1<<1)
870#define DSTATE_DOT_CLOCK_GATING (1<<0)
871#define DSPCLK_GATE_D 0x6200
872# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
873# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
874# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
875# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
876# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
877# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
878# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
879# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
880# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
881# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
882# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
883# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
884# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
885# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
886# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
887# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
888# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
889# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
890# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
891# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
892# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
893# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
894# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
895# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
896# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
897# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
898# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
899# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
900/**
901 * This bit must be set on the 830 to prevent hangs when turning off the
902 * overlay scaler.
903 */
904# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
905# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
906# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
907# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
908# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
909
910#define RENCLK_GATE_D1 0x6204
911# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
912# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
913# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
914# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
915# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
916# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
917# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
918# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
919# define MAG_CLOCK_GATE_DISABLE (1 << 5)
920/** This bit must be unset on 855,865 */
921# define MECI_CLOCK_GATE_DISABLE (1 << 4)
922# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
923# define MEC_CLOCK_GATE_DISABLE (1 << 2)
924# define MECO_CLOCK_GATE_DISABLE (1 << 1)
925/** This bit must be set on 855,865. */
926# define SV_CLOCK_GATE_DISABLE (1 << 0)
927# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
928# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
929# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
930# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
931# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
932# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
933# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
934# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
935# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
936# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
937# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
938# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
939# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
940# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
941# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
942# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
943# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
944
945# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
946/** This bit must always be set on 965G/965GM */
947# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
948# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
949# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
950# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
951# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
952# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
953/** This bit must always be set on 965G */
954# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
955# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
956# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
957# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
958# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
959# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
960# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
961# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
962# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
963# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
964# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
965# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
966# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
967# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
968# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
969# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
970# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
971# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
972# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
973
974#define RENCLK_GATE_D2 0x6208
975#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
976#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
977#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
978#define RAMCLK_GATE_D 0x6210 /* CRL only */
979#define DEUC 0x6214 /* CRL only */
980
981/*
982 * Palette regs
983 */
984
985#define _PALETTE_A 0x0a000
986#define _PALETTE_B 0x0a800
987#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
988
989/* MCH MMIO space */
990
991/*
992 * MCHBAR mirror.
993 *
994 * This mirrors the MCHBAR MMIO space whose location is determined by
995 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
996 * every way. It is not accessible from the CP register read instructions.
997 *
998 */
999#define MCHBAR_MIRROR_BASE 0x10000
1000
1001#define MCHBAR_MIRROR_BASE_SNB 0x140000
1002
1003/** 915-945 and GM965 MCH register controlling DRAM channel access */
1004#define DCC 0x10200
1005#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1006#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1007#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1008#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1009#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1010#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1011
1012/** Pineview MCH register contains DDR3 setting */
1013#define CSHRDDR3CTL 0x101a8
1014#define CSHRDDR3CTL_DDR3 (1 << 2)
1015
1016/** 965 MCH register controlling DRAM channel configuration */
1017#define C0DRB3 0x10206
1018#define C1DRB3 0x10606
1019
1020/* Clocking configuration register */
1021#define CLKCFG 0x10c00
1022#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1023#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1024#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1025#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1026#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1027#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1028/* Note, below two are guess */
1029#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1030#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1031#define CLKCFG_FSB_MASK (7 << 0)
1032#define CLKCFG_MEM_533 (1 << 4)
1033#define CLKCFG_MEM_667 (2 << 4)
1034#define CLKCFG_MEM_800 (3 << 4)
1035#define CLKCFG_MEM_MASK (7 << 4)
1036
1037#define TSC1 0x11001
1038#define TSE (1<<0)
1039#define TR1 0x11006
1040#define TSFS 0x11020
1041#define TSFS_SLOPE_MASK 0x0000ff00
1042#define TSFS_SLOPE_SHIFT 8
1043#define TSFS_INTR_MASK 0x000000ff
1044
1045#define CRSTANDVID 0x11100
1046#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1047#define PXVFREQ_PX_MASK 0x7f000000
1048#define PXVFREQ_PX_SHIFT 24
1049#define VIDFREQ_BASE 0x11110
1050#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1051#define VIDFREQ2 0x11114
1052#define VIDFREQ3 0x11118
1053#define VIDFREQ4 0x1111c
1054#define VIDFREQ_P0_MASK 0x1f000000
1055#define VIDFREQ_P0_SHIFT 24
1056#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1057#define VIDFREQ_P0_CSCLK_SHIFT 20
1058#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1059#define VIDFREQ_P0_CRCLK_SHIFT 16
1060#define VIDFREQ_P1_MASK 0x00001f00
1061#define VIDFREQ_P1_SHIFT 8
1062#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1063#define VIDFREQ_P1_CSCLK_SHIFT 4
1064#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1065#define INTTOEXT_BASE_ILK 0x11300
1066#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1067#define INTTOEXT_MAP3_SHIFT 24
1068#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1069#define INTTOEXT_MAP2_SHIFT 16
1070#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1071#define INTTOEXT_MAP1_SHIFT 8
1072#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1073#define INTTOEXT_MAP0_SHIFT 0
1074#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1075#define MEMSWCTL 0x11170 /* Ironlake only */
1076#define MEMCTL_CMD_MASK 0xe000
1077#define MEMCTL_CMD_SHIFT 13
1078#define MEMCTL_CMD_RCLK_OFF 0
1079#define MEMCTL_CMD_RCLK_ON 1
1080#define MEMCTL_CMD_CHFREQ 2
1081#define MEMCTL_CMD_CHVID 3
1082#define MEMCTL_CMD_VMMOFF 4
1083#define MEMCTL_CMD_VMMON 5
1084#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1085 when command complete */
1086#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1087#define MEMCTL_FREQ_SHIFT 8
1088#define MEMCTL_SFCAVM (1<<7)
1089#define MEMCTL_TGT_VID_MASK 0x007f
1090#define MEMIHYST 0x1117c
1091#define MEMINTREN 0x11180 /* 16 bits */
1092#define MEMINT_RSEXIT_EN (1<<8)
1093#define MEMINT_CX_SUPR_EN (1<<7)
1094#define MEMINT_CONT_BUSY_EN (1<<6)
1095#define MEMINT_AVG_BUSY_EN (1<<5)
1096#define MEMINT_EVAL_CHG_EN (1<<4)
1097#define MEMINT_MON_IDLE_EN (1<<3)
1098#define MEMINT_UP_EVAL_EN (1<<2)
1099#define MEMINT_DOWN_EVAL_EN (1<<1)
1100#define MEMINT_SW_CMD_EN (1<<0)
1101#define MEMINTRSTR 0x11182 /* 16 bits */
1102#define MEM_RSEXIT_MASK 0xc000
1103#define MEM_RSEXIT_SHIFT 14
1104#define MEM_CONT_BUSY_MASK 0x3000
1105#define MEM_CONT_BUSY_SHIFT 12
1106#define MEM_AVG_BUSY_MASK 0x0c00
1107#define MEM_AVG_BUSY_SHIFT 10
1108#define MEM_EVAL_CHG_MASK 0x0300
1109#define MEM_EVAL_BUSY_SHIFT 8
1110#define MEM_MON_IDLE_MASK 0x00c0
1111#define MEM_MON_IDLE_SHIFT 6
1112#define MEM_UP_EVAL_MASK 0x0030
1113#define MEM_UP_EVAL_SHIFT 4
1114#define MEM_DOWN_EVAL_MASK 0x000c
1115#define MEM_DOWN_EVAL_SHIFT 2
1116#define MEM_SW_CMD_MASK 0x0003
1117#define MEM_INT_STEER_GFX 0
1118#define MEM_INT_STEER_CMR 1
1119#define MEM_INT_STEER_SMI 2
1120#define MEM_INT_STEER_SCI 3
1121#define MEMINTRSTS 0x11184
1122#define MEMINT_RSEXIT (1<<7)
1123#define MEMINT_CONT_BUSY (1<<6)
1124#define MEMINT_AVG_BUSY (1<<5)
1125#define MEMINT_EVAL_CHG (1<<4)
1126#define MEMINT_MON_IDLE (1<<3)
1127#define MEMINT_UP_EVAL (1<<2)
1128#define MEMINT_DOWN_EVAL (1<<1)
1129#define MEMINT_SW_CMD (1<<0)
1130#define MEMMODECTL 0x11190
1131#define MEMMODE_BOOST_EN (1<<31)
1132#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1133#define MEMMODE_BOOST_FREQ_SHIFT 24
1134#define MEMMODE_IDLE_MODE_MASK 0x00030000
1135#define MEMMODE_IDLE_MODE_SHIFT 16
1136#define MEMMODE_IDLE_MODE_EVAL 0
1137#define MEMMODE_IDLE_MODE_CONT 1
1138#define MEMMODE_HWIDLE_EN (1<<15)
1139#define MEMMODE_SWMODE_EN (1<<14)
1140#define MEMMODE_RCLK_GATE (1<<13)
1141#define MEMMODE_HW_UPDATE (1<<12)
1142#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1143#define MEMMODE_FSTART_SHIFT 8
1144#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1145#define MEMMODE_FMAX_SHIFT 4
1146#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1147#define RCBMAXAVG 0x1119c
1148#define MEMSWCTL2 0x1119e /* Cantiga only */
1149#define SWMEMCMD_RENDER_OFF (0 << 13)
1150#define SWMEMCMD_RENDER_ON (1 << 13)
1151#define SWMEMCMD_SWFREQ (2 << 13)
1152#define SWMEMCMD_TARVID (3 << 13)
1153#define SWMEMCMD_VRM_OFF (4 << 13)
1154#define SWMEMCMD_VRM_ON (5 << 13)
1155#define CMDSTS (1<<12)
1156#define SFCAVM (1<<11)
1157#define SWFREQ_MASK 0x0380 /* P0-7 */
1158#define SWFREQ_SHIFT 7
1159#define TARVID_MASK 0x001f
1160#define MEMSTAT_CTG 0x111a0
1161#define RCBMINAVG 0x111a0
1162#define RCUPEI 0x111b0
1163#define RCDNEI 0x111b4
1164#define RSTDBYCTL 0x111b8
1165#define RS1EN (1<<31)
1166#define RS2EN (1<<30)
1167#define RS3EN (1<<29)
1168#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1169#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1170#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1171#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1172#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1173#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1174#define RSX_STATUS_MASK (7<<20)
1175#define RSX_STATUS_ON (0<<20)
1176#define RSX_STATUS_RC1 (1<<20)
1177#define RSX_STATUS_RC1E (2<<20)
1178#define RSX_STATUS_RS1 (3<<20)
1179#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1180#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1181#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1182#define RSX_STATUS_RSVD2 (7<<20)
1183#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1184#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1185#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1186#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1187#define RS1CONTSAV_MASK (3<<14)
1188#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1189#define RS1CONTSAV_RSVD (1<<14)
1190#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1191#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1192#define NORMSLEXLAT_MASK (3<<12)
1193#define SLOW_RS123 (0<<12)
1194#define SLOW_RS23 (1<<12)
1195#define SLOW_RS3 (2<<12)
1196#define NORMAL_RS123 (3<<12)
1197#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1198#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1199#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1200#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1201#define RS_CSTATE_MASK (3<<4)
1202#define RS_CSTATE_C367_RS1 (0<<4)
1203#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1204#define RS_CSTATE_RSVD (2<<4)
1205#define RS_CSTATE_C367_RS2 (3<<4)
1206#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1207#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1208#define VIDCTL 0x111c0
1209#define VIDSTS 0x111c8
1210#define VIDSTART 0x111cc /* 8 bits */
1211#define MEMSTAT_ILK 0x111f8
1212#define MEMSTAT_VID_MASK 0x7f00
1213#define MEMSTAT_VID_SHIFT 8
1214#define MEMSTAT_PSTATE_MASK 0x00f8
1215#define MEMSTAT_PSTATE_SHIFT 3
1216#define MEMSTAT_MON_ACTV (1<<2)
1217#define MEMSTAT_SRC_CTL_MASK 0x0003
1218#define MEMSTAT_SRC_CTL_CORE 0
1219#define MEMSTAT_SRC_CTL_TRB 1
1220#define MEMSTAT_SRC_CTL_THM 2
1221#define MEMSTAT_SRC_CTL_STDBY 3
1222#define RCPREVBSYTUPAVG 0x113b8
1223#define RCPREVBSYTDNAVG 0x113bc
1224#define PMMISC 0x11214
1225#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1226#define SDEW 0x1124c
1227#define CSIEW0 0x11250
1228#define CSIEW1 0x11254
1229#define CSIEW2 0x11258
1230#define PEW 0x1125c
1231#define DEW 0x11270
1232#define MCHAFE 0x112c0
1233#define CSIEC 0x112e0
1234#define DMIEC 0x112e4
1235#define DDREC 0x112e8
1236#define PEG0EC 0x112ec
1237#define PEG1EC 0x112f0
1238#define GFXEC 0x112f4
1239#define RPPREVBSYTUPAVG 0x113b8
1240#define RPPREVBSYTDNAVG 0x113bc
1241#define ECR 0x11600
1242#define ECR_GPFE (1<<31)
1243#define ECR_IMONE (1<<30)
1244#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1245#define OGW0 0x11608
1246#define OGW1 0x1160c
1247#define EG0 0x11610
1248#define EG1 0x11614
1249#define EG2 0x11618
1250#define EG3 0x1161c
1251#define EG4 0x11620
1252#define EG5 0x11624
1253#define EG6 0x11628
1254#define EG7 0x1162c
1255#define PXW 0x11664
1256#define PXWL 0x11680
1257#define LCFUSE02 0x116c0
1258#define LCFUSE_HIV_MASK 0x000000ff
1259#define CSIPLL0 0x12c10
1260#define DDRMPLL1 0X12c20
1261#define PEG_BAND_GAP_DATA 0x14d68
1262
1263#define GEN6_GT_PERF_STATUS 0x145948
1264#define GEN6_RP_STATE_LIMITS 0x145994
1265#define GEN6_RP_STATE_CAP 0x145998
1266
1267/*
1268 * Logical Context regs
1269 */
1270#define CCID 0x2180
1271#define CCID_EN (1<<0)
1272/*
1273 * Overlay regs
1274 */
1275
1276#define OVADD 0x30000
1277#define DOVSTA 0x30008
1278#define OC_BUF (0x3<<20)
1279#define OGAMC5 0x30010
1280#define OGAMC4 0x30014
1281#define OGAMC3 0x30018
1282#define OGAMC2 0x3001c
1283#define OGAMC1 0x30020
1284#define OGAMC0 0x30024
1285
1286/*
1287 * Display engine regs
1288 */
1289
1290/* Pipe A timing regs */
1291#define _HTOTAL_A 0x60000
1292#define _HBLANK_A 0x60004
1293#define _HSYNC_A 0x60008
1294#define _VTOTAL_A 0x6000c
1295#define _VBLANK_A 0x60010
1296#define _VSYNC_A 0x60014
1297#define _PIPEASRC 0x6001c
1298#define _BCLRPAT_A 0x60020
1299
1300/* Pipe B timing regs */
1301#define _HTOTAL_B 0x61000
1302#define _HBLANK_B 0x61004
1303#define _HSYNC_B 0x61008
1304#define _VTOTAL_B 0x6100c
1305#define _VBLANK_B 0x61010
1306#define _VSYNC_B 0x61014
1307#define _PIPEBSRC 0x6101c
1308#define _BCLRPAT_B 0x61020
1309
1310#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1311#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1312#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1313#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1314#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1315#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1316#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1317
1318/* VGA port control */
1319#define ADPA 0x61100
1320#define ADPA_DAC_ENABLE (1<<31)
1321#define ADPA_DAC_DISABLE 0
1322#define ADPA_PIPE_SELECT_MASK (1<<30)
1323#define ADPA_PIPE_A_SELECT 0
1324#define ADPA_PIPE_B_SELECT (1<<30)
1325#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1326#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1327#define ADPA_SETS_HVPOLARITY 0
1328#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1329#define ADPA_VSYNC_CNTL_ENABLE 0
1330#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1331#define ADPA_HSYNC_CNTL_ENABLE 0
1332#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1333#define ADPA_VSYNC_ACTIVE_LOW 0
1334#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1335#define ADPA_HSYNC_ACTIVE_LOW 0
1336#define ADPA_DPMS_MASK (~(3<<10))
1337#define ADPA_DPMS_ON (0<<10)
1338#define ADPA_DPMS_SUSPEND (1<<10)
1339#define ADPA_DPMS_STANDBY (2<<10)
1340#define ADPA_DPMS_OFF (3<<10)
1341
1342
1343/* Hotplug control (945+ only) */
1344#define PORT_HOTPLUG_EN 0x61110
1345#define HDMIB_HOTPLUG_INT_EN (1 << 29)
1346#define DPB_HOTPLUG_INT_EN (1 << 29)
1347#define HDMIC_HOTPLUG_INT_EN (1 << 28)
1348#define DPC_HOTPLUG_INT_EN (1 << 28)
1349#define HDMID_HOTPLUG_INT_EN (1 << 27)
1350#define DPD_HOTPLUG_INT_EN (1 << 27)
1351#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1352#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1353#define TV_HOTPLUG_INT_EN (1 << 18)
1354#define CRT_HOTPLUG_INT_EN (1 << 9)
1355#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1356#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1357/* must use period 64 on GM45 according to docs */
1358#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1359#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1360#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1361#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1362#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1363#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1364#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1365#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1366#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1367#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1368#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1369#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1370
1371#define PORT_HOTPLUG_STAT 0x61114
1372#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1373#define DPB_HOTPLUG_INT_STATUS (1 << 29)
1374#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1375#define DPC_HOTPLUG_INT_STATUS (1 << 28)
1376#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1377#define DPD_HOTPLUG_INT_STATUS (1 << 27)
1378#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1379#define TV_HOTPLUG_INT_STATUS (1 << 10)
1380#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1381#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1382#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1383#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1384#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1385#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1386
1387/* SDVO port control */
1388#define SDVOB 0x61140
1389#define SDVOC 0x61160
1390#define SDVO_ENABLE (1 << 31)
1391#define SDVO_PIPE_B_SELECT (1 << 30)
1392#define SDVO_STALL_SELECT (1 << 29)
1393#define SDVO_INTERRUPT_ENABLE (1 << 26)
1394/**
1395 * 915G/GM SDVO pixel multiplier.
1396 *
1397 * Programmed value is multiplier - 1, up to 5x.
1398 *
1399 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1400 */
1401#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1402#define SDVO_PORT_MULTIPLY_SHIFT 23
1403#define SDVO_PHASE_SELECT_MASK (15 << 19)
1404#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1405#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1406#define SDVOC_GANG_MODE (1 << 16)
1407#define SDVO_ENCODING_SDVO (0x0 << 10)
1408#define SDVO_ENCODING_HDMI (0x2 << 10)
1409/** Requird for HDMI operation */
1410#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1411#define SDVO_COLOR_RANGE_16_235 (1 << 8)
1412#define SDVO_BORDER_ENABLE (1 << 7)
1413#define SDVO_AUDIO_ENABLE (1 << 6)
1414/** New with 965, default is to be set */
1415#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1416/** New with 965, default is to be set */
1417#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1418#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1419#define SDVO_DETECTED (1 << 2)
1420/* Bits to be preserved when writing */
1421#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1422#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1423
1424/* DVO port control */
1425#define DVOA 0x61120
1426#define DVOB 0x61140
1427#define DVOC 0x61160
1428#define DVO_ENABLE (1 << 31)
1429#define DVO_PIPE_B_SELECT (1 << 30)
1430#define DVO_PIPE_STALL_UNUSED (0 << 28)
1431#define DVO_PIPE_STALL (1 << 28)
1432#define DVO_PIPE_STALL_TV (2 << 28)
1433#define DVO_PIPE_STALL_MASK (3 << 28)
1434#define DVO_USE_VGA_SYNC (1 << 15)
1435#define DVO_DATA_ORDER_I740 (0 << 14)
1436#define DVO_DATA_ORDER_FP (1 << 14)
1437#define DVO_VSYNC_DISABLE (1 << 11)
1438#define DVO_HSYNC_DISABLE (1 << 10)
1439#define DVO_VSYNC_TRISTATE (1 << 9)
1440#define DVO_HSYNC_TRISTATE (1 << 8)
1441#define DVO_BORDER_ENABLE (1 << 7)
1442#define DVO_DATA_ORDER_GBRG (1 << 6)
1443#define DVO_DATA_ORDER_RGGB (0 << 6)
1444#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1445#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1446#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1447#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1448#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1449#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1450#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1451#define DVO_PRESERVE_MASK (0x7<<24)
1452#define DVOA_SRCDIM 0x61124
1453#define DVOB_SRCDIM 0x61144
1454#define DVOC_SRCDIM 0x61164
1455#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1456#define DVO_SRCDIM_VERTICAL_SHIFT 0
1457
1458/* LVDS port control */
1459#define LVDS 0x61180
1460/*
1461 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1462 * the DPLL semantics change when the LVDS is assigned to that pipe.
1463 */
1464#define LVDS_PORT_EN (1 << 31)
1465/* Selects pipe B for LVDS data. Must be set on pre-965. */
1466#define LVDS_PIPEB_SELECT (1 << 30)
1467#define LVDS_PIPE_MASK (1 << 30)
1468#define LVDS_PIPE(pipe) ((pipe) << 30)
1469/* LVDS dithering flag on 965/g4x platform */
1470#define LVDS_ENABLE_DITHER (1 << 25)
1471/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1472#define LVDS_VSYNC_POLARITY (1 << 21)
1473#define LVDS_HSYNC_POLARITY (1 << 20)
1474
1475/* Enable border for unscaled (or aspect-scaled) display */
1476#define LVDS_BORDER_ENABLE (1 << 15)
1477/*
1478 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1479 * pixel.
1480 */
1481#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1482#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1483#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1484/*
1485 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1486 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1487 * on.
1488 */
1489#define LVDS_A3_POWER_MASK (3 << 6)
1490#define LVDS_A3_POWER_DOWN (0 << 6)
1491#define LVDS_A3_POWER_UP (3 << 6)
1492/*
1493 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1494 * is set.
1495 */
1496#define LVDS_CLKB_POWER_MASK (3 << 4)
1497#define LVDS_CLKB_POWER_DOWN (0 << 4)
1498#define LVDS_CLKB_POWER_UP (3 << 4)
1499/*
1500 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1501 * setting for whether we are in dual-channel mode. The B3 pair will
1502 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1503 */
1504#define LVDS_B0B3_POWER_MASK (3 << 2)
1505#define LVDS_B0B3_POWER_DOWN (0 << 2)
1506#define LVDS_B0B3_POWER_UP (3 << 2)
1507
1508/* Video Data Island Packet control */
1509#define VIDEO_DIP_DATA 0x61178
1510#define VIDEO_DIP_CTL 0x61170
1511#define VIDEO_DIP_ENABLE (1 << 31)
1512#define VIDEO_DIP_PORT_B (1 << 29)
1513#define VIDEO_DIP_PORT_C (2 << 29)
1514#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1515#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1516#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1517#define VIDEO_DIP_SELECT_AVI (0 << 19)
1518#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1519#define VIDEO_DIP_SELECT_SPD (3 << 19)
1520#define VIDEO_DIP_SELECT_MASK (3 << 19)
1521#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1522#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1523#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1524
1525/* Panel power sequencing */
1526#define PP_STATUS 0x61200
1527#define PP_ON (1 << 31)
1528/*
1529 * Indicates that all dependencies of the panel are on:
1530 *
1531 * - PLL enabled
1532 * - pipe enabled
1533 * - LVDS/DVOB/DVOC on
1534 */
1535#define PP_READY (1 << 30)
1536#define PP_SEQUENCE_NONE (0 << 28)
1537#define PP_SEQUENCE_ON (1 << 28)
1538#define PP_SEQUENCE_OFF (2 << 28)
1539#define PP_SEQUENCE_MASK 0x30000000
1540#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1541#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1542#define PP_SEQUENCE_STATE_MASK 0x0000000f
1543#define PP_CONTROL 0x61204
1544#define POWER_TARGET_ON (1 << 0)
1545#define PP_ON_DELAYS 0x61208
1546#define PP_OFF_DELAYS 0x6120c
1547#define PP_DIVISOR 0x61210
1548
1549/* Panel fitting */
1550#define PFIT_CONTROL 0x61230
1551#define PFIT_ENABLE (1 << 31)
1552#define PFIT_PIPE_MASK (3 << 29)
1553#define PFIT_PIPE_SHIFT 29
1554#define VERT_INTERP_DISABLE (0 << 10)
1555#define VERT_INTERP_BILINEAR (1 << 10)
1556#define VERT_INTERP_MASK (3 << 10)
1557#define VERT_AUTO_SCALE (1 << 9)
1558#define HORIZ_INTERP_DISABLE (0 << 6)
1559#define HORIZ_INTERP_BILINEAR (1 << 6)
1560#define HORIZ_INTERP_MASK (3 << 6)
1561#define HORIZ_AUTO_SCALE (1 << 5)
1562#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1563#define PFIT_FILTER_FUZZY (0 << 24)
1564#define PFIT_SCALING_AUTO (0 << 26)
1565#define PFIT_SCALING_PROGRAMMED (1 << 26)
1566#define PFIT_SCALING_PILLAR (2 << 26)
1567#define PFIT_SCALING_LETTER (3 << 26)
1568#define PFIT_PGM_RATIOS 0x61234
1569#define PFIT_VERT_SCALE_MASK 0xfff00000
1570#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1571/* Pre-965 */
1572#define PFIT_VERT_SCALE_SHIFT 20
1573#define PFIT_VERT_SCALE_MASK 0xfff00000
1574#define PFIT_HORIZ_SCALE_SHIFT 4
1575#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1576/* 965+ */
1577#define PFIT_VERT_SCALE_SHIFT_965 16
1578#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1579#define PFIT_HORIZ_SCALE_SHIFT_965 0
1580#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1581
1582#define PFIT_AUTO_RATIOS 0x61238
1583
1584/* Backlight control */
1585#define BLC_PWM_CTL 0x61254
1586#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1587#define BLC_PWM_CTL2 0x61250 /* 965+ only */
1588#define BLM_COMBINATION_MODE (1 << 30)
1589/*
1590 * This is the most significant 15 bits of the number of backlight cycles in a
1591 * complete cycle of the modulated backlight control.
1592 *
1593 * The actual value is this field multiplied by two.
1594 */
1595#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1596#define BLM_LEGACY_MODE (1 << 16)
1597/*
1598 * This is the number of cycles out of the backlight modulation cycle for which
1599 * the backlight is on.
1600 *
1601 * This field must be no greater than the number of cycles in the complete
1602 * backlight modulation cycle.
1603 */
1604#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1605#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1606
1607#define BLC_HIST_CTL 0x61260
1608
1609/* TV port control */
1610#define TV_CTL 0x68000
1611/** Enables the TV encoder */
1612# define TV_ENC_ENABLE (1 << 31)
1613/** Sources the TV encoder input from pipe B instead of A. */
1614# define TV_ENC_PIPEB_SELECT (1 << 30)
1615/** Outputs composite video (DAC A only) */
1616# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1617/** Outputs SVideo video (DAC B/C) */
1618# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1619/** Outputs Component video (DAC A/B/C) */
1620# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1621/** Outputs Composite and SVideo (DAC A/B/C) */
1622# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1623# define TV_TRILEVEL_SYNC (1 << 21)
1624/** Enables slow sync generation (945GM only) */
1625# define TV_SLOW_SYNC (1 << 20)
1626/** Selects 4x oversampling for 480i and 576p */
1627# define TV_OVERSAMPLE_4X (0 << 18)
1628/** Selects 2x oversampling for 720p and 1080i */
1629# define TV_OVERSAMPLE_2X (1 << 18)
1630/** Selects no oversampling for 1080p */
1631# define TV_OVERSAMPLE_NONE (2 << 18)
1632/** Selects 8x oversampling */
1633# define TV_OVERSAMPLE_8X (3 << 18)
1634/** Selects progressive mode rather than interlaced */
1635# define TV_PROGRESSIVE (1 << 17)
1636/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1637# define TV_PAL_BURST (1 << 16)
1638/** Field for setting delay of Y compared to C */
1639# define TV_YC_SKEW_MASK (7 << 12)
1640/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1641# define TV_ENC_SDP_FIX (1 << 11)
1642/**
1643 * Enables a fix for the 915GM only.
1644 *
1645 * Not sure what it does.
1646 */
1647# define TV_ENC_C0_FIX (1 << 10)
1648/** Bits that must be preserved by software */
1649# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1650# define TV_FUSE_STATE_MASK (3 << 4)
1651/** Read-only state that reports all features enabled */
1652# define TV_FUSE_STATE_ENABLED (0 << 4)
1653/** Read-only state that reports that Macrovision is disabled in hardware*/
1654# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1655/** Read-only state that reports that TV-out is disabled in hardware. */
1656# define TV_FUSE_STATE_DISABLED (2 << 4)
1657/** Normal operation */
1658# define TV_TEST_MODE_NORMAL (0 << 0)
1659/** Encoder test pattern 1 - combo pattern */
1660# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1661/** Encoder test pattern 2 - full screen vertical 75% color bars */
1662# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1663/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1664# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1665/** Encoder test pattern 4 - random noise */
1666# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1667/** Encoder test pattern 5 - linear color ramps */
1668# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1669/**
1670 * This test mode forces the DACs to 50% of full output.
1671 *
1672 * This is used for load detection in combination with TVDAC_SENSE_MASK
1673 */
1674# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1675# define TV_TEST_MODE_MASK (7 << 0)
1676
1677#define TV_DAC 0x68004
1678# define TV_DAC_SAVE 0x00ffff00
1679/**
1680 * Reports that DAC state change logic has reported change (RO).
1681 *
1682 * This gets cleared when TV_DAC_STATE_EN is cleared
1683*/
1684# define TVDAC_STATE_CHG (1 << 31)
1685# define TVDAC_SENSE_MASK (7 << 28)
1686/** Reports that DAC A voltage is above the detect threshold */
1687# define TVDAC_A_SENSE (1 << 30)
1688/** Reports that DAC B voltage is above the detect threshold */
1689# define TVDAC_B_SENSE (1 << 29)
1690/** Reports that DAC C voltage is above the detect threshold */
1691# define TVDAC_C_SENSE (1 << 28)
1692/**
1693 * Enables DAC state detection logic, for load-based TV detection.
1694 *
1695 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1696 * to off, for load detection to work.
1697 */
1698# define TVDAC_STATE_CHG_EN (1 << 27)
1699/** Sets the DAC A sense value to high */
1700# define TVDAC_A_SENSE_CTL (1 << 26)
1701/** Sets the DAC B sense value to high */
1702# define TVDAC_B_SENSE_CTL (1 << 25)
1703/** Sets the DAC C sense value to high */
1704# define TVDAC_C_SENSE_CTL (1 << 24)
1705/** Overrides the ENC_ENABLE and DAC voltage levels */
1706# define DAC_CTL_OVERRIDE (1 << 7)
1707/** Sets the slew rate. Must be preserved in software */
1708# define ENC_TVDAC_SLEW_FAST (1 << 6)
1709# define DAC_A_1_3_V (0 << 4)
1710# define DAC_A_1_1_V (1 << 4)
1711# define DAC_A_0_7_V (2 << 4)
1712# define DAC_A_MASK (3 << 4)
1713# define DAC_B_1_3_V (0 << 2)
1714# define DAC_B_1_1_V (1 << 2)
1715# define DAC_B_0_7_V (2 << 2)
1716# define DAC_B_MASK (3 << 2)
1717# define DAC_C_1_3_V (0 << 0)
1718# define DAC_C_1_1_V (1 << 0)
1719# define DAC_C_0_7_V (2 << 0)
1720# define DAC_C_MASK (3 << 0)
1721
1722/**
1723 * CSC coefficients are stored in a floating point format with 9 bits of
1724 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1725 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1726 * -1 (0x3) being the only legal negative value.
1727 */
1728#define TV_CSC_Y 0x68010
1729# define TV_RY_MASK 0x07ff0000
1730# define TV_RY_SHIFT 16
1731# define TV_GY_MASK 0x00000fff
1732# define TV_GY_SHIFT 0
1733
1734#define TV_CSC_Y2 0x68014
1735# define TV_BY_MASK 0x07ff0000
1736# define TV_BY_SHIFT 16
1737/**
1738 * Y attenuation for component video.
1739 *
1740 * Stored in 1.9 fixed point.
1741 */
1742# define TV_AY_MASK 0x000003ff
1743# define TV_AY_SHIFT 0
1744
1745#define TV_CSC_U 0x68018
1746# define TV_RU_MASK 0x07ff0000
1747# define TV_RU_SHIFT 16
1748# define TV_GU_MASK 0x000007ff
1749# define TV_GU_SHIFT 0
1750
1751#define TV_CSC_U2 0x6801c
1752# define TV_BU_MASK 0x07ff0000
1753# define TV_BU_SHIFT 16
1754/**
1755 * U attenuation for component video.
1756 *
1757 * Stored in 1.9 fixed point.
1758 */
1759# define TV_AU_MASK 0x000003ff
1760# define TV_AU_SHIFT 0
1761
1762#define TV_CSC_V 0x68020
1763# define TV_RV_MASK 0x0fff0000
1764# define TV_RV_SHIFT 16
1765# define TV_GV_MASK 0x000007ff
1766# define TV_GV_SHIFT 0
1767
1768#define TV_CSC_V2 0x68024
1769# define TV_BV_MASK 0x07ff0000
1770# define TV_BV_SHIFT 16
1771/**
1772 * V attenuation for component video.
1773 *
1774 * Stored in 1.9 fixed point.
1775 */
1776# define TV_AV_MASK 0x000007ff
1777# define TV_AV_SHIFT 0
1778
1779#define TV_CLR_KNOBS 0x68028
1780/** 2s-complement brightness adjustment */
1781# define TV_BRIGHTNESS_MASK 0xff000000
1782# define TV_BRIGHTNESS_SHIFT 24
1783/** Contrast adjustment, as a 2.6 unsigned floating point number */
1784# define TV_CONTRAST_MASK 0x00ff0000
1785# define TV_CONTRAST_SHIFT 16
1786/** Saturation adjustment, as a 2.6 unsigned floating point number */
1787# define TV_SATURATION_MASK 0x0000ff00
1788# define TV_SATURATION_SHIFT 8
1789/** Hue adjustment, as an integer phase angle in degrees */
1790# define TV_HUE_MASK 0x000000ff
1791# define TV_HUE_SHIFT 0
1792
1793#define TV_CLR_LEVEL 0x6802c
1794/** Controls the DAC level for black */
1795# define TV_BLACK_LEVEL_MASK 0x01ff0000
1796# define TV_BLACK_LEVEL_SHIFT 16
1797/** Controls the DAC level for blanking */
1798# define TV_BLANK_LEVEL_MASK 0x000001ff
1799# define TV_BLANK_LEVEL_SHIFT 0
1800
1801#define TV_H_CTL_1 0x68030
1802/** Number of pixels in the hsync. */
1803# define TV_HSYNC_END_MASK 0x1fff0000
1804# define TV_HSYNC_END_SHIFT 16
1805/** Total number of pixels minus one in the line (display and blanking). */
1806# define TV_HTOTAL_MASK 0x00001fff
1807# define TV_HTOTAL_SHIFT 0
1808
1809#define TV_H_CTL_2 0x68034
1810/** Enables the colorburst (needed for non-component color) */
1811# define TV_BURST_ENA (1 << 31)
1812/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1813# define TV_HBURST_START_SHIFT 16
1814# define TV_HBURST_START_MASK 0x1fff0000
1815/** Length of the colorburst */
1816# define TV_HBURST_LEN_SHIFT 0
1817# define TV_HBURST_LEN_MASK 0x0001fff
1818
1819#define TV_H_CTL_3 0x68038
1820/** End of hblank, measured in pixels minus one from start of hsync */
1821# define TV_HBLANK_END_SHIFT 16
1822# define TV_HBLANK_END_MASK 0x1fff0000
1823/** Start of hblank, measured in pixels minus one from start of hsync */
1824# define TV_HBLANK_START_SHIFT 0
1825# define TV_HBLANK_START_MASK 0x0001fff
1826
1827#define TV_V_CTL_1 0x6803c
1828/** XXX */
1829# define TV_NBR_END_SHIFT 16
1830# define TV_NBR_END_MASK 0x07ff0000
1831/** XXX */
1832# define TV_VI_END_F1_SHIFT 8
1833# define TV_VI_END_F1_MASK 0x00003f00
1834/** XXX */
1835# define TV_VI_END_F2_SHIFT 0
1836# define TV_VI_END_F2_MASK 0x0000003f
1837
1838#define TV_V_CTL_2 0x68040
1839/** Length of vsync, in half lines */
1840# define TV_VSYNC_LEN_MASK 0x07ff0000
1841# define TV_VSYNC_LEN_SHIFT 16
1842/** Offset of the start of vsync in field 1, measured in one less than the
1843 * number of half lines.
1844 */
1845# define TV_VSYNC_START_F1_MASK 0x00007f00
1846# define TV_VSYNC_START_F1_SHIFT 8
1847/**
1848 * Offset of the start of vsync in field 2, measured in one less than the
1849 * number of half lines.
1850 */
1851# define TV_VSYNC_START_F2_MASK 0x0000007f
1852# define TV_VSYNC_START_F2_SHIFT 0
1853
1854#define TV_V_CTL_3 0x68044
1855/** Enables generation of the equalization signal */
1856# define TV_EQUAL_ENA (1 << 31)
1857/** Length of vsync, in half lines */
1858# define TV_VEQ_LEN_MASK 0x007f0000
1859# define TV_VEQ_LEN_SHIFT 16
1860/** Offset of the start of equalization in field 1, measured in one less than
1861 * the number of half lines.
1862 */
1863# define TV_VEQ_START_F1_MASK 0x0007f00
1864# define TV_VEQ_START_F1_SHIFT 8
1865/**
1866 * Offset of the start of equalization in field 2, measured in one less than
1867 * the number of half lines.
1868 */
1869# define TV_VEQ_START_F2_MASK 0x000007f
1870# define TV_VEQ_START_F2_SHIFT 0
1871
1872#define TV_V_CTL_4 0x68048
1873/**
1874 * Offset to start of vertical colorburst, measured in one less than the
1875 * number of lines from vertical start.
1876 */
1877# define TV_VBURST_START_F1_MASK 0x003f0000
1878# define TV_VBURST_START_F1_SHIFT 16
1879/**
1880 * Offset to the end of vertical colorburst, measured in one less than the
1881 * number of lines from the start of NBR.
1882 */
1883# define TV_VBURST_END_F1_MASK 0x000000ff
1884# define TV_VBURST_END_F1_SHIFT 0
1885
1886#define TV_V_CTL_5 0x6804c
1887/**
1888 * Offset to start of vertical colorburst, measured in one less than the
1889 * number of lines from vertical start.
1890 */
1891# define TV_VBURST_START_F2_MASK 0x003f0000
1892# define TV_VBURST_START_F2_SHIFT 16
1893/**
1894 * Offset to the end of vertical colorburst, measured in one less than the
1895 * number of lines from the start of NBR.
1896 */
1897# define TV_VBURST_END_F2_MASK 0x000000ff
1898# define TV_VBURST_END_F2_SHIFT 0
1899
1900#define TV_V_CTL_6 0x68050
1901/**
1902 * Offset to start of vertical colorburst, measured in one less than the
1903 * number of lines from vertical start.
1904 */
1905# define TV_VBURST_START_F3_MASK 0x003f0000
1906# define TV_VBURST_START_F3_SHIFT 16
1907/**
1908 * Offset to the end of vertical colorburst, measured in one less than the
1909 * number of lines from the start of NBR.
1910 */
1911# define TV_VBURST_END_F3_MASK 0x000000ff
1912# define TV_VBURST_END_F3_SHIFT 0
1913
1914#define TV_V_CTL_7 0x68054
1915/**
1916 * Offset to start of vertical colorburst, measured in one less than the
1917 * number of lines from vertical start.
1918 */
1919# define TV_VBURST_START_F4_MASK 0x003f0000
1920# define TV_VBURST_START_F4_SHIFT 16
1921/**
1922 * Offset to the end of vertical colorburst, measured in one less than the
1923 * number of lines from the start of NBR.
1924 */
1925# define TV_VBURST_END_F4_MASK 0x000000ff
1926# define TV_VBURST_END_F4_SHIFT 0
1927
1928#define TV_SC_CTL_1 0x68060
1929/** Turns on the first subcarrier phase generation DDA */
1930# define TV_SC_DDA1_EN (1 << 31)
1931/** Turns on the first subcarrier phase generation DDA */
1932# define TV_SC_DDA2_EN (1 << 30)
1933/** Turns on the first subcarrier phase generation DDA */
1934# define TV_SC_DDA3_EN (1 << 29)
1935/** Sets the subcarrier DDA to reset frequency every other field */
1936# define TV_SC_RESET_EVERY_2 (0 << 24)
1937/** Sets the subcarrier DDA to reset frequency every fourth field */
1938# define TV_SC_RESET_EVERY_4 (1 << 24)
1939/** Sets the subcarrier DDA to reset frequency every eighth field */
1940# define TV_SC_RESET_EVERY_8 (2 << 24)
1941/** Sets the subcarrier DDA to never reset the frequency */
1942# define TV_SC_RESET_NEVER (3 << 24)
1943/** Sets the peak amplitude of the colorburst.*/
1944# define TV_BURST_LEVEL_MASK 0x00ff0000
1945# define TV_BURST_LEVEL_SHIFT 16
1946/** Sets the increment of the first subcarrier phase generation DDA */
1947# define TV_SCDDA1_INC_MASK 0x00000fff
1948# define TV_SCDDA1_INC_SHIFT 0
1949
1950#define TV_SC_CTL_2 0x68064
1951/** Sets the rollover for the second subcarrier phase generation DDA */
1952# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1953# define TV_SCDDA2_SIZE_SHIFT 16
1954/** Sets the increent of the second subcarrier phase generation DDA */
1955# define TV_SCDDA2_INC_MASK 0x00007fff
1956# define TV_SCDDA2_INC_SHIFT 0
1957
1958#define TV_SC_CTL_3 0x68068
1959/** Sets the rollover for the third subcarrier phase generation DDA */
1960# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1961# define TV_SCDDA3_SIZE_SHIFT 16
1962/** Sets the increent of the third subcarrier phase generation DDA */
1963# define TV_SCDDA3_INC_MASK 0x00007fff
1964# define TV_SCDDA3_INC_SHIFT 0
1965
1966#define TV_WIN_POS 0x68070
1967/** X coordinate of the display from the start of horizontal active */
1968# define TV_XPOS_MASK 0x1fff0000
1969# define TV_XPOS_SHIFT 16
1970/** Y coordinate of the display from the start of vertical active (NBR) */
1971# define TV_YPOS_MASK 0x00000fff
1972# define TV_YPOS_SHIFT 0
1973
1974#define TV_WIN_SIZE 0x68074
1975/** Horizontal size of the display window, measured in pixels*/
1976# define TV_XSIZE_MASK 0x1fff0000
1977# define TV_XSIZE_SHIFT 16
1978/**
1979 * Vertical size of the display window, measured in pixels.
1980 *
1981 * Must be even for interlaced modes.
1982 */
1983# define TV_YSIZE_MASK 0x00000fff
1984# define TV_YSIZE_SHIFT 0
1985
1986#define TV_FILTER_CTL_1 0x68080
1987/**
1988 * Enables automatic scaling calculation.
1989 *
1990 * If set, the rest of the registers are ignored, and the calculated values can
1991 * be read back from the register.
1992 */
1993# define TV_AUTO_SCALE (1 << 31)
1994/**
1995 * Disables the vertical filter.
1996 *
1997 * This is required on modes more than 1024 pixels wide */
1998# define TV_V_FILTER_BYPASS (1 << 29)
1999/** Enables adaptive vertical filtering */
2000# define TV_VADAPT (1 << 28)
2001# define TV_VADAPT_MODE_MASK (3 << 26)
2002/** Selects the least adaptive vertical filtering mode */
2003# define TV_VADAPT_MODE_LEAST (0 << 26)
2004/** Selects the moderately adaptive vertical filtering mode */
2005# define TV_VADAPT_MODE_MODERATE (1 << 26)
2006/** Selects the most adaptive vertical filtering mode */
2007# define TV_VADAPT_MODE_MOST (3 << 26)
2008/**
2009 * Sets the horizontal scaling factor.
2010 *
2011 * This should be the fractional part of the horizontal scaling factor divided
2012 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2013 *
2014 * (src width - 1) / ((oversample * dest width) - 1)
2015 */
2016# define TV_HSCALE_FRAC_MASK 0x00003fff
2017# define TV_HSCALE_FRAC_SHIFT 0
2018
2019#define TV_FILTER_CTL_2 0x68084
2020/**
2021 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2022 *
2023 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2024 */
2025# define TV_VSCALE_INT_MASK 0x00038000
2026# define TV_VSCALE_INT_SHIFT 15
2027/**
2028 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2029 *
2030 * \sa TV_VSCALE_INT_MASK
2031 */
2032# define TV_VSCALE_FRAC_MASK 0x00007fff
2033# define TV_VSCALE_FRAC_SHIFT 0
2034
2035#define TV_FILTER_CTL_3 0x68088
2036/**
2037 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2038 *
2039 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2040 *
2041 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2042 */
2043# define TV_VSCALE_IP_INT_MASK 0x00038000
2044# define TV_VSCALE_IP_INT_SHIFT 15
2045/**
2046 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2047 *
2048 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2049 *
2050 * \sa TV_VSCALE_IP_INT_MASK
2051 */
2052# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2053# define TV_VSCALE_IP_FRAC_SHIFT 0
2054
2055#define TV_CC_CONTROL 0x68090
2056# define TV_CC_ENABLE (1 << 31)
2057/**
2058 * Specifies which field to send the CC data in.
2059 *
2060 * CC data is usually sent in field 0.
2061 */
2062# define TV_CC_FID_MASK (1 << 27)
2063# define TV_CC_FID_SHIFT 27
2064/** Sets the horizontal position of the CC data. Usually 135. */
2065# define TV_CC_HOFF_MASK 0x03ff0000
2066# define TV_CC_HOFF_SHIFT 16
2067/** Sets the vertical position of the CC data. Usually 21 */
2068# define TV_CC_LINE_MASK 0x0000003f
2069# define TV_CC_LINE_SHIFT 0
2070
2071#define TV_CC_DATA 0x68094
2072# define TV_CC_RDY (1 << 31)
2073/** Second word of CC data to be transmitted. */
2074# define TV_CC_DATA_2_MASK 0x007f0000
2075# define TV_CC_DATA_2_SHIFT 16
2076/** First word of CC data to be transmitted. */
2077# define TV_CC_DATA_1_MASK 0x0000007f
2078# define TV_CC_DATA_1_SHIFT 0
2079
2080#define TV_H_LUMA_0 0x68100
2081#define TV_H_LUMA_59 0x681ec
2082#define TV_H_CHROMA_0 0x68200
2083#define TV_H_CHROMA_59 0x682ec
2084#define TV_V_LUMA_0 0x68300
2085#define TV_V_LUMA_42 0x683a8
2086#define TV_V_CHROMA_0 0x68400
2087#define TV_V_CHROMA_42 0x684a8
2088
2089/* Display Port */
2090#define DP_A 0x64000 /* eDP */
2091#define DP_B 0x64100
2092#define DP_C 0x64200
2093#define DP_D 0x64300
2094
2095#define DP_PORT_EN (1 << 31)
2096#define DP_PIPEB_SELECT (1 << 30)
2097#define DP_PIPE_MASK (1 << 30)
2098
2099/* Link training mode - select a suitable mode for each stage */
2100#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2101#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2102#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2103#define DP_LINK_TRAIN_OFF (3 << 28)
2104#define DP_LINK_TRAIN_MASK (3 << 28)
2105#define DP_LINK_TRAIN_SHIFT 28
2106
2107/* CPT Link training mode */
2108#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2109#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2110#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2111#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2112#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2113#define DP_LINK_TRAIN_SHIFT_CPT 8
2114
2115/* Signal voltages. These are mostly controlled by the other end */
2116#define DP_VOLTAGE_0_4 (0 << 25)
2117#define DP_VOLTAGE_0_6 (1 << 25)
2118#define DP_VOLTAGE_0_8 (2 << 25)
2119#define DP_VOLTAGE_1_2 (3 << 25)
2120#define DP_VOLTAGE_MASK (7 << 25)
2121#define DP_VOLTAGE_SHIFT 25
2122
2123/* Signal pre-emphasis levels, like voltages, the other end tells us what
2124 * they want
2125 */
2126#define DP_PRE_EMPHASIS_0 (0 << 22)
2127#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2128#define DP_PRE_EMPHASIS_6 (2 << 22)
2129#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2130#define DP_PRE_EMPHASIS_MASK (7 << 22)
2131#define DP_PRE_EMPHASIS_SHIFT 22
2132
2133/* How many wires to use. I guess 3 was too hard */
2134#define DP_PORT_WIDTH_1 (0 << 19)
2135#define DP_PORT_WIDTH_2 (1 << 19)
2136#define DP_PORT_WIDTH_4 (3 << 19)
2137#define DP_PORT_WIDTH_MASK (7 << 19)
2138
2139/* Mystic DPCD version 1.1 special mode */
2140#define DP_ENHANCED_FRAMING (1 << 18)
2141
2142/* eDP */
2143#define DP_PLL_FREQ_270MHZ (0 << 16)
2144#define DP_PLL_FREQ_160MHZ (1 << 16)
2145#define DP_PLL_FREQ_MASK (3 << 16)
2146
2147/** locked once port is enabled */
2148#define DP_PORT_REVERSAL (1 << 15)
2149
2150/* eDP */
2151#define DP_PLL_ENABLE (1 << 14)
2152
2153/** sends the clock on lane 15 of the PEG for debug */
2154#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2155
2156#define DP_SCRAMBLING_DISABLE (1 << 12)
2157#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2158
2159/** limit RGB values to avoid confusing TVs */
2160#define DP_COLOR_RANGE_16_235 (1 << 8)
2161
2162/** Turn on the audio link */
2163#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2164
2165/** vs and hs sync polarity */
2166#define DP_SYNC_VS_HIGH (1 << 4)
2167#define DP_SYNC_HS_HIGH (1 << 3)
2168
2169/** A fantasy */
2170#define DP_DETECTED (1 << 2)
2171
2172/** The aux channel provides a way to talk to the
2173 * signal sink for DDC etc. Max packet size supported
2174 * is 20 bytes in each direction, hence the 5 fixed
2175 * data registers
2176 */
2177#define DPA_AUX_CH_CTL 0x64010
2178#define DPA_AUX_CH_DATA1 0x64014
2179#define DPA_AUX_CH_DATA2 0x64018
2180#define DPA_AUX_CH_DATA3 0x6401c
2181#define DPA_AUX_CH_DATA4 0x64020
2182#define DPA_AUX_CH_DATA5 0x64024
2183
2184#define DPB_AUX_CH_CTL 0x64110
2185#define DPB_AUX_CH_DATA1 0x64114
2186#define DPB_AUX_CH_DATA2 0x64118
2187#define DPB_AUX_CH_DATA3 0x6411c
2188#define DPB_AUX_CH_DATA4 0x64120
2189#define DPB_AUX_CH_DATA5 0x64124
2190
2191#define DPC_AUX_CH_CTL 0x64210
2192#define DPC_AUX_CH_DATA1 0x64214
2193#define DPC_AUX_CH_DATA2 0x64218
2194#define DPC_AUX_CH_DATA3 0x6421c
2195#define DPC_AUX_CH_DATA4 0x64220
2196#define DPC_AUX_CH_DATA5 0x64224
2197
2198#define DPD_AUX_CH_CTL 0x64310
2199#define DPD_AUX_CH_DATA1 0x64314
2200#define DPD_AUX_CH_DATA2 0x64318
2201#define DPD_AUX_CH_DATA3 0x6431c
2202#define DPD_AUX_CH_DATA4 0x64320
2203#define DPD_AUX_CH_DATA5 0x64324
2204
2205#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2206#define DP_AUX_CH_CTL_DONE (1 << 30)
2207#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2208#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2209#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2210#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2211#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2212#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2213#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2214#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2215#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2216#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2217#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2218#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2219#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2220#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2221#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2222#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2223#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2224#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2225#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2226
2227/*
2228 * Computing GMCH M and N values for the Display Port link
2229 *
2230 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2231 *
2232 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2233 *
2234 * The GMCH value is used internally
2235 *
2236 * bytes_per_pixel is the number of bytes coming out of the plane,
2237 * which is after the LUTs, so we want the bytes for our color format.
2238 * For our current usage, this is always 3, one byte for R, G and B.
2239 */
2240#define _PIPEA_GMCH_DATA_M 0x70050
2241#define _PIPEB_GMCH_DATA_M 0x71050
2242
2243/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2244#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2245#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2246
2247#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2248
2249#define _PIPEA_GMCH_DATA_N 0x70054
2250#define _PIPEB_GMCH_DATA_N 0x71054
2251#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2252
2253/*
2254 * Computing Link M and N values for the Display Port link
2255 *
2256 * Link M / N = pixel_clock / ls_clk
2257 *
2258 * (the DP spec calls pixel_clock the 'strm_clk')
2259 *
2260 * The Link value is transmitted in the Main Stream
2261 * Attributes and VB-ID.
2262 */
2263
2264#define _PIPEA_DP_LINK_M 0x70060
2265#define _PIPEB_DP_LINK_M 0x71060
2266#define PIPEA_DP_LINK_M_MASK (0xffffff)
2267
2268#define _PIPEA_DP_LINK_N 0x70064
2269#define _PIPEB_DP_LINK_N 0x71064
2270#define PIPEA_DP_LINK_N_MASK (0xffffff)
2271
2272#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2273#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2274#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2275#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2276
2277/* Display & cursor control */
2278
2279/* Pipe A */
2280#define _PIPEADSL 0x70000
2281#define DSL_LINEMASK 0x00000fff
2282#define _PIPEACONF 0x70008
2283#define PIPECONF_ENABLE (1<<31)
2284#define PIPECONF_DISABLE 0
2285#define PIPECONF_DOUBLE_WIDE (1<<30)
2286#define I965_PIPECONF_ACTIVE (1<<30)
2287#define PIPECONF_SINGLE_WIDE 0
2288#define PIPECONF_PIPE_UNLOCKED 0
2289#define PIPECONF_PIPE_LOCKED (1<<25)
2290#define PIPECONF_PALETTE 0
2291#define PIPECONF_GAMMA (1<<24)
2292#define PIPECONF_FORCE_BORDER (1<<25)
2293#define PIPECONF_PROGRESSIVE (0 << 21)
2294#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2295#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2296#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2297#define PIPECONF_BPP_MASK (0x000000e0)
2298#define PIPECONF_BPP_8 (0<<5)
2299#define PIPECONF_BPP_10 (1<<5)
2300#define PIPECONF_BPP_6 (2<<5)
2301#define PIPECONF_BPP_12 (3<<5)
2302#define PIPECONF_DITHER_EN (1<<4)
2303#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2304#define PIPECONF_DITHER_TYPE_SP (0<<2)
2305#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2306#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2307#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2308#define _PIPEASTAT 0x70024
2309#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2310#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2311#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2312#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2313#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2314#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2315#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2316#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2317#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2318#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2319#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2320#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2321#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2322#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2323#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2324#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2325#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2326#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2327#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2328#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2329#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2330#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2331#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2332#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2333#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2334#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2335#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2336#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2337#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2338#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2339#define PIPE_8BPC (0 << 5)
2340#define PIPE_10BPC (1 << 5)
2341#define PIPE_6BPC (2 << 5)
2342#define PIPE_12BPC (3 << 5)
2343
2344#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2345#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2346#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2347#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2348#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2349#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2350
2351#define DSPARB 0x70030
2352#define DSPARB_CSTART_MASK (0x7f << 7)
2353#define DSPARB_CSTART_SHIFT 7
2354#define DSPARB_BSTART_MASK (0x7f)
2355#define DSPARB_BSTART_SHIFT 0
2356#define DSPARB_BEND_SHIFT 9 /* on 855 */
2357#define DSPARB_AEND_SHIFT 0
2358
2359#define DSPFW1 0x70034
2360#define DSPFW_SR_SHIFT 23
2361#define DSPFW_SR_MASK (0x1ff<<23)
2362#define DSPFW_CURSORB_SHIFT 16
2363#define DSPFW_CURSORB_MASK (0x3f<<16)
2364#define DSPFW_PLANEB_SHIFT 8
2365#define DSPFW_PLANEB_MASK (0x7f<<8)
2366#define DSPFW_PLANEA_MASK (0x7f)
2367#define DSPFW2 0x70038
2368#define DSPFW_CURSORA_MASK 0x00003f00
2369#define DSPFW_CURSORA_SHIFT 8
2370#define DSPFW_PLANEC_MASK (0x7f)
2371#define DSPFW3 0x7003c
2372#define DSPFW_HPLL_SR_EN (1<<31)
2373#define DSPFW_CURSOR_SR_SHIFT 24
2374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
2375#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2376#define DSPFW_HPLL_CURSOR_SHIFT 16
2377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2378#define DSPFW_HPLL_SR_MASK (0x1ff)
2379
2380/* FIFO watermark sizes etc */
2381#define G4X_FIFO_LINE_SIZE 64
2382#define I915_FIFO_LINE_SIZE 64
2383#define I830_FIFO_LINE_SIZE 32
2384
2385#define G4X_FIFO_SIZE 127
2386#define I965_FIFO_SIZE 512
2387#define I945_FIFO_SIZE 127
2388#define I915_FIFO_SIZE 95
2389#define I855GM_FIFO_SIZE 127 /* In cachelines */
2390#define I830_FIFO_SIZE 95
2391
2392#define G4X_MAX_WM 0x3f
2393#define I915_MAX_WM 0x3f
2394
2395#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2396#define PINEVIEW_FIFO_LINE_SIZE 64
2397#define PINEVIEW_MAX_WM 0x1ff
2398#define PINEVIEW_DFT_WM 0x3f
2399#define PINEVIEW_DFT_HPLLOFF_WM 0
2400#define PINEVIEW_GUARD_WM 10
2401#define PINEVIEW_CURSOR_FIFO 64
2402#define PINEVIEW_CURSOR_MAX_WM 0x3f
2403#define PINEVIEW_CURSOR_DFT_WM 0
2404#define PINEVIEW_CURSOR_GUARD_WM 5
2405
2406#define I965_CURSOR_FIFO 64
2407#define I965_CURSOR_MAX_WM 32
2408#define I965_CURSOR_DFT_WM 8
2409
2410/* define the Watermark register on Ironlake */
2411#define WM0_PIPEA_ILK 0x45100
2412#define WM0_PIPE_PLANE_MASK (0x7f<<16)
2413#define WM0_PIPE_PLANE_SHIFT 16
2414#define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2415#define WM0_PIPE_SPRITE_SHIFT 8
2416#define WM0_PIPE_CURSOR_MASK (0x1f)
2417
2418#define WM0_PIPEB_ILK 0x45104
2419#define WM1_LP_ILK 0x45108
2420#define WM1_LP_SR_EN (1<<31)
2421#define WM1_LP_LATENCY_SHIFT 24
2422#define WM1_LP_LATENCY_MASK (0x7f<<24)
2423#define WM1_LP_FBC_MASK (0xf<<20)
2424#define WM1_LP_FBC_SHIFT 20
2425#define WM1_LP_SR_MASK (0x1ff<<8)
2426#define WM1_LP_SR_SHIFT 8
2427#define WM1_LP_CURSOR_MASK (0x3f)
2428#define WM2_LP_ILK 0x4510c
2429#define WM2_LP_EN (1<<31)
2430#define WM3_LP_ILK 0x45110
2431#define WM3_LP_EN (1<<31)
2432#define WM1S_LP_ILK 0x45120
2433#define WM1S_LP_EN (1<<31)
2434
2435/* Memory latency timer register */
2436#define MLTR_ILK 0x11222
2437#define MLTR_WM1_SHIFT 0
2438#define MLTR_WM2_SHIFT 8
2439/* the unit of memory self-refresh latency time is 0.5us */
2440#define ILK_SRLT_MASK 0x3f
2441#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2442#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2443#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2444
2445/* define the fifo size on Ironlake */
2446#define ILK_DISPLAY_FIFO 128
2447#define ILK_DISPLAY_MAXWM 64
2448#define ILK_DISPLAY_DFTWM 8
2449#define ILK_CURSOR_FIFO 32
2450#define ILK_CURSOR_MAXWM 16
2451#define ILK_CURSOR_DFTWM 8
2452
2453#define ILK_DISPLAY_SR_FIFO 512
2454#define ILK_DISPLAY_MAX_SRWM 0x1ff
2455#define ILK_DISPLAY_DFT_SRWM 0x3f
2456#define ILK_CURSOR_SR_FIFO 64
2457#define ILK_CURSOR_MAX_SRWM 0x3f
2458#define ILK_CURSOR_DFT_SRWM 8
2459
2460#define ILK_FIFO_LINE_SIZE 64
2461
2462/* define the WM info on Sandybridge */
2463#define SNB_DISPLAY_FIFO 128
2464#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2465#define SNB_DISPLAY_DFTWM 8
2466#define SNB_CURSOR_FIFO 32
2467#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2468#define SNB_CURSOR_DFTWM 8
2469
2470#define SNB_DISPLAY_SR_FIFO 512
2471#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2472#define SNB_DISPLAY_DFT_SRWM 0x3f
2473#define SNB_CURSOR_SR_FIFO 64
2474#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2475#define SNB_CURSOR_DFT_SRWM 8
2476
2477#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2478
2479#define SNB_FIFO_LINE_SIZE 64
2480
2481
2482/* the address where we get all kinds of latency value */
2483#define SSKPD 0x5d10
2484#define SSKPD_WM_MASK 0x3f
2485#define SSKPD_WM0_SHIFT 0
2486#define SSKPD_WM1_SHIFT 8
2487#define SSKPD_WM2_SHIFT 16
2488#define SSKPD_WM3_SHIFT 24
2489
2490#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2491#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2492#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2493#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2494#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2495
2496/*
2497 * The two pipe frame counter registers are not synchronized, so
2498 * reading a stable value is somewhat tricky. The following code
2499 * should work:
2500 *
2501 * do {
2502 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2503 * PIPE_FRAME_HIGH_SHIFT;
2504 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2505 * PIPE_FRAME_LOW_SHIFT);
2506 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2507 * PIPE_FRAME_HIGH_SHIFT);
2508 * } while (high1 != high2);
2509 * frame = (high1 << 8) | low1;
2510 */
2511#define _PIPEAFRAMEHIGH 0x70040
2512#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2513#define PIPE_FRAME_HIGH_SHIFT 0
2514#define _PIPEAFRAMEPIXEL 0x70044
2515#define PIPE_FRAME_LOW_MASK 0xff000000
2516#define PIPE_FRAME_LOW_SHIFT 24
2517#define PIPE_PIXEL_MASK 0x00ffffff
2518#define PIPE_PIXEL_SHIFT 0
2519/* GM45+ just has to be different */
2520#define _PIPEA_FRMCOUNT_GM45 0x70040
2521#define _PIPEA_FLIPCOUNT_GM45 0x70044
2522#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2523
2524/* Cursor A & B regs */
2525#define _CURACNTR 0x70080
2526/* Old style CUR*CNTR flags (desktop 8xx) */
2527#define CURSOR_ENABLE 0x80000000
2528#define CURSOR_GAMMA_ENABLE 0x40000000
2529#define CURSOR_STRIDE_MASK 0x30000000
2530#define CURSOR_FORMAT_SHIFT 24
2531#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2532#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2533#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2534#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2535#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2536#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2537/* New style CUR*CNTR flags */
2538#define CURSOR_MODE 0x27
2539#define CURSOR_MODE_DISABLE 0x00
2540#define CURSOR_MODE_64_32B_AX 0x07
2541#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2542#define MCURSOR_PIPE_SELECT (1 << 28)
2543#define MCURSOR_PIPE_A 0x00
2544#define MCURSOR_PIPE_B (1 << 28)
2545#define MCURSOR_GAMMA_ENABLE (1 << 26)
2546#define _CURABASE 0x70084
2547#define _CURAPOS 0x70088
2548#define CURSOR_POS_MASK 0x007FF
2549#define CURSOR_POS_SIGN 0x8000
2550#define CURSOR_X_SHIFT 0
2551#define CURSOR_Y_SHIFT 16
2552#define CURSIZE 0x700a0
2553#define _CURBCNTR 0x700c0
2554#define _CURBBASE 0x700c4
2555#define _CURBPOS 0x700c8
2556
2557#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2558#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2559#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2560
2561/* Display A control */
2562#define _DSPACNTR 0x70180
2563#define DISPLAY_PLANE_ENABLE (1<<31)
2564#define DISPLAY_PLANE_DISABLE 0
2565#define DISPPLANE_GAMMA_ENABLE (1<<30)
2566#define DISPPLANE_GAMMA_DISABLE 0
2567#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2568#define DISPPLANE_8BPP (0x2<<26)
2569#define DISPPLANE_15_16BPP (0x4<<26)
2570#define DISPPLANE_16BPP (0x5<<26)
2571#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2572#define DISPPLANE_32BPP (0x7<<26)
2573#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2574#define DISPPLANE_STEREO_ENABLE (1<<25)
2575#define DISPPLANE_STEREO_DISABLE 0
2576#define DISPPLANE_SEL_PIPE_SHIFT 24
2577#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2578#define DISPPLANE_SEL_PIPE_A 0
2579#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2580#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2581#define DISPPLANE_SRC_KEY_DISABLE 0
2582#define DISPPLANE_LINE_DOUBLE (1<<20)
2583#define DISPPLANE_NO_LINE_DOUBLE 0
2584#define DISPPLANE_STEREO_POLARITY_FIRST 0
2585#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2586#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2587#define DISPPLANE_TILED (1<<10)
2588#define _DSPAADDR 0x70184
2589#define _DSPASTRIDE 0x70188
2590#define _DSPAPOS 0x7018C /* reserved */
2591#define _DSPASIZE 0x70190
2592#define _DSPASURF 0x7019C /* 965+ only */
2593#define _DSPATILEOFF 0x701A4 /* 965+ only */
2594
2595#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2596#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2597#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2598#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2599#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2600#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2601#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2602
2603/* VBIOS flags */
2604#define SWF00 0x71410
2605#define SWF01 0x71414
2606#define SWF02 0x71418
2607#define SWF03 0x7141c
2608#define SWF04 0x71420
2609#define SWF05 0x71424
2610#define SWF06 0x71428
2611#define SWF10 0x70410
2612#define SWF11 0x70414
2613#define SWF14 0x71420
2614#define SWF30 0x72414
2615#define SWF31 0x72418
2616#define SWF32 0x7241c
2617
2618/* Pipe B */
2619#define _PIPEBDSL 0x71000
2620#define _PIPEBCONF 0x71008
2621#define _PIPEBSTAT 0x71024
2622#define _PIPEBFRAMEHIGH 0x71040
2623#define _PIPEBFRAMEPIXEL 0x71044
2624#define _PIPEB_FRMCOUNT_GM45 0x71040
2625#define _PIPEB_FLIPCOUNT_GM45 0x71044
2626
2627
2628/* Display B control */
2629#define _DSPBCNTR 0x71180
2630#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2631#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2632#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2633#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2634#define _DSPBADDR 0x71184
2635#define _DSPBSTRIDE 0x71188
2636#define _DSPBPOS 0x7118C
2637#define _DSPBSIZE 0x71190
2638#define _DSPBSURF 0x7119C
2639#define _DSPBTILEOFF 0x711A4
2640
2641/* VBIOS regs */
2642#define VGACNTRL 0x71400
2643# define VGA_DISP_DISABLE (1 << 31)
2644# define VGA_2X_MODE (1 << 30)
2645# define VGA_PIPE_B_SELECT (1 << 29)
2646
2647/* Ironlake */
2648
2649#define CPU_VGACNTRL 0x41000
2650
2651#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2652#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2653#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2654#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2655#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2656#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2657#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2658#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2659#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2660
2661/* refresh rate hardware control */
2662#define RR_HW_CTL 0x45300
2663#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2664#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2665
2666#define FDI_PLL_BIOS_0 0x46000
2667#define FDI_PLL_FB_CLOCK_MASK 0xff
2668#define FDI_PLL_BIOS_1 0x46004
2669#define FDI_PLL_BIOS_2 0x46008
2670#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2671#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2672#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2673
2674#define PCH_DSPCLK_GATE_D 0x42020
2675# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2676# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2677# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2678# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2679
2680#define PCH_3DCGDIS0 0x46020
2681# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2682# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2683
2684#define PCH_3DCGDIS1 0x46024
2685# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2686
2687#define FDI_PLL_FREQ_CTL 0x46030
2688#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2689#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2690#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2691
2692
2693#define _PIPEA_DATA_M1 0x60030
2694#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2695#define TU_SIZE_MASK 0x7e000000
2696#define PIPE_DATA_M1_OFFSET 0
2697#define _PIPEA_DATA_N1 0x60034
2698#define PIPE_DATA_N1_OFFSET 0
2699
2700#define _PIPEA_DATA_M2 0x60038
2701#define PIPE_DATA_M2_OFFSET 0
2702#define _PIPEA_DATA_N2 0x6003c
2703#define PIPE_DATA_N2_OFFSET 0
2704
2705#define _PIPEA_LINK_M1 0x60040
2706#define PIPE_LINK_M1_OFFSET 0
2707#define _PIPEA_LINK_N1 0x60044
2708#define PIPE_LINK_N1_OFFSET 0
2709
2710#define _PIPEA_LINK_M2 0x60048
2711#define PIPE_LINK_M2_OFFSET 0
2712#define _PIPEA_LINK_N2 0x6004c
2713#define PIPE_LINK_N2_OFFSET 0
2714
2715/* PIPEB timing regs are same start from 0x61000 */
2716
2717#define _PIPEB_DATA_M1 0x61030
2718#define _PIPEB_DATA_N1 0x61034
2719
2720#define _PIPEB_DATA_M2 0x61038
2721#define _PIPEB_DATA_N2 0x6103c
2722
2723#define _PIPEB_LINK_M1 0x61040
2724#define _PIPEB_LINK_N1 0x61044
2725
2726#define _PIPEB_LINK_M2 0x61048
2727#define _PIPEB_LINK_N2 0x6104c
2728
2729#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2730#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2731#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2732#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2733#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2734#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2735#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2736#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2737
2738/* CPU panel fitter */
2739/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2740#define _PFA_CTL_1 0x68080
2741#define _PFB_CTL_1 0x68880
2742#define PF_ENABLE (1<<31)
2743#define PF_FILTER_MASK (3<<23)
2744#define PF_FILTER_PROGRAMMED (0<<23)
2745#define PF_FILTER_MED_3x3 (1<<23)
2746#define PF_FILTER_EDGE_ENHANCE (2<<23)
2747#define PF_FILTER_EDGE_SOFTEN (3<<23)
2748#define _PFA_WIN_SZ 0x68074
2749#define _PFB_WIN_SZ 0x68874
2750#define _PFA_WIN_POS 0x68070
2751#define _PFB_WIN_POS 0x68870
2752#define _PFA_VSCALE 0x68084
2753#define _PFB_VSCALE 0x68884
2754#define _PFA_HSCALE 0x68090
2755#define _PFB_HSCALE 0x68890
2756
2757#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2758#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2759#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2760#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2761#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2762
2763/* legacy palette */
2764#define _LGC_PALETTE_A 0x4a000
2765#define _LGC_PALETTE_B 0x4a800
2766#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2767
2768/* interrupts */
2769#define DE_MASTER_IRQ_CONTROL (1 << 31)
2770#define DE_SPRITEB_FLIP_DONE (1 << 29)
2771#define DE_SPRITEA_FLIP_DONE (1 << 28)
2772#define DE_PLANEB_FLIP_DONE (1 << 27)
2773#define DE_PLANEA_FLIP_DONE (1 << 26)
2774#define DE_PCU_EVENT (1 << 25)
2775#define DE_GTT_FAULT (1 << 24)
2776#define DE_POISON (1 << 23)
2777#define DE_PERFORM_COUNTER (1 << 22)
2778#define DE_PCH_EVENT (1 << 21)
2779#define DE_AUX_CHANNEL_A (1 << 20)
2780#define DE_DP_A_HOTPLUG (1 << 19)
2781#define DE_GSE (1 << 18)
2782#define DE_PIPEB_VBLANK (1 << 15)
2783#define DE_PIPEB_EVEN_FIELD (1 << 14)
2784#define DE_PIPEB_ODD_FIELD (1 << 13)
2785#define DE_PIPEB_LINE_COMPARE (1 << 12)
2786#define DE_PIPEB_VSYNC (1 << 11)
2787#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2788#define DE_PIPEA_VBLANK (1 << 7)
2789#define DE_PIPEA_EVEN_FIELD (1 << 6)
2790#define DE_PIPEA_ODD_FIELD (1 << 5)
2791#define DE_PIPEA_LINE_COMPARE (1 << 4)
2792#define DE_PIPEA_VSYNC (1 << 3)
2793#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2794
2795/* More Ivybridge lolz */
2796#define DE_ERR_DEBUG_IVB (1<<30)
2797#define DE_GSE_IVB (1<<29)
2798#define DE_PCH_EVENT_IVB (1<<28)
2799#define DE_DP_A_HOTPLUG_IVB (1<<27)
2800#define DE_AUX_CHANNEL_A_IVB (1<<26)
2801#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2802#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2803#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2804#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2805#define DE_PIPEB_VBLANK_IVB (1<<5)
2806#define DE_PIPEA_VBLANK_IVB (1<<0)
2807
2808#define DEISR 0x44000
2809#define DEIMR 0x44004
2810#define DEIIR 0x44008
2811#define DEIER 0x4400c
2812
2813/* GT interrupt */
2814#define GT_PIPE_NOTIFY (1 << 4)
2815#define GT_SYNC_STATUS (1 << 2)
2816#define GT_USER_INTERRUPT (1 << 0)
2817#define GT_BSD_USER_INTERRUPT (1 << 5)
2818#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2819#define GT_BLT_USER_INTERRUPT (1 << 22)
2820
2821#define GTISR 0x44010
2822#define GTIMR 0x44014
2823#define GTIIR 0x44018
2824#define GTIER 0x4401c
2825
2826#define ILK_DISPLAY_CHICKEN2 0x42004
2827/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2828#define ILK_ELPIN_409_SELECT (1 << 25)
2829#define ILK_DPARB_GATE (1<<22)
2830#define ILK_VSDPFD_FULL (1<<21)
2831#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2832#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2833#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2834#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2835#define ILK_HDCP_DISABLE (1<<25)
2836#define ILK_eDP_A_DISABLE (1<<24)
2837#define ILK_DESKTOP (1<<23)
2838#define ILK_DSPCLK_GATE 0x42020
2839#define IVB_VRHUNIT_CLK_GATE (1<<28)
2840#define ILK_DPARB_CLK_GATE (1<<5)
2841#define ILK_DPFD_CLK_GATE (1<<7)
2842
2843/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2844#define ILK_CLK_FBC (1<<7)
2845#define ILK_DPFC_DIS1 (1<<8)
2846#define ILK_DPFC_DIS2 (1<<9)
2847
2848#define DISP_ARB_CTL 0x45000
2849#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2850#define DISP_FBC_WM_DIS (1<<15)
2851
2852/* PCH */
2853
2854/* south display engine interrupt */
2855#define SDE_AUDIO_POWER_D (1 << 27)
2856#define SDE_AUDIO_POWER_C (1 << 26)
2857#define SDE_AUDIO_POWER_B (1 << 25)
2858#define SDE_AUDIO_POWER_SHIFT (25)
2859#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2860#define SDE_GMBUS (1 << 24)
2861#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2862#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2863#define SDE_AUDIO_HDCP_MASK (3 << 22)
2864#define SDE_AUDIO_TRANSB (1 << 21)
2865#define SDE_AUDIO_TRANSA (1 << 20)
2866#define SDE_AUDIO_TRANS_MASK (3 << 20)
2867#define SDE_POISON (1 << 19)
2868/* 18 reserved */
2869#define SDE_FDI_RXB (1 << 17)
2870#define SDE_FDI_RXA (1 << 16)
2871#define SDE_FDI_MASK (3 << 16)
2872#define SDE_AUXD (1 << 15)
2873#define SDE_AUXC (1 << 14)
2874#define SDE_AUXB (1 << 13)
2875#define SDE_AUX_MASK (7 << 13)
2876/* 12 reserved */
2877#define SDE_CRT_HOTPLUG (1 << 11)
2878#define SDE_PORTD_HOTPLUG (1 << 10)
2879#define SDE_PORTC_HOTPLUG (1 << 9)
2880#define SDE_PORTB_HOTPLUG (1 << 8)
2881#define SDE_SDVOB_HOTPLUG (1 << 6)
2882#define SDE_HOTPLUG_MASK (0xf << 8)
2883#define SDE_TRANSB_CRC_DONE (1 << 5)
2884#define SDE_TRANSB_CRC_ERR (1 << 4)
2885#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2886#define SDE_TRANSA_CRC_DONE (1 << 2)
2887#define SDE_TRANSA_CRC_ERR (1 << 1)
2888#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2889#define SDE_TRANS_MASK (0x3f)
2890/* CPT */
2891#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2892#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2893#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2894#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2895#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2896 SDE_PORTD_HOTPLUG_CPT | \
2897 SDE_PORTC_HOTPLUG_CPT | \
2898 SDE_PORTB_HOTPLUG_CPT)
2899
2900#define SDEISR 0xc4000
2901#define SDEIMR 0xc4004
2902#define SDEIIR 0xc4008
2903#define SDEIER 0xc400c
2904
2905/* digital port hotplug */
2906#define PCH_PORT_HOTPLUG 0xc4030
2907#define PORTD_HOTPLUG_ENABLE (1 << 20)
2908#define PORTD_PULSE_DURATION_2ms (0)
2909#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2910#define PORTD_PULSE_DURATION_6ms (2 << 18)
2911#define PORTD_PULSE_DURATION_100ms (3 << 18)
2912#define PORTD_HOTPLUG_NO_DETECT (0)
2913#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2914#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2915#define PORTC_HOTPLUG_ENABLE (1 << 12)
2916#define PORTC_PULSE_DURATION_2ms (0)
2917#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2918#define PORTC_PULSE_DURATION_6ms (2 << 10)
2919#define PORTC_PULSE_DURATION_100ms (3 << 10)
2920#define PORTC_HOTPLUG_NO_DETECT (0)
2921#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2922#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2923#define PORTB_HOTPLUG_ENABLE (1 << 4)
2924#define PORTB_PULSE_DURATION_2ms (0)
2925#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2926#define PORTB_PULSE_DURATION_6ms (2 << 2)
2927#define PORTB_PULSE_DURATION_100ms (3 << 2)
2928#define PORTB_HOTPLUG_NO_DETECT (0)
2929#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2930#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2931
2932#define PCH_GPIOA 0xc5010
2933#define PCH_GPIOB 0xc5014
2934#define PCH_GPIOC 0xc5018
2935#define PCH_GPIOD 0xc501c
2936#define PCH_GPIOE 0xc5020
2937#define PCH_GPIOF 0xc5024
2938
2939#define PCH_GMBUS0 0xc5100
2940#define PCH_GMBUS1 0xc5104
2941#define PCH_GMBUS2 0xc5108
2942#define PCH_GMBUS3 0xc510c
2943#define PCH_GMBUS4 0xc5110
2944#define PCH_GMBUS5 0xc5120
2945
2946#define _PCH_DPLL_A 0xc6014
2947#define _PCH_DPLL_B 0xc6018
2948#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2949
2950#define _PCH_FPA0 0xc6040
2951#define FP_CB_TUNE (0x3<<22)
2952#define _PCH_FPA1 0xc6044
2953#define _PCH_FPB0 0xc6048
2954#define _PCH_FPB1 0xc604c
2955#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2956#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2957
2958#define PCH_DPLL_TEST 0xc606c
2959
2960#define PCH_DREF_CONTROL 0xC6200
2961#define DREF_CONTROL_MASK 0x7fc3
2962#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2963#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2964#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2965#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2966#define DREF_SSC_SOURCE_DISABLE (0<<11)
2967#define DREF_SSC_SOURCE_ENABLE (2<<11)
2968#define DREF_SSC_SOURCE_MASK (3<<11)
2969#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2970#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2971#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2972#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2973#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2974#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2975#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2976#define DREF_SSC4_DOWNSPREAD (0<<6)
2977#define DREF_SSC4_CENTERSPREAD (1<<6)
2978#define DREF_SSC1_DISABLE (0<<1)
2979#define DREF_SSC1_ENABLE (1<<1)
2980#define DREF_SSC4_DISABLE (0)
2981#define DREF_SSC4_ENABLE (1)
2982
2983#define PCH_RAWCLK_FREQ 0xc6204
2984#define FDL_TP1_TIMER_SHIFT 12
2985#define FDL_TP1_TIMER_MASK (3<<12)
2986#define FDL_TP2_TIMER_SHIFT 10
2987#define FDL_TP2_TIMER_MASK (3<<10)
2988#define RAWCLK_FREQ_MASK 0x3ff
2989
2990#define PCH_DPLL_TMR_CFG 0xc6208
2991
2992#define PCH_SSC4_PARMS 0xc6210
2993#define PCH_SSC4_AUX_PARMS 0xc6214
2994
2995#define PCH_DPLL_SEL 0xc7000
2996#define TRANSA_DPLL_ENABLE (1<<3)
2997#define TRANSA_DPLLB_SEL (1<<0)
2998#define TRANSA_DPLLA_SEL 0
2999#define TRANSB_DPLL_ENABLE (1<<7)
3000#define TRANSB_DPLLB_SEL (1<<4)
3001#define TRANSB_DPLLA_SEL (0)
3002#define TRANSC_DPLL_ENABLE (1<<11)
3003#define TRANSC_DPLLB_SEL (1<<8)
3004#define TRANSC_DPLLA_SEL (0)
3005
3006/* transcoder */
3007
3008#define _TRANS_HTOTAL_A 0xe0000
3009#define TRANS_HTOTAL_SHIFT 16
3010#define TRANS_HACTIVE_SHIFT 0
3011#define _TRANS_HBLANK_A 0xe0004
3012#define TRANS_HBLANK_END_SHIFT 16
3013#define TRANS_HBLANK_START_SHIFT 0
3014#define _TRANS_HSYNC_A 0xe0008
3015#define TRANS_HSYNC_END_SHIFT 16
3016#define TRANS_HSYNC_START_SHIFT 0
3017#define _TRANS_VTOTAL_A 0xe000c
3018#define TRANS_VTOTAL_SHIFT 16
3019#define TRANS_VACTIVE_SHIFT 0
3020#define _TRANS_VBLANK_A 0xe0010
3021#define TRANS_VBLANK_END_SHIFT 16
3022#define TRANS_VBLANK_START_SHIFT 0
3023#define _TRANS_VSYNC_A 0xe0014
3024#define TRANS_VSYNC_END_SHIFT 16
3025#define TRANS_VSYNC_START_SHIFT 0
3026
3027#define _TRANSA_DATA_M1 0xe0030
3028#define _TRANSA_DATA_N1 0xe0034
3029#define _TRANSA_DATA_M2 0xe0038
3030#define _TRANSA_DATA_N2 0xe003c
3031#define _TRANSA_DP_LINK_M1 0xe0040
3032#define _TRANSA_DP_LINK_N1 0xe0044
3033#define _TRANSA_DP_LINK_M2 0xe0048
3034#define _TRANSA_DP_LINK_N2 0xe004c
3035
3036/* Per-transcoder DIP controls */
3037
3038#define _VIDEO_DIP_CTL_A 0xe0200
3039#define _VIDEO_DIP_DATA_A 0xe0208
3040#define _VIDEO_DIP_GCP_A 0xe0210
3041
3042#define _VIDEO_DIP_CTL_B 0xe1200
3043#define _VIDEO_DIP_DATA_B 0xe1208
3044#define _VIDEO_DIP_GCP_B 0xe1210
3045
3046#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3047#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3048#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3049
3050#define _TRANS_HTOTAL_B 0xe1000
3051#define _TRANS_HBLANK_B 0xe1004
3052#define _TRANS_HSYNC_B 0xe1008
3053#define _TRANS_VTOTAL_B 0xe100c
3054#define _TRANS_VBLANK_B 0xe1010
3055#define _TRANS_VSYNC_B 0xe1014
3056
3057#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3058#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3059#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3060#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3061#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3062#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3063
3064#define _TRANSB_DATA_M1 0xe1030
3065#define _TRANSB_DATA_N1 0xe1034
3066#define _TRANSB_DATA_M2 0xe1038
3067#define _TRANSB_DATA_N2 0xe103c
3068#define _TRANSB_DP_LINK_M1 0xe1040
3069#define _TRANSB_DP_LINK_N1 0xe1044
3070#define _TRANSB_DP_LINK_M2 0xe1048
3071#define _TRANSB_DP_LINK_N2 0xe104c
3072
3073#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3074#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3075#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3076#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3077#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3078#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3079#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3080#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3081
3082#define _TRANSACONF 0xf0008
3083#define _TRANSBCONF 0xf1008
3084#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3085#define TRANS_DISABLE (0<<31)
3086#define TRANS_ENABLE (1<<31)
3087#define TRANS_STATE_MASK (1<<30)
3088#define TRANS_STATE_DISABLE (0<<30)
3089#define TRANS_STATE_ENABLE (1<<30)
3090#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3091#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3092#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3093#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3094#define TRANS_DP_AUDIO_ONLY (1<<26)
3095#define TRANS_DP_VIDEO_AUDIO (0<<26)
3096#define TRANS_PROGRESSIVE (0<<21)
3097#define TRANS_8BPC (0<<5)
3098#define TRANS_10BPC (1<<5)
3099#define TRANS_6BPC (2<<5)
3100#define TRANS_12BPC (3<<5)
3101
3102#define _TRANSA_CHICKEN2 0xf0064
3103#define _TRANSB_CHICKEN2 0xf1064
3104#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3105#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3106
3107#define SOUTH_CHICKEN1 0xc2000
3108#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3109#define FDIA_PHASE_SYNC_SHIFT_EN 18
3110#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3111#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3112#define SOUTH_CHICKEN2 0xc2004
3113#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3114
3115#define _FDI_RXA_CHICKEN 0xc200c
3116#define _FDI_RXB_CHICKEN 0xc2010
3117#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3118#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3119#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3120
3121#define SOUTH_DSPCLK_GATE_D 0xc2020
3122#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3123
3124/* CPU: FDI_TX */
3125#define _FDI_TXA_CTL 0x60100
3126#define _FDI_TXB_CTL 0x61100
3127#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3128#define FDI_TX_DISABLE (0<<31)
3129#define FDI_TX_ENABLE (1<<31)
3130#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3131#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3132#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3133#define FDI_LINK_TRAIN_NONE (3<<28)
3134#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3135#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3136#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3137#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3138#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3139#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3140#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3141#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3142/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3143 SNB has different settings. */
3144/* SNB A-stepping */
3145#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3146#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3147#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3148#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3149/* SNB B-stepping */
3150#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3151#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3152#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3153#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3154#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3155#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3156#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3157#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3158#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3159#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3160/* Ironlake: hardwired to 1 */
3161#define FDI_TX_PLL_ENABLE (1<<14)
3162
3163/* Ivybridge has different bits for lolz */
3164#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3165#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3166#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3167#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3168
3169/* both Tx and Rx */
3170#define FDI_LINK_TRAIN_AUTO (1<<10)
3171#define FDI_SCRAMBLING_ENABLE (0<<7)
3172#define FDI_SCRAMBLING_DISABLE (1<<7)
3173
3174/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3175#define _FDI_RXA_CTL 0xf000c
3176#define _FDI_RXB_CTL 0xf100c
3177#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3178#define FDI_RX_ENABLE (1<<31)
3179/* train, dp width same as FDI_TX */
3180#define FDI_FS_ERRC_ENABLE (1<<27)
3181#define FDI_FE_ERRC_ENABLE (1<<26)
3182#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3183#define FDI_8BPC (0<<16)
3184#define FDI_10BPC (1<<16)
3185#define FDI_6BPC (2<<16)
3186#define FDI_12BPC (3<<16)
3187#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3188#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3189#define FDI_RX_PLL_ENABLE (1<<13)
3190#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3191#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3192#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3193#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3194#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3195#define FDI_PCDCLK (1<<4)
3196/* CPT */
3197#define FDI_AUTO_TRAINING (1<<10)
3198#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3199#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3200#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3201#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3202#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3203
3204#define _FDI_RXA_MISC 0xf0010
3205#define _FDI_RXB_MISC 0xf1010
3206#define _FDI_RXA_TUSIZE1 0xf0030
3207#define _FDI_RXA_TUSIZE2 0xf0038
3208#define _FDI_RXB_TUSIZE1 0xf1030
3209#define _FDI_RXB_TUSIZE2 0xf1038
3210#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3211#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3212#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3213
3214/* FDI_RX interrupt register format */
3215#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3216#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3217#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3218#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3219#define FDI_RX_FS_CODE_ERR (1<<6)
3220#define FDI_RX_FE_CODE_ERR (1<<5)
3221#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3222#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3223#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3224#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3225#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3226
3227#define _FDI_RXA_IIR 0xf0014
3228#define _FDI_RXA_IMR 0xf0018
3229#define _FDI_RXB_IIR 0xf1014
3230#define _FDI_RXB_IMR 0xf1018
3231#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3232#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3233
3234#define FDI_PLL_CTL_1 0xfe000
3235#define FDI_PLL_CTL_2 0xfe004
3236
3237/* CRT */
3238#define PCH_ADPA 0xe1100
3239#define ADPA_TRANS_SELECT_MASK (1<<30)
3240#define ADPA_TRANS_A_SELECT 0
3241#define ADPA_TRANS_B_SELECT (1<<30)
3242#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3243#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3244#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3245#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3246#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3247#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3248#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3249#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3250#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3251#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3252#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3253#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3254#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3255#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3256#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3257#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3258#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3259#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3260#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3261
3262/* or SDVOB */
3263#define HDMIB 0xe1140
3264#define PORT_ENABLE (1 << 31)
3265#define TRANSCODER_A (0)
3266#define TRANSCODER_B (1 << 30)
3267#define TRANSCODER(pipe) ((pipe) << 30)
3268#define TRANSCODER_MASK (1 << 30)
3269#define COLOR_FORMAT_8bpc (0)
3270#define COLOR_FORMAT_12bpc (3 << 26)
3271#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3272#define SDVO_ENCODING (0)
3273#define TMDS_ENCODING (2 << 10)
3274#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3275/* CPT */
3276#define HDMI_MODE_SELECT (1 << 9)
3277#define DVI_MODE_SELECT (0)
3278#define SDVOB_BORDER_ENABLE (1 << 7)
3279#define AUDIO_ENABLE (1 << 6)
3280#define VSYNC_ACTIVE_HIGH (1 << 4)
3281#define HSYNC_ACTIVE_HIGH (1 << 3)
3282#define PORT_DETECTED (1 << 2)
3283
3284/* PCH SDVOB multiplex with HDMIB */
3285#define PCH_SDVOB HDMIB
3286
3287#define HDMIC 0xe1150
3288#define HDMID 0xe1160
3289
3290#define PCH_LVDS 0xe1180
3291#define LVDS_DETECTED (1 << 1)
3292
3293#define BLC_PWM_CPU_CTL2 0x48250
3294#define PWM_ENABLE (1 << 31)
3295#define PWM_PIPE_A (0 << 29)
3296#define PWM_PIPE_B (1 << 29)
3297#define BLC_PWM_CPU_CTL 0x48254
3298
3299#define BLC_PWM_PCH_CTL1 0xc8250
3300#define PWM_PCH_ENABLE (1 << 31)
3301#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3302#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3303#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3304#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3305
3306#define BLC_PWM_PCH_CTL2 0xc8254
3307
3308#define PCH_PP_STATUS 0xc7200
3309#define PCH_PP_CONTROL 0xc7204
3310#define PANEL_UNLOCK_REGS (0xabcd << 16)
3311#define EDP_FORCE_VDD (1 << 3)
3312#define EDP_BLC_ENABLE (1 << 2)
3313#define PANEL_POWER_RESET (1 << 1)
3314#define PANEL_POWER_OFF (0 << 0)
3315#define PANEL_POWER_ON (1 << 0)
3316#define PCH_PP_ON_DELAYS 0xc7208
3317#define EDP_PANEL (1 << 30)
3318#define PCH_PP_OFF_DELAYS 0xc720c
3319#define PCH_PP_DIVISOR 0xc7210
3320
3321#define PCH_DP_B 0xe4100
3322#define PCH_DPB_AUX_CH_CTL 0xe4110
3323#define PCH_DPB_AUX_CH_DATA1 0xe4114
3324#define PCH_DPB_AUX_CH_DATA2 0xe4118
3325#define PCH_DPB_AUX_CH_DATA3 0xe411c
3326#define PCH_DPB_AUX_CH_DATA4 0xe4120
3327#define PCH_DPB_AUX_CH_DATA5 0xe4124
3328
3329#define PCH_DP_C 0xe4200
3330#define PCH_DPC_AUX_CH_CTL 0xe4210
3331#define PCH_DPC_AUX_CH_DATA1 0xe4214
3332#define PCH_DPC_AUX_CH_DATA2 0xe4218
3333#define PCH_DPC_AUX_CH_DATA3 0xe421c
3334#define PCH_DPC_AUX_CH_DATA4 0xe4220
3335#define PCH_DPC_AUX_CH_DATA5 0xe4224
3336
3337#define PCH_DP_D 0xe4300
3338#define PCH_DPD_AUX_CH_CTL 0xe4310
3339#define PCH_DPD_AUX_CH_DATA1 0xe4314
3340#define PCH_DPD_AUX_CH_DATA2 0xe4318
3341#define PCH_DPD_AUX_CH_DATA3 0xe431c
3342#define PCH_DPD_AUX_CH_DATA4 0xe4320
3343#define PCH_DPD_AUX_CH_DATA5 0xe4324
3344
3345/* CPT */
3346#define PORT_TRANS_A_SEL_CPT 0
3347#define PORT_TRANS_B_SEL_CPT (1<<29)
3348#define PORT_TRANS_C_SEL_CPT (2<<29)
3349#define PORT_TRANS_SEL_MASK (3<<29)
3350#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3351
3352#define TRANS_DP_CTL_A 0xe0300
3353#define TRANS_DP_CTL_B 0xe1300
3354#define TRANS_DP_CTL_C 0xe2300
3355#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3356#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3357#define TRANS_DP_PORT_SEL_B (0<<29)
3358#define TRANS_DP_PORT_SEL_C (1<<29)
3359#define TRANS_DP_PORT_SEL_D (2<<29)
3360#define TRANS_DP_PORT_SEL_NONE (3<<29)
3361#define TRANS_DP_PORT_SEL_MASK (3<<29)
3362#define TRANS_DP_AUDIO_ONLY (1<<26)
3363#define TRANS_DP_ENH_FRAMING (1<<18)
3364#define TRANS_DP_8BPC (0<<9)
3365#define TRANS_DP_10BPC (1<<9)
3366#define TRANS_DP_6BPC (2<<9)
3367#define TRANS_DP_12BPC (3<<9)
3368#define TRANS_DP_BPC_MASK (3<<9)
3369#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3370#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3371#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3372#define TRANS_DP_HSYNC_ACTIVE_LOW 0
3373#define TRANS_DP_SYNC_MASK (3<<3)
3374
3375/* SNB eDP training params */
3376/* SNB A-stepping */
3377#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3378#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3379#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3380#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3381/* SNB B-stepping */
3382#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3383#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3384#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3385#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3386#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3387#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3388
3389#define FORCEWAKE 0xA18C
3390#define FORCEWAKE_ACK 0x130090
3391
3392#define GT_FIFO_FREE_ENTRIES 0x120008
3393#define GT_FIFO_NUM_RESERVED_ENTRIES 20
3394
3395#define GEN6_RPNSWREQ 0xA008
3396#define GEN6_TURBO_DISABLE (1<<31)
3397#define GEN6_FREQUENCY(x) ((x)<<25)
3398#define GEN6_OFFSET(x) ((x)<<19)
3399#define GEN6_AGGRESSIVE_TURBO (0<<15)
3400#define GEN6_RC_VIDEO_FREQ 0xA00C
3401#define GEN6_RC_CONTROL 0xA090
3402#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3403#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3404#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3405#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3406#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3407#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3408#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3409#define GEN6_RP_DOWN_TIMEOUT 0xA010
3410#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3411#define GEN6_RPSTAT1 0xA01C
3412#define GEN6_CAGF_SHIFT 8
3413#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3414#define GEN6_RP_CONTROL 0xA024
3415#define GEN6_RP_MEDIA_TURBO (1<<11)
3416#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3417#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3418#define GEN6_RP_ENABLE (1<<7)
3419#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3420#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3421#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3422#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3423#define GEN6_RP_UP_THRESHOLD 0xA02C
3424#define GEN6_RP_DOWN_THRESHOLD 0xA030
3425#define GEN6_RP_CUR_UP_EI 0xA050
3426#define GEN6_CURICONT_MASK 0xffffff
3427#define GEN6_RP_CUR_UP 0xA054
3428#define GEN6_CURBSYTAVG_MASK 0xffffff
3429#define GEN6_RP_PREV_UP 0xA058
3430#define GEN6_RP_CUR_DOWN_EI 0xA05C
3431#define GEN6_CURIAVG_MASK 0xffffff
3432#define GEN6_RP_CUR_DOWN 0xA060
3433#define GEN6_RP_PREV_DOWN 0xA064
3434#define GEN6_RP_UP_EI 0xA068
3435#define GEN6_RP_DOWN_EI 0xA06C
3436#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3437#define GEN6_RC_STATE 0xA094
3438#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3439#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3440#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3441#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3442#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3443#define GEN6_RC_SLEEP 0xA0B0
3444#define GEN6_RC1e_THRESHOLD 0xA0B4
3445#define GEN6_RC6_THRESHOLD 0xA0B8
3446#define GEN6_RC6p_THRESHOLD 0xA0BC
3447#define GEN6_RC6pp_THRESHOLD 0xA0C0
3448#define GEN6_PMINTRMSK 0xA168
3449
3450#define GEN6_PMISR 0x44020
3451#define GEN6_PMIMR 0x44024 /* rps_lock */
3452#define GEN6_PMIIR 0x44028
3453#define GEN6_PMIER 0x4402C
3454#define GEN6_PM_MBOX_EVENT (1<<25)
3455#define GEN6_PM_THERMAL_EVENT (1<<24)
3456#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3457#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3458#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3459#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3460#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3461#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3462 GEN6_PM_RP_DOWN_THRESHOLD | \
3463 GEN6_PM_RP_DOWN_TIMEOUT)
3464
3465#define GEN6_PCODE_MAILBOX 0x138124
3466#define GEN6_PCODE_READY (1<<31)
3467#define GEN6_READ_OC_PARAMS 0xc
3468#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3469#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3470#define GEN6_PCODE_DATA 0x138128
3471#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3472
3473#endif /* _I915_REG_H_ */