Loading...
Note: File does not exist in v5.4.
1/*
2 * Netburst Performance Events (P4, old Xeon)
3 *
4 * Copyright (C) 2010 Parallels, Inc., Cyrill Gorcunov <gorcunov@openvz.org>
5 * Copyright (C) 2010 Intel Corporation, Lin Ming <ming.m.lin@intel.com>
6 *
7 * For licencing details see kernel-base/COPYING
8 */
9
10#ifdef CONFIG_CPU_SUP_INTEL
11
12#include <asm/perf_event_p4.h>
13
14#define P4_CNTR_LIMIT 3
15/*
16 * array indices: 0,1 - HT threads, used with HT enabled cpu
17 */
18struct p4_event_bind {
19 unsigned int opcode; /* Event code and ESCR selector */
20 unsigned int escr_msr[2]; /* ESCR MSR for this event */
21 unsigned int escr_emask; /* valid ESCR EventMask bits */
22 unsigned int shared; /* event is shared across threads */
23 char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */
24};
25
26struct p4_pebs_bind {
27 unsigned int metric_pebs;
28 unsigned int metric_vert;
29};
30
31/* it sets P4_PEBS_ENABLE_UOP_TAG as well */
32#define P4_GEN_PEBS_BIND(name, pebs, vert) \
33 [P4_PEBS_METRIC__##name] = { \
34 .metric_pebs = pebs | P4_PEBS_ENABLE_UOP_TAG, \
35 .metric_vert = vert, \
36 }
37
38/*
39 * note we have P4_PEBS_ENABLE_UOP_TAG always set here
40 *
41 * it's needed for mapping P4_PEBS_CONFIG_METRIC_MASK bits of
42 * event configuration to find out which values are to be
43 * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
44 * resgisters
45 */
46static struct p4_pebs_bind p4_pebs_bind_map[] = {
47 P4_GEN_PEBS_BIND(1stl_cache_load_miss_retired, 0x0000001, 0x0000001),
48 P4_GEN_PEBS_BIND(2ndl_cache_load_miss_retired, 0x0000002, 0x0000001),
49 P4_GEN_PEBS_BIND(dtlb_load_miss_retired, 0x0000004, 0x0000001),
50 P4_GEN_PEBS_BIND(dtlb_store_miss_retired, 0x0000004, 0x0000002),
51 P4_GEN_PEBS_BIND(dtlb_all_miss_retired, 0x0000004, 0x0000003),
52 P4_GEN_PEBS_BIND(tagged_mispred_branch, 0x0018000, 0x0000010),
53 P4_GEN_PEBS_BIND(mob_load_replay_retired, 0x0000200, 0x0000001),
54 P4_GEN_PEBS_BIND(split_load_retired, 0x0000400, 0x0000001),
55 P4_GEN_PEBS_BIND(split_store_retired, 0x0000400, 0x0000002),
56};
57
58/*
59 * Note that we don't use CCCR1 here, there is an
60 * exception for P4_BSQ_ALLOCATION but we just have
61 * no workaround
62 *
63 * consider this binding as resources which particular
64 * event may borrow, it doesn't contain EventMask,
65 * Tags and friends -- they are left to a caller
66 */
67static struct p4_event_bind p4_event_bind_map[] = {
68 [P4_EVENT_TC_DELIVER_MODE] = {
69 .opcode = P4_OPCODE(P4_EVENT_TC_DELIVER_MODE),
70 .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
71 .escr_emask =
72 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) |
73 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DB) |
74 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DI) |
75 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BD) |
76 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BB) |
77 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BI) |
78 P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, ID),
79 .shared = 1,
80 .cntr = { {4, 5, -1}, {6, 7, -1} },
81 },
82 [P4_EVENT_BPU_FETCH_REQUEST] = {
83 .opcode = P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST),
84 .escr_msr = { MSR_P4_BPU_ESCR0, MSR_P4_BPU_ESCR1 },
85 .escr_emask =
86 P4_ESCR_EMASK_BIT(P4_EVENT_BPU_FETCH_REQUEST, TCMISS),
87 .cntr = { {0, -1, -1}, {2, -1, -1} },
88 },
89 [P4_EVENT_ITLB_REFERENCE] = {
90 .opcode = P4_OPCODE(P4_EVENT_ITLB_REFERENCE),
91 .escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
92 .escr_emask =
93 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT) |
94 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, MISS) |
95 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT_UK),
96 .cntr = { {0, -1, -1}, {2, -1, -1} },
97 },
98 [P4_EVENT_MEMORY_CANCEL] = {
99 .opcode = P4_OPCODE(P4_EVENT_MEMORY_CANCEL),
100 .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
101 .escr_emask =
102 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL) |
103 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_CANCEL, 64K_CONF),
104 .cntr = { {8, 9, -1}, {10, 11, -1} },
105 },
106 [P4_EVENT_MEMORY_COMPLETE] = {
107 .opcode = P4_OPCODE(P4_EVENT_MEMORY_COMPLETE),
108 .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
109 .escr_emask =
110 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_COMPLETE, LSC) |
111 P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_COMPLETE, SSC),
112 .cntr = { {8, 9, -1}, {10, 11, -1} },
113 },
114 [P4_EVENT_LOAD_PORT_REPLAY] = {
115 .opcode = P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY),
116 .escr_msr = { MSR_P4_SAAT_ESCR0, MSR_P4_SAAT_ESCR1 },
117 .escr_emask =
118 P4_ESCR_EMASK_BIT(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD),
119 .cntr = { {8, 9, -1}, {10, 11, -1} },
120 },
121 [P4_EVENT_STORE_PORT_REPLAY] = {
122 .opcode = P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY),
123 .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
124 .escr_emask =
125 P4_ESCR_EMASK_BIT(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST),
126 .cntr = { {8, 9, -1}, {10, 11, -1} },
127 },
128 [P4_EVENT_MOB_LOAD_REPLAY] = {
129 .opcode = P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY),
130 .escr_msr = { MSR_P4_MOB_ESCR0, MSR_P4_MOB_ESCR1 },
131 .escr_emask =
132 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, NO_STA) |
133 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, NO_STD) |
134 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA) |
135 P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR),
136 .cntr = { {0, -1, -1}, {2, -1, -1} },
137 },
138 [P4_EVENT_PAGE_WALK_TYPE] = {
139 .opcode = P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE),
140 .escr_msr = { MSR_P4_PMH_ESCR0, MSR_P4_PMH_ESCR1 },
141 .escr_emask =
142 P4_ESCR_EMASK_BIT(P4_EVENT_PAGE_WALK_TYPE, DTMISS) |
143 P4_ESCR_EMASK_BIT(P4_EVENT_PAGE_WALK_TYPE, ITMISS),
144 .shared = 1,
145 .cntr = { {0, -1, -1}, {2, -1, -1} },
146 },
147 [P4_EVENT_BSQ_CACHE_REFERENCE] = {
148 .opcode = P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),
149 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
150 .escr_emask =
151 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
152 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
153 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
154 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
155 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
156 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM) |
157 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
158 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
159 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),
160 .cntr = { {0, -1, -1}, {2, -1, -1} },
161 },
162 [P4_EVENT_IOQ_ALLOCATION] = {
163 .opcode = P4_OPCODE(P4_EVENT_IOQ_ALLOCATION),
164 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
165 .escr_emask =
166 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, DEFAULT) |
167 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, ALL_READ) |
168 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE) |
169 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_UC) |
170 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WC) |
171 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WT) |
172 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WP) |
173 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WB) |
174 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, OWN) |
175 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, OTHER) |
176 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, PREFETCH),
177 .cntr = { {0, -1, -1}, {2, -1, -1} },
178 },
179 [P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */
180 .opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES),
181 .escr_msr = { MSR_P4_FSB_ESCR1, MSR_P4_FSB_ESCR1 },
182 .escr_emask =
183 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT) |
184 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ) |
185 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE) |
186 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC) |
187 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC) |
188 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT) |
189 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP) |
190 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB) |
191 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN) |
192 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER) |
193 P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH),
194 .cntr = { {2, -1, -1}, {3, -1, -1} },
195 },
196 [P4_EVENT_FSB_DATA_ACTIVITY] = {
197 .opcode = P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY),
198 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
199 .escr_emask =
200 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
201 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN) |
202 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER) |
203 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV) |
204 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN) |
205 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER),
206 .shared = 1,
207 .cntr = { {0, -1, -1}, {2, -1, -1} },
208 },
209 [P4_EVENT_BSQ_ALLOCATION] = { /* shared ESCR, broken CCCR1 */
210 .opcode = P4_OPCODE(P4_EVENT_BSQ_ALLOCATION),
211 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR0 },
212 .escr_emask =
213 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0) |
214 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1) |
215 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0) |
216 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1) |
217 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE) |
218 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE) |
219 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE) |
220 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE) |
221 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE) |
222 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE) |
223 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0) |
224 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1) |
225 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2),
226 .cntr = { {0, -1, -1}, {1, -1, -1} },
227 },
228 [P4_EVENT_BSQ_ACTIVE_ENTRIES] = { /* shared ESCR */
229 .opcode = P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES),
230 .escr_msr = { MSR_P4_BSU_ESCR1 , MSR_P4_BSU_ESCR1 },
231 .escr_emask =
232 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0) |
233 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1) |
234 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0) |
235 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1) |
236 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE) |
237 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE) |
238 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE) |
239 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE) |
240 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE) |
241 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE) |
242 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0) |
243 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1) |
244 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2),
245 .cntr = { {2, -1, -1}, {3, -1, -1} },
246 },
247 [P4_EVENT_SSE_INPUT_ASSIST] = {
248 .opcode = P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST),
249 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
250 .escr_emask =
251 P4_ESCR_EMASK_BIT(P4_EVENT_SSE_INPUT_ASSIST, ALL),
252 .shared = 1,
253 .cntr = { {8, 9, -1}, {10, 11, -1} },
254 },
255 [P4_EVENT_PACKED_SP_UOP] = {
256 .opcode = P4_OPCODE(P4_EVENT_PACKED_SP_UOP),
257 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
258 .escr_emask =
259 P4_ESCR_EMASK_BIT(P4_EVENT_PACKED_SP_UOP, ALL),
260 .shared = 1,
261 .cntr = { {8, 9, -1}, {10, 11, -1} },
262 },
263 [P4_EVENT_PACKED_DP_UOP] = {
264 .opcode = P4_OPCODE(P4_EVENT_PACKED_DP_UOP),
265 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
266 .escr_emask =
267 P4_ESCR_EMASK_BIT(P4_EVENT_PACKED_DP_UOP, ALL),
268 .shared = 1,
269 .cntr = { {8, 9, -1}, {10, 11, -1} },
270 },
271 [P4_EVENT_SCALAR_SP_UOP] = {
272 .opcode = P4_OPCODE(P4_EVENT_SCALAR_SP_UOP),
273 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
274 .escr_emask =
275 P4_ESCR_EMASK_BIT(P4_EVENT_SCALAR_SP_UOP, ALL),
276 .shared = 1,
277 .cntr = { {8, 9, -1}, {10, 11, -1} },
278 },
279 [P4_EVENT_SCALAR_DP_UOP] = {
280 .opcode = P4_OPCODE(P4_EVENT_SCALAR_DP_UOP),
281 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
282 .escr_emask =
283 P4_ESCR_EMASK_BIT(P4_EVENT_SCALAR_DP_UOP, ALL),
284 .shared = 1,
285 .cntr = { {8, 9, -1}, {10, 11, -1} },
286 },
287 [P4_EVENT_64BIT_MMX_UOP] = {
288 .opcode = P4_OPCODE(P4_EVENT_64BIT_MMX_UOP),
289 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
290 .escr_emask =
291 P4_ESCR_EMASK_BIT(P4_EVENT_64BIT_MMX_UOP, ALL),
292 .shared = 1,
293 .cntr = { {8, 9, -1}, {10, 11, -1} },
294 },
295 [P4_EVENT_128BIT_MMX_UOP] = {
296 .opcode = P4_OPCODE(P4_EVENT_128BIT_MMX_UOP),
297 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
298 .escr_emask =
299 P4_ESCR_EMASK_BIT(P4_EVENT_128BIT_MMX_UOP, ALL),
300 .shared = 1,
301 .cntr = { {8, 9, -1}, {10, 11, -1} },
302 },
303 [P4_EVENT_X87_FP_UOP] = {
304 .opcode = P4_OPCODE(P4_EVENT_X87_FP_UOP),
305 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
306 .escr_emask =
307 P4_ESCR_EMASK_BIT(P4_EVENT_X87_FP_UOP, ALL),
308 .shared = 1,
309 .cntr = { {8, 9, -1}, {10, 11, -1} },
310 },
311 [P4_EVENT_TC_MISC] = {
312 .opcode = P4_OPCODE(P4_EVENT_TC_MISC),
313 .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
314 .escr_emask =
315 P4_ESCR_EMASK_BIT(P4_EVENT_TC_MISC, FLUSH),
316 .cntr = { {4, 5, -1}, {6, 7, -1} },
317 },
318 [P4_EVENT_GLOBAL_POWER_EVENTS] = {
319 .opcode = P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS),
320 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
321 .escr_emask =
322 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING),
323 .cntr = { {0, -1, -1}, {2, -1, -1} },
324 },
325 [P4_EVENT_TC_MS_XFER] = {
326 .opcode = P4_OPCODE(P4_EVENT_TC_MS_XFER),
327 .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
328 .escr_emask =
329 P4_ESCR_EMASK_BIT(P4_EVENT_TC_MS_XFER, CISC),
330 .cntr = { {4, 5, -1}, {6, 7, -1} },
331 },
332 [P4_EVENT_UOP_QUEUE_WRITES] = {
333 .opcode = P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES),
334 .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
335 .escr_emask =
336 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD) |
337 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER) |
338 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM),
339 .cntr = { {4, 5, -1}, {6, 7, -1} },
340 },
341 [P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE] = {
342 .opcode = P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE),
343 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
344 .escr_emask =
345 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL) |
346 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL) |
347 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN) |
348 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT),
349 .cntr = { {4, 5, -1}, {6, 7, -1} },
350 },
351 [P4_EVENT_RETIRED_BRANCH_TYPE] = {
352 .opcode = P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE),
353 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
354 .escr_emask =
355 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
356 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
357 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
358 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT),
359 .cntr = { {4, 5, -1}, {6, 7, -1} },
360 },
361 [P4_EVENT_RESOURCE_STALL] = {
362 .opcode = P4_OPCODE(P4_EVENT_RESOURCE_STALL),
363 .escr_msr = { MSR_P4_ALF_ESCR0, MSR_P4_ALF_ESCR1 },
364 .escr_emask =
365 P4_ESCR_EMASK_BIT(P4_EVENT_RESOURCE_STALL, SBFULL),
366 .cntr = { {12, 13, 16}, {14, 15, 17} },
367 },
368 [P4_EVENT_WC_BUFFER] = {
369 .opcode = P4_OPCODE(P4_EVENT_WC_BUFFER),
370 .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
371 .escr_emask =
372 P4_ESCR_EMASK_BIT(P4_EVENT_WC_BUFFER, WCB_EVICTS) |
373 P4_ESCR_EMASK_BIT(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS),
374 .shared = 1,
375 .cntr = { {8, 9, -1}, {10, 11, -1} },
376 },
377 [P4_EVENT_B2B_CYCLES] = {
378 .opcode = P4_OPCODE(P4_EVENT_B2B_CYCLES),
379 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
380 .escr_emask = 0,
381 .cntr = { {0, -1, -1}, {2, -1, -1} },
382 },
383 [P4_EVENT_BNR] = {
384 .opcode = P4_OPCODE(P4_EVENT_BNR),
385 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
386 .escr_emask = 0,
387 .cntr = { {0, -1, -1}, {2, -1, -1} },
388 },
389 [P4_EVENT_SNOOP] = {
390 .opcode = P4_OPCODE(P4_EVENT_SNOOP),
391 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
392 .escr_emask = 0,
393 .cntr = { {0, -1, -1}, {2, -1, -1} },
394 },
395 [P4_EVENT_RESPONSE] = {
396 .opcode = P4_OPCODE(P4_EVENT_RESPONSE),
397 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
398 .escr_emask = 0,
399 .cntr = { {0, -1, -1}, {2, -1, -1} },
400 },
401 [P4_EVENT_FRONT_END_EVENT] = {
402 .opcode = P4_OPCODE(P4_EVENT_FRONT_END_EVENT),
403 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
404 .escr_emask =
405 P4_ESCR_EMASK_BIT(P4_EVENT_FRONT_END_EVENT, NBOGUS) |
406 P4_ESCR_EMASK_BIT(P4_EVENT_FRONT_END_EVENT, BOGUS),
407 .cntr = { {12, 13, 16}, {14, 15, 17} },
408 },
409 [P4_EVENT_EXECUTION_EVENT] = {
410 .opcode = P4_OPCODE(P4_EVENT_EXECUTION_EVENT),
411 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
412 .escr_emask =
413 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0) |
414 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1) |
415 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2) |
416 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3) |
417 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
418 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
419 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
420 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3),
421 .cntr = { {12, 13, 16}, {14, 15, 17} },
422 },
423 [P4_EVENT_REPLAY_EVENT] = {
424 .opcode = P4_OPCODE(P4_EVENT_REPLAY_EVENT),
425 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
426 .escr_emask =
427 P4_ESCR_EMASK_BIT(P4_EVENT_REPLAY_EVENT, NBOGUS) |
428 P4_ESCR_EMASK_BIT(P4_EVENT_REPLAY_EVENT, BOGUS),
429 .cntr = { {12, 13, 16}, {14, 15, 17} },
430 },
431 [P4_EVENT_INSTR_RETIRED] = {
432 .opcode = P4_OPCODE(P4_EVENT_INSTR_RETIRED),
433 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
434 .escr_emask =
435 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
436 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSTAG) |
437 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG) |
438 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSTAG),
439 .cntr = { {12, 13, 16}, {14, 15, 17} },
440 },
441 [P4_EVENT_UOPS_RETIRED] = {
442 .opcode = P4_OPCODE(P4_EVENT_UOPS_RETIRED),
443 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
444 .escr_emask =
445 P4_ESCR_EMASK_BIT(P4_EVENT_UOPS_RETIRED, NBOGUS) |
446 P4_ESCR_EMASK_BIT(P4_EVENT_UOPS_RETIRED, BOGUS),
447 .cntr = { {12, 13, 16}, {14, 15, 17} },
448 },
449 [P4_EVENT_UOP_TYPE] = {
450 .opcode = P4_OPCODE(P4_EVENT_UOP_TYPE),
451 .escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
452 .escr_emask =
453 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_TYPE, TAGLOADS) |
454 P4_ESCR_EMASK_BIT(P4_EVENT_UOP_TYPE, TAGSTORES),
455 .cntr = { {12, 13, 16}, {14, 15, 17} },
456 },
457 [P4_EVENT_BRANCH_RETIRED] = {
458 .opcode = P4_OPCODE(P4_EVENT_BRANCH_RETIRED),
459 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
460 .escr_emask =
461 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMNP) |
462 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMNM) |
463 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMTP) |
464 P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMTM),
465 .cntr = { {12, 13, 16}, {14, 15, 17} },
466 },
467 [P4_EVENT_MISPRED_BRANCH_RETIRED] = {
468 .opcode = P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
469 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
470 .escr_emask =
471 P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
472 .cntr = { {12, 13, 16}, {14, 15, 17} },
473 },
474 [P4_EVENT_X87_ASSIST] = {
475 .opcode = P4_OPCODE(P4_EVENT_X87_ASSIST),
476 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
477 .escr_emask =
478 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, FPSU) |
479 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, FPSO) |
480 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, POAO) |
481 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, POAU) |
482 P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, PREA),
483 .cntr = { {12, 13, 16}, {14, 15, 17} },
484 },
485 [P4_EVENT_MACHINE_CLEAR] = {
486 .opcode = P4_OPCODE(P4_EVENT_MACHINE_CLEAR),
487 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
488 .escr_emask =
489 P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, CLEAR) |
490 P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, MOCLEAR) |
491 P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, SMCLEAR),
492 .cntr = { {12, 13, 16}, {14, 15, 17} },
493 },
494 [P4_EVENT_INSTR_COMPLETED] = {
495 .opcode = P4_OPCODE(P4_EVENT_INSTR_COMPLETED),
496 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
497 .escr_emask =
498 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_COMPLETED, NBOGUS) |
499 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_COMPLETED, BOGUS),
500 .cntr = { {12, 13, 16}, {14, 15, 17} },
501 },
502};
503
504#define P4_GEN_CACHE_EVENT(event, bit, metric) \
505 p4_config_pack_escr(P4_ESCR_EVENT(event) | \
506 P4_ESCR_EMASK_BIT(event, bit)) | \
507 p4_config_pack_cccr(metric | \
508 P4_CCCR_ESEL(P4_OPCODE_ESEL(P4_OPCODE(event))))
509
510static __initconst const u64 p4_hw_cache_event_ids
511 [PERF_COUNT_HW_CACHE_MAX]
512 [PERF_COUNT_HW_CACHE_OP_MAX]
513 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
514{
515 [ C(L1D ) ] = {
516 [ C(OP_READ) ] = {
517 [ C(RESULT_ACCESS) ] = 0x0,
518 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
519 P4_PEBS_METRIC__1stl_cache_load_miss_retired),
520 },
521 },
522 [ C(LL ) ] = {
523 [ C(OP_READ) ] = {
524 [ C(RESULT_ACCESS) ] = 0x0,
525 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
526 P4_PEBS_METRIC__2ndl_cache_load_miss_retired),
527 },
528},
529 [ C(DTLB) ] = {
530 [ C(OP_READ) ] = {
531 [ C(RESULT_ACCESS) ] = 0x0,
532 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
533 P4_PEBS_METRIC__dtlb_load_miss_retired),
534 },
535 [ C(OP_WRITE) ] = {
536 [ C(RESULT_ACCESS) ] = 0x0,
537 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
538 P4_PEBS_METRIC__dtlb_store_miss_retired),
539 },
540 },
541 [ C(ITLB) ] = {
542 [ C(OP_READ) ] = {
543 [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
544 P4_PEBS_METRIC__none),
545 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
546 P4_PEBS_METRIC__none),
547 },
548 [ C(OP_WRITE) ] = {
549 [ C(RESULT_ACCESS) ] = -1,
550 [ C(RESULT_MISS) ] = -1,
551 },
552 [ C(OP_PREFETCH) ] = {
553 [ C(RESULT_ACCESS) ] = -1,
554 [ C(RESULT_MISS) ] = -1,
555 },
556 },
557 [ C(NODE) ] = {
558 [ C(OP_READ) ] = {
559 [ C(RESULT_ACCESS) ] = -1,
560 [ C(RESULT_MISS) ] = -1,
561 },
562 [ C(OP_WRITE) ] = {
563 [ C(RESULT_ACCESS) ] = -1,
564 [ C(RESULT_MISS) ] = -1,
565 },
566 [ C(OP_PREFETCH) ] = {
567 [ C(RESULT_ACCESS) ] = -1,
568 [ C(RESULT_MISS) ] = -1,
569 },
570 },
571};
572
573/*
574 * Because of Netburst being quite restricted in how many
575 * identical events may run simultaneously, we introduce event aliases,
576 * ie the different events which have the same functionality but
577 * utilize non-intersected resources (ESCR/CCCR/counter registers).
578 *
579 * This allow us to relax restrictions a bit and run two or more
580 * identical events together.
581 *
582 * Never set any custom internal bits such as P4_CONFIG_HT,
583 * P4_CONFIG_ALIASABLE or bits for P4_PEBS_METRIC, they are
584 * either up to date automatically or not applicable at all.
585 */
586struct p4_event_alias {
587 u64 original;
588 u64 alternative;
589} p4_event_aliases[] = {
590 {
591 /*
592 * Non-halted cycles can be substituted with non-sleeping cycles (see
593 * Intel SDM Vol3b for details). We need this alias to be able
594 * to run nmi-watchdog and 'perf top' (or any other user space tool
595 * which is interested in running PERF_COUNT_HW_CPU_CYCLES)
596 * simultaneously.
597 */
598 .original =
599 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
600 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
601 .alternative =
602 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_EXECUTION_EVENT) |
603 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0)|
604 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1)|
605 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2)|
606 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3)|
607 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
608 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
609 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
610 P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3))|
611 p4_config_pack_cccr(P4_CCCR_THRESHOLD(15) | P4_CCCR_COMPLEMENT |
612 P4_CCCR_COMPARE),
613 },
614};
615
616static u64 p4_get_alias_event(u64 config)
617{
618 u64 config_match;
619 int i;
620
621 /*
622 * Only event with special mark is allowed,
623 * we're to be sure it didn't come as malformed
624 * RAW event.
625 */
626 if (!(config & P4_CONFIG_ALIASABLE))
627 return 0;
628
629 config_match = config & P4_CONFIG_EVENT_ALIAS_MASK;
630
631 for (i = 0; i < ARRAY_SIZE(p4_event_aliases); i++) {
632 if (config_match == p4_event_aliases[i].original) {
633 config_match = p4_event_aliases[i].alternative;
634 break;
635 } else if (config_match == p4_event_aliases[i].alternative) {
636 config_match = p4_event_aliases[i].original;
637 break;
638 }
639 }
640
641 if (i >= ARRAY_SIZE(p4_event_aliases))
642 return 0;
643
644 return config_match | (config & P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS);
645}
646
647static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
648 /* non-halted CPU clocks */
649 [PERF_COUNT_HW_CPU_CYCLES] =
650 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
651 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)) |
652 P4_CONFIG_ALIASABLE,
653
654 /*
655 * retired instructions
656 * in a sake of simplicity we don't use the FSB tagging
657 */
658 [PERF_COUNT_HW_INSTRUCTIONS] =
659 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_INSTR_RETIRED) |
660 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
661 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG)),
662
663 /* cache hits */
664 [PERF_COUNT_HW_CACHE_REFERENCES] =
665 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
666 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
667 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
668 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
669 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
670 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
671 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),
672
673 /* cache misses */
674 [PERF_COUNT_HW_CACHE_MISSES] =
675 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
676 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
677 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
678 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),
679
680 /* branch instructions retired */
681 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =
682 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_RETIRED_BRANCH_TYPE) |
683 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
684 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
685 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
686 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT)),
687
688 /* mispredicted branches retired */
689 [PERF_COUNT_HW_BRANCH_MISSES] =
690 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_MISPRED_BRANCH_RETIRED) |
691 P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS)),
692
693 /* bus ready clocks (cpu is driving #DRDY_DRV\#DRDY_OWN): */
694 [PERF_COUNT_HW_BUS_CYCLES] =
695 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_FSB_DATA_ACTIVITY) |
696 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
697 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN)) |
698 p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
699};
700
701static struct p4_event_bind *p4_config_get_bind(u64 config)
702{
703 unsigned int evnt = p4_config_unpack_event(config);
704 struct p4_event_bind *bind = NULL;
705
706 if (evnt < ARRAY_SIZE(p4_event_bind_map))
707 bind = &p4_event_bind_map[evnt];
708
709 return bind;
710}
711
712static u64 p4_pmu_event_map(int hw_event)
713{
714 struct p4_event_bind *bind;
715 unsigned int esel;
716 u64 config;
717
718 config = p4_general_events[hw_event];
719 bind = p4_config_get_bind(config);
720 esel = P4_OPCODE_ESEL(bind->opcode);
721 config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
722
723 return config;
724}
725
726/* check cpu model specifics */
727static bool p4_event_match_cpu_model(unsigned int event_idx)
728{
729 /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
730 if (event_idx == P4_EVENT_INSTR_COMPLETED) {
731 if (boot_cpu_data.x86_model != 3 &&
732 boot_cpu_data.x86_model != 4 &&
733 boot_cpu_data.x86_model != 6)
734 return false;
735 }
736
737 /*
738 * For info
739 * - IQ_ESCR0, IQ_ESCR1 only for models 1 and 2
740 */
741
742 return true;
743}
744
745static int p4_validate_raw_event(struct perf_event *event)
746{
747 unsigned int v, emask;
748
749 /* User data may have out-of-bound event index */
750 v = p4_config_unpack_event(event->attr.config);
751 if (v >= ARRAY_SIZE(p4_event_bind_map))
752 return -EINVAL;
753
754 /* It may be unsupported: */
755 if (!p4_event_match_cpu_model(v))
756 return -EINVAL;
757
758 /*
759 * NOTE: P4_CCCR_THREAD_ANY has not the same meaning as
760 * in Architectural Performance Monitoring, it means not
761 * on _which_ logical cpu to count but rather _when_, ie it
762 * depends on logical cpu state -- count event if one cpu active,
763 * none, both or any, so we just allow user to pass any value
764 * desired.
765 *
766 * In turn we always set Tx_OS/Tx_USR bits bound to logical
767 * cpu without their propagation to another cpu
768 */
769
770 /*
771 * if an event is shared across the logical threads
772 * the user needs special permissions to be able to use it
773 */
774 if (p4_ht_active() && p4_event_bind_map[v].shared) {
775 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
776 return -EACCES;
777 }
778
779 /* ESCR EventMask bits may be invalid */
780 emask = p4_config_unpack_escr(event->attr.config) & P4_ESCR_EVENTMASK_MASK;
781 if (emask & ~p4_event_bind_map[v].escr_emask)
782 return -EINVAL;
783
784 /*
785 * it may have some invalid PEBS bits
786 */
787 if (p4_config_pebs_has(event->attr.config, P4_PEBS_CONFIG_ENABLE))
788 return -EINVAL;
789
790 v = p4_config_unpack_metric(event->attr.config);
791 if (v >= ARRAY_SIZE(p4_pebs_bind_map))
792 return -EINVAL;
793
794 return 0;
795}
796
797static int p4_hw_config(struct perf_event *event)
798{
799 int cpu = get_cpu();
800 int rc = 0;
801 u32 escr, cccr;
802
803 /*
804 * the reason we use cpu that early is that: if we get scheduled
805 * first time on the same cpu -- we will not need swap thread
806 * specific flags in config (and will save some cpu cycles)
807 */
808
809 cccr = p4_default_cccr_conf(cpu);
810 escr = p4_default_escr_conf(cpu, event->attr.exclude_kernel,
811 event->attr.exclude_user);
812 event->hw.config = p4_config_pack_escr(escr) |
813 p4_config_pack_cccr(cccr);
814
815 if (p4_ht_active() && p4_ht_thread(cpu))
816 event->hw.config = p4_set_ht_bit(event->hw.config);
817
818 if (event->attr.type == PERF_TYPE_RAW) {
819 struct p4_event_bind *bind;
820 unsigned int esel;
821 /*
822 * Clear bits we reserve to be managed by kernel itself
823 * and never allowed from a user space
824 */
825 event->attr.config &= P4_CONFIG_MASK;
826
827 rc = p4_validate_raw_event(event);
828 if (rc)
829 goto out;
830
831 /*
832 * Note that for RAW events we allow user to use P4_CCCR_RESERVED
833 * bits since we keep additional info here (for cache events and etc)
834 */
835 event->hw.config |= event->attr.config;
836 bind = p4_config_get_bind(event->attr.config);
837 if (!bind) {
838 rc = -EINVAL;
839 goto out;
840 }
841 esel = P4_OPCODE_ESEL(bind->opcode);
842 event->hw.config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
843 }
844
845 rc = x86_setup_perfctr(event);
846out:
847 put_cpu();
848 return rc;
849}
850
851static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
852{
853 u64 v;
854
855 /* an official way for overflow indication */
856 rdmsrl(hwc->config_base, v);
857 if (v & P4_CCCR_OVF) {
858 wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF);
859 return 1;
860 }
861
862 /*
863 * In some circumstances the overflow might issue an NMI but did
864 * not set P4_CCCR_OVF bit. Because a counter holds a negative value
865 * we simply check for high bit being set, if it's cleared it means
866 * the counter has reached zero value and continued counting before
867 * real NMI signal was received:
868 */
869 rdmsrl(hwc->event_base, v);
870 if (!(v & ARCH_P4_UNFLAGGED_BIT))
871 return 1;
872
873 return 0;
874}
875
876static void p4_pmu_disable_pebs(void)
877{
878 /*
879 * FIXME
880 *
881 * It's still allowed that two threads setup same cache
882 * events so we can't simply clear metrics until we knew
883 * no one is depending on us, so we need kind of counter
884 * for "ReplayEvent" users.
885 *
886 * What is more complex -- RAW events, if user (for some
887 * reason) will pass some cache event metric with improper
888 * event opcode -- it's fine from hardware point of view
889 * but completely nonsense from "meaning" of such action.
890 *
891 * So at moment let leave metrics turned on forever -- it's
892 * ok for now but need to be revisited!
893 *
894 * (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)0);
895 * (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
896 */
897}
898
899static inline void p4_pmu_disable_event(struct perf_event *event)
900{
901 struct hw_perf_event *hwc = &event->hw;
902
903 /*
904 * If event gets disabled while counter is in overflowed
905 * state we need to clear P4_CCCR_OVF, otherwise interrupt get
906 * asserted again and again
907 */
908 (void)checking_wrmsrl(hwc->config_base,
909 (u64)(p4_config_unpack_cccr(hwc->config)) &
910 ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
911}
912
913static void p4_pmu_disable_all(void)
914{
915 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
916 int idx;
917
918 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
919 struct perf_event *event = cpuc->events[idx];
920 if (!test_bit(idx, cpuc->active_mask))
921 continue;
922 p4_pmu_disable_event(event);
923 }
924
925 p4_pmu_disable_pebs();
926}
927
928/* configuration must be valid */
929static void p4_pmu_enable_pebs(u64 config)
930{
931 struct p4_pebs_bind *bind;
932 unsigned int idx;
933
934 BUILD_BUG_ON(P4_PEBS_METRIC__max > P4_PEBS_CONFIG_METRIC_MASK);
935
936 idx = p4_config_unpack_metric(config);
937 if (idx == P4_PEBS_METRIC__none)
938 return;
939
940 bind = &p4_pebs_bind_map[idx];
941
942 (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs);
943 (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert);
944}
945
946static void p4_pmu_enable_event(struct perf_event *event)
947{
948 struct hw_perf_event *hwc = &event->hw;
949 int thread = p4_ht_config_thread(hwc->config);
950 u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
951 unsigned int idx = p4_config_unpack_event(hwc->config);
952 struct p4_event_bind *bind;
953 u64 escr_addr, cccr;
954
955 bind = &p4_event_bind_map[idx];
956 escr_addr = (u64)bind->escr_msr[thread];
957
958 /*
959 * - we dont support cascaded counters yet
960 * - and counter 1 is broken (erratum)
961 */
962 WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
963 WARN_ON_ONCE(hwc->idx == 1);
964
965 /* we need a real Event value */
966 escr_conf &= ~P4_ESCR_EVENT_MASK;
967 escr_conf |= P4_ESCR_EVENT(P4_OPCODE_EVNT(bind->opcode));
968
969 cccr = p4_config_unpack_cccr(hwc->config);
970
971 /*
972 * it could be Cache event so we need to write metrics
973 * into additional MSRs
974 */
975 p4_pmu_enable_pebs(hwc->config);
976
977 (void)checking_wrmsrl(escr_addr, escr_conf);
978 (void)checking_wrmsrl(hwc->config_base,
979 (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
980}
981
982static void p4_pmu_enable_all(int added)
983{
984 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
985 int idx;
986
987 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
988 struct perf_event *event = cpuc->events[idx];
989 if (!test_bit(idx, cpuc->active_mask))
990 continue;
991 p4_pmu_enable_event(event);
992 }
993}
994
995static int p4_pmu_handle_irq(struct pt_regs *regs)
996{
997 struct perf_sample_data data;
998 struct cpu_hw_events *cpuc;
999 struct perf_event *event;
1000 struct hw_perf_event *hwc;
1001 int idx, handled = 0;
1002 u64 val;
1003
1004 perf_sample_data_init(&data, 0);
1005
1006 cpuc = &__get_cpu_var(cpu_hw_events);
1007
1008 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1009 int overflow;
1010
1011 if (!test_bit(idx, cpuc->active_mask)) {
1012 /* catch in-flight IRQs */
1013 if (__test_and_clear_bit(idx, cpuc->running))
1014 handled++;
1015 continue;
1016 }
1017
1018 event = cpuc->events[idx];
1019 hwc = &event->hw;
1020
1021 WARN_ON_ONCE(hwc->idx != idx);
1022
1023 /* it might be unflagged overflow */
1024 overflow = p4_pmu_clear_cccr_ovf(hwc);
1025
1026 val = x86_perf_event_update(event);
1027 if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1))))
1028 continue;
1029
1030 handled += overflow;
1031
1032 /* event overflow for sure */
1033 data.period = event->hw.last_period;
1034
1035 if (!x86_perf_event_set_period(event))
1036 continue;
1037 if (perf_event_overflow(event, &data, regs))
1038 x86_pmu_stop(event, 0);
1039 }
1040
1041 if (handled)
1042 inc_irq_stat(apic_perf_irqs);
1043
1044 /*
1045 * When dealing with the unmasking of the LVTPC on P4 perf hw, it has
1046 * been observed that the OVF bit flag has to be cleared first _before_
1047 * the LVTPC can be unmasked.
1048 *
1049 * The reason is the NMI line will continue to be asserted while the OVF
1050 * bit is set. This causes a second NMI to generate if the LVTPC is
1051 * unmasked before the OVF bit is cleared, leading to unknown NMI
1052 * messages.
1053 */
1054 apic_write(APIC_LVTPC, APIC_DM_NMI);
1055
1056 return handled;
1057}
1058
1059/*
1060 * swap thread specific fields according to a thread
1061 * we are going to run on
1062 */
1063static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
1064{
1065 u32 escr, cccr;
1066
1067 /*
1068 * we either lucky and continue on same cpu or no HT support
1069 */
1070 if (!p4_should_swap_ts(hwc->config, cpu))
1071 return;
1072
1073 /*
1074 * the event is migrated from an another logical
1075 * cpu, so we need to swap thread specific flags
1076 */
1077
1078 escr = p4_config_unpack_escr(hwc->config);
1079 cccr = p4_config_unpack_cccr(hwc->config);
1080
1081 if (p4_ht_thread(cpu)) {
1082 cccr &= ~P4_CCCR_OVF_PMI_T0;
1083 cccr |= P4_CCCR_OVF_PMI_T1;
1084 if (escr & P4_ESCR_T0_OS) {
1085 escr &= ~P4_ESCR_T0_OS;
1086 escr |= P4_ESCR_T1_OS;
1087 }
1088 if (escr & P4_ESCR_T0_USR) {
1089 escr &= ~P4_ESCR_T0_USR;
1090 escr |= P4_ESCR_T1_USR;
1091 }
1092 hwc->config = p4_config_pack_escr(escr);
1093 hwc->config |= p4_config_pack_cccr(cccr);
1094 hwc->config |= P4_CONFIG_HT;
1095 } else {
1096 cccr &= ~P4_CCCR_OVF_PMI_T1;
1097 cccr |= P4_CCCR_OVF_PMI_T0;
1098 if (escr & P4_ESCR_T1_OS) {
1099 escr &= ~P4_ESCR_T1_OS;
1100 escr |= P4_ESCR_T0_OS;
1101 }
1102 if (escr & P4_ESCR_T1_USR) {
1103 escr &= ~P4_ESCR_T1_USR;
1104 escr |= P4_ESCR_T0_USR;
1105 }
1106 hwc->config = p4_config_pack_escr(escr);
1107 hwc->config |= p4_config_pack_cccr(cccr);
1108 hwc->config &= ~P4_CONFIG_HT;
1109 }
1110}
1111
1112/*
1113 * ESCR address hashing is tricky, ESCRs are not sequential
1114 * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and
1115 * the metric between any ESCRs is laid in range [0xa0,0xe1]
1116 *
1117 * so we make ~70% filled hashtable
1118 */
1119
1120#define P4_ESCR_MSR_BASE 0x000003a0
1121#define P4_ESCR_MSR_MAX 0x000003e1
1122#define P4_ESCR_MSR_TABLE_SIZE (P4_ESCR_MSR_MAX - P4_ESCR_MSR_BASE + 1)
1123#define P4_ESCR_MSR_IDX(msr) (msr - P4_ESCR_MSR_BASE)
1124#define P4_ESCR_MSR_TABLE_ENTRY(msr) [P4_ESCR_MSR_IDX(msr)] = msr
1125
1126static const unsigned int p4_escr_table[P4_ESCR_MSR_TABLE_SIZE] = {
1127 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR0),
1128 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR1),
1129 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR0),
1130 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR1),
1131 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR0),
1132 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR1),
1133 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR0),
1134 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR1),
1135 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR2),
1136 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR3),
1137 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR4),
1138 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR5),
1139 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR0),
1140 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR1),
1141 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR0),
1142 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR1),
1143 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR0),
1144 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR1),
1145 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR0),
1146 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR1),
1147 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR0),
1148 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR1),
1149 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR0),
1150 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR1),
1151 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR0),
1152 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR1),
1153 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR0),
1154 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR1),
1155 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR0),
1156 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR1),
1157 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR0),
1158 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR1),
1159 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR0),
1160 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR1),
1161 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR0),
1162 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR1),
1163 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR0),
1164 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR1),
1165 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR0),
1166 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR1),
1167 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR0),
1168 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR1),
1169 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR0),
1170 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR1),
1171 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR0),
1172 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR1),
1173};
1174
1175static int p4_get_escr_idx(unsigned int addr)
1176{
1177 unsigned int idx = P4_ESCR_MSR_IDX(addr);
1178
1179 if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE ||
1180 !p4_escr_table[idx] ||
1181 p4_escr_table[idx] != addr)) {
1182 WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);
1183 return -1;
1184 }
1185
1186 return idx;
1187}
1188
1189static int p4_next_cntr(int thread, unsigned long *used_mask,
1190 struct p4_event_bind *bind)
1191{
1192 int i, j;
1193
1194 for (i = 0; i < P4_CNTR_LIMIT; i++) {
1195 j = bind->cntr[thread][i];
1196 if (j != -1 && !test_bit(j, used_mask))
1197 return j;
1198 }
1199
1200 return -1;
1201}
1202
1203static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1204{
1205 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1206 unsigned long escr_mask[BITS_TO_LONGS(P4_ESCR_MSR_TABLE_SIZE)];
1207 int cpu = smp_processor_id();
1208 struct hw_perf_event *hwc;
1209 struct p4_event_bind *bind;
1210 unsigned int i, thread, num;
1211 int cntr_idx, escr_idx;
1212 u64 config_alias;
1213 int pass;
1214
1215 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1216 bitmap_zero(escr_mask, P4_ESCR_MSR_TABLE_SIZE);
1217
1218 for (i = 0, num = n; i < n; i++, num--) {
1219
1220 hwc = &cpuc->event_list[i]->hw;
1221 thread = p4_ht_thread(cpu);
1222 pass = 0;
1223
1224again:
1225 /*
1226 * It's possible to hit a circular lock
1227 * between original and alternative events
1228 * if both are scheduled already.
1229 */
1230 if (pass > 2)
1231 goto done;
1232
1233 bind = p4_config_get_bind(hwc->config);
1234 escr_idx = p4_get_escr_idx(bind->escr_msr[thread]);
1235 if (unlikely(escr_idx == -1))
1236 goto done;
1237
1238 if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) {
1239 cntr_idx = hwc->idx;
1240 if (assign)
1241 assign[i] = hwc->idx;
1242 goto reserve;
1243 }
1244
1245 cntr_idx = p4_next_cntr(thread, used_mask, bind);
1246 if (cntr_idx == -1 || test_bit(escr_idx, escr_mask)) {
1247 /*
1248 * Check whether an event alias is still available.
1249 */
1250 config_alias = p4_get_alias_event(hwc->config);
1251 if (!config_alias)
1252 goto done;
1253 hwc->config = config_alias;
1254 pass++;
1255 goto again;
1256 }
1257
1258 p4_pmu_swap_config_ts(hwc, cpu);
1259 if (assign)
1260 assign[i] = cntr_idx;
1261reserve:
1262 set_bit(cntr_idx, used_mask);
1263 set_bit(escr_idx, escr_mask);
1264 }
1265
1266done:
1267 return num ? -ENOSPC : 0;
1268}
1269
1270static __initconst const struct x86_pmu p4_pmu = {
1271 .name = "Netburst P4/Xeon",
1272 .handle_irq = p4_pmu_handle_irq,
1273 .disable_all = p4_pmu_disable_all,
1274 .enable_all = p4_pmu_enable_all,
1275 .enable = p4_pmu_enable_event,
1276 .disable = p4_pmu_disable_event,
1277 .eventsel = MSR_P4_BPU_CCCR0,
1278 .perfctr = MSR_P4_BPU_PERFCTR0,
1279 .event_map = p4_pmu_event_map,
1280 .max_events = ARRAY_SIZE(p4_general_events),
1281 .get_event_constraints = x86_get_event_constraints,
1282 /*
1283 * IF HT disabled we may need to use all
1284 * ARCH_P4_MAX_CCCR counters simulaneously
1285 * though leave it restricted at moment assuming
1286 * HT is on
1287 */
1288 .num_counters = ARCH_P4_MAX_CCCR,
1289 .apic = 1,
1290 .cntval_bits = ARCH_P4_CNTRVAL_BITS,
1291 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
1292 .max_period = (1ULL << (ARCH_P4_CNTRVAL_BITS - 1)) - 1,
1293 .hw_config = p4_hw_config,
1294 .schedule_events = p4_pmu_schedule_events,
1295 /*
1296 * This handles erratum N15 in intel doc 249199-029,
1297 * the counter may not be updated correctly on write
1298 * so we need a second write operation to do the trick
1299 * (the official workaround didn't work)
1300 *
1301 * the former idea is taken from OProfile code
1302 */
1303 .perfctr_second_write = 1,
1304};
1305
1306static __init int p4_pmu_init(void)
1307{
1308 unsigned int low, high;
1309
1310 /* If we get stripped -- indexing fails */
1311 BUILD_BUG_ON(ARCH_P4_MAX_CCCR > X86_PMC_MAX_GENERIC);
1312
1313 rdmsr(MSR_IA32_MISC_ENABLE, low, high);
1314 if (!(low & (1 << 7))) {
1315 pr_cont("unsupported Netburst CPU model %d ",
1316 boot_cpu_data.x86_model);
1317 return -ENODEV;
1318 }
1319
1320 memcpy(hw_cache_event_ids, p4_hw_cache_event_ids,
1321 sizeof(hw_cache_event_ids));
1322
1323 pr_cont("Netburst events, ");
1324
1325 x86_pmu = p4_pmu;
1326
1327 return 0;
1328}
1329
1330#endif /* CONFIG_CPU_SUP_INTEL */