1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef _ASM_SPARC64_TOPOLOGY_H
 3#define _ASM_SPARC64_TOPOLOGY_H
 4
 5#ifdef CONFIG_NUMA
 6
 7#include <asm/mmzone.h>
 8
 9static inline int cpu_to_node(int cpu)
10{
11	return numa_cpu_lookup_table[cpu];
12}
13
 
 
14#define cpumask_of_node(node) ((node) == -1 ?				\
15			       cpu_all_mask :				\
16			       &numa_cpumask_lookup_table[node])
17
18struct pci_bus;
19#ifdef CONFIG_PCI
20int pcibus_to_node(struct pci_bus *pbus);
21#else
22static inline int pcibus_to_node(struct pci_bus *pbus)
23{
24	return -1;
25}
26#endif
27
28#define cpumask_of_pcibus(bus)	\
29	(pcibus_to_node(bus) == -1 ? \
30	 cpu_all_mask : \
31	 cpumask_of_node(pcibus_to_node(bus)))
32
33int __node_distance(int, int);
34#define node_distance(a, b) __node_distance(a, b)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
35
36#else /* CONFIG_NUMA */
37
38#include <asm-generic/topology.h>
39
40#endif /* !(CONFIG_NUMA) */
41
42#ifdef CONFIG_SMP
43
44#include <asm/cpudata.h>
45
46#define topology_physical_package_id(cpu)	(cpu_data(cpu).proc_id)
47#define topology_core_id(cpu)			(cpu_data(cpu).core_id)
48#define topology_core_cpumask(cpu)		(&cpu_core_sib_map[cpu])
49#define topology_core_cache_cpumask(cpu)	(&cpu_core_sib_cache_map[cpu])
50#define topology_sibling_cpumask(cpu)		(&per_cpu(cpu_sibling_map, cpu))
 
51#endif /* CONFIG_SMP */
52
53extern cpumask_t cpu_core_map[NR_CPUS];
54extern cpumask_t cpu_core_sib_map[NR_CPUS];
55extern cpumask_t cpu_core_sib_cache_map[NR_CPUS];
56
57/**
58 * Return cores that shares the last level cache.
59 */
60static inline const struct cpumask *cpu_coregroup_mask(int cpu)
61{
62	return &cpu_core_sib_cache_map[cpu];
63}
64
65#endif /* _ASM_SPARC64_TOPOLOGY_H */

 
 1#ifndef _ASM_SPARC64_TOPOLOGY_H
 2#define _ASM_SPARC64_TOPOLOGY_H
 3
 4#ifdef CONFIG_NUMA
 5
 6#include <asm/mmzone.h>
 7
 8static inline int cpu_to_node(int cpu)
 9{
10	return numa_cpu_lookup_table[cpu];
11}
12
13#define parent_node(node)	(node)
14
15#define cpumask_of_node(node) ((node) == -1 ?				\
16			       cpu_all_mask :				\
17			       &numa_cpumask_lookup_table[node])
18
19struct pci_bus;
20#ifdef CONFIG_PCI
21extern int pcibus_to_node(struct pci_bus *pbus);
22#else
23static inline int pcibus_to_node(struct pci_bus *pbus)
24{
25	return -1;
26}
27#endif
28
29#define cpumask_of_pcibus(bus)	\
30	(pcibus_to_node(bus) == -1 ? \
31	 cpu_all_mask : \
32	 cpumask_of_node(pcibus_to_node(bus)))
33
34#define SD_NODE_INIT (struct sched_domain) {		\
35	.min_interval		= 8,			\
36	.max_interval		= 32,			\
37	.busy_factor		= 32,			\
38	.imbalance_pct		= 125,			\
39	.cache_nice_tries	= 2,			\
40	.busy_idx		= 3,			\
41	.idle_idx		= 2,			\
42	.newidle_idx		= 0, 			\
43	.wake_idx		= 0,			\
44	.forkexec_idx		= 0,			\
45	.flags			= SD_LOAD_BALANCE	\
46				| SD_BALANCE_FORK	\
47				| SD_BALANCE_EXEC	\
48				| SD_SERIALIZE,		\
49	.last_balance		= jiffies,		\
50	.balance_interval	= 1,			\
51}
52
53#else /* CONFIG_NUMA */
54
55#include <asm-generic/topology.h>
56
57#endif /* !(CONFIG_NUMA) */
58
59#ifdef CONFIG_SMP
 
 
 
60#define topology_physical_package_id(cpu)	(cpu_data(cpu).proc_id)
61#define topology_core_id(cpu)			(cpu_data(cpu).core_id)
62#define topology_core_cpumask(cpu)		(&cpu_core_map[cpu])
63#define topology_thread_cpumask(cpu)		(&per_cpu(cpu_sibling_map, cpu))
64#define mc_capable()				(sparc64_multi_core)
65#define smt_capable()				(sparc64_multi_core)
66#endif /* CONFIG_SMP */
67
68extern cpumask_t cpu_core_map[NR_CPUS];
 
 
 
 
 
 
69static inline const struct cpumask *cpu_coregroup_mask(int cpu)
70{
71        return &cpu_core_map[cpu];
72}
73
74#endif /* _ASM_SPARC64_TOPOLOGY_H */