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v5.4
  1// SPDX-License-Identifier: GPL-2.0
  2#include <linux/seq_file.h>
  3#include <linux/kernel.h>
  4#include <linux/module.h>
  5#include <asm/machvec.h>
  6#include <asm/processor.h>
  7
  8static const char *cpu_name[] = {
  9	[CPU_SH7201]	= "SH7201",
 10	[CPU_SH7203]	= "SH7203",	[CPU_SH7263]	= "SH7263",
 11	[CPU_SH7264]	= "SH7264",	[CPU_SH7269]	= "SH7269",
 12	[CPU_SH7206]	= "SH7206",	[CPU_SH7619]	= "SH7619",
 13	[CPU_SH7705]	= "SH7705",	[CPU_SH7706]	= "SH7706",
 14	[CPU_SH7707]	= "SH7707",	[CPU_SH7708]	= "SH7708",
 15	[CPU_SH7709]	= "SH7709",	[CPU_SH7710]	= "SH7710",
 16	[CPU_SH7712]	= "SH7712",	[CPU_SH7720]	= "SH7720",
 17	[CPU_SH7721]	= "SH7721",	[CPU_SH7729]	= "SH7729",
 18	[CPU_SH7750]	= "SH7750",	[CPU_SH7750S]	= "SH7750S",
 19	[CPU_SH7750R]	= "SH7750R",	[CPU_SH7751]	= "SH7751",
 20	[CPU_SH7751R]	= "SH7751R",	[CPU_SH7760]	= "SH7760",
 21	[CPU_SH4_202]	= "SH4-202",	[CPU_SH4_501]	= "SH4-501",
 22	[CPU_SH7763]	= "SH7763",	[CPU_SH7770]	= "SH7770",
 23	[CPU_SH7780]	= "SH7780",	[CPU_SH7781]	= "SH7781",
 24	[CPU_SH7343]	= "SH7343",	[CPU_SH7785]	= "SH7785",
 25	[CPU_SH7786]	= "SH7786",	[CPU_SH7757]	= "SH7757",
 26	[CPU_SH7722]	= "SH7722",	[CPU_SHX3]	= "SH-X3",
 27	[CPU_SH5_101]	= "SH5-101",	[CPU_SH5_103]	= "SH5-103",
 28	[CPU_MXG]	= "MX-G",	[CPU_SH7723]	= "SH7723",
 29	[CPU_SH7366]	= "SH7366",	[CPU_SH7724]	= "SH7724",
 30	[CPU_SH7372]	= "SH7372",	[CPU_SH7734]	= "SH7734",
 31	[CPU_J2]	= "J2",
 32	[CPU_SH_NONE]	= "Unknown"
 33};
 34
 35const char *get_cpu_subtype(struct sh_cpuinfo *c)
 36{
 37	return cpu_name[c->type];
 38}
 39EXPORT_SYMBOL(get_cpu_subtype);
 40
 41#ifdef CONFIG_PROC_FS
 42/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
 43static const char *cpu_flags[] = {
 44	"none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
 45	"ptea", "llsc", "l2", "op32", "pteaex", NULL
 46};
 47
 48static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
 49{
 50	unsigned long i;
 51
 52	seq_printf(m, "cpu flags\t:");
 53
 54	if (!c->flags) {
 55		seq_printf(m, " %s\n", cpu_flags[0]);
 56		return;
 57	}
 58
 59	for (i = 0; cpu_flags[i]; i++)
 60		if ((c->flags & (1 << i)))
 61			seq_printf(m, " %s", cpu_flags[i+1]);
 62
 63	seq_printf(m, "\n");
 64}
 65
 66static void show_cacheinfo(struct seq_file *m, const char *type,
 67			   struct cache_info info)
 68{
 69	unsigned int cache_size;
 70
 71	cache_size = info.ways * info.sets * info.linesz;
 72
 73	seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
 74		   type, cache_size >> 10, info.ways);
 75}
 76
 77/*
 78 *	Get CPU information for use by the procfs.
 79 */
 80static int show_cpuinfo(struct seq_file *m, void *v)
 81{
 82	struct sh_cpuinfo *c = v;
 83	unsigned int cpu = c - cpu_data;
 84
 85	if (!cpu_online(cpu))
 86		return 0;
 87
 88	if (cpu == 0)
 89		seq_printf(m, "machine\t\t: %s\n", get_system_type());
 90	else
 91		seq_printf(m, "\n");
 92
 93	seq_printf(m, "processor\t: %d\n", cpu);
 94	seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
 95	seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
 96	if (c->cut_major == -1)
 97		seq_printf(m, "cut\t\t: unknown\n");
 98	else if (c->cut_minor == -1)
 99		seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
100	else
101		seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
102
103	show_cpuflags(m, c);
104
105	seq_printf(m, "cache type\t: ");
106
107	/*
108	 * Check for what type of cache we have, we support both the
109	 * unified cache on the SH-2 and SH-3, as well as the harvard
110	 * style cache on the SH-4.
111	 */
112	if (c->icache.flags & SH_CACHE_COMBINED) {
113		seq_printf(m, "unified\n");
114		show_cacheinfo(m, "cache", c->icache);
115	} else {
116		seq_printf(m, "split (harvard)\n");
117		show_cacheinfo(m, "icache", c->icache);
118		show_cacheinfo(m, "dcache", c->dcache);
119	}
120
121	/* Optional secondary cache */
122	if (c->flags & CPU_HAS_L2_CACHE)
123		show_cacheinfo(m, "scache", c->scache);
124
125	seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
126
127	seq_printf(m, "bogomips\t: %lu.%02lu\n",
128		     c->loops_per_jiffy/(500000/HZ),
129		     (c->loops_per_jiffy/(5000/HZ)) % 100);
130
131	return 0;
132}
133
134static void *c_start(struct seq_file *m, loff_t *pos)
135{
136	return *pos < NR_CPUS ? cpu_data + *pos : NULL;
137}
138static void *c_next(struct seq_file *m, void *v, loff_t *pos)
139{
140	++*pos;
141	return c_start(m, pos);
142}
143static void c_stop(struct seq_file *m, void *v)
144{
145}
146const struct seq_operations cpuinfo_op = {
147	.start	= c_start,
148	.next	= c_next,
149	.stop	= c_stop,
150	.show	= show_cpuinfo,
151};
152#endif /* CONFIG_PROC_FS */
v3.1
 
  1#include <linux/seq_file.h>
  2#include <linux/kernel.h>
  3#include <linux/module.h>
  4#include <asm/machvec.h>
  5#include <asm/processor.h>
  6
  7static const char *cpu_name[] = {
  8	[CPU_SH7201]	= "SH7201",
  9	[CPU_SH7203]	= "SH7203",	[CPU_SH7263]	= "SH7263",
 
 10	[CPU_SH7206]	= "SH7206",	[CPU_SH7619]	= "SH7619",
 11	[CPU_SH7705]	= "SH7705",	[CPU_SH7706]	= "SH7706",
 12	[CPU_SH7707]	= "SH7707",	[CPU_SH7708]	= "SH7708",
 13	[CPU_SH7709]	= "SH7709",	[CPU_SH7710]	= "SH7710",
 14	[CPU_SH7712]	= "SH7712",	[CPU_SH7720]	= "SH7720",
 15	[CPU_SH7721]	= "SH7721",	[CPU_SH7729]	= "SH7729",
 16	[CPU_SH7750]	= "SH7750",	[CPU_SH7750S]	= "SH7750S",
 17	[CPU_SH7750R]	= "SH7750R",	[CPU_SH7751]	= "SH7751",
 18	[CPU_SH7751R]	= "SH7751R",	[CPU_SH7760]	= "SH7760",
 19	[CPU_SH4_202]	= "SH4-202",	[CPU_SH4_501]	= "SH4-501",
 20	[CPU_SH7763]	= "SH7763",	[CPU_SH7770]	= "SH7770",
 21	[CPU_SH7780]	= "SH7780",	[CPU_SH7781]	= "SH7781",
 22	[CPU_SH7343]	= "SH7343",	[CPU_SH7785]	= "SH7785",
 23	[CPU_SH7786]	= "SH7786",	[CPU_SH7757]	= "SH7757",
 24	[CPU_SH7722]	= "SH7722",	[CPU_SHX3]	= "SH-X3",
 25	[CPU_SH5_101]	= "SH5-101",	[CPU_SH5_103]	= "SH5-103",
 26	[CPU_MXG]	= "MX-G",	[CPU_SH7723]	= "SH7723",
 27	[CPU_SH7366]	= "SH7366",	[CPU_SH7724]	= "SH7724",
 28	[CPU_SH7372]	= "SH7372",	[CPU_SH_NONE]	= "Unknown"
 
 
 29};
 30
 31const char *get_cpu_subtype(struct sh_cpuinfo *c)
 32{
 33	return cpu_name[c->type];
 34}
 35EXPORT_SYMBOL(get_cpu_subtype);
 36
 37#ifdef CONFIG_PROC_FS
 38/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
 39static const char *cpu_flags[] = {
 40	"none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
 41	"ptea", "llsc", "l2", "op32", "pteaex", NULL
 42};
 43
 44static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
 45{
 46	unsigned long i;
 47
 48	seq_printf(m, "cpu flags\t:");
 49
 50	if (!c->flags) {
 51		seq_printf(m, " %s\n", cpu_flags[0]);
 52		return;
 53	}
 54
 55	for (i = 0; cpu_flags[i]; i++)
 56		if ((c->flags & (1 << i)))
 57			seq_printf(m, " %s", cpu_flags[i+1]);
 58
 59	seq_printf(m, "\n");
 60}
 61
 62static void show_cacheinfo(struct seq_file *m, const char *type,
 63			   struct cache_info info)
 64{
 65	unsigned int cache_size;
 66
 67	cache_size = info.ways * info.sets * info.linesz;
 68
 69	seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
 70		   type, cache_size >> 10, info.ways);
 71}
 72
 73/*
 74 *	Get CPU information for use by the procfs.
 75 */
 76static int show_cpuinfo(struct seq_file *m, void *v)
 77{
 78	struct sh_cpuinfo *c = v;
 79	unsigned int cpu = c - cpu_data;
 80
 81	if (!cpu_online(cpu))
 82		return 0;
 83
 84	if (cpu == 0)
 85		seq_printf(m, "machine\t\t: %s\n", get_system_type());
 86	else
 87		seq_printf(m, "\n");
 88
 89	seq_printf(m, "processor\t: %d\n", cpu);
 90	seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
 91	seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
 92	if (c->cut_major == -1)
 93		seq_printf(m, "cut\t\t: unknown\n");
 94	else if (c->cut_minor == -1)
 95		seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
 96	else
 97		seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
 98
 99	show_cpuflags(m, c);
100
101	seq_printf(m, "cache type\t: ");
102
103	/*
104	 * Check for what type of cache we have, we support both the
105	 * unified cache on the SH-2 and SH-3, as well as the harvard
106	 * style cache on the SH-4.
107	 */
108	if (c->icache.flags & SH_CACHE_COMBINED) {
109		seq_printf(m, "unified\n");
110		show_cacheinfo(m, "cache", c->icache);
111	} else {
112		seq_printf(m, "split (harvard)\n");
113		show_cacheinfo(m, "icache", c->icache);
114		show_cacheinfo(m, "dcache", c->dcache);
115	}
116
117	/* Optional secondary cache */
118	if (c->flags & CPU_HAS_L2_CACHE)
119		show_cacheinfo(m, "scache", c->scache);
120
121	seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
122
123	seq_printf(m, "bogomips\t: %lu.%02lu\n",
124		     c->loops_per_jiffy/(500000/HZ),
125		     (c->loops_per_jiffy/(5000/HZ)) % 100);
126
127	return 0;
128}
129
130static void *c_start(struct seq_file *m, loff_t *pos)
131{
132	return *pos < NR_CPUS ? cpu_data + *pos : NULL;
133}
134static void *c_next(struct seq_file *m, void *v, loff_t *pos)
135{
136	++*pos;
137	return c_start(m, pos);
138}
139static void c_stop(struct seq_file *m, void *v)
140{
141}
142const struct seq_operations cpuinfo_op = {
143	.start	= c_start,
144	.next	= c_next,
145	.stop	= c_stop,
146	.show	= show_cpuinfo,
147};
148#endif /* CONFIG_PROC_FS */