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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2000, 2001 Kanoj Sarcar
5 * Copyright (C) 2000, 2001 Ralf Baechle
6 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
7 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
8 */
9#include <linux/cache.h>
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/smp.h>
14#include <linux/spinlock.h>
15#include <linux/threads.h>
16#include <linux/export.h>
17#include <linux/time.h>
18#include <linux/timex.h>
19#include <linux/sched/mm.h>
20#include <linux/cpumask.h>
21#include <linux/cpu.h>
22#include <linux/err.h>
23#include <linux/ftrace.h>
24#include <linux/irqdomain.h>
25#include <linux/of.h>
26#include <linux/of_irq.h>
27
28#include <linux/atomic.h>
29#include <asm/cpu.h>
30#include <asm/ginvt.h>
31#include <asm/processor.h>
32#include <asm/idle.h>
33#include <asm/r4k-timer.h>
34#include <asm/mips-cps.h>
35#include <asm/mmu_context.h>
36#include <asm/time.h>
37#include <asm/setup.h>
38#include <asm/maar.h>
39
40int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP]; /* Map physical to logical */
41EXPORT_SYMBOL(__cpu_number_map);
42
43int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
44EXPORT_SYMBOL(__cpu_logical_map);
45
46/* Number of TCs (or siblings in Intel speak) per CPU core */
47int smp_num_siblings = 1;
48EXPORT_SYMBOL(smp_num_siblings);
49
50/* representing the TCs (or siblings in Intel speak) of each logical CPU */
51cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
52EXPORT_SYMBOL(cpu_sibling_map);
53
54/* representing the core map of multi-core chips of each logical CPU */
55cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
56EXPORT_SYMBOL(cpu_core_map);
57
58static DECLARE_COMPLETION(cpu_starting);
59static DECLARE_COMPLETION(cpu_running);
60
61/*
62 * A logcal cpu mask containing only one VPE per core to
63 * reduce the number of IPIs on large MT systems.
64 */
65cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
66EXPORT_SYMBOL(cpu_foreign_map);
67
68/* representing cpus for which sibling maps can be computed */
69static cpumask_t cpu_sibling_setup_map;
70
71/* representing cpus for which core maps can be computed */
72static cpumask_t cpu_core_setup_map;
73
74cpumask_t cpu_coherent_mask;
75
76#ifdef CONFIG_GENERIC_IRQ_IPI
77static struct irq_desc *call_desc;
78static struct irq_desc *sched_desc;
79#endif
80
81static inline void set_cpu_sibling_map(int cpu)
82{
83 int i;
84
85 cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
86
87 if (smp_num_siblings > 1) {
88 for_each_cpu(i, &cpu_sibling_setup_map) {
89 if (cpus_are_siblings(cpu, i)) {
90 cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
91 cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
92 }
93 }
94 } else
95 cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
96}
97
98static inline void set_cpu_core_map(int cpu)
99{
100 int i;
101
102 cpumask_set_cpu(cpu, &cpu_core_setup_map);
103
104 for_each_cpu(i, &cpu_core_setup_map) {
105 if (cpu_data[cpu].package == cpu_data[i].package) {
106 cpumask_set_cpu(i, &cpu_core_map[cpu]);
107 cpumask_set_cpu(cpu, &cpu_core_map[i]);
108 }
109 }
110}
111
112/*
113 * Calculate a new cpu_foreign_map mask whenever a
114 * new cpu appears or disappears.
115 */
116void calculate_cpu_foreign_map(void)
117{
118 int i, k, core_present;
119 cpumask_t temp_foreign_map;
120
121 /* Re-calculate the mask */
122 cpumask_clear(&temp_foreign_map);
123 for_each_online_cpu(i) {
124 core_present = 0;
125 for_each_cpu(k, &temp_foreign_map)
126 if (cpus_are_siblings(i, k))
127 core_present = 1;
128 if (!core_present)
129 cpumask_set_cpu(i, &temp_foreign_map);
130 }
131
132 for_each_online_cpu(i)
133 cpumask_andnot(&cpu_foreign_map[i],
134 &temp_foreign_map, &cpu_sibling_map[i]);
135}
136
137const struct plat_smp_ops *mp_ops;
138EXPORT_SYMBOL(mp_ops);
139
140void register_smp_ops(const struct plat_smp_ops *ops)
141{
142 if (mp_ops)
143 printk(KERN_WARNING "Overriding previously set SMP ops\n");
144
145 mp_ops = ops;
146}
147
148#ifdef CONFIG_GENERIC_IRQ_IPI
149void mips_smp_send_ipi_single(int cpu, unsigned int action)
150{
151 mips_smp_send_ipi_mask(cpumask_of(cpu), action);
152}
153
154void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
155{
156 unsigned long flags;
157 unsigned int core;
158 int cpu;
159
160 local_irq_save(flags);
161
162 switch (action) {
163 case SMP_CALL_FUNCTION:
164 __ipi_send_mask(call_desc, mask);
165 break;
166
167 case SMP_RESCHEDULE_YOURSELF:
168 __ipi_send_mask(sched_desc, mask);
169 break;
170
171 default:
172 BUG();
173 }
174
175 if (mips_cpc_present()) {
176 for_each_cpu(cpu, mask) {
177 if (cpus_are_siblings(cpu, smp_processor_id()))
178 continue;
179
180 core = cpu_core(&cpu_data[cpu]);
181
182 while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
183 mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
184 mips_cpc_lock_other(core);
185 write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
186 mips_cpc_unlock_other();
187 mips_cm_unlock_other();
188 }
189 }
190 }
191
192 local_irq_restore(flags);
193}
194
195
196static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
197{
198 scheduler_ipi();
199
200 return IRQ_HANDLED;
201}
202
203static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
204{
205 generic_smp_call_function_interrupt();
206
207 return IRQ_HANDLED;
208}
209
210static struct irqaction irq_resched = {
211 .handler = ipi_resched_interrupt,
212 .flags = IRQF_PERCPU,
213 .name = "IPI resched"
214};
215
216static struct irqaction irq_call = {
217 .handler = ipi_call_interrupt,
218 .flags = IRQF_PERCPU,
219 .name = "IPI call"
220};
221
222static void smp_ipi_init_one(unsigned int virq,
223 struct irqaction *action)
224{
225 int ret;
226
227 irq_set_handler(virq, handle_percpu_irq);
228 ret = setup_irq(virq, action);
229 BUG_ON(ret);
230}
231
232static unsigned int call_virq, sched_virq;
233
234int mips_smp_ipi_allocate(const struct cpumask *mask)
235{
236 int virq;
237 struct irq_domain *ipidomain;
238 struct device_node *node;
239
240 node = of_irq_find_parent(of_root);
241 ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
242
243 /*
244 * Some platforms have half DT setup. So if we found irq node but
245 * didn't find an ipidomain, try to search for one that is not in the
246 * DT.
247 */
248 if (node && !ipidomain)
249 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
250
251 /*
252 * There are systems which use IPI IRQ domains, but only have one
253 * registered when some runtime condition is met. For example a Malta
254 * kernel may include support for GIC & CPU interrupt controller IPI
255 * IRQ domains, but if run on a system with no GIC & no MT ASE then
256 * neither will be supported or registered.
257 *
258 * We only have a problem if we're actually using multiple CPUs so fail
259 * loudly if that is the case. Otherwise simply return, skipping IPI
260 * setup, if we're running with only a single CPU.
261 */
262 if (!ipidomain) {
263 BUG_ON(num_present_cpus() > 1);
264 return 0;
265 }
266
267 virq = irq_reserve_ipi(ipidomain, mask);
268 BUG_ON(!virq);
269 if (!call_virq)
270 call_virq = virq;
271
272 virq = irq_reserve_ipi(ipidomain, mask);
273 BUG_ON(!virq);
274 if (!sched_virq)
275 sched_virq = virq;
276
277 if (irq_domain_is_ipi_per_cpu(ipidomain)) {
278 int cpu;
279
280 for_each_cpu(cpu, mask) {
281 smp_ipi_init_one(call_virq + cpu, &irq_call);
282 smp_ipi_init_one(sched_virq + cpu, &irq_resched);
283 }
284 } else {
285 smp_ipi_init_one(call_virq, &irq_call);
286 smp_ipi_init_one(sched_virq, &irq_resched);
287 }
288
289 return 0;
290}
291
292int mips_smp_ipi_free(const struct cpumask *mask)
293{
294 struct irq_domain *ipidomain;
295 struct device_node *node;
296
297 node = of_irq_find_parent(of_root);
298 ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
299
300 /*
301 * Some platforms have half DT setup. So if we found irq node but
302 * didn't find an ipidomain, try to search for one that is not in the
303 * DT.
304 */
305 if (node && !ipidomain)
306 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
307
308 BUG_ON(!ipidomain);
309
310 if (irq_domain_is_ipi_per_cpu(ipidomain)) {
311 int cpu;
312
313 for_each_cpu(cpu, mask) {
314 remove_irq(call_virq + cpu, &irq_call);
315 remove_irq(sched_virq + cpu, &irq_resched);
316 }
317 }
318 irq_destroy_ipi(call_virq, mask);
319 irq_destroy_ipi(sched_virq, mask);
320 return 0;
321}
322
323
324static int __init mips_smp_ipi_init(void)
325{
326 if (num_possible_cpus() == 1)
327 return 0;
328
329 mips_smp_ipi_allocate(cpu_possible_mask);
330
331 call_desc = irq_to_desc(call_virq);
332 sched_desc = irq_to_desc(sched_virq);
333
334 return 0;
335}
336early_initcall(mips_smp_ipi_init);
337#endif
338
339/*
340 * First C code run on the secondary CPUs after being started up by
341 * the master.
342 */
343asmlinkage void start_secondary(void)
344{
345 unsigned int cpu;
346
347 cpu_probe();
348 per_cpu_trap_init(false);
349 mips_clockevent_init();
350 mp_ops->init_secondary();
351 cpu_report();
352 maar_init();
353
354 /*
355 * XXX parity protection should be folded in here when it's converted
356 * to an option instead of something based on .cputype
357 */
358
359 calibrate_delay();
360 preempt_disable();
361 cpu = smp_processor_id();
362 cpu_data[cpu].udelay_val = loops_per_jiffy;
363
364 cpumask_set_cpu(cpu, &cpu_coherent_mask);
365 notify_cpu_starting(cpu);
366
367 /* Notify boot CPU that we're starting & ready to sync counters */
368 complete(&cpu_starting);
369
370 synchronise_count_slave(cpu);
371
372 /* The CPU is running and counters synchronised, now mark it online */
373 set_cpu_online(cpu, true);
374
375 set_cpu_sibling_map(cpu);
376 set_cpu_core_map(cpu);
377
378 calculate_cpu_foreign_map();
379
380 /*
381 * Notify boot CPU that we're up & online and it can safely return
382 * from __cpu_up
383 */
384 complete(&cpu_running);
385
386 /*
387 * irq will be enabled in ->smp_finish(), enabling it too early
388 * is dangerous.
389 */
390 WARN_ON_ONCE(!irqs_disabled());
391 mp_ops->smp_finish();
392
393 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
394}
395
396static void stop_this_cpu(void *dummy)
397{
398 /*
399 * Remove this CPU:
400 */
401
402 set_cpu_online(smp_processor_id(), false);
403 calculate_cpu_foreign_map();
404 local_irq_disable();
405 while (1);
406}
407
408void smp_send_stop(void)
409{
410 smp_call_function(stop_this_cpu, NULL, 0);
411}
412
413void __init smp_cpus_done(unsigned int max_cpus)
414{
415}
416
417/* called from main before smp_init() */
418void __init smp_prepare_cpus(unsigned int max_cpus)
419{
420 init_new_context(current, &init_mm);
421 current_thread_info()->cpu = 0;
422 mp_ops->prepare_cpus(max_cpus);
423 set_cpu_sibling_map(0);
424 set_cpu_core_map(0);
425 calculate_cpu_foreign_map();
426#ifndef CONFIG_HOTPLUG_CPU
427 init_cpu_present(cpu_possible_mask);
428#endif
429 cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
430}
431
432/* preload SMP state for boot cpu */
433void smp_prepare_boot_cpu(void)
434{
435 if (mp_ops->prepare_boot_cpu)
436 mp_ops->prepare_boot_cpu();
437 set_cpu_possible(0, true);
438 set_cpu_online(0, true);
439}
440
441int __cpu_up(unsigned int cpu, struct task_struct *tidle)
442{
443 int err;
444
445 err = mp_ops->boot_secondary(cpu, tidle);
446 if (err)
447 return err;
448
449 /* Wait for CPU to start and be ready to sync counters */
450 if (!wait_for_completion_timeout(&cpu_starting,
451 msecs_to_jiffies(1000))) {
452 pr_crit("CPU%u: failed to start\n", cpu);
453 return -EIO;
454 }
455
456 synchronise_count_master(cpu);
457
458 /* Wait for CPU to finish startup & mark itself online before return */
459 wait_for_completion(&cpu_running);
460 return 0;
461}
462
463/* Not really SMP stuff ... */
464int setup_profiling_timer(unsigned int multiplier)
465{
466 return 0;
467}
468
469static void flush_tlb_all_ipi(void *info)
470{
471 local_flush_tlb_all();
472}
473
474void flush_tlb_all(void)
475{
476 if (cpu_has_mmid) {
477 htw_stop();
478 ginvt_full();
479 sync_ginv();
480 instruction_hazard();
481 htw_start();
482 return;
483 }
484
485 on_each_cpu(flush_tlb_all_ipi, NULL, 1);
486}
487
488static void flush_tlb_mm_ipi(void *mm)
489{
490 drop_mmu_context((struct mm_struct *)mm);
491}
492
493/*
494 * Special Variant of smp_call_function for use by TLB functions:
495 *
496 * o No return value
497 * o collapses to normal function call on UP kernels
498 * o collapses to normal function call on systems with a single shared
499 * primary cache.
500 */
501static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
502{
503 smp_call_function(func, info, 1);
504}
505
506static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
507{
508 preempt_disable();
509
510 smp_on_other_tlbs(func, info);
511 func(info);
512
513 preempt_enable();
514}
515
516/*
517 * The following tlb flush calls are invoked when old translations are
518 * being torn down, or pte attributes are changing. For single threaded
519 * address spaces, a new context is obtained on the current cpu, and tlb
520 * context on other cpus are invalidated to force a new context allocation
521 * at switch_mm time, should the mm ever be used on other cpus. For
522 * multithreaded address spaces, intercpu interrupts have to be sent.
523 * Another case where intercpu interrupts are required is when the target
524 * mm might be active on another cpu (eg debuggers doing the flushes on
525 * behalf of debugees, kswapd stealing pages from another process etc).
526 * Kanoj 07/00.
527 */
528
529void flush_tlb_mm(struct mm_struct *mm)
530{
531 preempt_disable();
532
533 if (cpu_has_mmid) {
534 /*
535 * No need to worry about other CPUs - the ginvt in
536 * drop_mmu_context() will be globalized.
537 */
538 } else if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
539 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
540 } else {
541 unsigned int cpu;
542
543 for_each_online_cpu(cpu) {
544 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
545 set_cpu_context(cpu, mm, 0);
546 }
547 }
548 drop_mmu_context(mm);
549
550 preempt_enable();
551}
552
553struct flush_tlb_data {
554 struct vm_area_struct *vma;
555 unsigned long addr1;
556 unsigned long addr2;
557};
558
559static void flush_tlb_range_ipi(void *info)
560{
561 struct flush_tlb_data *fd = info;
562
563 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
564}
565
566void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
567{
568 struct mm_struct *mm = vma->vm_mm;
569 unsigned long addr;
570 u32 old_mmid;
571
572 preempt_disable();
573 if (cpu_has_mmid) {
574 htw_stop();
575 old_mmid = read_c0_memorymapid();
576 write_c0_memorymapid(cpu_asid(0, mm));
577 mtc0_tlbw_hazard();
578 addr = round_down(start, PAGE_SIZE * 2);
579 end = round_up(end, PAGE_SIZE * 2);
580 do {
581 ginvt_va_mmid(addr);
582 sync_ginv();
583 addr += PAGE_SIZE * 2;
584 } while (addr < end);
585 write_c0_memorymapid(old_mmid);
586 instruction_hazard();
587 htw_start();
588 } else if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
589 struct flush_tlb_data fd = {
590 .vma = vma,
591 .addr1 = start,
592 .addr2 = end,
593 };
594
595 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
596 local_flush_tlb_range(vma, start, end);
597 } else {
598 unsigned int cpu;
599 int exec = vma->vm_flags & VM_EXEC;
600
601 for_each_online_cpu(cpu) {
602 /*
603 * flush_cache_range() will only fully flush icache if
604 * the VMA is executable, otherwise we must invalidate
605 * ASID without it appearing to has_valid_asid() as if
606 * mm has been completely unused by that CPU.
607 */
608 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
609 set_cpu_context(cpu, mm, !exec);
610 }
611 local_flush_tlb_range(vma, start, end);
612 }
613 preempt_enable();
614}
615
616static void flush_tlb_kernel_range_ipi(void *info)
617{
618 struct flush_tlb_data *fd = info;
619
620 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
621}
622
623void flush_tlb_kernel_range(unsigned long start, unsigned long end)
624{
625 struct flush_tlb_data fd = {
626 .addr1 = start,
627 .addr2 = end,
628 };
629
630 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
631}
632
633static void flush_tlb_page_ipi(void *info)
634{
635 struct flush_tlb_data *fd = info;
636
637 local_flush_tlb_page(fd->vma, fd->addr1);
638}
639
640void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
641{
642 u32 old_mmid;
643
644 preempt_disable();
645 if (cpu_has_mmid) {
646 htw_stop();
647 old_mmid = read_c0_memorymapid();
648 write_c0_memorymapid(cpu_asid(0, vma->vm_mm));
649 mtc0_tlbw_hazard();
650 ginvt_va_mmid(page);
651 sync_ginv();
652 write_c0_memorymapid(old_mmid);
653 instruction_hazard();
654 htw_start();
655 } else if ((atomic_read(&vma->vm_mm->mm_users) != 1) ||
656 (current->mm != vma->vm_mm)) {
657 struct flush_tlb_data fd = {
658 .vma = vma,
659 .addr1 = page,
660 };
661
662 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
663 local_flush_tlb_page(vma, page);
664 } else {
665 unsigned int cpu;
666
667 for_each_online_cpu(cpu) {
668 /*
669 * flush_cache_page() only does partial flushes, so
670 * invalidate ASID without it appearing to
671 * has_valid_asid() as if mm has been completely unused
672 * by that CPU.
673 */
674 if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
675 set_cpu_context(cpu, vma->vm_mm, 1);
676 }
677 local_flush_tlb_page(vma, page);
678 }
679 preempt_enable();
680}
681
682static void flush_tlb_one_ipi(void *info)
683{
684 unsigned long vaddr = (unsigned long) info;
685
686 local_flush_tlb_one(vaddr);
687}
688
689void flush_tlb_one(unsigned long vaddr)
690{
691 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
692}
693
694EXPORT_SYMBOL(flush_tlb_page);
695EXPORT_SYMBOL(flush_tlb_one);
696
697#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
698
699static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
700static DEFINE_PER_CPU(call_single_data_t, tick_broadcast_csd);
701
702void tick_broadcast(const struct cpumask *mask)
703{
704 atomic_t *count;
705 call_single_data_t *csd;
706 int cpu;
707
708 for_each_cpu(cpu, mask) {
709 count = &per_cpu(tick_broadcast_count, cpu);
710 csd = &per_cpu(tick_broadcast_csd, cpu);
711
712 if (atomic_inc_return(count) == 1)
713 smp_call_function_single_async(cpu, csd);
714 }
715}
716
717static void tick_broadcast_callee(void *info)
718{
719 int cpu = smp_processor_id();
720 tick_receive_broadcast();
721 atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
722}
723
724static int __init tick_broadcast_init(void)
725{
726 call_single_data_t *csd;
727 int cpu;
728
729 for (cpu = 0; cpu < NR_CPUS; cpu++) {
730 csd = &per_cpu(tick_broadcast_csd, cpu);
731 csd->func = tick_broadcast_callee;
732 }
733
734 return 0;
735}
736early_initcall(tick_broadcast_init);
737
738#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2000, 2001 Kanoj Sarcar
17 * Copyright (C) 2000, 2001 Ralf Baechle
18 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
19 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
20 */
21#include <linux/cache.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/smp.h>
26#include <linux/spinlock.h>
27#include <linux/threads.h>
28#include <linux/module.h>
29#include <linux/time.h>
30#include <linux/timex.h>
31#include <linux/sched.h>
32#include <linux/cpumask.h>
33#include <linux/cpu.h>
34#include <linux/err.h>
35#include <linux/ftrace.h>
36
37#include <linux/atomic.h>
38#include <asm/cpu.h>
39#include <asm/processor.h>
40#include <asm/r4k-timer.h>
41#include <asm/system.h>
42#include <asm/mmu_context.h>
43#include <asm/time.h>
44
45#ifdef CONFIG_MIPS_MT_SMTC
46#include <asm/mipsmtregs.h>
47#endif /* CONFIG_MIPS_MT_SMTC */
48
49volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
50
51int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
52EXPORT_SYMBOL(__cpu_number_map);
53
54int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
55EXPORT_SYMBOL(__cpu_logical_map);
56
57/* Number of TCs (or siblings in Intel speak) per CPU core */
58int smp_num_siblings = 1;
59EXPORT_SYMBOL(smp_num_siblings);
60
61/* representing the TCs (or siblings in Intel speak) of each logical CPU */
62cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
63EXPORT_SYMBOL(cpu_sibling_map);
64
65/* representing cpus for which sibling maps can be computed */
66static cpumask_t cpu_sibling_setup_map;
67
68static inline void set_cpu_sibling_map(int cpu)
69{
70 int i;
71
72 cpu_set(cpu, cpu_sibling_setup_map);
73
74 if (smp_num_siblings > 1) {
75 for_each_cpu_mask(i, cpu_sibling_setup_map) {
76 if (cpu_data[cpu].core == cpu_data[i].core) {
77 cpu_set(i, cpu_sibling_map[cpu]);
78 cpu_set(cpu, cpu_sibling_map[i]);
79 }
80 }
81 } else
82 cpu_set(cpu, cpu_sibling_map[cpu]);
83}
84
85struct plat_smp_ops *mp_ops;
86
87__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
88{
89 if (mp_ops)
90 printk(KERN_WARNING "Overriding previously set SMP ops\n");
91
92 mp_ops = ops;
93}
94
95/*
96 * First C code run on the secondary CPUs after being started up by
97 * the master.
98 */
99asmlinkage __cpuinit void start_secondary(void)
100{
101 unsigned int cpu;
102
103#ifdef CONFIG_MIPS_MT_SMTC
104 /* Only do cpu_probe for first TC of CPU */
105 if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
106#endif /* CONFIG_MIPS_MT_SMTC */
107 cpu_probe();
108 cpu_report();
109 per_cpu_trap_init();
110 mips_clockevent_init();
111 mp_ops->init_secondary();
112
113 /*
114 * XXX parity protection should be folded in here when it's converted
115 * to an option instead of something based on .cputype
116 */
117
118 calibrate_delay();
119 preempt_disable();
120 cpu = smp_processor_id();
121 cpu_data[cpu].udelay_val = loops_per_jiffy;
122
123 notify_cpu_starting(cpu);
124
125 mp_ops->smp_finish();
126 set_cpu_sibling_map(cpu);
127
128 cpu_set(cpu, cpu_callin_map);
129
130 synchronise_count_slave();
131
132 cpu_idle();
133}
134
135/*
136 * Call into both interrupt handlers, as we share the IPI for them
137 */
138void __irq_entry smp_call_function_interrupt(void)
139{
140 irq_enter();
141 generic_smp_call_function_single_interrupt();
142 generic_smp_call_function_interrupt();
143 irq_exit();
144}
145
146static void stop_this_cpu(void *dummy)
147{
148 /*
149 * Remove this CPU:
150 */
151 cpu_clear(smp_processor_id(), cpu_online_map);
152 for (;;) {
153 if (cpu_wait)
154 (*cpu_wait)(); /* Wait if available. */
155 }
156}
157
158void smp_send_stop(void)
159{
160 smp_call_function(stop_this_cpu, NULL, 0);
161}
162
163void __init smp_cpus_done(unsigned int max_cpus)
164{
165 mp_ops->cpus_done();
166 synchronise_count_master();
167}
168
169/* called from main before smp_init() */
170void __init smp_prepare_cpus(unsigned int max_cpus)
171{
172 init_new_context(current, &init_mm);
173 current_thread_info()->cpu = 0;
174 mp_ops->prepare_cpus(max_cpus);
175 set_cpu_sibling_map(0);
176#ifndef CONFIG_HOTPLUG_CPU
177 init_cpu_present(&cpu_possible_map);
178#endif
179}
180
181/* preload SMP state for boot cpu */
182void __devinit smp_prepare_boot_cpu(void)
183{
184 set_cpu_possible(0, true);
185 set_cpu_online(0, true);
186 cpu_set(0, cpu_callin_map);
187}
188
189/*
190 * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
191 * and keep control until "cpu_online(cpu)" is set. Note: cpu is
192 * physical, not logical.
193 */
194static struct task_struct *cpu_idle_thread[NR_CPUS];
195
196struct create_idle {
197 struct work_struct work;
198 struct task_struct *idle;
199 struct completion done;
200 int cpu;
201};
202
203static void __cpuinit do_fork_idle(struct work_struct *work)
204{
205 struct create_idle *c_idle =
206 container_of(work, struct create_idle, work);
207
208 c_idle->idle = fork_idle(c_idle->cpu);
209 complete(&c_idle->done);
210}
211
212int __cpuinit __cpu_up(unsigned int cpu)
213{
214 struct task_struct *idle;
215
216 /*
217 * Processor goes to start_secondary(), sets online flag
218 * The following code is purely to make sure
219 * Linux can schedule processes on this slave.
220 */
221 if (!cpu_idle_thread[cpu]) {
222 /*
223 * Schedule work item to avoid forking user task
224 * Ported from arch/x86/kernel/smpboot.c
225 */
226 struct create_idle c_idle = {
227 .cpu = cpu,
228 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
229 };
230
231 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
232 schedule_work(&c_idle.work);
233 wait_for_completion(&c_idle.done);
234 idle = cpu_idle_thread[cpu] = c_idle.idle;
235
236 if (IS_ERR(idle))
237 panic(KERN_ERR "Fork failed for CPU %d", cpu);
238 } else {
239 idle = cpu_idle_thread[cpu];
240 init_idle(idle, cpu);
241 }
242
243 mp_ops->boot_secondary(cpu, idle);
244
245 /*
246 * Trust is futile. We should really have timeouts ...
247 */
248 while (!cpu_isset(cpu, cpu_callin_map))
249 udelay(100);
250
251 cpu_set(cpu, cpu_online_map);
252
253 return 0;
254}
255
256/* Not really SMP stuff ... */
257int setup_profiling_timer(unsigned int multiplier)
258{
259 return 0;
260}
261
262static void flush_tlb_all_ipi(void *info)
263{
264 local_flush_tlb_all();
265}
266
267void flush_tlb_all(void)
268{
269 on_each_cpu(flush_tlb_all_ipi, NULL, 1);
270}
271
272static void flush_tlb_mm_ipi(void *mm)
273{
274 local_flush_tlb_mm((struct mm_struct *)mm);
275}
276
277/*
278 * Special Variant of smp_call_function for use by TLB functions:
279 *
280 * o No return value
281 * o collapses to normal function call on UP kernels
282 * o collapses to normal function call on systems with a single shared
283 * primary cache.
284 * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core.
285 */
286static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
287{
288#ifndef CONFIG_MIPS_MT_SMTC
289 smp_call_function(func, info, 1);
290#endif
291}
292
293static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
294{
295 preempt_disable();
296
297 smp_on_other_tlbs(func, info);
298 func(info);
299
300 preempt_enable();
301}
302
303/*
304 * The following tlb flush calls are invoked when old translations are
305 * being torn down, or pte attributes are changing. For single threaded
306 * address spaces, a new context is obtained on the current cpu, and tlb
307 * context on other cpus are invalidated to force a new context allocation
308 * at switch_mm time, should the mm ever be used on other cpus. For
309 * multithreaded address spaces, intercpu interrupts have to be sent.
310 * Another case where intercpu interrupts are required is when the target
311 * mm might be active on another cpu (eg debuggers doing the flushes on
312 * behalf of debugees, kswapd stealing pages from another process etc).
313 * Kanoj 07/00.
314 */
315
316void flush_tlb_mm(struct mm_struct *mm)
317{
318 preempt_disable();
319
320 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
321 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
322 } else {
323 cpumask_t mask = cpu_online_map;
324 unsigned int cpu;
325
326 cpu_clear(smp_processor_id(), mask);
327 for_each_cpu_mask(cpu, mask)
328 if (cpu_context(cpu, mm))
329 cpu_context(cpu, mm) = 0;
330 }
331 local_flush_tlb_mm(mm);
332
333 preempt_enable();
334}
335
336struct flush_tlb_data {
337 struct vm_area_struct *vma;
338 unsigned long addr1;
339 unsigned long addr2;
340};
341
342static void flush_tlb_range_ipi(void *info)
343{
344 struct flush_tlb_data *fd = info;
345
346 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
347}
348
349void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
350{
351 struct mm_struct *mm = vma->vm_mm;
352
353 preempt_disable();
354 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
355 struct flush_tlb_data fd = {
356 .vma = vma,
357 .addr1 = start,
358 .addr2 = end,
359 };
360
361 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
362 } else {
363 cpumask_t mask = cpu_online_map;
364 unsigned int cpu;
365
366 cpu_clear(smp_processor_id(), mask);
367 for_each_cpu_mask(cpu, mask)
368 if (cpu_context(cpu, mm))
369 cpu_context(cpu, mm) = 0;
370 }
371 local_flush_tlb_range(vma, start, end);
372 preempt_enable();
373}
374
375static void flush_tlb_kernel_range_ipi(void *info)
376{
377 struct flush_tlb_data *fd = info;
378
379 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
380}
381
382void flush_tlb_kernel_range(unsigned long start, unsigned long end)
383{
384 struct flush_tlb_data fd = {
385 .addr1 = start,
386 .addr2 = end,
387 };
388
389 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
390}
391
392static void flush_tlb_page_ipi(void *info)
393{
394 struct flush_tlb_data *fd = info;
395
396 local_flush_tlb_page(fd->vma, fd->addr1);
397}
398
399void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
400{
401 preempt_disable();
402 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
403 struct flush_tlb_data fd = {
404 .vma = vma,
405 .addr1 = page,
406 };
407
408 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
409 } else {
410 cpumask_t mask = cpu_online_map;
411 unsigned int cpu;
412
413 cpu_clear(smp_processor_id(), mask);
414 for_each_cpu_mask(cpu, mask)
415 if (cpu_context(cpu, vma->vm_mm))
416 cpu_context(cpu, vma->vm_mm) = 0;
417 }
418 local_flush_tlb_page(vma, page);
419 preempt_enable();
420}
421
422static void flush_tlb_one_ipi(void *info)
423{
424 unsigned long vaddr = (unsigned long) info;
425
426 local_flush_tlb_one(vaddr);
427}
428
429void flush_tlb_one(unsigned long vaddr)
430{
431 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
432}
433
434EXPORT_SYMBOL(flush_tlb_page);
435EXPORT_SYMBOL(flush_tlb_one);