Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ARM_HW_BREAKPOINT_H
3#define _ARM_HW_BREAKPOINT_H
4
5#ifdef __KERNEL__
6
7struct task_struct;
8
9#ifdef CONFIG_HAVE_HW_BREAKPOINT
10
11struct arch_hw_breakpoint_ctrl {
12 u32 __reserved : 9,
13 mismatch : 1,
14 : 9,
15 len : 8,
16 type : 2,
17 privilege : 2,
18 enabled : 1;
19};
20
21struct arch_hw_breakpoint {
22 u32 address;
23 u32 trigger;
24 struct arch_hw_breakpoint_ctrl step_ctrl;
25 struct arch_hw_breakpoint_ctrl ctrl;
26};
27
28static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
29{
30 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
31 (ctrl.privilege << 1) | ctrl.enabled;
32}
33
34static inline void decode_ctrl_reg(u32 reg,
35 struct arch_hw_breakpoint_ctrl *ctrl)
36{
37 ctrl->enabled = reg & 0x1;
38 reg >>= 1;
39 ctrl->privilege = reg & 0x3;
40 reg >>= 2;
41 ctrl->type = reg & 0x3;
42 reg >>= 2;
43 ctrl->len = reg & 0xff;
44 reg >>= 17;
45 ctrl->mismatch = reg & 0x1;
46}
47
48/* Debug architecture numbers. */
49#define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
50#define ARM_DEBUG_ARCH_V6 1
51#define ARM_DEBUG_ARCH_V6_1 2
52#define ARM_DEBUG_ARCH_V7_ECP14 3
53#define ARM_DEBUG_ARCH_V7_MM 4
54#define ARM_DEBUG_ARCH_V7_1 5
55#define ARM_DEBUG_ARCH_V8 6
56
57/* Breakpoint */
58#define ARM_BREAKPOINT_EXECUTE 0
59
60/* Watchpoints */
61#define ARM_BREAKPOINT_LOAD 1
62#define ARM_BREAKPOINT_STORE 2
63#define ARM_FSR_ACCESS_MASK (1 << 11)
64
65/* Privilege Levels */
66#define ARM_BREAKPOINT_PRIV 1
67#define ARM_BREAKPOINT_USER 2
68
69/* Lengths */
70#define ARM_BREAKPOINT_LEN_1 0x1
71#define ARM_BREAKPOINT_LEN_2 0x3
72#define ARM_BREAKPOINT_LEN_4 0xf
73#define ARM_BREAKPOINT_LEN_8 0xff
74
75/* Limits */
76#define ARM_MAX_BRP 16
77#define ARM_MAX_WRP 16
78#define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
79
80/* DSCR method of entry bits. */
81#define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
82#define ARM_ENTRY_BREAKPOINT 0x1
83#define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
84#define ARM_ENTRY_SYNC_WATCHPOINT 0xa
85
86/* DSCR monitor/halting bits. */
87#define ARM_DSCR_HDBGEN (1 << 14)
88#define ARM_DSCR_MDBGEN (1 << 15)
89
90/* OSLSR os lock model bits */
91#define ARM_OSLSR_OSLM0 (1 << 0)
92
93/* opcode2 numbers for the co-processor instructions. */
94#define ARM_OP2_BVR 4
95#define ARM_OP2_BCR 5
96#define ARM_OP2_WVR 6
97#define ARM_OP2_WCR 7
98
99/* Base register numbers for the debug registers. */
100#define ARM_BASE_BVR 64
101#define ARM_BASE_BCR 80
102#define ARM_BASE_WVR 96
103#define ARM_BASE_WCR 112
104
105/* Accessor macros for the debug registers. */
106#define ARM_DBG_READ(N, M, OP2, VAL) do {\
107 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
108} while (0)
109
110#define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
111 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
112} while (0)
113
114struct perf_event_attr;
115struct notifier_block;
116struct perf_event;
117struct pmu;
118
119extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
120 int *gen_len, int *gen_type);
121extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
122extern int hw_breakpoint_arch_parse(struct perf_event *bp,
123 const struct perf_event_attr *attr,
124 struct arch_hw_breakpoint *hw);
125extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
126 unsigned long val, void *data);
127
128extern u8 arch_get_debug_arch(void);
129extern u8 arch_get_max_wp_len(void);
130extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
131
132int arch_install_hw_breakpoint(struct perf_event *bp);
133void arch_uninstall_hw_breakpoint(struct perf_event *bp);
134void hw_breakpoint_pmu_read(struct perf_event *bp);
135int hw_breakpoint_slots(int type);
136
137#else
138static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
139
140#endif /* CONFIG_HAVE_HW_BREAKPOINT */
141#endif /* __KERNEL__ */
142#endif /* _ARM_HW_BREAKPOINT_H */
1#ifndef _ARM_HW_BREAKPOINT_H
2#define _ARM_HW_BREAKPOINT_H
3
4#ifdef __KERNEL__
5
6struct task_struct;
7
8#ifdef CONFIG_HAVE_HW_BREAKPOINT
9
10struct arch_hw_breakpoint_ctrl {
11 u32 __reserved : 9,
12 mismatch : 1,
13 : 9,
14 len : 8,
15 type : 2,
16 privilege : 2,
17 enabled : 1;
18};
19
20struct arch_hw_breakpoint {
21 u32 address;
22 u32 trigger;
23 struct arch_hw_breakpoint_ctrl step_ctrl;
24 struct arch_hw_breakpoint_ctrl ctrl;
25};
26
27static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
28{
29 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
30 (ctrl.privilege << 1) | ctrl.enabled;
31}
32
33static inline void decode_ctrl_reg(u32 reg,
34 struct arch_hw_breakpoint_ctrl *ctrl)
35{
36 ctrl->enabled = reg & 0x1;
37 reg >>= 1;
38 ctrl->privilege = reg & 0x3;
39 reg >>= 2;
40 ctrl->type = reg & 0x3;
41 reg >>= 2;
42 ctrl->len = reg & 0xff;
43 reg >>= 17;
44 ctrl->mismatch = reg & 0x1;
45}
46
47/* Debug architecture numbers. */
48#define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
49#define ARM_DEBUG_ARCH_V6 1
50#define ARM_DEBUG_ARCH_V6_1 2
51#define ARM_DEBUG_ARCH_V7_ECP14 3
52#define ARM_DEBUG_ARCH_V7_MM 4
53
54/* Breakpoint */
55#define ARM_BREAKPOINT_EXECUTE 0
56
57/* Watchpoints */
58#define ARM_BREAKPOINT_LOAD 1
59#define ARM_BREAKPOINT_STORE 2
60
61/* Privilege Levels */
62#define ARM_BREAKPOINT_PRIV 1
63#define ARM_BREAKPOINT_USER 2
64
65/* Lengths */
66#define ARM_BREAKPOINT_LEN_1 0x1
67#define ARM_BREAKPOINT_LEN_2 0x3
68#define ARM_BREAKPOINT_LEN_4 0xf
69#define ARM_BREAKPOINT_LEN_8 0xff
70
71/* Limits */
72#define ARM_MAX_BRP 16
73#define ARM_MAX_WRP 16
74#define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
75
76/* DSCR method of entry bits. */
77#define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
78#define ARM_ENTRY_BREAKPOINT 0x1
79#define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
80#define ARM_ENTRY_SYNC_WATCHPOINT 0xa
81
82/* DSCR monitor/halting bits. */
83#define ARM_DSCR_HDBGEN (1 << 14)
84#define ARM_DSCR_MDBGEN (1 << 15)
85
86/* opcode2 numbers for the co-processor instructions. */
87#define ARM_OP2_BVR 4
88#define ARM_OP2_BCR 5
89#define ARM_OP2_WVR 6
90#define ARM_OP2_WCR 7
91
92/* Base register numbers for the debug registers. */
93#define ARM_BASE_BVR 64
94#define ARM_BASE_BCR 80
95#define ARM_BASE_WVR 96
96#define ARM_BASE_WCR 112
97
98/* Accessor macros for the debug registers. */
99#define ARM_DBG_READ(M, OP2, VAL) do {\
100 asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\
101} while (0)
102
103#define ARM_DBG_WRITE(M, OP2, VAL) do {\
104 asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\
105} while (0)
106
107struct notifier_block;
108struct perf_event;
109struct pmu;
110
111extern struct pmu perf_ops_bp;
112extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
113 int *gen_len, int *gen_type);
114extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
115extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
116extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
117 unsigned long val, void *data);
118
119extern u8 arch_get_debug_arch(void);
120extern u8 arch_get_max_wp_len(void);
121extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
122
123int arch_install_hw_breakpoint(struct perf_event *bp);
124void arch_uninstall_hw_breakpoint(struct perf_event *bp);
125void hw_breakpoint_pmu_read(struct perf_event *bp);
126int hw_breakpoint_slots(int type);
127
128#else
129static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
130
131#endif /* CONFIG_HAVE_HW_BREAKPOINT */
132#endif /* __KERNEL__ */
133#endif /* _ARM_HW_BREAKPOINT_H */