Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2013 Realtek Corporation.*/
3
4#ifndef __RTL88E_DM_H__
5#define __RTL88E_DM_H__
6
7#define MAIN_ANT 0
8#define AUX_ANT 1
9#define MAIN_ANT_CG_TRX 1
10#define AUX_ANT_CG_TRX 0
11#define MAIN_ANT_CGCS_RX 0
12#define AUX_ANT_CGCS_RX 1
13
14/*RF REG LIST*/
15#define DM_REG_RF_MODE_11N 0x00
16#define DM_REG_RF_0B_11N 0x0B
17#define DM_REG_CHNBW_11N 0x18
18#define DM_REG_T_METER_11N 0x24
19#define DM_REG_RF_25_11N 0x25
20#define DM_REG_RF_26_11N 0x26
21#define DM_REG_RF_27_11N 0x27
22#define DM_REG_RF_2B_11N 0x2B
23#define DM_REG_RF_2C_11N 0x2C
24#define DM_REG_RXRF_A3_11N 0x3C
25#define DM_REG_T_METER_92D_11N 0x42
26#define DM_REG_T_METER_88E_11N 0x42
27
28/*BB REG LIST*/
29/*PAGE 8 */
30#define DM_REG_BB_CTRL_11N 0x800
31#define DM_REG_RF_PIN_11N 0x804
32#define DM_REG_PSD_CTRL_11N 0x808
33#define DM_REG_TX_ANT_CTRL_11N 0x80C
34#define DM_REG_BB_PWR_SAV5_11N 0x818
35#define DM_REG_CCK_RPT_FORMAT_11N 0x824
36#define DM_REG_RX_DEFAULT_A_11N 0x858
37#define DM_REG_RX_DEFAULT_B_11N 0x85A
38#define DM_REG_BB_PWR_SAV3_11N 0x85C
39#define DM_REG_ANTSEL_CTRL_11N 0x860
40#define DM_REG_RX_ANT_CTRL_11N 0x864
41#define DM_REG_PIN_CTRL_11N 0x870
42#define DM_REG_BB_PWR_SAV1_11N 0x874
43#define DM_REG_ANTSEL_PATH_11N 0x878
44#define DM_REG_BB_3WIRE_11N 0x88C
45#define DM_REG_SC_CNT_11N 0x8C4
46#define DM_REG_PSD_DATA_11N 0x8B4
47/*PAGE 9*/
48#define DM_REG_ANT_MAPPING1_11N 0x914
49#define DM_REG_ANT_MAPPING2_11N 0x918
50/*PAGE A*/
51#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
52#define DM_REG_CCK_CCA_11N 0xA0A
53#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
54#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
55#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
56#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
57#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
58#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
59#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
60#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
61#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
62#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
63#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
64#define DM_REG_CCK_FA_RST_11N 0xA2C
65#define DM_REG_CCK_FA_MSB_11N 0xA58
66#define DM_REG_CCK_FA_LSB_11N 0xA5C
67#define DM_REG_CCK_CCA_CNT_11N 0xA60
68#define DM_REG_BB_PWR_SAV4_11N 0xA74
69/*PAGE B */
70#define DM_REG_LNA_SWITCH_11N 0xB2C
71#define DM_REG_PATH_SWITCH_11N 0xB30
72#define DM_REG_RSSI_CTRL_11N 0xB38
73#define DM_REG_CONFIG_ANTA_11N 0xB68
74#define DM_REG_RSSI_BT_11N 0xB9C
75/*PAGE C */
76#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
77#define DM_REG_RX_PATH_11N 0xC04
78#define DM_REG_TRMUX_11N 0xC08
79#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
80#define DM_REG_RXIQI_MATRIX_11N 0xC14
81#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
82#define DM_REG_IGI_A_11N 0xC50
83#define DM_REG_ANTDIV_PARA2_11N 0xC54
84#define DM_REG_IGI_B_11N 0xC58
85#define DM_REG_ANTDIV_PARA3_11N 0xC5C
86#define DM_REG_BB_PWR_SAV2_11N 0xC70
87#define DM_REG_RX_OFF_11N 0xC7C
88#define DM_REG_TXIQK_MATRIXA_11N 0xC80
89#define DM_REG_TXIQK_MATRIXB_11N 0xC88
90#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
91#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
92#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
93#define DM_REG_ANTDIV_PARA1_11N 0xCA4
94#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
95/*PAGE D */
96#define DM_REG_OFDM_FA_RSTD_11N 0xD00
97#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
98#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
99#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
100/*PAGE E */
101#define DM_REG_TXAGC_A_6_18_11N 0xE00
102#define DM_REG_TXAGC_A_24_54_11N 0xE04
103#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
104#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
105#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
106#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
107#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
108#define DM_REG_FPGA0_IQK_11N 0xE28
109#define DM_REG_TXIQK_TONE_A_11N 0xE30
110#define DM_REG_RXIQK_TONE_A_11N 0xE34
111#define DM_REG_TXIQK_PI_A_11N 0xE38
112#define DM_REG_RXIQK_PI_A_11N 0xE3C
113#define DM_REG_TXIQK_11N 0xE40
114#define DM_REG_RXIQK_11N 0xE44
115#define DM_REG_IQK_AGC_PTS_11N 0xE48
116#define DM_REG_IQK_AGC_RSP_11N 0xE4C
117#define DM_REG_BLUETOOTH_11N 0xE6C
118#define DM_REG_RX_WAIT_CCA_11N 0xE70
119#define DM_REG_TX_CCK_RFON_11N 0xE74
120#define DM_REG_TX_CCK_BBON_11N 0xE78
121#define DM_REG_OFDM_RFON_11N 0xE7C
122#define DM_REG_OFDM_BBON_11N 0xE80
123#define DM_REG_TX2RX_11N 0xE84
124#define DM_REG_TX2TX_11N 0xE88
125#define DM_REG_RX_CCK_11N 0xE8C
126#define DM_REG_RX_OFDM_11N 0xED0
127#define DM_REG_RX_WAIT_RIFS_11N 0xED4
128#define DM_REG_RX2RX_11N 0xED8
129#define DM_REG_STANDBY_11N 0xEDC
130#define DM_REG_SLEEP_11N 0xEE0
131#define DM_REG_PMPD_ANAEN_11N 0xEEC
132
133/*MAC REG LIST*/
134#define DM_REG_BB_RST_11N 0x02
135#define DM_REG_ANTSEL_PIN_11N 0x4C
136#define DM_REG_EARLY_MODE_11N 0x4D0
137#define DM_REG_RSSI_MONITOR_11N 0x4FE
138#define DM_REG_EDCA_VO_11N 0x500
139#define DM_REG_EDCA_VI_11N 0x504
140#define DM_REG_EDCA_BE_11N 0x508
141#define DM_REG_EDCA_BK_11N 0x50C
142#define DM_REG_TXPAUSE_11N 0x522
143#define DM_REG_RESP_TX_11N 0x6D8
144#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
145#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
146
147
148/*DIG Related*/
149#define DM_BIT_IGI_11N 0x0000007F
150
151#define HAL_DM_DIG_DISABLE BIT(0)
152#define HAL_DM_HIPWR_DISABLE BIT(1)
153
154#define OFDM_TABLE_LENGTH 43
155#define CCK_TABLE_LENGTH 33
156
157#define OFDM_TABLE_SIZE 43
158#define CCK_TABLE_SIZE 33
159
160#define BW_AUTO_SWITCH_HIGH_LOW 25
161#define BW_AUTO_SWITCH_LOW_HIGH 30
162
163#define DM_DIG_FA_UPPER 0x3e
164#define DM_DIG_FA_LOWER 0x1e
165#define DM_DIG_FA_TH0 0x200
166#define DM_DIG_FA_TH1 0x300
167#define DM_DIG_FA_TH2 0x400
168
169#define RXPATHSELECTION_SS_TH_W 30
170#define RXPATHSELECTION_DIFF_TH 18
171
172#define DM_RATR_STA_INIT 0
173#define DM_RATR_STA_HIGH 1
174#define DM_RATR_STA_MIDDLE 2
175#define DM_RATR_STA_LOW 3
176
177#define CTS2SELF_THVAL 30
178#define REGC38_TH 20
179
180#define WAIOTTHVAL 25
181
182#define TXHIGHPWRLEVEL_NORMAL 0
183#define TXHIGHPWRLEVEL_LEVEL1 1
184#define TXHIGHPWRLEVEL_LEVEL2 2
185#define TXHIGHPWRLEVEL_BT1 3
186#define TXHIGHPWRLEVEL_BT2 4
187
188#define DM_TYPE_BYFW 0
189#define DM_TYPE_BYDRIVER 1
190
191#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
192#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
193#define TXPWRTRACK_MAX_IDX 6
194
195struct swat_t {
196 u8 failure_cnt;
197 u8 try_flag;
198 u8 stop_trying;
199
200 long pre_rssi;
201 long trying_threshold;
202 u8 cur_antenna;
203 u8 pre_antenna;
204
205};
206
207enum FAT_STATE {
208 FAT_NORMAL_STATE = 0,
209 FAT_TRAINING_STATE = 1,
210};
211
212enum tag_dynamic_init_gain_operation_type_definition {
213 DIG_TYPE_THRESH_HIGH = 0,
214 DIG_TYPE_THRESH_LOW = 1,
215 DIG_TYPE_BACKOFF = 2,
216 DIG_TYPE_RX_GAIN_MIN = 3,
217 DIG_TYPE_RX_GAIN_MAX = 4,
218 DIG_TYPE_ENABLE = 5,
219 DIG_TYPE_DISABLE = 6,
220 DIG_OP_TYPE_MAX
221};
222
223enum dm_1r_cca_e {
224 CCA_1R = 0,
225 CCA_2R = 1,
226 CCA_MAX = 2,
227};
228
229enum dm_rf_e {
230 RF_SAVE = 0,
231 RF_NORMAL = 1,
232 RF_MAX = 2,
233};
234
235enum dm_sw_ant_switch_e {
236 ANS_ANTENNA_B = 1,
237 ANS_ANTENNA_A = 2,
238 ANS_ANTENNA_MAX = 3,
239};
240
241enum pwr_track_control_method {
242 BBSWING,
243 TXAGC
244};
245
246void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
247 u8 *pdesc, u32 mac_id);
248void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
249 u8 antsel_tr_mux, u32 mac_id,
250 u32 rx_pwdb_all);
251void rtl88e_dm_fast_antenna_training_callback(struct timer_list *t);
252void rtl88e_dm_init(struct ieee80211_hw *hw);
253void rtl88e_dm_watchdog(struct ieee80211_hw *hw);
254void rtl88e_dm_write_dig(struct ieee80211_hw *hw);
255void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw);
256void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
257void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
258void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
259 u8 type, u8 *pdirection, u32 *poutwrite_val);
260#endif