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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * HD-audio stream operations
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/export.h>
9#include <linux/clocksource.h>
10#include <sound/core.h>
11#include <sound/pcm.h>
12#include <sound/hdaudio.h>
13#include <sound/hda_register.h>
14#include "trace.h"
15
16/**
17 * snd_hdac_get_stream_stripe_ctl - get stripe control value
18 * @bus: HD-audio core bus
19 * @substream: PCM substream
20 */
21int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
22 struct snd_pcm_substream *substream)
23{
24 struct snd_pcm_runtime *runtime = substream->runtime;
25 unsigned int channels = runtime->channels,
26 rate = runtime->rate,
27 bits_per_sample = runtime->sample_bits,
28 max_sdo_lines, value, sdo_line;
29
30 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
31 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
32
33 /* following is from HD audio spec */
34 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
35 if (rate > 48000)
36 value = (channels * bits_per_sample *
37 (rate / 48000)) / sdo_line;
38 else
39 value = (channels * bits_per_sample) / sdo_line;
40
41 if (value >= bus->sdo_limit)
42 break;
43 }
44
45 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
46 return sdo_line >> 1;
47}
48EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
49
50/**
51 * snd_hdac_stream_init - initialize each stream (aka device)
52 * @bus: HD-audio core bus
53 * @azx_dev: HD-audio core stream object to initialize
54 * @idx: stream index number
55 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
56 * @tag: the tag id to assign
57 *
58 * Assign the starting bdl address to each stream (device) and initialize.
59 */
60void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
61 int idx, int direction, int tag)
62{
63 azx_dev->bus = bus;
64 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
65 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
66 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
67 azx_dev->sd_int_sta_mask = 1 << idx;
68 azx_dev->index = idx;
69 azx_dev->direction = direction;
70 azx_dev->stream_tag = tag;
71 snd_hdac_dsp_lock_init(azx_dev);
72 list_add_tail(&azx_dev->list, &bus->stream_list);
73}
74EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
75
76/**
77 * snd_hdac_stream_start - start a stream
78 * @azx_dev: HD-audio core stream to start
79 * @fresh_start: false = wallclock timestamp relative to period wallclock
80 *
81 * Start a stream, set start_wallclk and set the running flag.
82 */
83void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
84{
85 struct hdac_bus *bus = azx_dev->bus;
86 int stripe_ctl;
87
88 trace_snd_hdac_stream_start(bus, azx_dev);
89
90 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
91 if (!fresh_start)
92 azx_dev->start_wallclk -= azx_dev->period_wallclk;
93
94 /* enable SIE */
95 snd_hdac_chip_updatel(bus, INTCTL,
96 1 << azx_dev->index,
97 1 << azx_dev->index);
98 /* set stripe control */
99 if (azx_dev->stripe) {
100 if (azx_dev->substream)
101 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
102 else
103 stripe_ctl = 0;
104 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
105 stripe_ctl);
106 }
107 /* set DMA start and interrupt mask */
108 snd_hdac_stream_updateb(azx_dev, SD_CTL,
109 0, SD_CTL_DMA_START | SD_INT_MASK);
110 azx_dev->running = true;
111}
112EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
113
114/**
115 * snd_hdac_stream_clear - stop a stream DMA
116 * @azx_dev: HD-audio core stream to stop
117 */
118void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
119{
120 snd_hdac_stream_updateb(azx_dev, SD_CTL,
121 SD_CTL_DMA_START | SD_INT_MASK, 0);
122 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
123 if (azx_dev->stripe)
124 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
125 azx_dev->running = false;
126}
127EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
128
129/**
130 * snd_hdac_stream_stop - stop a stream
131 * @azx_dev: HD-audio core stream to stop
132 *
133 * Stop a stream DMA and disable stream interrupt
134 */
135void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
136{
137 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
138
139 snd_hdac_stream_clear(azx_dev);
140 /* disable SIE */
141 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
142}
143EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
144
145/**
146 * snd_hdac_stream_reset - reset a stream
147 * @azx_dev: HD-audio core stream to reset
148 */
149void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
150{
151 unsigned char val;
152 int timeout;
153 int dma_run_state;
154
155 snd_hdac_stream_clear(azx_dev);
156
157 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
158
159 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
160 udelay(3);
161 timeout = 300;
162 do {
163 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
164 SD_CTL_STREAM_RESET;
165 if (val)
166 break;
167 } while (--timeout);
168
169 if (azx_dev->bus->dma_stop_delay && dma_run_state)
170 udelay(azx_dev->bus->dma_stop_delay);
171
172 val &= ~SD_CTL_STREAM_RESET;
173 snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
174 udelay(3);
175
176 timeout = 300;
177 /* waiting for hardware to report that the stream is out of reset */
178 do {
179 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
180 SD_CTL_STREAM_RESET;
181 if (!val)
182 break;
183 } while (--timeout);
184
185 /* reset first position - may not be synced with hw at this time */
186 if (azx_dev->posbuf)
187 *azx_dev->posbuf = 0;
188}
189EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
190
191/**
192 * snd_hdac_stream_setup - set up the SD for streaming
193 * @azx_dev: HD-audio core stream to set up
194 */
195int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
196{
197 struct hdac_bus *bus = azx_dev->bus;
198 struct snd_pcm_runtime *runtime;
199 unsigned int val;
200
201 if (azx_dev->substream)
202 runtime = azx_dev->substream->runtime;
203 else
204 runtime = NULL;
205 /* make sure the run bit is zero for SD */
206 snd_hdac_stream_clear(azx_dev);
207 /* program the stream_tag */
208 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
209 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
210 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
211 if (!bus->snoop)
212 val |= SD_CTL_TRAFFIC_PRIO;
213 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
214
215 /* program the length of samples in cyclic buffer */
216 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
217
218 /* program the stream format */
219 /* this value needs to be the same as the one programmed */
220 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
221
222 /* program the stream LVI (last valid index) of the BDL */
223 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
224
225 /* program the BDL address */
226 /* lower BDL address */
227 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
228 /* upper BDL address */
229 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
230 upper_32_bits(azx_dev->bdl.addr));
231
232 /* enable the position buffer */
233 if (bus->use_posbuf && bus->posbuf.addr) {
234 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
235 snd_hdac_chip_writel(bus, DPLBASE,
236 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
237 }
238
239 /* set the interrupt enable bits in the descriptor control register */
240 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
241
242 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
243
244 /* when LPIB delay correction gives a small negative value,
245 * we ignore it; currently set the threshold statically to
246 * 64 frames
247 */
248 if (runtime && runtime->period_size > 64)
249 azx_dev->delay_negative_threshold =
250 -frames_to_bytes(runtime, 64);
251 else
252 azx_dev->delay_negative_threshold = 0;
253
254 /* wallclk has 24Mhz clock source */
255 if (runtime)
256 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
257 runtime->rate) * 1000);
258
259 return 0;
260}
261EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
262
263/**
264 * snd_hdac_stream_cleanup - cleanup a stream
265 * @azx_dev: HD-audio core stream to clean up
266 */
267void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
268{
269 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
270 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
271 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
272 azx_dev->bufsize = 0;
273 azx_dev->period_bytes = 0;
274 azx_dev->format_val = 0;
275}
276EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
277
278/**
279 * snd_hdac_stream_assign - assign a stream for the PCM
280 * @bus: HD-audio core bus
281 * @substream: PCM substream to assign
282 *
283 * Look for an unused stream for the given PCM substream, assign it
284 * and return the stream object. If no stream is free, returns NULL.
285 * The function tries to keep using the same stream object when it's used
286 * beforehand. Also, when bus->reverse_assign flag is set, the last free
287 * or matching entry is returned. This is needed for some strange codecs.
288 */
289struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
290 struct snd_pcm_substream *substream)
291{
292 struct hdac_stream *azx_dev;
293 struct hdac_stream *res = NULL;
294
295 /* make a non-zero unique key for the substream */
296 int key = (substream->pcm->device << 16) | (substream->number << 2) |
297 (substream->stream + 1);
298
299 list_for_each_entry(azx_dev, &bus->stream_list, list) {
300 if (azx_dev->direction != substream->stream)
301 continue;
302 if (azx_dev->opened)
303 continue;
304 if (azx_dev->assigned_key == key) {
305 res = azx_dev;
306 break;
307 }
308 if (!res || bus->reverse_assign)
309 res = azx_dev;
310 }
311 if (res) {
312 spin_lock_irq(&bus->reg_lock);
313 res->opened = 1;
314 res->running = 0;
315 res->assigned_key = key;
316 res->substream = substream;
317 spin_unlock_irq(&bus->reg_lock);
318 }
319 return res;
320}
321EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
322
323/**
324 * snd_hdac_stream_release - release the assigned stream
325 * @azx_dev: HD-audio core stream to release
326 *
327 * Release the stream that has been assigned by snd_hdac_stream_assign().
328 */
329void snd_hdac_stream_release(struct hdac_stream *azx_dev)
330{
331 struct hdac_bus *bus = azx_dev->bus;
332
333 spin_lock_irq(&bus->reg_lock);
334 azx_dev->opened = 0;
335 azx_dev->running = 0;
336 azx_dev->substream = NULL;
337 spin_unlock_irq(&bus->reg_lock);
338}
339EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
340
341/**
342 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
343 * direction
344 *
345 * @bus: HD-audio core bus
346 * @dir: direction for the stream to be found
347 * @stream_tag: stream tag for stream to be found
348 */
349struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
350 int dir, int stream_tag)
351{
352 struct hdac_stream *s;
353
354 list_for_each_entry(s, &bus->stream_list, list) {
355 if (s->direction == dir && s->stream_tag == stream_tag)
356 return s;
357 }
358
359 return NULL;
360}
361EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
362
363/*
364 * set up a BDL entry
365 */
366static int setup_bdle(struct hdac_bus *bus,
367 struct snd_dma_buffer *dmab,
368 struct hdac_stream *azx_dev, __le32 **bdlp,
369 int ofs, int size, int with_ioc)
370{
371 __le32 *bdl = *bdlp;
372
373 while (size > 0) {
374 dma_addr_t addr;
375 int chunk;
376
377 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
378 return -EINVAL;
379
380 addr = snd_sgbuf_get_addr(dmab, ofs);
381 /* program the address field of the BDL entry */
382 bdl[0] = cpu_to_le32((u32)addr);
383 bdl[1] = cpu_to_le32(upper_32_bits(addr));
384 /* program the size field of the BDL entry */
385 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
386 /* one BDLE cannot cross 4K boundary on CTHDA chips */
387 if (bus->align_bdle_4k) {
388 u32 remain = 0x1000 - (ofs & 0xfff);
389
390 if (chunk > remain)
391 chunk = remain;
392 }
393 bdl[2] = cpu_to_le32(chunk);
394 /* program the IOC to enable interrupt
395 * only when the whole fragment is processed
396 */
397 size -= chunk;
398 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
399 bdl += 4;
400 azx_dev->frags++;
401 ofs += chunk;
402 }
403 *bdlp = bdl;
404 return ofs;
405}
406
407/**
408 * snd_hdac_stream_setup_periods - set up BDL entries
409 * @azx_dev: HD-audio core stream to set up
410 *
411 * Set up the buffer descriptor table of the given stream based on the
412 * period and buffer sizes of the assigned PCM substream.
413 */
414int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
415{
416 struct hdac_bus *bus = azx_dev->bus;
417 struct snd_pcm_substream *substream = azx_dev->substream;
418 struct snd_pcm_runtime *runtime = substream->runtime;
419 __le32 *bdl;
420 int i, ofs, periods, period_bytes;
421 int pos_adj, pos_align;
422
423 /* reset BDL address */
424 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
425 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
426
427 period_bytes = azx_dev->period_bytes;
428 periods = azx_dev->bufsize / period_bytes;
429
430 /* program the initial BDL entries */
431 bdl = (__le32 *)azx_dev->bdl.area;
432 ofs = 0;
433 azx_dev->frags = 0;
434
435 pos_adj = bus->bdl_pos_adj;
436 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
437 pos_align = pos_adj;
438 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
439 if (!pos_adj)
440 pos_adj = pos_align;
441 else
442 pos_adj = roundup(pos_adj, pos_align);
443 pos_adj = frames_to_bytes(runtime, pos_adj);
444 if (pos_adj >= period_bytes) {
445 dev_warn(bus->dev, "Too big adjustment %d\n",
446 pos_adj);
447 pos_adj = 0;
448 } else {
449 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
450 azx_dev,
451 &bdl, ofs, pos_adj, true);
452 if (ofs < 0)
453 goto error;
454 }
455 } else
456 pos_adj = 0;
457
458 for (i = 0; i < periods; i++) {
459 if (i == periods - 1 && pos_adj)
460 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
461 azx_dev, &bdl, ofs,
462 period_bytes - pos_adj, 0);
463 else
464 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
465 azx_dev, &bdl, ofs,
466 period_bytes,
467 !azx_dev->no_period_wakeup);
468 if (ofs < 0)
469 goto error;
470 }
471 return 0;
472
473 error:
474 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
475 azx_dev->bufsize, period_bytes);
476 return -EINVAL;
477}
478EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
479
480/**
481 * snd_hdac_stream_set_params - set stream parameters
482 * @azx_dev: HD-audio core stream for which parameters are to be set
483 * @format_val: format value parameter
484 *
485 * Setup the HD-audio core stream parameters from substream of the stream
486 * and passed format value
487 */
488int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
489 unsigned int format_val)
490{
491
492 unsigned int bufsize, period_bytes;
493 struct snd_pcm_substream *substream = azx_dev->substream;
494 struct snd_pcm_runtime *runtime;
495 int err;
496
497 if (!substream)
498 return -EINVAL;
499 runtime = substream->runtime;
500 bufsize = snd_pcm_lib_buffer_bytes(substream);
501 period_bytes = snd_pcm_lib_period_bytes(substream);
502
503 if (bufsize != azx_dev->bufsize ||
504 period_bytes != azx_dev->period_bytes ||
505 format_val != azx_dev->format_val ||
506 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
507 azx_dev->bufsize = bufsize;
508 azx_dev->period_bytes = period_bytes;
509 azx_dev->format_val = format_val;
510 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
511 err = snd_hdac_stream_setup_periods(azx_dev);
512 if (err < 0)
513 return err;
514 }
515 return 0;
516}
517EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
518
519static u64 azx_cc_read(const struct cyclecounter *cc)
520{
521 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
522
523 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
524}
525
526static void azx_timecounter_init(struct hdac_stream *azx_dev,
527 bool force, u64 last)
528{
529 struct timecounter *tc = &azx_dev->tc;
530 struct cyclecounter *cc = &azx_dev->cc;
531 u64 nsec;
532
533 cc->read = azx_cc_read;
534 cc->mask = CLOCKSOURCE_MASK(32);
535
536 /*
537 * Converting from 24 MHz to ns means applying a 125/3 factor.
538 * To avoid any saturation issues in intermediate operations,
539 * the 125 factor is applied first. The division is applied
540 * last after reading the timecounter value.
541 * Applying the 1/3 factor as part of the multiplication
542 * requires at least 20 bits for a decent precision, however
543 * overflows occur after about 4 hours or less, not a option.
544 */
545
546 cc->mult = 125; /* saturation after 195 years */
547 cc->shift = 0;
548
549 nsec = 0; /* audio time is elapsed time since trigger */
550 timecounter_init(tc, cc, nsec);
551 if (force) {
552 /*
553 * force timecounter to use predefined value,
554 * used for synchronized starts
555 */
556 tc->cycle_last = last;
557 }
558}
559
560/**
561 * snd_hdac_stream_timecounter_init - initialize time counter
562 * @azx_dev: HD-audio core stream (master stream)
563 * @streams: bit flags of streams to set up
564 *
565 * Initializes the time counter of streams marked by the bit flags (each
566 * bit corresponds to the stream index).
567 * The trigger timestamp of PCM substream assigned to the given stream is
568 * updated accordingly, too.
569 */
570void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
571 unsigned int streams)
572{
573 struct hdac_bus *bus = azx_dev->bus;
574 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
575 struct hdac_stream *s;
576 bool inited = false;
577 u64 cycle_last = 0;
578 int i = 0;
579
580 list_for_each_entry(s, &bus->stream_list, list) {
581 if (streams & (1 << i)) {
582 azx_timecounter_init(s, inited, cycle_last);
583 if (!inited) {
584 inited = true;
585 cycle_last = s->tc.cycle_last;
586 }
587 }
588 i++;
589 }
590
591 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
592 runtime->trigger_tstamp_latched = true;
593}
594EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
595
596/**
597 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
598 * @azx_dev: HD-audio core stream (master stream)
599 * @set: true = set, false = clear
600 * @streams: bit flags of streams to sync
601 * @reg: the stream sync register address
602 */
603void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
604 unsigned int streams, unsigned int reg)
605{
606 struct hdac_bus *bus = azx_dev->bus;
607 unsigned int val;
608
609 if (!reg)
610 reg = AZX_REG_SSYNC;
611 val = _snd_hdac_chip_readl(bus, reg);
612 if (set)
613 val |= streams;
614 else
615 val &= ~streams;
616 _snd_hdac_chip_writel(bus, reg, val);
617}
618EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
619
620/**
621 * snd_hdac_stream_sync - sync with start/stop trigger operation
622 * @azx_dev: HD-audio core stream (master stream)
623 * @start: true = start, false = stop
624 * @streams: bit flags of streams to sync
625 *
626 * For @start = true, wait until all FIFOs get ready.
627 * For @start = false, wait until all RUN bits are cleared.
628 */
629void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
630 unsigned int streams)
631{
632 struct hdac_bus *bus = azx_dev->bus;
633 int i, nwait, timeout;
634 struct hdac_stream *s;
635
636 for (timeout = 5000; timeout; timeout--) {
637 nwait = 0;
638 i = 0;
639 list_for_each_entry(s, &bus->stream_list, list) {
640 if (!(streams & (1 << i++)))
641 continue;
642
643 if (start) {
644 /* check FIFO gets ready */
645 if (!(snd_hdac_stream_readb(s, SD_STS) &
646 SD_STS_FIFO_READY))
647 nwait++;
648 } else {
649 /* check RUN bit is cleared */
650 if (snd_hdac_stream_readb(s, SD_CTL) &
651 SD_CTL_DMA_START) {
652 nwait++;
653 /*
654 * Perform stream reset if DMA RUN
655 * bit not cleared within given timeout
656 */
657 if (timeout == 1)
658 snd_hdac_stream_reset(s);
659 }
660 }
661 }
662 if (!nwait)
663 break;
664 cpu_relax();
665 }
666}
667EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
668
669#ifdef CONFIG_SND_HDA_DSP_LOADER
670/**
671 * snd_hdac_dsp_prepare - prepare for DSP loading
672 * @azx_dev: HD-audio core stream used for DSP loading
673 * @format: HD-audio stream format
674 * @byte_size: data chunk byte size
675 * @bufp: allocated buffer
676 *
677 * Allocate the buffer for the given size and set up the given stream for
678 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
679 */
680int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
681 unsigned int byte_size, struct snd_dma_buffer *bufp)
682{
683 struct hdac_bus *bus = azx_dev->bus;
684 __le32 *bdl;
685 int err;
686
687 snd_hdac_dsp_lock(azx_dev);
688 spin_lock_irq(&bus->reg_lock);
689 if (azx_dev->running || azx_dev->locked) {
690 spin_unlock_irq(&bus->reg_lock);
691 err = -EBUSY;
692 goto unlock;
693 }
694 azx_dev->locked = true;
695 spin_unlock_irq(&bus->reg_lock);
696
697 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
698 byte_size, bufp);
699 if (err < 0)
700 goto err_alloc;
701
702 azx_dev->substream = NULL;
703 azx_dev->bufsize = byte_size;
704 azx_dev->period_bytes = byte_size;
705 azx_dev->format_val = format;
706
707 snd_hdac_stream_reset(azx_dev);
708
709 /* reset BDL address */
710 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
711 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
712
713 azx_dev->frags = 0;
714 bdl = (__le32 *)azx_dev->bdl.area;
715 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
716 if (err < 0)
717 goto error;
718
719 snd_hdac_stream_setup(azx_dev);
720 snd_hdac_dsp_unlock(azx_dev);
721 return azx_dev->stream_tag;
722
723 error:
724 snd_dma_free_pages(bufp);
725 err_alloc:
726 spin_lock_irq(&bus->reg_lock);
727 azx_dev->locked = false;
728 spin_unlock_irq(&bus->reg_lock);
729 unlock:
730 snd_hdac_dsp_unlock(azx_dev);
731 return err;
732}
733EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
734
735/**
736 * snd_hdac_dsp_trigger - start / stop DSP loading
737 * @azx_dev: HD-audio core stream used for DSP loading
738 * @start: trigger start or stop
739 */
740void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
741{
742 if (start)
743 snd_hdac_stream_start(azx_dev, true);
744 else
745 snd_hdac_stream_stop(azx_dev);
746}
747EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
748
749/**
750 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
751 * @azx_dev: HD-audio core stream used for DSP loading
752 * @dmab: buffer used by DSP loading
753 */
754void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
755 struct snd_dma_buffer *dmab)
756{
757 struct hdac_bus *bus = azx_dev->bus;
758
759 if (!dmab->area || !azx_dev->locked)
760 return;
761
762 snd_hdac_dsp_lock(azx_dev);
763 /* reset BDL address */
764 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
765 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
766 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
767 azx_dev->bufsize = 0;
768 azx_dev->period_bytes = 0;
769 azx_dev->format_val = 0;
770
771 snd_dma_free_pages(dmab);
772 dmab->area = NULL;
773
774 spin_lock_irq(&bus->reg_lock);
775 azx_dev->locked = false;
776 spin_unlock_irq(&bus->reg_lock);
777 snd_hdac_dsp_unlock(azx_dev);
778}
779EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
780#endif /* CONFIG_SND_HDA_DSP_LOADER */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * HD-audio stream operations
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/export.h>
9#include <linux/clocksource.h>
10#include <sound/compress_driver.h>
11#include <sound/core.h>
12#include <sound/pcm.h>
13#include <sound/hdaudio.h>
14#include <sound/hda_register.h>
15#include "trace.h"
16
17/*
18 * the hdac_stream library is intended to be used with the following
19 * transitions. The states are not formally defined in the code but loosely
20 * inspired by boolean variables. Note that the 'prepared' field is not used
21 * in this library but by the callers during the hw_params/prepare transitions
22 *
23 * |
24 * stream_init() |
25 * v
26 * +--+-------+
27 * | unused |
28 * +--+----+--+
29 * | ^
30 * stream_assign() | | stream_release()
31 * v |
32 * +--+----+--+
33 * | opened |
34 * +--+----+--+
35 * | ^
36 * stream_reset() | |
37 * stream_setup() | | stream_cleanup()
38 * v |
39 * +--+----+--+
40 * | prepared |
41 * +--+----+--+
42 * | ^
43 * stream_start() | | stream_stop()
44 * v |
45 * +--+----+--+
46 * | running |
47 * +----------+
48 */
49
50/**
51 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus
53 * @substream: PCM substream
54 */
55int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 struct snd_pcm_substream *substream)
57{
58 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->channels,
60 rate = runtime->rate,
61 bits_per_sample = runtime->sample_bits,
62 max_sdo_lines, value, sdo_line;
63
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
66
67 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
69 if (rate > 48000)
70 value = (channels * bits_per_sample *
71 (rate / 48000)) / sdo_line;
72 else
73 value = (channels * bits_per_sample) / sdo_line;
74
75 if (value >= bus->sdo_limit)
76 break;
77 }
78
79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
80 return sdo_line >> 1;
81}
82EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
83
84/**
85 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign
91 *
92 * Assign the starting bdl address to each stream (device) and initialize.
93 */
94void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int direction, int tag)
96{
97 azx_dev->bus = bus;
98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx;
103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->stream_list);
107
108 if (bus->spbcap) {
109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
110 AZX_SPB_INTERVAL * idx +
111 AZX_SPB_SPIB;
112
113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
114 AZX_SPB_INTERVAL * idx +
115 AZX_SPB_MAXFIFO;
116 }
117
118 if (bus->drsmcap)
119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
120 AZX_DRSM_INTERVAL * idx;
121}
122EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123
124/**
125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start
127 *
128 * Start a stream, set start_wallclk and set the running flag.
129 */
130void snd_hdac_stream_start(struct hdac_stream *azx_dev)
131{
132 struct hdac_bus *bus = azx_dev->bus;
133 int stripe_ctl;
134
135 trace_snd_hdac_stream_start(bus, azx_dev);
136
137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
138
139 /* enable SIE */
140 snd_hdac_chip_updatel(bus, INTCTL,
141 1 << azx_dev->index,
142 1 << azx_dev->index);
143 /* set stripe control */
144 if (azx_dev->stripe) {
145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
147 else
148 stripe_ctl = 0;
149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
150 stripe_ctl);
151 }
152 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword)
154 snd_hdac_stream_updatel(azx_dev, SD_CTL,
155 0, SD_CTL_DMA_START | SD_INT_MASK);
156 else
157 snd_hdac_stream_updateb(azx_dev, SD_CTL,
158 0, SD_CTL_DMA_START | SD_INT_MASK);
159 azx_dev->running = true;
160}
161EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162
163/**
164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
165 * @azx_dev: HD-audio core stream to stop
166 */
167static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
168{
169 snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 SD_CTL_DMA_START | SD_INT_MASK, 0);
171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
172 if (azx_dev->stripe)
173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
174 azx_dev->running = false;
175}
176
177/**
178 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop
180 *
181 * Stop a stream DMA and disable stream interrupt
182 */
183void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
184{
185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
186
187 snd_hdac_stream_clear(azx_dev);
188 /* disable SIE */
189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
190}
191EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192
193/**
194 * snd_hdac_stop_streams - stop all streams
195 * @bus: HD-audio core bus
196 */
197void snd_hdac_stop_streams(struct hdac_bus *bus)
198{
199 struct hdac_stream *stream;
200
201 list_for_each_entry(stream, &bus->stream_list, list)
202 snd_hdac_stream_stop(stream);
203}
204EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
205
206/**
207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
208 * @bus: HD-audio core bus
209 */
210void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
211{
212
213 if (bus->chip_init) {
214 snd_hdac_stop_streams(bus);
215 snd_hdac_bus_stop_chip(bus);
216 }
217}
218EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
219
220/**
221 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset
223 */
224void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225{
226 unsigned char val;
227 int dma_run_state;
228
229 snd_hdac_stream_clear(azx_dev);
230
231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
232
233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
234
235 /* wait for hardware to report that the stream entered reset */
236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
237
238 if (azx_dev->bus->dma_stop_delay && dma_run_state)
239 udelay(azx_dev->bus->dma_stop_delay);
240
241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
242
243 /* wait for hardware to report that the stream is out of reset */
244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
245
246 /* reset first position - may not be synced with hw at this time */
247 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0;
249}
250EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251
252/**
253 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PCM or code-loading.
256 */
257int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading)
258{
259 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime;
261 unsigned int val;
262 u16 reg;
263 int ret;
264
265 if (azx_dev->substream)
266 runtime = azx_dev->substream->runtime;
267 else
268 runtime = NULL;
269 /* make sure the run bit is zero for SD */
270 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
273 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
274 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
275 if (!bus->snoop)
276 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
278
279 /* program the length of samples in cyclic buffer */
280 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
281
282 /* program the stream format */
283 /* this value needs to be the same as the one programmed */
284 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
285
286 /* program the stream LVI (last valid index) of the BDL */
287 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
288
289 /* program the BDL address */
290 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
292 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
294 upper_32_bits(azx_dev->bdl.addr));
295
296 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.addr) {
298 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
299 snd_hdac_chip_writel(bus, DPLBASE,
300 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
301 }
302
303 /* set the interrupt enable bits in the descriptor control register */
304 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
305
306 if (!code_loading) {
307 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */
308 ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg,
309 reg & AZX_SD_FIFOSIZE_MASK, 3, 300);
310 if (ret)
311 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n",
312 AZX_REG_SD_FIFOSIZE, ret);
313 azx_dev->fifo_size = reg;
314 }
315
316 /* when LPIB delay correction gives a small negative value,
317 * we ignore it; currently set the threshold statically to
318 * 64 frames
319 */
320 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runtime, 64);
323 else
324 azx_dev->delay_negative_threshold = 0;
325
326 /* wallclk has 24Mhz clock source */
327 if (runtime)
328 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->rate) * 1000);
330
331 return 0;
332}
333EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
334
335/**
336 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up
338 */
339void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
340{
341 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
342 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
343 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
344 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0;
347}
348EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
349
350/**
351 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign
354 *
355 * Look for an unused stream for the given PCM substream, assign it
356 * and return the stream object. If no stream is free, returns NULL.
357 * The function tries to keep using the same stream object when it's used
358 * beforehand. Also, when bus->reverse_assign flag is set, the last free
359 * or matching entry is returned. This is needed for some strange codecs.
360 */
361struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
362 struct snd_pcm_substream *substream)
363{
364 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL;
366
367 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | (substream->stream + 1);
369
370 if (substream->pcm)
371 key |= (substream->pcm->device << 16);
372
373 spin_lock_irq(&bus->reg_lock);
374 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != substream->stream)
376 continue;
377 if (azx_dev->opened)
378 continue;
379 if (azx_dev->assigned_key == key) {
380 res = azx_dev;
381 break;
382 }
383 if (!res || bus->reverse_assign)
384 res = azx_dev;
385 }
386 if (res) {
387 res->opened = 1;
388 res->running = 0;
389 res->assigned_key = key;
390 res->substream = substream;
391 }
392 spin_unlock_irq(&bus->reg_lock);
393 return res;
394}
395EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
396
397/**
398 * snd_hdac_stream_release_locked - release the assigned stream
399 * @azx_dev: HD-audio core stream to release
400 *
401 * Release the stream that has been assigned by snd_hdac_stream_assign().
402 * The bus->reg_lock needs to be taken at a higher level
403 */
404void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
405{
406 azx_dev->opened = 0;
407 azx_dev->running = 0;
408 azx_dev->substream = NULL;
409}
410EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
411
412/**
413 * snd_hdac_stream_release - release the assigned stream
414 * @azx_dev: HD-audio core stream to release
415 *
416 * Release the stream that has been assigned by snd_hdac_stream_assign().
417 */
418void snd_hdac_stream_release(struct hdac_stream *azx_dev)
419{
420 struct hdac_bus *bus = azx_dev->bus;
421
422 spin_lock_irq(&bus->reg_lock);
423 snd_hdac_stream_release_locked(azx_dev);
424 spin_unlock_irq(&bus->reg_lock);
425}
426EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
427
428/**
429 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
430 * direction
431 *
432 * @bus: HD-audio core bus
433 * @dir: direction for the stream to be found
434 * @stream_tag: stream tag for stream to be found
435 */
436struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
437 int dir, int stream_tag)
438{
439 struct hdac_stream *s;
440
441 list_for_each_entry(s, &bus->stream_list, list) {
442 if (s->direction == dir && s->stream_tag == stream_tag)
443 return s;
444 }
445
446 return NULL;
447}
448EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
449
450/*
451 * set up a BDL entry
452 */
453static int setup_bdle(struct hdac_bus *bus,
454 struct snd_dma_buffer *dmab,
455 struct hdac_stream *azx_dev, __le32 **bdlp,
456 int ofs, int size, int with_ioc)
457{
458 __le32 *bdl = *bdlp;
459
460 while (size > 0) {
461 dma_addr_t addr;
462 int chunk;
463
464 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
465 return -EINVAL;
466
467 addr = snd_sgbuf_get_addr(dmab, ofs);
468 /* program the address field of the BDL entry */
469 bdl[0] = cpu_to_le32((u32)addr);
470 bdl[1] = cpu_to_le32(upper_32_bits(addr));
471 /* program the size field of the BDL entry */
472 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
473 /* one BDLE cannot cross 4K boundary on CTHDA chips */
474 if (bus->align_bdle_4k) {
475 u32 remain = 0x1000 - (ofs & 0xfff);
476
477 if (chunk > remain)
478 chunk = remain;
479 }
480 bdl[2] = cpu_to_le32(chunk);
481 /* program the IOC to enable interrupt
482 * only when the whole fragment is processed
483 */
484 size -= chunk;
485 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
486 bdl += 4;
487 azx_dev->frags++;
488 ofs += chunk;
489 }
490 *bdlp = bdl;
491 return ofs;
492}
493
494/**
495 * snd_hdac_stream_setup_periods - set up BDL entries
496 * @azx_dev: HD-audio core stream to set up
497 *
498 * Set up the buffer descriptor table of the given stream based on the
499 * period and buffer sizes of the assigned PCM substream.
500 */
501int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
502{
503 struct hdac_bus *bus = azx_dev->bus;
504 struct snd_pcm_substream *substream = azx_dev->substream;
505 struct snd_compr_stream *cstream = azx_dev->cstream;
506 struct snd_pcm_runtime *runtime = NULL;
507 struct snd_dma_buffer *dmab;
508 __le32 *bdl;
509 int i, ofs, periods, period_bytes;
510 int pos_adj, pos_align;
511
512 if (substream) {
513 runtime = substream->runtime;
514 dmab = snd_pcm_get_dma_buf(substream);
515 } else if (cstream) {
516 dmab = snd_pcm_get_dma_buf(cstream);
517 } else {
518 WARN(1, "No substream or cstream assigned\n");
519 return -EINVAL;
520 }
521
522 /* reset BDL address */
523 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
524 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
525
526 period_bytes = azx_dev->period_bytes;
527 periods = azx_dev->bufsize / period_bytes;
528
529 /* program the initial BDL entries */
530 bdl = (__le32 *)azx_dev->bdl.area;
531 ofs = 0;
532 azx_dev->frags = 0;
533
534 pos_adj = bus->bdl_pos_adj;
535 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
536 pos_align = pos_adj;
537 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
538 if (!pos_adj)
539 pos_adj = pos_align;
540 else
541 pos_adj = roundup(pos_adj, pos_align);
542 pos_adj = frames_to_bytes(runtime, pos_adj);
543 if (pos_adj >= period_bytes) {
544 dev_warn(bus->dev, "Too big adjustment %d\n",
545 pos_adj);
546 pos_adj = 0;
547 } else {
548 ofs = setup_bdle(bus, dmab, azx_dev,
549 &bdl, ofs, pos_adj, true);
550 if (ofs < 0)
551 goto error;
552 }
553 } else
554 pos_adj = 0;
555
556 for (i = 0; i < periods; i++) {
557 if (i == periods - 1 && pos_adj)
558 ofs = setup_bdle(bus, dmab, azx_dev,
559 &bdl, ofs, period_bytes - pos_adj, 0);
560 else
561 ofs = setup_bdle(bus, dmab, azx_dev,
562 &bdl, ofs, period_bytes,
563 !azx_dev->no_period_wakeup);
564 if (ofs < 0)
565 goto error;
566 }
567 return 0;
568
569 error:
570 dev_dbg(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
571 azx_dev->bufsize, period_bytes);
572 return -EINVAL;
573}
574EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
575
576/**
577 * snd_hdac_stream_set_params - set stream parameters
578 * @azx_dev: HD-audio core stream for which parameters are to be set
579 * @format_val: format value parameter
580 *
581 * Setup the HD-audio core stream parameters from substream of the stream
582 * and passed format value
583 */
584int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
585 unsigned int format_val)
586{
587 struct snd_pcm_substream *substream = azx_dev->substream;
588 struct snd_compr_stream *cstream = azx_dev->cstream;
589 unsigned int bufsize, period_bytes;
590 unsigned int no_period_wakeup;
591 int err;
592
593 if (substream) {
594 bufsize = snd_pcm_lib_buffer_bytes(substream);
595 period_bytes = snd_pcm_lib_period_bytes(substream);
596 no_period_wakeup = substream->runtime->no_period_wakeup;
597 } else if (cstream) {
598 bufsize = cstream->runtime->buffer_size;
599 period_bytes = cstream->runtime->fragment_size;
600 no_period_wakeup = 0;
601 } else {
602 return -EINVAL;
603 }
604
605 if (bufsize != azx_dev->bufsize ||
606 period_bytes != azx_dev->period_bytes ||
607 format_val != azx_dev->format_val ||
608 no_period_wakeup != azx_dev->no_period_wakeup) {
609 azx_dev->bufsize = bufsize;
610 azx_dev->period_bytes = period_bytes;
611 azx_dev->format_val = format_val;
612 azx_dev->no_period_wakeup = no_period_wakeup;
613 err = snd_hdac_stream_setup_periods(azx_dev);
614 if (err < 0)
615 return err;
616 }
617 return 0;
618}
619EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
620
621static u64 azx_cc_read(const struct cyclecounter *cc)
622{
623 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
624
625 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
626}
627
628static void azx_timecounter_init(struct hdac_stream *azx_dev,
629 bool force, u64 last)
630{
631 struct timecounter *tc = &azx_dev->tc;
632 struct cyclecounter *cc = &azx_dev->cc;
633 u64 nsec;
634
635 cc->read = azx_cc_read;
636 cc->mask = CLOCKSOURCE_MASK(32);
637
638 /*
639 * Calculate the optimal mult/shift values. The counter wraps
640 * around after ~178.9 seconds.
641 */
642 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
643 NSEC_PER_SEC, 178);
644
645 nsec = 0; /* audio time is elapsed time since trigger */
646 timecounter_init(tc, cc, nsec);
647 if (force) {
648 /*
649 * force timecounter to use predefined value,
650 * used for synchronized starts
651 */
652 tc->cycle_last = last;
653 }
654}
655
656/**
657 * snd_hdac_stream_timecounter_init - initialize time counter
658 * @azx_dev: HD-audio core stream (master stream)
659 * @streams: bit flags of streams to set up
660 *
661 * Initializes the time counter of streams marked by the bit flags (each
662 * bit corresponds to the stream index).
663 * The trigger timestamp of PCM substream assigned to the given stream is
664 * updated accordingly, too.
665 */
666void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
667 unsigned int streams)
668{
669 struct hdac_bus *bus = azx_dev->bus;
670 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
671 struct hdac_stream *s;
672 bool inited = false;
673 u64 cycle_last = 0;
674
675 list_for_each_entry(s, &bus->stream_list, list) {
676 if ((streams & (1 << s->index))) {
677 azx_timecounter_init(s, inited, cycle_last);
678 if (!inited) {
679 inited = true;
680 cycle_last = s->tc.cycle_last;
681 }
682 }
683 }
684
685 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
686 runtime->trigger_tstamp_latched = true;
687}
688EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
689
690/**
691 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
692 * @azx_dev: HD-audio core stream (master stream)
693 * @set: true = set, false = clear
694 * @streams: bit flags of streams to sync
695 * @reg: the stream sync register address
696 */
697void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
698 unsigned int streams, unsigned int reg)
699{
700 struct hdac_bus *bus = azx_dev->bus;
701 unsigned int val;
702
703 if (!reg)
704 reg = AZX_REG_SSYNC;
705 val = _snd_hdac_chip_readl(bus, reg);
706 if (set)
707 val |= streams;
708 else
709 val &= ~streams;
710 _snd_hdac_chip_writel(bus, reg, val);
711}
712EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
713
714/**
715 * snd_hdac_stream_sync - sync with start/stop trigger operation
716 * @azx_dev: HD-audio core stream (master stream)
717 * @start: true = start, false = stop
718 * @streams: bit flags of streams to sync
719 *
720 * For @start = true, wait until all FIFOs get ready.
721 * For @start = false, wait until all RUN bits are cleared.
722 */
723void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
724 unsigned int streams)
725{
726 struct hdac_bus *bus = azx_dev->bus;
727 int nwait, timeout;
728 struct hdac_stream *s;
729
730 for (timeout = 5000; timeout; timeout--) {
731 nwait = 0;
732 list_for_each_entry(s, &bus->stream_list, list) {
733 if (!(streams & (1 << s->index)))
734 continue;
735
736 if (start) {
737 /* check FIFO gets ready */
738 if (!(snd_hdac_stream_readb(s, SD_STS) &
739 SD_STS_FIFO_READY))
740 nwait++;
741 } else {
742 /* check RUN bit is cleared */
743 if (snd_hdac_stream_readb(s, SD_CTL) &
744 SD_CTL_DMA_START) {
745 nwait++;
746 /*
747 * Perform stream reset if DMA RUN
748 * bit not cleared within given timeout
749 */
750 if (timeout == 1)
751 snd_hdac_stream_reset(s);
752 }
753 }
754 }
755 if (!nwait)
756 break;
757 cpu_relax();
758 }
759}
760EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
761
762/**
763 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
764 * @bus: HD-audio core bus
765 * @enable: flag to enable/disable SPIB
766 * @index: stream index for which SPIB need to be enabled
767 */
768void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
769 bool enable, int index)
770{
771 u32 mask = 0;
772
773 if (!bus->spbcap) {
774 dev_err(bus->dev, "Address of SPB capability is NULL\n");
775 return;
776 }
777
778 mask |= (1 << index);
779
780 if (enable)
781 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
782 else
783 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
784}
785EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
786
787/**
788 * snd_hdac_stream_set_spib - sets the spib value of a stream
789 * @bus: HD-audio core bus
790 * @azx_dev: hdac_stream
791 * @value: spib value to set
792 */
793int snd_hdac_stream_set_spib(struct hdac_bus *bus,
794 struct hdac_stream *azx_dev, u32 value)
795{
796 if (!bus->spbcap) {
797 dev_err(bus->dev, "Address of SPB capability is NULL\n");
798 return -EINVAL;
799 }
800
801 writel(value, azx_dev->spib_addr);
802
803 return 0;
804}
805EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
806
807/**
808 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
809 * @bus: HD-audio core bus
810 * @azx_dev: hdac_stream
811 *
812 * Return maxfifo for the stream
813 */
814int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
815 struct hdac_stream *azx_dev)
816{
817 if (!bus->spbcap) {
818 dev_err(bus->dev, "Address of SPB capability is NULL\n");
819 return -EINVAL;
820 }
821
822 return readl(azx_dev->fifo_addr);
823}
824EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
825
826/**
827 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
828 * @bus: HD-audio core bus
829 * @enable: flag to enable/disable DRSM
830 * @index: stream index for which DRSM need to be enabled
831 */
832void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
833 bool enable, int index)
834{
835 u32 mask = 0;
836
837 if (!bus->drsmcap) {
838 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
839 return;
840 }
841
842 mask |= (1 << index);
843
844 if (enable)
845 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
846 else
847 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
848}
849EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
850
851/*
852 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
853 * @azx_dev: HD-audio core stream to await RSM for
854 *
855 * Returns 0 on success and -ETIMEDOUT upon a timeout.
856 */
857int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
858{
859 struct hdac_bus *bus = azx_dev->bus;
860 u32 mask, reg;
861 int ret;
862
863 mask = 1 << azx_dev->index;
864
865 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
866 bus->drsmcap + AZX_REG_DRSM_CTL);
867 if (ret)
868 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
869 return ret;
870}
871EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
872
873/**
874 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
875 * @bus: HD-audio core bus
876 * @azx_dev: hdac_stream
877 * @value: dpib value to set
878 */
879int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
880 struct hdac_stream *azx_dev, u32 value)
881{
882 if (!bus->drsmcap) {
883 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
884 return -EINVAL;
885 }
886
887 writel(value, azx_dev->dpibr_addr);
888
889 return 0;
890}
891EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
892
893/**
894 * snd_hdac_stream_set_lpib - sets the lpib value of a stream
895 * @azx_dev: hdac_stream
896 * @value: lpib value to set
897 */
898int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
899{
900 snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
901
902 return 0;
903}
904EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
905
906#ifdef CONFIG_SND_HDA_DSP_LOADER
907/**
908 * snd_hdac_dsp_prepare - prepare for DSP loading
909 * @azx_dev: HD-audio core stream used for DSP loading
910 * @format: HD-audio stream format
911 * @byte_size: data chunk byte size
912 * @bufp: allocated buffer
913 *
914 * Allocate the buffer for the given size and set up the given stream for
915 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
916 */
917int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
918 unsigned int byte_size, struct snd_dma_buffer *bufp)
919{
920 struct hdac_bus *bus = azx_dev->bus;
921 __le32 *bdl;
922 int err;
923
924 snd_hdac_dsp_lock(azx_dev);
925 spin_lock_irq(&bus->reg_lock);
926 if (azx_dev->running || azx_dev->locked) {
927 spin_unlock_irq(&bus->reg_lock);
928 err = -EBUSY;
929 goto unlock;
930 }
931 azx_dev->locked = true;
932 spin_unlock_irq(&bus->reg_lock);
933
934 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
935 byte_size, bufp);
936 if (err < 0)
937 goto err_alloc;
938
939 azx_dev->substream = NULL;
940 azx_dev->bufsize = byte_size;
941 azx_dev->period_bytes = byte_size;
942 azx_dev->format_val = format;
943
944 snd_hdac_stream_reset(azx_dev);
945
946 /* reset BDL address */
947 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
948 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
949
950 azx_dev->frags = 0;
951 bdl = (__le32 *)azx_dev->bdl.area;
952 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
953 if (err < 0)
954 goto error;
955
956 snd_hdac_stream_setup(azx_dev, true);
957 snd_hdac_dsp_unlock(azx_dev);
958 return azx_dev->stream_tag;
959
960 error:
961 snd_dma_free_pages(bufp);
962 err_alloc:
963 spin_lock_irq(&bus->reg_lock);
964 azx_dev->locked = false;
965 spin_unlock_irq(&bus->reg_lock);
966 unlock:
967 snd_hdac_dsp_unlock(azx_dev);
968 return err;
969}
970EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
971
972/**
973 * snd_hdac_dsp_trigger - start / stop DSP loading
974 * @azx_dev: HD-audio core stream used for DSP loading
975 * @start: trigger start or stop
976 */
977void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
978{
979 if (start)
980 snd_hdac_stream_start(azx_dev);
981 else
982 snd_hdac_stream_stop(azx_dev);
983}
984EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
985
986/**
987 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
988 * @azx_dev: HD-audio core stream used for DSP loading
989 * @dmab: buffer used by DSP loading
990 */
991void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
992 struct snd_dma_buffer *dmab)
993{
994 struct hdac_bus *bus = azx_dev->bus;
995
996 if (!dmab->area || !azx_dev->locked)
997 return;
998
999 snd_hdac_dsp_lock(azx_dev);
1000 /* reset BDL address */
1001 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
1002 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
1003 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
1004 azx_dev->bufsize = 0;
1005 azx_dev->period_bytes = 0;
1006 azx_dev->format_val = 0;
1007
1008 snd_dma_free_pages(dmab);
1009 dmab->area = NULL;
1010
1011 spin_lock_irq(&bus->reg_lock);
1012 azx_dev->locked = false;
1013 spin_unlock_irq(&bus->reg_lock);
1014 snd_hdac_dsp_unlock(azx_dev);
1015}
1016EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1017#endif /* CONFIG_SND_HDA_DSP_LOADER */