1/*
  2 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
  3 *
  4 * This software is available to you under a choice of one of two
  5 * licenses.  You may choose to be licensed under the terms of the GNU
  6 * General Public License (GPL) Version 2, available from the file
  7 * COPYING in the main directory of this source tree, or the
  8 * OpenIB.org BSD license below:
  9 *
 10 *     Redistribution and use in source and binary forms, with or
 11 *     without modification, are permitted provided that the following
 12 *     conditions are met:
 13 *
 14 *      - Redistributions of source code must retain the above
 15 *        copyright notice, this list of conditions and the following
 16 *        disclaimer.
 17 *
 18 *      - Redistributions in binary form must reproduce the above
 19 *        copyright notice, this list of conditions and the following
 20 *        disclaimer in the documentation and/or other materials
 21 *        provided with the distribution.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 30 * SOFTWARE.
 31 *
 32 */
 33
 34#ifndef __MLX5_ACCEL_H__
 35#define __MLX5_ACCEL_H__
 36
 37#include <linux/mlx5/driver.h>
 38
 39enum mlx5_accel_esp_aes_gcm_keymat_iv_algo {
 40	MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ,
 41};
 42
 43enum mlx5_accel_esp_flags {
 44	MLX5_ACCEL_ESP_FLAGS_TUNNEL            = 0,    /* Default */
 45	MLX5_ACCEL_ESP_FLAGS_TRANSPORT         = 1UL << 0,
 46	MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED     = 1UL << 1,
 47	MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP = 1UL << 2,
 48};
 49
 50enum mlx5_accel_esp_action {
 51	MLX5_ACCEL_ESP_ACTION_DECRYPT,
 52	MLX5_ACCEL_ESP_ACTION_ENCRYPT,
 53};
 54
 55enum mlx5_accel_esp_keymats {
 56	MLX5_ACCEL_ESP_KEYMAT_AES_NONE,
 57	MLX5_ACCEL_ESP_KEYMAT_AES_GCM,
 58};
 59
 60enum mlx5_accel_esp_replay {
 61	MLX5_ACCEL_ESP_REPLAY_NONE,
 62	MLX5_ACCEL_ESP_REPLAY_BMP,
 63};
 64
 65struct aes_gcm_keymat {
 66	u64   seq_iv;
 67	enum mlx5_accel_esp_aes_gcm_keymat_iv_algo iv_algo;
 68
 69	u32   salt;
 70	u32   icv_len;
 71
 72	u32   key_len;
 73	u32   aes_key[256 / 32];
 74};
 75
 76struct mlx5_accel_esp_xfrm_attrs {
 77	enum mlx5_accel_esp_action action;
 78	u32   esn;
 79	__be32 spi;
 80	u32   seq;
 81	u32   tfc_pad;
 82	u32   flags;
 83	u32   sa_handle;
 84	enum mlx5_accel_esp_replay replay_type;
 85	union {
 86		struct {
 87			u32 size;
 88
 89		} bmp;
 90	} replay;
 91	enum mlx5_accel_esp_keymats keymat_type;
 92	union {
 93		struct aes_gcm_keymat aes_gcm;
 94	} keymat;
 95
 96	union {
 97		__be32 a4;
 98		__be32 a6[4];
 99	} saddr;
100
101	union {
102		__be32 a4;
103		__be32 a6[4];
104	} daddr;
105
106	u8 is_ipv6;
107};
108
109struct mlx5_accel_esp_xfrm {
110	struct mlx5_core_dev  *mdev;
111	struct mlx5_accel_esp_xfrm_attrs attrs;
112};
113
114enum {
115	MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA = 1UL << 0,
116};
117
118enum mlx5_accel_ipsec_cap {
119	MLX5_ACCEL_IPSEC_CAP_DEVICE		= 1 << 0,
120	MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA	= 1 << 1,
121	MLX5_ACCEL_IPSEC_CAP_ESP		= 1 << 2,
122	MLX5_ACCEL_IPSEC_CAP_IPV6		= 1 << 3,
123	MLX5_ACCEL_IPSEC_CAP_LSO		= 1 << 4,
124	MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER	= 1 << 5,
125	MLX5_ACCEL_IPSEC_CAP_ESN		= 1 << 6,
126	MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN	= 1 << 7,
127};
128
129#ifdef CONFIG_MLX5_ACCEL
130
131u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
132
133struct mlx5_accel_esp_xfrm *
134mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
135			   const struct mlx5_accel_esp_xfrm_attrs *attrs,
136			   u32 flags);
137void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm);
138int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
139			       const struct mlx5_accel_esp_xfrm_attrs *attrs);
140
141#else
142
143static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
144
145static inline struct mlx5_accel_esp_xfrm *
146mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
147			   const struct mlx5_accel_esp_xfrm_attrs *attrs,
148			   u32 flags) { return ERR_PTR(-EOPNOTSUPP); }
149static inline void
150mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) {}
151static inline int
152mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
153			   const struct mlx5_accel_esp_xfrm_attrs *attrs) { return -EOPNOTSUPP; }
154
155#endif /* CONFIG_MLX5_ACCEL */
156#endif /* __MLX5_ACCEL_H__ */