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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/component.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/list.h>
21#include <linux/iommu.h>
22#include <linux/types.h>
23#include <linux/of_graph.h>
24#include <linux/of_device.h>
25#include <linux/sizes.h>
26#include <linux/kthread.h>
27
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_plane_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/drm_fb_helper.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36struct msm_kms;
37struct msm_gpu;
38struct msm_mmu;
39struct msm_mdss;
40struct msm_rd_state;
41struct msm_perf_state;
42struct msm_gem_submit;
43struct msm_fence_context;
44struct msm_gem_address_space;
45struct msm_gem_vma;
46struct msm_disp_state;
47
48#define MAX_CRTCS 8
49#define MAX_PLANES 20
50#define MAX_ENCODERS 8
51#define MAX_BRIDGES 8
52#define MAX_CONNECTORS 8
53
54#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
55
56struct msm_file_private {
57 rwlock_t queuelock;
58 struct list_head submitqueues;
59 int queueid;
60 struct msm_gem_address_space *aspace;
61 struct kref ref;
62 int seqno;
63};
64
65enum msm_mdp_plane_property {
66 PLANE_PROP_ZPOS,
67 PLANE_PROP_ALPHA,
68 PLANE_PROP_PREMULTIPLIED,
69 PLANE_PROP_MAX_NUM
70};
71
72#define MSM_GPU_MAX_RINGS 4
73#define MAX_H_TILES_PER_DISPLAY 2
74
75/**
76 * enum msm_display_caps - features/capabilities supported by displays
77 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
78 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
79 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
80 * @MSM_DISPLAY_CAP_EDID: EDID supported
81 */
82enum msm_display_caps {
83 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
84 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
85 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
86 MSM_DISPLAY_CAP_EDID = BIT(3),
87};
88
89/**
90 * enum msm_event_wait - type of HW events to wait for
91 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
92 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
93 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
94 */
95enum msm_event_wait {
96 MSM_ENC_COMMIT_DONE = 0,
97 MSM_ENC_TX_COMPLETE,
98 MSM_ENC_VBLANK,
99};
100
101/**
102 * struct msm_display_topology - defines a display topology pipeline
103 * @num_lm: number of layer mixers used
104 * @num_enc: number of compression encoder blocks used
105 * @num_intf: number of interfaces the panel is mounted on
106 */
107struct msm_display_topology {
108 u32 num_lm;
109 u32 num_enc;
110 u32 num_intf;
111 u32 num_dspp;
112};
113
114/**
115 * struct msm_display_info - defines display properties
116 * @intf_type: DRM_MODE_ENCODER_ type
117 * @capabilities: Bitmask of display flags
118 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
119 * @h_tile_instance: Controller instance used per tile. Number of elements is
120 * based on num_of_h_tiles
121 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
122 * used instead of panel TE in cmd mode panels
123 */
124struct msm_display_info {
125 int intf_type;
126 uint32_t capabilities;
127 uint32_t num_of_h_tiles;
128 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
129 bool is_te_using_watchdog_timer;
130};
131
132/* Commit/Event thread specific structure */
133struct msm_drm_thread {
134 struct drm_device *dev;
135 unsigned int crtc_id;
136 struct kthread_worker *worker;
137};
138
139struct msm_drm_private {
140
141 struct drm_device *dev;
142
143 struct msm_kms *kms;
144
145 /* subordinate devices, if present: */
146 struct platform_device *gpu_pdev;
147
148 /* top level MDSS wrapper device (for MDP5/DPU only) */
149 struct msm_mdss *mdss;
150
151 /* possibly this should be in the kms component, but it is
152 * shared by both mdp4 and mdp5..
153 */
154 struct hdmi *hdmi;
155
156 /* eDP is for mdp5 only, but kms has not been created
157 * when edp_bind() and edp_init() are called. Here is the only
158 * place to keep the edp instance.
159 */
160 struct msm_edp *edp;
161
162 /* DSI is shared by mdp4 and mdp5 */
163 struct msm_dsi *dsi[2];
164
165 struct msm_dp *dp;
166
167 /* when we have more than one 'msm_gpu' these need to be an array: */
168 struct msm_gpu *gpu;
169 struct msm_file_private *lastctx;
170 /* gpu is only set on open(), but we need this info earlier */
171 bool is_a2xx;
172 bool has_cached_coherent;
173
174 struct drm_fb_helper *fbdev;
175
176 struct msm_rd_state *rd; /* debugfs to dump all submits */
177 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
178 struct msm_perf_state *perf;
179
180 /**
181 * List of all GEM objects (mainly for debugfs, protected by obj_lock
182 * (acquire before per GEM object lock)
183 */
184 struct list_head objects;
185 struct mutex obj_lock;
186
187 /**
188 * LRUs of inactive GEM objects. Every bo is either in one of the
189 * inactive lists (depending on whether or not it is shrinkable) or
190 * gpu->active_list (for the gpu it is active on[1]), or transiently
191 * on a temporary list as the shrinker is running.
192 *
193 * Note that inactive_willneed also contains pinned and vmap'd bos,
194 * but the number of pinned-but-not-active objects is small (scanout
195 * buffers, ringbuffer, etc).
196 *
197 * These lists are protected by mm_lock (which should be acquired
198 * before per GEM object lock). One should *not* hold mm_lock in
199 * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
200 *
201 * [1] if someone ever added support for the old 2d cores, there could be
202 * more than one gpu object
203 */
204 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */
205 struct list_head inactive_dontneed; /* inactive + shrinkable */
206 struct list_head inactive_unpinned; /* inactive + purged or unpinned */
207 long shrinkable_count; /* write access under mm_lock */
208 long evictable_count; /* write access under mm_lock */
209 struct mutex mm_lock;
210
211 struct workqueue_struct *wq;
212
213 unsigned int num_planes;
214 struct drm_plane *planes[MAX_PLANES];
215
216 unsigned int num_crtcs;
217 struct drm_crtc *crtcs[MAX_CRTCS];
218
219 struct msm_drm_thread event_thread[MAX_CRTCS];
220
221 unsigned int num_encoders;
222 struct drm_encoder *encoders[MAX_ENCODERS];
223
224 unsigned int num_bridges;
225 struct drm_bridge *bridges[MAX_BRIDGES];
226
227 unsigned int num_connectors;
228 struct drm_connector *connectors[MAX_CONNECTORS];
229
230 /* Properties */
231 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
232
233 /* VRAM carveout, used when no IOMMU: */
234 struct {
235 unsigned long size;
236 dma_addr_t paddr;
237 /* NOTE: mm managed at the page level, size is in # of pages
238 * and position mm_node->start is in # of pages:
239 */
240 struct drm_mm mm;
241 spinlock_t lock; /* Protects drm_mm node allocation/removal */
242 } vram;
243
244 struct notifier_block vmap_notifier;
245 struct shrinker shrinker;
246
247 struct drm_atomic_state *pm_state;
248
249 /* For hang detection, in ms */
250 unsigned int hangcheck_period;
251};
252
253struct msm_format {
254 uint32_t pixel_format;
255};
256
257struct msm_pending_timer;
258
259int msm_atomic_prepare_fb(struct drm_plane *plane,
260 struct drm_plane_state *new_state);
261int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
262 struct msm_kms *kms, int crtc_idx);
263void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
264void msm_atomic_commit_tail(struct drm_atomic_state *state);
265struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
266void msm_atomic_state_clear(struct drm_atomic_state *state);
267void msm_atomic_state_free(struct drm_atomic_state *state);
268
269int msm_crtc_enable_vblank(struct drm_crtc *crtc);
270void msm_crtc_disable_vblank(struct drm_crtc *crtc);
271
272int msm_gem_init_vma(struct msm_gem_address_space *aspace,
273 struct msm_gem_vma *vma, int npages,
274 u64 range_start, u64 range_end);
275void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
276 struct msm_gem_vma *vma);
277void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
278 struct msm_gem_vma *vma);
279int msm_gem_map_vma(struct msm_gem_address_space *aspace,
280 struct msm_gem_vma *vma, int prot,
281 struct sg_table *sgt, int npages);
282void msm_gem_close_vma(struct msm_gem_address_space *aspace,
283 struct msm_gem_vma *vma);
284
285
286struct msm_gem_address_space *
287msm_gem_address_space_get(struct msm_gem_address_space *aspace);
288
289void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
290
291struct msm_gem_address_space *
292msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
293 u64 va_start, u64 size);
294
295int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
296void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
297
298bool msm_use_mmu(struct drm_device *dev);
299
300int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
301 struct drm_file *file);
302
303#ifdef CONFIG_DEBUG_FS
304unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
305#endif
306
307void msm_gem_shrinker_init(struct drm_device *dev);
308void msm_gem_shrinker_cleanup(struct drm_device *dev);
309
310struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
311int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
312void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
313int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
314struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
315 struct dma_buf_attachment *attach, struct sg_table *sg);
316int msm_gem_prime_pin(struct drm_gem_object *obj);
317void msm_gem_prime_unpin(struct drm_gem_object *obj);
318
319int msm_framebuffer_prepare(struct drm_framebuffer *fb,
320 struct msm_gem_address_space *aspace);
321void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
322 struct msm_gem_address_space *aspace);
323uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
324 struct msm_gem_address_space *aspace, int plane);
325struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
326const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
327struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
328 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
329struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
330 int w, int h, int p, uint32_t format);
331
332struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
333void msm_fbdev_free(struct drm_device *dev);
334
335struct hdmi;
336int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
337 struct drm_encoder *encoder);
338void __init msm_hdmi_register(void);
339void __exit msm_hdmi_unregister(void);
340
341struct msm_edp;
342void __init msm_edp_register(void);
343void __exit msm_edp_unregister(void);
344int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
345 struct drm_encoder *encoder);
346
347struct msm_dsi;
348#ifdef CONFIG_DRM_MSM_DSI
349void __init msm_dsi_register(void);
350void __exit msm_dsi_unregister(void);
351int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
352 struct drm_encoder *encoder);
353void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
354
355#else
356static inline void __init msm_dsi_register(void)
357{
358}
359static inline void __exit msm_dsi_unregister(void)
360{
361}
362static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
363 struct drm_device *dev,
364 struct drm_encoder *encoder)
365{
366 return -EINVAL;
367}
368static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
369{
370}
371
372#endif
373
374#ifdef CONFIG_DRM_MSM_DP
375int __init msm_dp_register(void);
376void __exit msm_dp_unregister(void);
377int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
378 struct drm_encoder *encoder);
379int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
380int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
381int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
382void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
383 struct drm_display_mode *mode,
384 struct drm_display_mode *adjusted_mode);
385void msm_dp_irq_postinstall(struct msm_dp *dp_display);
386void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
387
388void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
389
390#else
391static inline int __init msm_dp_register(void)
392{
393 return -EINVAL;
394}
395static inline void __exit msm_dp_unregister(void)
396{
397}
398static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
399 struct drm_device *dev,
400 struct drm_encoder *encoder)
401{
402 return -EINVAL;
403}
404static inline int msm_dp_display_enable(struct msm_dp *dp,
405 struct drm_encoder *encoder)
406{
407 return -EINVAL;
408}
409static inline int msm_dp_display_disable(struct msm_dp *dp,
410 struct drm_encoder *encoder)
411{
412 return -EINVAL;
413}
414static inline int msm_dp_display_pre_disable(struct msm_dp *dp,
415 struct drm_encoder *encoder)
416{
417 return -EINVAL;
418}
419static inline void msm_dp_display_mode_set(struct msm_dp *dp,
420 struct drm_encoder *encoder,
421 struct drm_display_mode *mode,
422 struct drm_display_mode *adjusted_mode)
423{
424}
425
426static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
427{
428}
429
430static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
431{
432}
433
434static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
435 struct drm_minor *minor)
436{
437}
438
439#endif
440
441void __init msm_mdp_register(void);
442void __exit msm_mdp_unregister(void);
443void __init msm_dpu_register(void);
444void __exit msm_dpu_unregister(void);
445
446#ifdef CONFIG_DEBUG_FS
447void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
448int msm_debugfs_late_init(struct drm_device *dev);
449int msm_rd_debugfs_init(struct drm_minor *minor);
450void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
451__printf(3, 4)
452void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
453 const char *fmt, ...);
454int msm_perf_debugfs_init(struct drm_minor *minor);
455void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
456#else
457static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
458__printf(3, 4)
459static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
460 struct msm_gem_submit *submit,
461 const char *fmt, ...) {}
462static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
463static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
464#endif
465
466struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
467
468struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
469 const char *name);
470void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
471 const char *dbgname);
472void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
473 const char *dbgname, phys_addr_t *size);
474void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
475 const char *dbgname);
476void msm_writel(u32 data, void __iomem *addr);
477u32 msm_readl(const void __iomem *addr);
478void msm_rmw(void __iomem *addr, u32 mask, u32 or);
479
480struct msm_gpu_submitqueue;
481int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
482struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
483 u32 id);
484int msm_submitqueue_create(struct drm_device *drm,
485 struct msm_file_private *ctx,
486 u32 prio, u32 flags, u32 *id);
487int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
488 struct drm_msm_submitqueue_query *args);
489int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
490void msm_submitqueue_close(struct msm_file_private *ctx);
491
492void msm_submitqueue_destroy(struct kref *kref);
493
494static inline void __msm_file_private_destroy(struct kref *kref)
495{
496 struct msm_file_private *ctx = container_of(kref,
497 struct msm_file_private, ref);
498
499 msm_gem_address_space_put(ctx->aspace);
500 kfree(ctx);
501}
502
503static inline void msm_file_private_put(struct msm_file_private *ctx)
504{
505 kref_put(&ctx->ref, __msm_file_private_destroy);
506}
507
508static inline struct msm_file_private *msm_file_private_get(
509 struct msm_file_private *ctx)
510{
511 kref_get(&ctx->ref);
512 return ctx;
513}
514
515#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
516#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
517
518static inline int align_pitch(int width, int bpp)
519{
520 int bytespp = (bpp + 7) / 8;
521 /* adreno needs pitch aligned to 32 pixels: */
522 return bytespp * ALIGN(width, 32);
523}
524
525/* for the generated headers: */
526#define INVALID_IDX(idx) ({BUG(); 0;})
527#define fui(x) ({BUG(); 0;})
528#define _mesa_float_to_half(x) ({BUG(); 0;})
529
530
531#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
532
533/* for conditionally setting boolean flag(s): */
534#define COND(bool, val) ((bool) ? (val) : 0)
535
536static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
537{
538 ktime_t now = ktime_get();
539 s64 remaining_jiffies;
540
541 if (ktime_compare(*timeout, now) < 0) {
542 remaining_jiffies = 0;
543 } else {
544 ktime_t rem = ktime_sub(*timeout, now);
545 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
546 }
547
548 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
549}
550
551#endif /* __MSM_DRV_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/devfreq.h>
15#include <linux/module.h>
16#include <linux/component.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22#include <linux/iommu.h>
23#include <linux/types.h>
24#include <linux/of_graph.h>
25#include <linux/of_device.h>
26#include <linux/sizes.h>
27#include <linux/kthread.h>
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/display/drm_dsc.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36#ifdef CONFIG_FAULT_INJECTION
37extern struct fault_attr fail_gem_alloc;
38extern struct fault_attr fail_gem_iova;
39#else
40# define should_fail(attr, size) 0
41#endif
42
43struct msm_kms;
44struct msm_gpu;
45struct msm_mmu;
46struct msm_mdss;
47struct msm_rd_state;
48struct msm_perf_state;
49struct msm_gem_submit;
50struct msm_fence_context;
51struct msm_gem_address_space;
52struct msm_gem_vma;
53struct msm_disp_state;
54
55#define MAX_CRTCS 8
56#define MAX_BRIDGES 8
57
58#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
59
60enum msm_dp_controller {
61 MSM_DP_CONTROLLER_0,
62 MSM_DP_CONTROLLER_1,
63 MSM_DP_CONTROLLER_2,
64 MSM_DP_CONTROLLER_3,
65 MSM_DP_CONTROLLER_COUNT,
66};
67
68enum msm_dsi_controller {
69 MSM_DSI_CONTROLLER_0,
70 MSM_DSI_CONTROLLER_1,
71 MSM_DSI_CONTROLLER_COUNT,
72};
73
74#define MSM_GPU_MAX_RINGS 4
75#define MAX_H_TILES_PER_DISPLAY 2
76
77/**
78 * struct msm_display_topology - defines a display topology pipeline
79 * @num_lm: number of layer mixers used
80 * @num_intf: number of interfaces the panel is mounted on
81 * @num_dspp: number of dspp blocks used
82 * @num_dsc: number of Display Stream Compression (DSC) blocks used
83 * @needs_cdm: indicates whether cdm block is needed for this display topology
84 */
85struct msm_display_topology {
86 u32 num_lm;
87 u32 num_intf;
88 u32 num_dspp;
89 u32 num_dsc;
90 bool needs_cdm;
91};
92
93/* Commit/Event thread specific structure */
94struct msm_drm_thread {
95 struct drm_device *dev;
96 struct kthread_worker *worker;
97};
98
99struct msm_drm_private {
100
101 struct drm_device *dev;
102
103 struct msm_kms *kms;
104 int (*kms_init)(struct drm_device *dev);
105
106 /* subordinate devices, if present: */
107 struct platform_device *gpu_pdev;
108
109 /* possibly this should be in the kms component, but it is
110 * shared by both mdp4 and mdp5..
111 */
112 struct hdmi *hdmi;
113
114 /* DSI is shared by mdp4 and mdp5 */
115 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
116
117 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
118
119 /* when we have more than one 'msm_gpu' these need to be an array: */
120 struct msm_gpu *gpu;
121
122 /* gpu is only set on open(), but we need this info earlier */
123 bool is_a2xx;
124 bool has_cached_coherent;
125
126 struct msm_rd_state *rd; /* debugfs to dump all submits */
127 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
128 struct msm_perf_state *perf;
129
130 /**
131 * List of all GEM objects (mainly for debugfs, protected by obj_lock
132 * (acquire before per GEM object lock)
133 */
134 struct list_head objects;
135 struct mutex obj_lock;
136
137 /**
138 * lru:
139 *
140 * The various LRU's that a GEM object is in at various stages of
141 * it's lifetime. Objects start out in the unbacked LRU. When
142 * pinned (for scannout or permanently mapped GPU buffers, like
143 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When
144 * unpinned, it moves into willneed or dontneed LRU depending on
145 * madvise state. When backing pages are evicted (willneed) or
146 * purged (dontneed) it moves back into the unbacked LRU.
147 *
148 * The dontneed LRU is considered by the shrinker for objects
149 * that are candidate for purging, and the willneed LRU is
150 * considered for objects that could be evicted.
151 */
152 struct {
153 /**
154 * unbacked:
155 *
156 * The LRU for GEM objects without backing pages allocated.
157 * This mostly exists so that objects are always is one
158 * LRU.
159 */
160 struct drm_gem_lru unbacked;
161
162 /**
163 * pinned:
164 *
165 * The LRU for pinned GEM objects
166 */
167 struct drm_gem_lru pinned;
168
169 /**
170 * willneed:
171 *
172 * The LRU for unpinned GEM objects which are in madvise
173 * WILLNEED state (ie. can be evicted)
174 */
175 struct drm_gem_lru willneed;
176
177 /**
178 * dontneed:
179 *
180 * The LRU for unpinned GEM objects which are in madvise
181 * DONTNEED state (ie. can be purged)
182 */
183 struct drm_gem_lru dontneed;
184
185 /**
186 * lock:
187 *
188 * Protects manipulation of all of the LRUs.
189 */
190 struct mutex lock;
191 } lru;
192
193 struct workqueue_struct *wq;
194
195 unsigned int num_crtcs;
196
197 struct msm_drm_thread event_thread[MAX_CRTCS];
198
199 /* VRAM carveout, used when no IOMMU: */
200 struct {
201 unsigned long size;
202 dma_addr_t paddr;
203 /* NOTE: mm managed at the page level, size is in # of pages
204 * and position mm_node->start is in # of pages:
205 */
206 struct drm_mm mm;
207 spinlock_t lock; /* Protects drm_mm node allocation/removal */
208 } vram;
209
210 struct notifier_block vmap_notifier;
211 struct shrinker *shrinker;
212
213 struct drm_atomic_state *pm_state;
214
215 /**
216 * hangcheck_period: For hang detection, in ms
217 *
218 * Note that in practice, a submit/job will get at least two hangcheck
219 * periods, due to checking for progress being implemented as simply
220 * "have the CP position registers changed since last time?"
221 */
222 unsigned int hangcheck_period;
223
224 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */
225 struct devfreq_simple_ondemand_data gpu_devfreq_config;
226
227 /**
228 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive
229 */
230 bool gpu_clamp_to_idle;
231
232 /**
233 * disable_err_irq:
234 *
235 * Disable handling of GPU hw error interrupts, to force fallback to
236 * sw hangcheck timer. Written (via debugfs) by igt tests to test
237 * the sw hangcheck mechanism.
238 */
239 bool disable_err_irq;
240};
241
242struct msm_format {
243 uint32_t pixel_format;
244};
245
246struct msm_pending_timer;
247
248int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
249 struct msm_kms *kms, int crtc_idx);
250void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
251void msm_atomic_commit_tail(struct drm_atomic_state *state);
252int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
253struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
254void msm_atomic_state_clear(struct drm_atomic_state *state);
255void msm_atomic_state_free(struct drm_atomic_state *state);
256
257int msm_crtc_enable_vblank(struct drm_crtc *crtc);
258void msm_crtc_disable_vblank(struct drm_crtc *crtc);
259
260int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
261void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
262
263struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
264bool msm_use_mmu(struct drm_device *dev);
265
266int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
267 struct drm_file *file);
268
269#ifdef CONFIG_DEBUG_FS
270unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
271#endif
272
273int msm_gem_shrinker_init(struct drm_device *dev);
274void msm_gem_shrinker_cleanup(struct drm_device *dev);
275
276struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
277int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
278void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
279struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
280 struct dma_buf_attachment *attach, struct sg_table *sg);
281int msm_gem_prime_pin(struct drm_gem_object *obj);
282void msm_gem_prime_unpin(struct drm_gem_object *obj);
283
284int msm_framebuffer_prepare(struct drm_framebuffer *fb,
285 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
286void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
287 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
288uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
289 struct msm_gem_address_space *aspace, int plane);
290struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
291const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
292struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
293 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
294struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
295 int w, int h, int p, uint32_t format);
296
297#ifdef CONFIG_DRM_FBDEV_EMULATION
298void msm_fbdev_setup(struct drm_device *dev);
299#else
300static inline void msm_fbdev_setup(struct drm_device *dev)
301{
302}
303#endif
304
305struct hdmi;
306#ifdef CONFIG_DRM_MSM_HDMI
307int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
308 struct drm_encoder *encoder);
309void __init msm_hdmi_register(void);
310void __exit msm_hdmi_unregister(void);
311#else
312static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
313 struct drm_encoder *encoder)
314{
315 return -EINVAL;
316}
317static inline void __init msm_hdmi_register(void) {}
318static inline void __exit msm_hdmi_unregister(void) {}
319#endif
320
321struct msm_dsi;
322#ifdef CONFIG_DRM_MSM_DSI
323int dsi_dev_attach(struct platform_device *pdev);
324void dsi_dev_detach(struct platform_device *pdev);
325void __init msm_dsi_register(void);
326void __exit msm_dsi_unregister(void);
327int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
328 struct drm_encoder *encoder);
329void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
330bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
331bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
332bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
333bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi);
334struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
335#else
336static inline void __init msm_dsi_register(void)
337{
338}
339static inline void __exit msm_dsi_unregister(void)
340{
341}
342static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
343 struct drm_device *dev,
344 struct drm_encoder *encoder)
345{
346 return -EINVAL;
347}
348static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
349{
350}
351static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
352{
353 return false;
354}
355static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
356{
357 return false;
358}
359static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
360{
361 return false;
362}
363static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi)
364{
365 return false;
366}
367
368static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
369{
370 return NULL;
371}
372#endif
373
374#ifdef CONFIG_DRM_MSM_DP
375int __init msm_dp_register(void);
376void __exit msm_dp_unregister(void);
377int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
378 struct drm_encoder *encoder, bool yuv_supported);
379void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
380bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,
381 const struct drm_display_mode *mode);
382bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,
383 const struct drm_display_mode *mode);
384bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
385
386#else
387static inline int __init msm_dp_register(void)
388{
389 return -EINVAL;
390}
391static inline void __exit msm_dp_unregister(void)
392{
393}
394static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
395 struct drm_device *dev,
396 struct drm_encoder *encoder,
397 bool yuv_supported)
398{
399 return -EINVAL;
400}
401
402static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
403{
404}
405
406static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,
407 const struct drm_display_mode *mode)
408{
409 return false;
410}
411
412static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,
413 const struct drm_display_mode *mode)
414{
415 return false;
416}
417
418static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
419{
420 return false;
421}
422
423#endif
424
425#ifdef CONFIG_DRM_MSM_MDP4
426void msm_mdp4_register(void);
427void msm_mdp4_unregister(void);
428#else
429static inline void msm_mdp4_register(void) {}
430static inline void msm_mdp4_unregister(void) {}
431#endif
432
433#ifdef CONFIG_DRM_MSM_MDP5
434void msm_mdp_register(void);
435void msm_mdp_unregister(void);
436#else
437static inline void msm_mdp_register(void) {}
438static inline void msm_mdp_unregister(void) {}
439#endif
440
441#ifdef CONFIG_DRM_MSM_DPU
442void msm_dpu_register(void);
443void msm_dpu_unregister(void);
444#else
445static inline void msm_dpu_register(void) {}
446static inline void msm_dpu_unregister(void) {}
447#endif
448
449#ifdef CONFIG_DRM_MSM_MDSS
450void msm_mdss_register(void);
451void msm_mdss_unregister(void);
452#else
453static inline void msm_mdss_register(void) {}
454static inline void msm_mdss_unregister(void) {}
455#endif
456
457#ifdef CONFIG_DEBUG_FS
458void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
459int msm_debugfs_late_init(struct drm_device *dev);
460int msm_rd_debugfs_init(struct drm_minor *minor);
461void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
462__printf(3, 4)
463void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
464 const char *fmt, ...);
465int msm_perf_debugfs_init(struct drm_minor *minor);
466void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
467#else
468static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
469__printf(3, 4)
470static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
471 struct msm_gem_submit *submit,
472 const char *fmt, ...) {}
473static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
474static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
475#endif
476
477struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
478
479struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
480 const char *name);
481void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
482void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
483 phys_addr_t *size);
484void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
485void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
486 struct platform_device *dev,
487 const char *name);
488
489struct icc_path *msm_icc_get(struct device *dev, const char *name);
490
491#define msm_writel(data, addr) writel((data), (addr))
492#define msm_readl(addr) readl((addr))
493
494static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
495{
496 u32 val = msm_readl(addr);
497
498 val &= ~mask;
499 msm_writel(val | or, addr);
500}
501
502/**
503 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
504 *
505 * @timer: hrtimer to control when the kthread work is triggered
506 * @work: the kthread work
507 * @worker: the kthread worker the work will be scheduled on
508 */
509struct msm_hrtimer_work {
510 struct hrtimer timer;
511 struct kthread_work work;
512 struct kthread_worker *worker;
513};
514
515void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
516 ktime_t wakeup_time,
517 enum hrtimer_mode mode);
518void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
519 struct kthread_worker *worker,
520 kthread_work_func_t fn,
521 clockid_t clock_id,
522 enum hrtimer_mode mode);
523
524#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
525#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
526
527static inline int align_pitch(int width, int bpp)
528{
529 int bytespp = (bpp + 7) / 8;
530 /* adreno needs pitch aligned to 32 pixels: */
531 return bytespp * ALIGN(width, 32);
532}
533
534/* for the generated headers: */
535#define INVALID_IDX(idx) ({BUG(); 0;})
536#define fui(x) ({BUG(); 0;})
537#define _mesa_float_to_half(x) ({BUG(); 0;})
538
539
540#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
541
542/* for conditionally setting boolean flag(s): */
543#define COND(bool, val) ((bool) ? (val) : 0)
544
545static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
546{
547 ktime_t now = ktime_get();
548 s64 remaining_jiffies;
549
550 if (ktime_compare(*timeout, now) < 0) {
551 remaining_jiffies = 0;
552 } else {
553 ktime_t rem = ktime_sub(*timeout, now);
554 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
555 }
556
557 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
558}
559
560/* Driver helpers */
561
562extern const struct component_master_ops msm_drm_ops;
563
564int msm_kms_pm_prepare(struct device *dev);
565void msm_kms_pm_complete(struct device *dev);
566
567int msm_drv_probe(struct device *dev,
568 int (*kms_init)(struct drm_device *dev),
569 struct msm_kms *kms);
570void msm_kms_shutdown(struct platform_device *pdev);
571
572bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver);
573
574#endif /* __MSM_DRV_H__ */