1/*
   2 * Copyright © 2012 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 * Authors:
  24 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25 *
  26 */
  27
  28#include <drm/drm_scdc_helper.h>
 
 
 
 
  29
  30#include "i915_drv.h"
 
 
  31#include "intel_audio.h"
 
 
  32#include "intel_combo_phy.h"
 
  33#include "intel_connector.h"
  34#include "intel_crtc.h"
 
 
  35#include "intel_ddi.h"
  36#include "intel_ddi_buf_trans.h"
  37#include "intel_de.h"
 
  38#include "intel_display_types.h"
 
 
  39#include "intel_dp.h"
 
  40#include "intel_dp_link_training.h"
  41#include "intel_dp_mst.h"
 
  42#include "intel_dpio_phy.h"
  43#include "intel_dsi.h"
  44#include "intel_fdi.h"
  45#include "intel_fifo_underrun.h"
  46#include "intel_gmbus.h"
  47#include "intel_hdcp.h"
  48#include "intel_hdmi.h"
  49#include "intel_hotplug.h"
 
  50#include "intel_lspcon.h"
  51#include "intel_panel.h"
 
  52#include "intel_pps.h"
  53#include "intel_psr.h"
  54#include "intel_sprite.h"
 
  55#include "intel_tc.h"
  56#include "intel_vdsc.h"
  57#include "intel_vrr.h"
  58#include "skl_scaler.h"
  59#include "skl_universal_plane.h"
  60
  61static const u8 index_to_dp_signal_levels[] = {
  62	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  63	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  64	[2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  65	[3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  66	[4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  67	[5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  68	[6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  69	[7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  70	[8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  71	[9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  72};
  73
  74static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  75				const struct intel_crtc_state *crtc_state)
  76{
  77	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  78	int n_entries, level, default_entry;
  79
  80	n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry);
  81	if (n_entries == 0)
  82		return 0;
  83	level = intel_bios_hdmi_level_shift(encoder);
  84	if (level < 0)
  85		level = default_entry;
  86
  87	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
  88		level = n_entries - 1;
  89
  90	return level;
  91}
  92
 
 
 
 
 
 
 
 
 
 
  93/*
  94 * Starting with Haswell, DDI port buffers must be programmed with correct
  95 * values in advance. This function programs the correct values for
  96 * DP/eDP/FDI use cases.
  97 */
  98void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
  99				  const struct intel_crtc_state *crtc_state)
 100{
 101	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 102	u32 iboost_bit = 0;
 103	int i, n_entries;
 104	enum port port = encoder->port;
 105	const struct ddi_buf_trans *ddi_translations;
 106
 107	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 108		ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 109							       &n_entries);
 110	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 111		ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
 112							       &n_entries);
 113	else
 114		ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
 115							      &n_entries);
 116
 117	/* If we're boosting the current, set bit 31 of trans1 */
 118	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 119	    intel_bios_encoder_dp_boost_level(encoder->devdata))
 120		iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 121
 122	for (i = 0; i < n_entries; i++) {
 123		intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 124			       ddi_translations[i].trans1 | iboost_bit);
 125		intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 126			       ddi_translations[i].trans2);
 127	}
 128}
 129
 130/*
 131 * Starting with Haswell, DDI port buffers must be programmed with correct
 132 * values in advance. This function programs the correct values for
 133 * HDMI/DVI use cases.
 134 */
 135static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 136					   int level)
 137{
 138	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 139	u32 iboost_bit = 0;
 140	int n_entries;
 141	enum port port = encoder->port;
 142	const struct ddi_buf_trans *ddi_translations;
 143
 144	ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
 145
 146	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 
 147		return;
 148	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 149		level = n_entries - 1;
 150
 151	/* If we're boosting the current, set bit 31 of trans1 */
 152	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 153	    intel_bios_encoder_hdmi_boost_level(encoder->devdata))
 154		iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 155
 156	/* Entry 9 is for HDMI: */
 157	intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 158		       ddi_translations[level].trans1 | iboost_bit);
 159	intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 160		       ddi_translations[level].trans2);
 
 
 
 
 
 
 
 
 
 
 
 
 161}
 162
 163void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 164			     enum port port)
 165{
 166	if (IS_BROXTON(dev_priv)) {
 167		udelay(16);
 168		return;
 169	}
 170
 171	if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 172			 DDI_BUF_IS_IDLE), 8))
 173		drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 174			port_name(port));
 175}
 176
 177static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 178				      enum port port)
 179{
 
 
 
 
 180	/* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 181	if (DISPLAY_VER(dev_priv) < 10) {
 182		usleep_range(518, 1000);
 183		return;
 184	}
 185
 186	if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 187			  DDI_BUF_IS_IDLE), 500))
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 188		drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 189			port_name(port));
 190}
 191
 192static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 193{
 194	switch (pll->info->id) {
 195	case DPLL_ID_WRPLL1:
 196		return PORT_CLK_SEL_WRPLL1;
 197	case DPLL_ID_WRPLL2:
 198		return PORT_CLK_SEL_WRPLL2;
 199	case DPLL_ID_SPLL:
 200		return PORT_CLK_SEL_SPLL;
 201	case DPLL_ID_LCPLL_810:
 202		return PORT_CLK_SEL_LCPLL_810;
 203	case DPLL_ID_LCPLL_1350:
 204		return PORT_CLK_SEL_LCPLL_1350;
 205	case DPLL_ID_LCPLL_2700:
 206		return PORT_CLK_SEL_LCPLL_2700;
 207	default:
 208		MISSING_CASE(pll->info->id);
 209		return PORT_CLK_SEL_NONE;
 210	}
 211}
 212
 213static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 214				  const struct intel_crtc_state *crtc_state)
 215{
 216	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 217	int clock = crtc_state->port_clock;
 218	const enum intel_dpll_id id = pll->info->id;
 219
 220	switch (id) {
 221	default:
 222		/*
 223		 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 224		 * here, so do warn if this get passed in
 225		 */
 226		MISSING_CASE(id);
 227		return DDI_CLK_SEL_NONE;
 228	case DPLL_ID_ICL_TBTPLL:
 229		switch (clock) {
 230		case 162000:
 231			return DDI_CLK_SEL_TBT_162;
 232		case 270000:
 233			return DDI_CLK_SEL_TBT_270;
 234		case 540000:
 235			return DDI_CLK_SEL_TBT_540;
 236		case 810000:
 237			return DDI_CLK_SEL_TBT_810;
 238		default:
 239			MISSING_CASE(clock);
 240			return DDI_CLK_SEL_NONE;
 241		}
 242	case DPLL_ID_ICL_MGPLL1:
 243	case DPLL_ID_ICL_MGPLL2:
 244	case DPLL_ID_ICL_MGPLL3:
 245	case DPLL_ID_ICL_MGPLL4:
 246	case DPLL_ID_TGL_MGPLL5:
 247	case DPLL_ID_TGL_MGPLL6:
 248		return DDI_CLK_SEL_MG;
 249	}
 250}
 251
 252static u32 ddi_buf_phy_link_rate(int port_clock)
 253{
 254	switch (port_clock) {
 255	case 162000:
 256		return DDI_BUF_PHY_LINK_RATE(0);
 257	case 216000:
 258		return DDI_BUF_PHY_LINK_RATE(4);
 259	case 243000:
 260		return DDI_BUF_PHY_LINK_RATE(5);
 261	case 270000:
 262		return DDI_BUF_PHY_LINK_RATE(1);
 263	case 324000:
 264		return DDI_BUF_PHY_LINK_RATE(6);
 265	case 432000:
 266		return DDI_BUF_PHY_LINK_RATE(7);
 267	case 540000:
 268		return DDI_BUF_PHY_LINK_RATE(2);
 269	case 810000:
 270		return DDI_BUF_PHY_LINK_RATE(3);
 271	default:
 272		MISSING_CASE(port_clock);
 273		return DDI_BUF_PHY_LINK_RATE(0);
 274	}
 275}
 276
 277static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 278				      const struct intel_crtc_state *crtc_state)
 279{
 280	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 281	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 282	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 283	enum phy phy = intel_port_to_phy(i915, encoder->port);
 284
 
 285	intel_dp->DP = dig_port->saved_port_bits |
 286		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 287	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
 
 
 
 
 
 
 288
 289	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 290		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 291		if (dig_port->tc_mode != TC_PORT_TBT_ALT)
 292			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 293	}
 294}
 295
 296static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 297				 enum port port)
 298{
 299	u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 300
 301	switch (val) {
 302	case DDI_CLK_SEL_NONE:
 303		return 0;
 304	case DDI_CLK_SEL_TBT_162:
 305		return 162000;
 306	case DDI_CLK_SEL_TBT_270:
 307		return 270000;
 308	case DDI_CLK_SEL_TBT_540:
 309		return 540000;
 310	case DDI_CLK_SEL_TBT_810:
 311		return 810000;
 312	default:
 313		MISSING_CASE(val);
 314		return 0;
 315	}
 316}
 317
 318static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 319{
 320	int dotclock;
 321
 322	if (pipe_config->has_pch_encoder)
 323		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 324						    &pipe_config->fdi_m_n);
 325	else if (intel_crtc_has_dp_encoder(pipe_config))
 326		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 327						    &pipe_config->dp_m_n);
 328	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 329		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 330	else
 331		dotclock = pipe_config->port_clock;
 332
 333	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 334	    !intel_crtc_has_dp_encoder(pipe_config))
 335		dotclock *= 2;
 336
 337	if (pipe_config->pixel_multiplier)
 338		dotclock /= pipe_config->pixel_multiplier;
 339
 340	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 
 341}
 342
 343void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 344			  const struct drm_connector_state *conn_state)
 345{
 346	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 347	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 348	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 349	u32 temp;
 350
 351	if (!intel_crtc_has_dp_encoder(crtc_state))
 352		return;
 353
 354	drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 355
 356	temp = DP_MSA_MISC_SYNC_CLOCK;
 357
 358	switch (crtc_state->pipe_bpp) {
 359	case 18:
 360		temp |= DP_MSA_MISC_6_BPC;
 361		break;
 362	case 24:
 363		temp |= DP_MSA_MISC_8_BPC;
 364		break;
 365	case 30:
 366		temp |= DP_MSA_MISC_10_BPC;
 367		break;
 368	case 36:
 369		temp |= DP_MSA_MISC_12_BPC;
 370		break;
 371	default:
 372		MISSING_CASE(crtc_state->pipe_bpp);
 373		break;
 374	}
 375
 376	/* nonsense combination */
 377	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 378		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 379
 380	if (crtc_state->limited_color_range)
 381		temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 382
 383	/*
 384	 * As per DP 1.2 spec section 2.3.4.3 while sending
 385	 * YCBCR 444 signals we should program MSA MISC1/0 fields with
 386	 * colorspace information.
 387	 */
 388	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 389		temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 390
 391	/*
 392	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 393	 * of Color Encoding Format and Content Color Gamut] while sending
 394	 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 395	 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 396	 */
 397	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 398		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 399
 400	intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 401}
 402
 403static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 404{
 405	if (master_transcoder == TRANSCODER_EDP)
 406		return 0;
 407	else
 408		return master_transcoder + 1;
 409}
 410
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 411/*
 412 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 413 *
 414 * Only intended to be used by intel_ddi_enable_transcoder_func() and
 415 * intel_ddi_config_transcoder_func().
 416 */
 417static u32
 418intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 419				      const struct intel_crtc_state *crtc_state)
 420{
 421	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 422	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 423	enum pipe pipe = crtc->pipe;
 424	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 425	enum port port = encoder->port;
 426	u32 temp;
 427
 428	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 429	temp = TRANS_DDI_FUNC_ENABLE;
 430	if (DISPLAY_VER(dev_priv) >= 12)
 431		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 432	else
 433		temp |= TRANS_DDI_SELECT_PORT(port);
 434
 435	switch (crtc_state->pipe_bpp) {
 
 
 
 436	case 18:
 437		temp |= TRANS_DDI_BPC_6;
 438		break;
 439	case 24:
 440		temp |= TRANS_DDI_BPC_8;
 441		break;
 442	case 30:
 443		temp |= TRANS_DDI_BPC_10;
 444		break;
 445	case 36:
 446		temp |= TRANS_DDI_BPC_12;
 447		break;
 448	default:
 449		BUG();
 450	}
 451
 452	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 453		temp |= TRANS_DDI_PVSYNC;
 454	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 455		temp |= TRANS_DDI_PHSYNC;
 456
 457	if (cpu_transcoder == TRANSCODER_EDP) {
 458		switch (pipe) {
 
 
 
 459		case PIPE_A:
 460			/* On Haswell, can only use the always-on power well for
 461			 * eDP when not using the panel fitter, and when not
 462			 * using motion blur mitigation (which we don't
 463			 * support). */
 464			if (crtc_state->pch_pfit.force_thru)
 465				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 466			else
 467				temp |= TRANS_DDI_EDP_INPUT_A_ON;
 468			break;
 469		case PIPE_B:
 470			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 471			break;
 472		case PIPE_C:
 473			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 474			break;
 475		default:
 476			BUG();
 477			break;
 478		}
 479	}
 480
 481	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 482		if (crtc_state->has_hdmi_sink)
 483			temp |= TRANS_DDI_MODE_SELECT_HDMI;
 484		else
 485			temp |= TRANS_DDI_MODE_SELECT_DVI;
 486
 487		if (crtc_state->hdmi_scrambling)
 488			temp |= TRANS_DDI_HDMI_SCRAMBLING;
 489		if (crtc_state->hdmi_high_tmds_clock_ratio)
 490			temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 
 
 491	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 492		temp |= TRANS_DDI_MODE_SELECT_FDI;
 493		temp |= (crtc_state->fdi_lanes - 1) << 1;
 494	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 495		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 
 
 
 496		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 497
 498		if (DISPLAY_VER(dev_priv) >= 12) {
 499			enum transcoder master;
 500
 501			master = crtc_state->mst_master_transcoder;
 502			drm_WARN_ON(&dev_priv->drm,
 503				    master == INVALID_TRANSCODER);
 504			temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 505		}
 506	} else {
 507		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 508		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 509	}
 510
 511	if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 512	    crtc_state->master_transcoder != INVALID_TRANSCODER) {
 513		u8 master_select =
 514			bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 515
 516		temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 517			TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 518	}
 519
 520	return temp;
 521}
 522
 523void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 524				      const struct intel_crtc_state *crtc_state)
 525{
 526	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 527	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 528	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 529
 530	if (DISPLAY_VER(dev_priv) >= 11) {
 531		enum transcoder master_transcoder = crtc_state->master_transcoder;
 532		u32 ctl2 = 0;
 533
 534		if (master_transcoder != INVALID_TRANSCODER) {
 535			u8 master_select =
 536				bdw_trans_port_sync_master_select(master_transcoder);
 537
 538			ctl2 |= PORT_SYNC_MODE_ENABLE |
 539				PORT_SYNC_MODE_MASTER_SELECT(master_select);
 540		}
 541
 542		intel_de_write(dev_priv,
 543			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 544	}
 545
 546	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 547		       intel_ddi_transcoder_func_reg_val_get(encoder,
 548							     crtc_state));
 549}
 550
 551/*
 552 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 553 * bit.
 554 */
 555static void
 556intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 557				 const struct intel_crtc_state *crtc_state)
 558{
 559	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 560	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 561	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 562	u32 ctl;
 563
 564	ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 565	ctl &= ~TRANS_DDI_FUNC_ENABLE;
 566	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 567}
 568
 569void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 570{
 571	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 572	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 573	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 574	u32 ctl;
 575
 576	if (DISPLAY_VER(dev_priv) >= 11)
 577		intel_de_write(dev_priv,
 578			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 579
 580	ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 581
 582	drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 583
 584	ctl &= ~TRANS_DDI_FUNC_ENABLE;
 585
 586	if (IS_DISPLAY_VER(dev_priv, 8, 10))
 587		ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 588			 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 589
 590	if (DISPLAY_VER(dev_priv) >= 12) {
 591		if (!intel_dp_mst_is_master_trans(crtc_state)) {
 592			ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 593				 TRANS_DDI_MODE_SELECT_MASK);
 594		}
 595	} else {
 596		ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 597	}
 598
 599	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 600
 601	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 602	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 603		drm_dbg_kms(&dev_priv->drm,
 604			    "Quirk Increase DDI disabled time\n");
 605		/* Quirk time at 100ms for reliable operation */
 606		msleep(100);
 607	}
 608}
 609
 610int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 611			       enum transcoder cpu_transcoder,
 612			       bool enable, u32 hdcp_mask)
 613{
 614	struct drm_device *dev = intel_encoder->base.dev;
 615	struct drm_i915_private *dev_priv = to_i915(dev);
 616	intel_wakeref_t wakeref;
 617	int ret = 0;
 618	u32 tmp;
 619
 620	wakeref = intel_display_power_get_if_enabled(dev_priv,
 621						     intel_encoder->power_domain);
 622	if (drm_WARN_ON(dev, !wakeref))
 623		return -ENXIO;
 624
 625	tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 626	if (enable)
 627		tmp |= hdcp_mask;
 628	else
 629		tmp &= ~hdcp_mask;
 630	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 631	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 632	return ret;
 633}
 634
 635bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 636{
 637	struct drm_device *dev = intel_connector->base.dev;
 638	struct drm_i915_private *dev_priv = to_i915(dev);
 639	struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 640	int type = intel_connector->base.connector_type;
 641	enum port port = encoder->port;
 642	enum transcoder cpu_transcoder;
 643	intel_wakeref_t wakeref;
 644	enum pipe pipe = 0;
 645	u32 tmp;
 646	bool ret;
 647
 648	wakeref = intel_display_power_get_if_enabled(dev_priv,
 649						     encoder->power_domain);
 650	if (!wakeref)
 651		return false;
 652
 653	if (!encoder->get_hw_state(encoder, &pipe)) {
 654		ret = false;
 655		goto out;
 656	}
 657
 658	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 659		cpu_transcoder = TRANSCODER_EDP;
 660	else
 661		cpu_transcoder = (enum transcoder) pipe;
 662
 663	tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 664
 665	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 666	case TRANS_DDI_MODE_SELECT_HDMI:
 667	case TRANS_DDI_MODE_SELECT_DVI:
 668		ret = type == DRM_MODE_CONNECTOR_HDMIA;
 669		break;
 670
 671	case TRANS_DDI_MODE_SELECT_DP_SST:
 672		ret = type == DRM_MODE_CONNECTOR_eDP ||
 673		      type == DRM_MODE_CONNECTOR_DisplayPort;
 674		break;
 675
 676	case TRANS_DDI_MODE_SELECT_DP_MST:
 677		/* if the transcoder is in MST state then
 678		 * connector isn't connected */
 679		ret = false;
 680		break;
 681
 682	case TRANS_DDI_MODE_SELECT_FDI:
 683		ret = type == DRM_MODE_CONNECTOR_VGA;
 
 
 
 
 
 684		break;
 685
 686	default:
 687		ret = false;
 688		break;
 689	}
 690
 691out:
 692	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 693
 694	return ret;
 695}
 696
 697static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 698					u8 *pipe_mask, bool *is_dp_mst)
 699{
 700	struct drm_device *dev = encoder->base.dev;
 701	struct drm_i915_private *dev_priv = to_i915(dev);
 702	enum port port = encoder->port;
 703	intel_wakeref_t wakeref;
 704	enum pipe p;
 705	u32 tmp;
 706	u8 mst_pipe_mask;
 707
 708	*pipe_mask = 0;
 709	*is_dp_mst = false;
 710
 711	wakeref = intel_display_power_get_if_enabled(dev_priv,
 712						     encoder->power_domain);
 713	if (!wakeref)
 714		return;
 715
 716	tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 717	if (!(tmp & DDI_BUF_CTL_ENABLE))
 718		goto out;
 719
 720	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 721		tmp = intel_de_read(dev_priv,
 722				    TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 723
 724		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 725		default:
 726			MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 727			fallthrough;
 728		case TRANS_DDI_EDP_INPUT_A_ON:
 729		case TRANS_DDI_EDP_INPUT_A_ONOFF:
 730			*pipe_mask = BIT(PIPE_A);
 731			break;
 732		case TRANS_DDI_EDP_INPUT_B_ONOFF:
 733			*pipe_mask = BIT(PIPE_B);
 734			break;
 735		case TRANS_DDI_EDP_INPUT_C_ONOFF:
 736			*pipe_mask = BIT(PIPE_C);
 737			break;
 738		}
 739
 740		goto out;
 741	}
 742
 743	mst_pipe_mask = 0;
 744	for_each_pipe(dev_priv, p) {
 745		enum transcoder cpu_transcoder = (enum transcoder)p;
 746		unsigned int port_mask, ddi_select;
 747		intel_wakeref_t trans_wakeref;
 748
 749		trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 750								   POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 751		if (!trans_wakeref)
 752			continue;
 753
 754		if (DISPLAY_VER(dev_priv) >= 12) {
 755			port_mask = TGL_TRANS_DDI_PORT_MASK;
 756			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 757		} else {
 758			port_mask = TRANS_DDI_PORT_MASK;
 759			ddi_select = TRANS_DDI_SELECT_PORT(port);
 760		}
 761
 762		tmp = intel_de_read(dev_priv,
 763				    TRANS_DDI_FUNC_CTL(cpu_transcoder));
 764		intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 765					trans_wakeref);
 766
 767		if ((tmp & port_mask) != ddi_select)
 768			continue;
 769
 770		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
 771		    TRANS_DDI_MODE_SELECT_DP_MST)
 
 772			mst_pipe_mask |= BIT(p);
 773
 774		*pipe_mask |= BIT(p);
 775	}
 776
 777	if (!*pipe_mask)
 778		drm_dbg_kms(&dev_priv->drm,
 779			    "No pipe for [ENCODER:%d:%s] found\n",
 780			    encoder->base.base.id, encoder->base.name);
 781
 782	if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 783		drm_dbg_kms(&dev_priv->drm,
 784			    "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 785			    encoder->base.base.id, encoder->base.name,
 786			    *pipe_mask);
 787		*pipe_mask = BIT(ffs(*pipe_mask) - 1);
 788	}
 789
 790	if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 791		drm_dbg_kms(&dev_priv->drm,
 792			    "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 793			    encoder->base.base.id, encoder->base.name,
 794			    *pipe_mask, mst_pipe_mask);
 795	else
 796		*is_dp_mst = mst_pipe_mask;
 797
 798out:
 799	if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 800		tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 801		if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 802			    BXT_PHY_LANE_POWERDOWN_ACK |
 803			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 804			drm_err(&dev_priv->drm,
 805				"[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 806				encoder->base.base.id, encoder->base.name, tmp);
 807	}
 808
 809	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 810}
 811
 812bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 813			    enum pipe *pipe)
 814{
 815	u8 pipe_mask;
 816	bool is_mst;
 817
 818	intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 819
 820	if (is_mst || !pipe_mask)
 821		return false;
 822
 823	*pipe = ffs(pipe_mask) - 1;
 824
 825	return true;
 826}
 827
 828static enum intel_display_power_domain
 829intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 
 830{
 831	/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
 
 
 
 
 832	 * DC states enabled at the same time, while for driver initiated AUX
 833	 * transfers we need the same AUX IOs to be powered but with DC states
 834	 * disabled. Accordingly use the AUX power domain here which leaves DC
 835	 * states enabled.
 836	 * However, for non-A AUX ports the corresponding non-EDP transcoders
 837	 * would have already enabled power well 2 and DC_OFF. This means we can
 838	 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 839	 * specific AUX_IO reference without powering up any extra wells.
 840	 * Note that PSR is enabled only on Port A even though this function
 841	 * returns the correct domain for other ports too.
 842	 */
 843	return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 844					      intel_aux_power_domain(dig_port);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 845}
 846
 847static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 848					struct intel_crtc_state *crtc_state)
 849{
 850	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 851	struct intel_digital_port *dig_port;
 852	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 853
 854	/*
 855	 * TODO: Add support for MST encoders. Atm, the following should never
 856	 * happen since fake-MST encoders don't set their get_power_domains()
 857	 * hook.
 858	 */
 859	if (drm_WARN_ON(&dev_priv->drm,
 860			intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 861		return;
 862
 863	dig_port = enc_to_dig_port(encoder);
 864
 865	if (!intel_phy_is_tc(dev_priv, phy) ||
 866	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
 867		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 868		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 869								   dig_port->ddi_io_power_domain);
 870	}
 871
 872	/*
 873	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 874	 * ports.
 875	 */
 876	if (intel_crtc_has_dp_encoder(crtc_state) ||
 877	    intel_phy_is_tc(dev_priv, phy)) {
 878		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 879		dig_port->aux_wakeref =
 880			intel_display_power_get(dev_priv,
 881						intel_ddi_main_link_aux_domain(dig_port));
 882	}
 883}
 884
 885void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 886				 const struct intel_crtc_state *crtc_state)
 887{
 888	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 889	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 890	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 891	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 892	u32 val;
 893
 894	if (cpu_transcoder != TRANSCODER_EDP) {
 895		if (DISPLAY_VER(dev_priv) >= 13)
 896			val = TGL_TRANS_CLK_SEL_PORT(phy);
 897		else if (DISPLAY_VER(dev_priv) >= 12)
 898			val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 899		else
 900			val = TRANS_CLK_SEL_PORT(encoder->port);
 901
 902		intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 903	}
 
 
 
 
 
 
 904}
 905
 906void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 907{
 908	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 909	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 910
 911	if (cpu_transcoder != TRANSCODER_EDP) {
 912		if (DISPLAY_VER(dev_priv) >= 12)
 913			intel_de_write(dev_priv,
 914				       TRANS_CLK_SEL(cpu_transcoder),
 915				       TGL_TRANS_CLK_SEL_DISABLED);
 916		else
 917			intel_de_write(dev_priv,
 918				       TRANS_CLK_SEL(cpu_transcoder),
 919				       TRANS_CLK_SEL_DISABLED);
 920	}
 921}
 922
 923static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 924				enum port port, u8 iboost)
 925{
 926	u32 tmp;
 927
 928	tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 929	tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 930	if (iboost)
 931		tmp |= iboost << BALANCE_LEG_SHIFT(port);
 932	else
 933		tmp |= BALANCE_LEG_DISABLE(port);
 934	intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 935}
 936
 937static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 938			       const struct intel_crtc_state *crtc_state,
 939			       int level)
 940{
 941	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 942	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 943	u8 iboost;
 944
 945	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 946		iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
 947	else
 948		iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
 949
 950	if (iboost == 0) {
 951		const struct ddi_buf_trans *ddi_translations;
 952		int n_entries;
 953
 954		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 955			ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
 956		else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 957			ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 958		else
 959			ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
 960
 961		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 962			return;
 963		if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 964			level = n_entries - 1;
 965
 966		iboost = ddi_translations[level].i_boost;
 967	}
 968
 969	/* Make sure that the requested I_boost is valid */
 970	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
 971		drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
 972		return;
 973	}
 974
 975	_skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
 976
 977	if (encoder->port == PORT_A && dig_port->max_lanes == 4)
 978		_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
 979}
 980
 981static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 982				    const struct intel_crtc_state *crtc_state,
 983				    int level)
 984{
 985	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 986	const struct bxt_ddi_buf_trans *ddi_translations;
 987	enum port port = encoder->port;
 988	int n_entries;
 989
 990	ddi_translations = bxt_get_buf_trans(encoder, crtc_state, &n_entries);
 991	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 992		return;
 993	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 994		level = n_entries - 1;
 995
 996	bxt_ddi_phy_set_signal_level(dev_priv, port,
 997				     ddi_translations[level].margin,
 998				     ddi_translations[level].scale,
 999				     ddi_translations[level].enable,
1000				     ddi_translations[level].deemphasis);
1001}
1002
1003static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1004				   const struct intel_crtc_state *crtc_state)
1005{
1006	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1007	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1008	enum port port = encoder->port;
1009	enum phy phy = intel_port_to_phy(dev_priv, port);
1010	int n_entries;
1011
1012	if (DISPLAY_VER(dev_priv) >= 12) {
1013		if (intel_phy_is_combo(dev_priv, phy))
1014			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1015		else if (IS_ALDERLAKE_P(dev_priv))
1016			adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
1017		else
1018			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
1019	} else if (DISPLAY_VER(dev_priv) == 11) {
1020		if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
1021			jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1022		else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1023			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1024		else if (intel_phy_is_combo(dev_priv, phy))
1025			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1026		else
1027			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
1028	} else if (IS_CANNONLAKE(dev_priv)) {
1029		cnl_get_buf_trans(encoder, crtc_state, &n_entries);
1030	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1031		bxt_get_buf_trans(encoder, crtc_state, &n_entries);
1032	} else {
1033		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1034			intel_ddi_get_buf_trans_edp(encoder, &n_entries);
1035		else
1036			intel_ddi_get_buf_trans_dp(encoder, &n_entries);
1037	}
1038
1039	if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1040		n_entries = 1;
1041	if (drm_WARN_ON(&dev_priv->drm,
1042			n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1043		n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1044
1045	return index_to_dp_signal_levels[n_entries - 1] &
1046		DP_TRAIN_VOLTAGE_SWING_MASK;
1047}
1048
1049/*
1050 * We assume that the full set of pre-emphasis values can be
1051 * used on all DDI platforms. Should that change we need to
1052 * rethink this code.
1053 */
1054static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1055{
1056	return DP_TRAIN_PRE_EMPH_LEVEL_3;
1057}
1058
1059static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1060				   const struct intel_crtc_state *crtc_state,
1061				   int level)
1062{
1063	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1064	const struct cnl_ddi_buf_trans *ddi_translations;
1065	enum port port = encoder->port;
1066	int n_entries, ln;
1067	u32 val;
1068
1069	ddi_translations = cnl_get_buf_trans(encoder, crtc_state, &n_entries);
1070
1071	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1072		return;
1073	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1074		level = n_entries - 1;
1075
1076	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1077	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1078	val &= ~SCALING_MODE_SEL_MASK;
1079	val |= SCALING_MODE_SEL(2);
1080	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1081
1082	/* Program PORT_TX_DW2 */
1083	val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
1084	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1085		 RCOMP_SCALAR_MASK);
1086	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1087	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1088	/* Rcomp scalar is fixed as 0x98 for every table entry */
1089	val |= RCOMP_SCALAR(0x98);
1090	intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
1091
1092	/* Program PORT_TX_DW4 */
1093	/* We cannot write to GRP. It would overrite individual loadgen */
1094	for (ln = 0; ln < 4; ln++) {
1095		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
1096		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1097			 CURSOR_COEFF_MASK);
1098		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1099		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1100		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1101		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
1102	}
1103
1104	/* Program PORT_TX_DW5 */
1105	/* All DW5 values are fixed for every table entry */
1106	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1107	val &= ~RTERM_SELECT_MASK;
1108	val |= RTERM_SELECT(6);
1109	val |= TAP3_DISABLE;
1110	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1111
1112	/* Program PORT_TX_DW7 */
1113	val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
1114	val &= ~N_SCALAR_MASK;
1115	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1116	intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
1117}
1118
1119static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
1120				    const struct intel_crtc_state *crtc_state,
1121				    int level)
1122{
1123	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1124	enum port port = encoder->port;
1125	int width, rate, ln;
1126	u32 val;
1127
1128	width = crtc_state->lane_count;
1129	rate = crtc_state->port_clock;
1130
1131	/*
1132	 * 1. If port type is eDP or DP,
1133	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1134	 * else clear to 0b.
1135	 */
1136	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
1137	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1138		val &= ~COMMON_KEEPER_EN;
1139	else
1140		val |= COMMON_KEEPER_EN;
1141	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
1142
1143	/* 2. Program loadgen select */
1144	/*
1145	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1146	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1147	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1148	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1149	 */
1150	for (ln = 0; ln <= 3; ln++) {
1151		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
1152		val &= ~LOADGEN_SELECT;
1153
1154		if ((rate <= 600000 && width == 4 && ln >= 1)  ||
1155		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1156			val |= LOADGEN_SELECT;
1157		}
1158		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
1159	}
1160
1161	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1162	val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
1163	val |= SUS_CLOCK_CONFIG;
1164	intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
1165
1166	/* 4. Clear training enable to change swing values */
1167	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1168	val &= ~TX_TRAINING_EN;
1169	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1170
1171	/* 5. Program swing and de-emphasis */
1172	cnl_ddi_vswing_program(encoder, crtc_state, level);
1173
1174	/* 6. Set training enable to trigger update */
1175	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
1176	val |= TX_TRAINING_EN;
1177	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
1178}
1179
1180static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1181					 const struct intel_crtc_state *crtc_state,
1182					 int level)
1183{
1184	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1185	const struct cnl_ddi_buf_trans *ddi_translations;
1186	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1187	int n_entries, ln;
1188	u32 val;
1189
1190	if (DISPLAY_VER(dev_priv) >= 12)
1191		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1192	else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
1193		ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1194	else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1195		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1196	else
1197		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
1198
1199	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1200		return;
1201	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1202		level = n_entries - 1;
1203
1204	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1205		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1206
1207		val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1208		intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
1209		intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1210			     intel_dp->hobl_active ? val : 0);
1211	}
1212
1213	/* Set PORT_TX_DW5 */
1214	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1215	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1216		  TAP2_DISABLE | TAP3_DISABLE);
1217	val |= SCALING_MODE_SEL(0x2);
1218	val |= RTERM_SELECT(0x6);
1219	val |= TAP3_DISABLE;
1220	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1221
1222	/* Program PORT_TX_DW2 */
1223	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
1224	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1225		 RCOMP_SCALAR_MASK);
1226	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1227	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1228	/* Program Rcomp scalar for every table entry */
1229	val |= RCOMP_SCALAR(0x98);
1230	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
 
1231
1232	/* Program PORT_TX_DW4 */
1233	/* We cannot write to GRP. It would overwrite individual loadgen. */
1234	for (ln = 0; ln <= 3; ln++) {
1235		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1236		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1237			 CURSOR_COEFF_MASK);
1238		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1239		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1240		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1241		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1242	}
1243
1244	/* Program PORT_TX_DW7 */
1245	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
1246	val &= ~N_SCALAR_MASK;
1247	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1248	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
 
 
 
1249}
1250
1251static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1252					      const struct intel_crtc_state *crtc_state,
1253					      int level)
1254{
1255	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1256	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1257	int width, rate, ln;
1258	u32 val;
1259
1260	width = crtc_state->lane_count;
1261	rate = crtc_state->port_clock;
1262
1263	/*
1264	 * 1. If port type is eDP or DP,
1265	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1266	 * else clear to 0b.
1267	 */
1268	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
1269	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1270		val &= ~COMMON_KEEPER_EN;
1271	else
1272		val |= COMMON_KEEPER_EN;
1273	intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1274
1275	/* 2. Program loadgen select */
1276	/*
1277	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1278	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1279	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1280	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1281	 */
1282	for (ln = 0; ln <= 3; ln++) {
1283		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1284		val &= ~LOADGEN_SELECT;
1285
1286		if ((rate <= 600000 && width == 4 && ln >= 1) ||
1287		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1288			val |= LOADGEN_SELECT;
1289		}
1290		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1291	}
1292
1293	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1294	val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
1295	val |= SUS_CLOCK_CONFIG;
1296	intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
1297
1298	/* 4. Clear training enable to change swing values */
1299	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1300	val &= ~TX_TRAINING_EN;
1301	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1302
1303	/* 5. Program swing and de-emphasis */
1304	icl_ddi_combo_vswing_program(encoder, crtc_state, level);
1305
1306	/* 6. Set training enable to trigger update */
1307	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1308	val |= TX_TRAINING_EN;
1309	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1310}
1311
1312static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1313					   const struct intel_crtc_state *crtc_state,
1314					   int level)
1315{
1316	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1317	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1318	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
1319	int n_entries, ln;
1320	u32 val;
1321
1322	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1323		return;
1324
1325	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
1326
1327	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1328		return;
1329	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1330		level = n_entries - 1;
1331
1332	/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
1333	for (ln = 0; ln < 2; ln++) {
1334		val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
1335		val &= ~CRI_USE_FS32;
1336		intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
1337
1338		val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
1339		val &= ~CRI_USE_FS32;
1340		intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
1341	}
1342
1343	/* Program MG_TX_SWINGCTRL with values from vswing table */
1344	for (ln = 0; ln < 2; ln++) {
1345		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
1346		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1347		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1348			ddi_translations[level].cri_txdeemph_override_17_12);
1349		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
1350
1351		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
1352		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1353		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1354			ddi_translations[level].cri_txdeemph_override_17_12);
1355		intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
 
 
1356	}
1357
1358	/* Program MG_TX_DRVCTRL with values from vswing table */
1359	for (ln = 0; ln < 2; ln++) {
1360		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
1361		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1362			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1363		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1364			ddi_translations[level].cri_txdeemph_override_5_0) |
1365			CRI_TXDEEMPH_OVERRIDE_11_6(
1366				ddi_translations[level].cri_txdeemph_override_11_6) |
1367			CRI_TXDEEMPH_OVERRIDE_EN;
1368		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
1369
1370		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
1371		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1372			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1373		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1374			ddi_translations[level].cri_txdeemph_override_5_0) |
1375			CRI_TXDEEMPH_OVERRIDE_11_6(
1376				ddi_translations[level].cri_txdeemph_override_11_6) |
1377			CRI_TXDEEMPH_OVERRIDE_EN;
1378		intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
1379
1380		/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1381	}
1382
1383	/*
1384	 * Program MG_CLKHUB<LN, port being used> with value from frequency table
1385	 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1386	 * values from table for which TX1 and TX2 enabled.
1387	 */
1388	for (ln = 0; ln < 2; ln++) {
1389		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
1390		if (crtc_state->port_clock < 300000)
1391			val |= CFG_LOW_RATE_LKREN_EN;
1392		else
1393			val &= ~CFG_LOW_RATE_LKREN_EN;
1394		intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
1395	}
1396
1397	/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1398	for (ln = 0; ln < 2; ln++) {
1399		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
1400		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1401		if (crtc_state->port_clock <= 500000) {
1402			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1403		} else {
1404			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1405				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1406		}
1407		intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
1408
1409		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
1410		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1411		if (crtc_state->port_clock <= 500000) {
1412			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1413		} else {
1414			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1415				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1416		}
1417		intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
1418	}
1419
1420	/* Program MG_TX_PISO_READLOAD with values from vswing table */
1421	for (ln = 0; ln < 2; ln++) {
1422		val = intel_de_read(dev_priv,
1423				    MG_TX1_PISO_READLOAD(ln, tc_port));
1424		val |= CRI_CALCINIT;
1425		intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1426			       val);
1427
1428		val = intel_de_read(dev_priv,
1429				    MG_TX2_PISO_READLOAD(ln, tc_port));
1430		val |= CRI_CALCINIT;
1431		intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1432			       val);
1433	}
1434}
1435
1436static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
1437				    const struct intel_crtc_state *crtc_state,
1438				    int level)
1439{
1440	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1441	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1442
1443	if (intel_phy_is_combo(dev_priv, phy))
1444		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1445	else
1446		icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1447}
1448
1449static void
1450tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1451				const struct intel_crtc_state *crtc_state,
1452				int level)
1453{
1454	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1455	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1456	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
1457	u32 val, dpcnt_mask, dpcnt_val;
1458	int n_entries, ln;
1459
1460	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1461		return;
1462
1463	if (IS_ALDERLAKE_P(dev_priv))
1464		ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
1465	else
1466		ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
1467
1468	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1469		return;
1470	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1471		level = n_entries - 1;
1472
1473	dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
1474		      DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1475		      DKL_TX_VSWING_CONTROL_MASK);
1476	dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
1477	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
1478	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
1479
1480	for (ln = 0; ln < 2; ln++) {
1481		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1482			       HIP_INDEX_VAL(tc_port, ln));
1483
1484		intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1485
1486		/* All the registers are RMW */
1487		val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
1488		val &= ~dpcnt_mask;
1489		val |= dpcnt_val;
1490		intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
1491
1492		val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
1493		val &= ~dpcnt_mask;
1494		val |= dpcnt_val;
1495		intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
1496
1497		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
1498		val &= ~DKL_TX_DP20BITMODE;
1499		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
1500
1501		if ((intel_crtc_has_dp_encoder(crtc_state) &&
1502		     crtc_state->port_clock == 162000) ||
1503		    (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1504		     crtc_state->port_clock == 594000))
1505			val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1506		else
1507			val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1508	}
1509}
1510
1511static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
1512				    const struct intel_crtc_state *crtc_state,
1513				    int level)
1514{
1515	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1516	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 
 
 
 
 
 
 
 
 
 
1517
1518	if (intel_phy_is_combo(dev_priv, phy))
1519		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1520	else
1521		tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1522}
1523
1524static int translate_signal_level(struct intel_dp *intel_dp,
1525				  u8 signal_levels)
1526{
1527	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1528	int i;
1529
1530	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1531		if (index_to_dp_signal_levels[i] == signal_levels)
1532			return i;
1533	}
1534
1535	drm_WARN(&i915->drm, 1,
1536		 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1537		 signal_levels);
1538
1539	return 0;
1540}
1541
1542static int intel_ddi_dp_level(struct intel_dp *intel_dp)
 
 
1543{
1544	u8 train_set = intel_dp->train_set[0];
1545	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1546					DP_TRAIN_PRE_EMPHASIS_MASK);
1547
1548	return translate_signal_level(intel_dp, signal_levels);
1549}
1550
1551static void
1552tgl_set_signal_levels(struct intel_dp *intel_dp,
1553		      const struct intel_crtc_state *crtc_state)
1554{
1555	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1556	int level = intel_ddi_dp_level(intel_dp);
1557
1558	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 
1559}
1560
1561static void
1562icl_set_signal_levels(struct intel_dp *intel_dp,
1563		      const struct intel_crtc_state *crtc_state)
1564{
1565	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1566	int level = intel_ddi_dp_level(intel_dp);
1567
1568	icl_ddi_vswing_sequence(encoder, crtc_state, level);
1569}
1570
1571static void
1572cnl_set_signal_levels(struct intel_dp *intel_dp,
1573		      const struct intel_crtc_state *crtc_state)
1574{
1575	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1576	int level = intel_ddi_dp_level(intel_dp);
1577
1578	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
1579}
 
 
 
1580
1581static void
1582bxt_set_signal_levels(struct intel_dp *intel_dp,
1583		      const struct intel_crtc_state *crtc_state)
1584{
1585	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1586	int level = intel_ddi_dp_level(intel_dp);
1587
1588	bxt_ddi_vswing_sequence(encoder, crtc_state, level);
1589}
1590
1591static void
1592hsw_set_signal_levels(struct intel_dp *intel_dp,
1593		      const struct intel_crtc_state *crtc_state)
1594{
1595	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1596	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1597	int level = intel_ddi_dp_level(intel_dp);
 
1598	enum port port = encoder->port;
1599	u32 signal_levels;
1600
 
 
 
 
 
 
 
1601	signal_levels = DDI_BUF_TRANS_SELECT(level);
1602
1603	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1604		    signal_levels);
1605
1606	intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1607	intel_dp->DP |= signal_levels;
1608
1609	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
1610		skl_ddi_set_iboost(encoder, crtc_state, level);
1611
1612	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1613	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1614}
1615
1616static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1617				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1618{
1619	mutex_lock(&i915->dpll.lock);
1620
1621	intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1622
1623	/*
1624	 * "This step and the step before must be
1625	 *  done with separate register writes."
1626	 */
1627	intel_de_rmw(i915, reg, clk_off, 0);
1628
1629	mutex_unlock(&i915->dpll.lock);
1630}
1631
1632static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1633				   u32 clk_off)
1634{
1635	mutex_lock(&i915->dpll.lock);
1636
1637	intel_de_rmw(i915, reg, 0, clk_off);
1638
1639	mutex_unlock(&i915->dpll.lock);
1640}
1641
1642static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1643				      u32 clk_off)
1644{
1645	return !(intel_de_read(i915, reg) & clk_off);
1646}
1647
1648static struct intel_shared_dpll *
1649_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1650		 u32 clk_sel_mask, u32 clk_sel_shift)
1651{
1652	enum intel_dpll_id id;
1653
1654	id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1655
1656	return intel_get_shared_dpll_by_id(i915, id);
1657}
1658
1659static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1660				  const struct intel_crtc_state *crtc_state)
1661{
1662	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1663	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1664	enum phy phy = intel_port_to_phy(i915, encoder->port);
1665
1666	if (drm_WARN_ON(&i915->drm, !pll))
1667		return;
1668
1669	_cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1670			      ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1671			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1672			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1673}
1674
1675static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1676{
1677	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1678	enum phy phy = intel_port_to_phy(i915, encoder->port);
1679
1680	_cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1681			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1682}
1683
1684static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1685{
1686	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1687	enum phy phy = intel_port_to_phy(i915, encoder->port);
1688
1689	return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1690					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1691}
1692
1693static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1694{
1695	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1696	enum phy phy = intel_port_to_phy(i915, encoder->port);
1697
1698	return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1699				ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1700				ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1701}
1702
1703static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1704				 const struct intel_crtc_state *crtc_state)
1705{
1706	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1707	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1708	enum phy phy = intel_port_to_phy(i915, encoder->port);
1709
1710	if (drm_WARN_ON(&i915->drm, !pll))
1711		return;
1712
1713	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1714			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1715			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1716			      RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1717}
1718
1719static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1720{
1721	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1722	enum phy phy = intel_port_to_phy(i915, encoder->port);
1723
1724	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1725			       RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1726}
1727
1728static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1729{
1730	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1731	enum phy phy = intel_port_to_phy(i915, encoder->port);
1732
1733	return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1734					 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1735}
1736
1737static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1738{
1739	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1740	enum phy phy = intel_port_to_phy(i915, encoder->port);
1741
1742	return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1743				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1744				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1745}
1746
1747static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1748				 const struct intel_crtc_state *crtc_state)
1749{
1750	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1751	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1752	enum phy phy = intel_port_to_phy(i915, encoder->port);
1753
1754	if (drm_WARN_ON(&i915->drm, !pll))
1755		return;
1756
1757	/*
1758	 * If we fail this, something went very wrong: first 2 PLLs should be
1759	 * used by first 2 phys and last 2 PLLs by last phys
1760	 */
1761	if (drm_WARN_ON(&i915->drm,
1762			(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1763			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1764		return;
1765
1766	_cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1767			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1768			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1769			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1770}
1771
1772static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1773{
1774	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1775	enum phy phy = intel_port_to_phy(i915, encoder->port);
1776
1777	_cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1778			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1779}
1780
1781static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1782{
1783	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1784	enum phy phy = intel_port_to_phy(i915, encoder->port);
1785
1786	return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1787					 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1788}
1789
1790static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1791{
1792	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1793	enum phy phy = intel_port_to_phy(i915, encoder->port);
1794	enum intel_dpll_id id;
1795	u32 val;
1796
1797	val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1798	val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1799	val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1800	id = val;
1801
1802	/*
1803	 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1804	 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1805	 * bit for phy C and D.
1806	 */
1807	if (phy >= PHY_C)
1808		id += DPLL_ID_DG1_DPLL2;
1809
1810	return intel_get_shared_dpll_by_id(i915, id);
1811}
1812
1813static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1814				       const struct intel_crtc_state *crtc_state)
1815{
1816	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1817	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1818	enum phy phy = intel_port_to_phy(i915, encoder->port);
1819
1820	if (drm_WARN_ON(&i915->drm, !pll))
1821		return;
1822
1823	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1824			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1825			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1826			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1827}
1828
1829static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1830{
1831	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1832	enum phy phy = intel_port_to_phy(i915, encoder->port);
1833
1834	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1835			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1836}
1837
1838static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1839{
1840	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1841	enum phy phy = intel_port_to_phy(i915, encoder->port);
1842
1843	return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1844					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1845}
1846
1847struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1848{
1849	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1850	enum phy phy = intel_port_to_phy(i915, encoder->port);
1851
1852	return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1853				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1854				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1855}
1856
1857static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1858				    const struct intel_crtc_state *crtc_state)
1859{
1860	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1861	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1862	enum port port = encoder->port;
1863
1864	if (drm_WARN_ON(&i915->drm, !pll))
1865		return;
1866
1867	/*
1868	 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1869	 *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1870	 */
1871	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1872
1873	icl_ddi_combo_enable_clock(encoder, crtc_state);
1874}
1875
1876static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1877{
1878	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1879	enum port port = encoder->port;
1880
1881	icl_ddi_combo_disable_clock(encoder);
1882
1883	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1884}
1885
1886static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1887{
1888	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1889	enum port port = encoder->port;
1890	u32 tmp;
1891
1892	tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1893
1894	if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1895		return false;
1896
1897	return icl_ddi_combo_is_clock_enabled(encoder);
1898}
1899
1900static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1901				    const struct intel_crtc_state *crtc_state)
1902{
1903	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1904	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1905	enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1906	enum port port = encoder->port;
1907
1908	if (drm_WARN_ON(&i915->drm, !pll))
1909		return;
1910
1911	intel_de_write(i915, DDI_CLK_SEL(port),
1912		       icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1913
1914	mutex_lock(&i915->dpll.lock);
1915
1916	intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1917		     ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1918
1919	mutex_unlock(&i915->dpll.lock);
1920}
1921
1922static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1923{
1924	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1925	enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1926	enum port port = encoder->port;
1927
1928	mutex_lock(&i915->dpll.lock);
1929
1930	intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1931		     0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1932
1933	mutex_unlock(&i915->dpll.lock);
1934
1935	intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1936}
1937
1938static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1939{
1940	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1941	enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1942	enum port port = encoder->port;
1943	u32 tmp;
1944
1945	tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1946
1947	if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1948		return false;
1949
1950	tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1951
1952	return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1953}
1954
1955static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1956{
1957	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1958	enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1959	enum port port = encoder->port;
1960	enum intel_dpll_id id;
1961	u32 tmp;
1962
1963	tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1964
1965	switch (tmp & DDI_CLK_SEL_MASK) {
1966	case DDI_CLK_SEL_TBT_162:
1967	case DDI_CLK_SEL_TBT_270:
1968	case DDI_CLK_SEL_TBT_540:
1969	case DDI_CLK_SEL_TBT_810:
1970		id = DPLL_ID_ICL_TBTPLL;
1971		break;
1972	case DDI_CLK_SEL_MG:
1973		id = icl_tc_port_to_pll_id(tc_port);
1974		break;
1975	default:
1976		MISSING_CASE(tmp);
1977		fallthrough;
1978	case DDI_CLK_SEL_NONE:
1979		return NULL;
1980	}
1981
1982	return intel_get_shared_dpll_by_id(i915, id);
1983}
1984
1985static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
1986				 const struct intel_crtc_state *crtc_state)
1987{
1988	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1989	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1990	enum port port = encoder->port;
1991
1992	if (drm_WARN_ON(&i915->drm, !pll))
1993		return;
1994
1995	_cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0,
1996			      DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
1997			      DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
1998			      DPCLKA_CFGCR0_DDI_CLK_OFF(port));
1999}
2000
2001static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
2002{
2003	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2004	enum port port = encoder->port;
2005
2006	_cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0,
2007			       DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2008}
2009
2010static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder)
2011{
2012	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2013	enum port port = encoder->port;
2014
2015	return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,
2016					 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2017}
2018
2019static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder)
2020{
2021	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2022	enum port port = encoder->port;
2023
2024	return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,
2025				DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
2026				DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
2027}
2028
2029static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
2030{
2031	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2032	enum intel_dpll_id id;
2033
2034	switch (encoder->port) {
2035	case PORT_A:
2036		id = DPLL_ID_SKL_DPLL0;
2037		break;
2038	case PORT_B:
2039		id = DPLL_ID_SKL_DPLL1;
2040		break;
2041	case PORT_C:
2042		id = DPLL_ID_SKL_DPLL2;
2043		break;
2044	default:
2045		MISSING_CASE(encoder->port);
2046		return NULL;
2047	}
2048
2049	return intel_get_shared_dpll_by_id(i915, id);
2050}
2051
2052static void skl_ddi_enable_clock(struct intel_encoder *encoder,
2053				 const struct intel_crtc_state *crtc_state)
2054{
2055	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2056	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2057	enum port port = encoder->port;
2058
2059	if (drm_WARN_ON(&i915->drm, !pll))
2060		return;
2061
2062	mutex_lock(&i915->dpll.lock);
2063
2064	intel_de_rmw(i915, DPLL_CTRL2,
2065		     DPLL_CTRL2_DDI_CLK_OFF(port) |
2066		     DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
2067		     DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2068		     DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2069
2070	mutex_unlock(&i915->dpll.lock);
2071}
2072
2073static void skl_ddi_disable_clock(struct intel_encoder *encoder)
2074{
2075	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2076	enum port port = encoder->port;
2077
2078	mutex_lock(&i915->dpll.lock);
2079
2080	intel_de_rmw(i915, DPLL_CTRL2,
2081		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
2082
2083	mutex_unlock(&i915->dpll.lock);
2084}
2085
2086static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
2087{
2088	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2089	enum port port = encoder->port;
2090
2091	/*
2092	 * FIXME Not sure if the override affects both
2093	 * the PLL selection and the CLK_OFF bit.
2094	 */
2095	return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
2096}
2097
2098static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
2099{
2100	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2101	enum port port = encoder->port;
2102	enum intel_dpll_id id;
2103	u32 tmp;
2104
2105	tmp = intel_de_read(i915, DPLL_CTRL2);
2106
2107	/*
2108	 * FIXME Not sure if the override affects both
2109	 * the PLL selection and the CLK_OFF bit.
2110	 */
2111	if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
2112		return NULL;
2113
2114	id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
2115		DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
2116
2117	return intel_get_shared_dpll_by_id(i915, id);
2118}
2119
2120void hsw_ddi_enable_clock(struct intel_encoder *encoder,
2121			  const struct intel_crtc_state *crtc_state)
2122{
2123	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2124	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2125	enum port port = encoder->port;
2126
2127	if (drm_WARN_ON(&i915->drm, !pll))
2128		return;
2129
2130	intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2131}
2132
2133void hsw_ddi_disable_clock(struct intel_encoder *encoder)
2134{
2135	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2136	enum port port = encoder->port;
2137
2138	intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2139}
2140
2141bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
2142{
2143	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2144	enum port port = encoder->port;
2145
2146	return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
2147}
2148
2149static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
2150{
2151	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2152	enum port port = encoder->port;
2153	enum intel_dpll_id id;
2154	u32 tmp;
2155
2156	tmp = intel_de_read(i915, PORT_CLK_SEL(port));
2157
2158	switch (tmp & PORT_CLK_SEL_MASK) {
2159	case PORT_CLK_SEL_WRPLL1:
2160		id = DPLL_ID_WRPLL1;
2161		break;
2162	case PORT_CLK_SEL_WRPLL2:
2163		id = DPLL_ID_WRPLL2;
2164		break;
2165	case PORT_CLK_SEL_SPLL:
2166		id = DPLL_ID_SPLL;
2167		break;
2168	case PORT_CLK_SEL_LCPLL_810:
2169		id = DPLL_ID_LCPLL_810;
2170		break;
2171	case PORT_CLK_SEL_LCPLL_1350:
2172		id = DPLL_ID_LCPLL_1350;
2173		break;
2174	case PORT_CLK_SEL_LCPLL_2700:
2175		id = DPLL_ID_LCPLL_2700;
2176		break;
2177	default:
2178		MISSING_CASE(tmp);
2179		fallthrough;
2180	case PORT_CLK_SEL_NONE:
2181		return NULL;
2182	}
2183
2184	return intel_get_shared_dpll_by_id(i915, id);
2185}
2186
2187void intel_ddi_enable_clock(struct intel_encoder *encoder,
2188			    const struct intel_crtc_state *crtc_state)
2189{
2190	if (encoder->enable_clock)
2191		encoder->enable_clock(encoder, crtc_state);
2192}
2193
2194static void intel_ddi_disable_clock(struct intel_encoder *encoder)
2195{
2196	if (encoder->disable_clock)
2197		encoder->disable_clock(encoder);
2198}
2199
2200void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2201{
2202	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2203	u32 port_mask;
2204	bool ddi_clk_needed;
2205
2206	/*
2207	 * In case of DP MST, we sanitize the primary encoder only, not the
2208	 * virtual ones.
2209	 */
2210	if (encoder->type == INTEL_OUTPUT_DP_MST)
2211		return;
2212
2213	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2214		u8 pipe_mask;
2215		bool is_mst;
2216
2217		intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2218		/*
2219		 * In the unlikely case that BIOS enables DP in MST mode, just
2220		 * warn since our MST HW readout is incomplete.
2221		 */
2222		if (drm_WARN_ON(&i915->drm, is_mst))
2223			return;
2224	}
2225
2226	port_mask = BIT(encoder->port);
2227	ddi_clk_needed = encoder->base.crtc;
2228
2229	if (encoder->type == INTEL_OUTPUT_DSI) {
2230		struct intel_encoder *other_encoder;
2231
2232		port_mask = intel_dsi_encoder_ports(encoder);
2233		/*
2234		 * Sanity check that we haven't incorrectly registered another
2235		 * encoder using any of the ports of this DSI encoder.
2236		 */
2237		for_each_intel_encoder(&i915->drm, other_encoder) {
2238			if (other_encoder == encoder)
2239				continue;
2240
2241			if (drm_WARN_ON(&i915->drm,
2242					port_mask & BIT(other_encoder->port)))
2243				return;
2244		}
2245		/*
2246		 * For DSI we keep the ddi clocks gated
2247		 * except during enable/disable sequence.
2248		 */
2249		ddi_clk_needed = false;
2250	}
2251
2252	if (ddi_clk_needed || !encoder->disable_clock ||
2253	    !encoder->is_clock_enabled(encoder))
2254		return;
2255
2256	drm_notice(&i915->drm,
2257		   "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2258		   encoder->base.base.id, encoder->base.name);
2259
2260	encoder->disable_clock(encoder);
2261}
2262
2263static void
2264icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2265		       const struct intel_crtc_state *crtc_state)
2266{
2267	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2268	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2269	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2270	u32 ln0, ln1, pin_assignment;
2271	u8 width;
2272
2273	if (!intel_phy_is_tc(dev_priv, phy) ||
2274	    dig_port->tc_mode == TC_PORT_TBT_ALT)
2275		return;
2276
2277	if (DISPLAY_VER(dev_priv) >= 12) {
2278		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2279			       HIP_INDEX_VAL(tc_port, 0x0));
2280		ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2281		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2282			       HIP_INDEX_VAL(tc_port, 0x1));
2283		ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2284	} else {
2285		ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2286		ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2287	}
2288
2289	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2290	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2291
2292	/* DPPATC */
2293	pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2294	width = crtc_state->lane_count;
2295
2296	switch (pin_assignment) {
2297	case 0x0:
2298		drm_WARN_ON(&dev_priv->drm,
2299			    dig_port->tc_mode != TC_PORT_LEGACY);
2300		if (width == 1) {
2301			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2302		} else {
2303			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2304			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2305		}
2306		break;
2307	case 0x1:
2308		if (width == 4) {
2309			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2310			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2311		}
2312		break;
2313	case 0x2:
2314		if (width == 2) {
2315			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2316			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2317		}
2318		break;
2319	case 0x3:
2320	case 0x5:
2321		if (width == 1) {
2322			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2323			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2324		} else {
2325			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2326			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2327		}
2328		break;
2329	case 0x4:
2330	case 0x6:
2331		if (width == 1) {
2332			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2333			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2334		} else {
2335			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2336			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2337		}
2338		break;
2339	default:
2340		MISSING_CASE(pin_assignment);
2341	}
2342
2343	if (DISPLAY_VER(dev_priv) >= 12) {
2344		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2345			       HIP_INDEX_VAL(tc_port, 0x0));
2346		intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2347		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2348			       HIP_INDEX_VAL(tc_port, 0x1));
2349		intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2350	} else {
2351		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2352		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2353	}
2354}
2355
2356static enum transcoder
2357tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2358{
2359	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2360		return crtc_state->mst_master_transcoder;
2361	else
2362		return crtc_state->cpu_transcoder;
2363}
2364
2365i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2366			 const struct intel_crtc_state *crtc_state)
2367{
2368	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2369
2370	if (DISPLAY_VER(dev_priv) >= 12)
2371		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2372	else
2373		return DP_TP_CTL(encoder->port);
2374}
2375
2376i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2377			    const struct intel_crtc_state *crtc_state)
2378{
2379	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2380
2381	if (DISPLAY_VER(dev_priv) >= 12)
2382		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2383	else
2384		return DP_TP_STATUS(encoder->port);
2385}
2386
2387static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2388							  const struct intel_crtc_state *crtc_state,
2389							  bool enable)
2390{
2391	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2392
2393	if (!crtc_state->vrr.enable)
2394		return;
2395
2396	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2397			       enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2398		drm_dbg_kms(&i915->drm,
2399			    "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2400			    enabledisable(enable));
2401}
2402
2403static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2404					const struct intel_crtc_state *crtc_state)
 
2405{
2406	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2407
2408	if (!crtc_state->fec_enable)
2409		return;
2410
2411	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2412		drm_dbg_kms(&i915->drm,
2413			    "Failed to set FEC_READY in the sink\n");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2414}
2415
2416static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2417				 const struct intel_crtc_state *crtc_state)
2418{
2419	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2420	struct intel_dp *intel_dp;
2421	u32 val;
2422
2423	if (!crtc_state->fec_enable)
2424		return;
2425
2426	intel_dp = enc_to_intel_dp(encoder);
2427	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2428	val |= DP_TP_CTL_FEC_ENABLE;
2429	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2430}
2431
2432static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2433					const struct intel_crtc_state *crtc_state)
2434{
2435	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2436	struct intel_dp *intel_dp;
2437	u32 val;
2438
2439	if (!crtc_state->fec_enable)
2440		return;
2441
2442	intel_dp = enc_to_intel_dp(encoder);
2443	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2444	val &= ~DP_TP_CTL_FEC_ENABLE;
2445	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2446	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2447}
2448
2449static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2450				     const struct intel_crtc_state *crtc_state)
2451{
2452	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2453	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2454	enum phy phy = intel_port_to_phy(i915, encoder->port);
2455
2456	if (intel_phy_is_combo(i915, phy)) {
2457		bool lane_reversal =
2458			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2459
2460		intel_combo_phy_power_up_lanes(i915, phy, false,
2461					       crtc_state->lane_count,
2462					       lane_reversal);
2463	}
2464}
2465
2466/* Splitter enable for eDP MSO is limited to certain pipes. */
2467static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2468{
2469	if (IS_ALDERLAKE_P(i915))
2470		return BIT(PIPE_A) | BIT(PIPE_B);
2471	else
2472		return BIT(PIPE_A);
2473}
2474
2475static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2476				     struct intel_crtc_state *pipe_config)
2477{
2478	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2479	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2480	enum pipe pipe = crtc->pipe;
2481	u32 dss1;
2482
2483	if (!HAS_MSO(i915))
2484		return;
2485
2486	dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2487
2488	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2489	if (!pipe_config->splitter.enable)
2490		return;
2491
2492	if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2493		pipe_config->splitter.enable = false;
2494		return;
2495	}
2496
2497	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2498	default:
2499		drm_WARN(&i915->drm, true,
2500			 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2501		fallthrough;
2502	case SPLITTER_CONFIGURATION_2_SEGMENT:
2503		pipe_config->splitter.link_count = 2;
2504		break;
2505	case SPLITTER_CONFIGURATION_4_SEGMENT:
2506		pipe_config->splitter.link_count = 4;
2507		break;
2508	}
2509
2510	pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2511}
2512
2513static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2514{
2515	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2516	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2517	enum pipe pipe = crtc->pipe;
2518	u32 dss1 = 0;
2519
2520	if (!HAS_MSO(i915))
2521		return;
2522
2523	if (crtc_state->splitter.enable) {
2524		dss1 |= SPLITTER_ENABLE;
2525		dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2526		if (crtc_state->splitter.link_count == 2)
2527			dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2528		else
2529			dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2530	}
2531
2532	intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2533		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2534		     OVERLAP_PIXELS_MASK, dss1);
2535}
2536
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2537static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2538				  struct intel_encoder *encoder,
2539				  const struct intel_crtc_state *crtc_state,
2540				  const struct drm_connector_state *conn_state)
2541{
2542	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2543	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2545	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2546	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2547	int level = intel_ddi_dp_level(intel_dp);
2548
2549	intel_dp_set_link_params(intel_dp,
2550				 crtc_state->port_clock,
2551				 crtc_state->lane_count);
2552
2553	/*
 
 
 
 
 
 
2554	 * 1. Enable Power Wells
2555	 *
2556	 * This was handled at the beginning of intel_atomic_commit_tail(),
2557	 * before we called down into this function.
2558	 */
2559
2560	/* 2. Enable Panel Power if PPS is required */
2561	intel_pps_on(intel_dp);
2562
2563	/*
2564	 * 3. For non-TBT Type-C ports, set FIA lane count
2565	 * (DFLEXDPSP.DPX4TXLATC)
2566	 *
2567	 * This was done before tgl_ddi_pre_enable_dp by
2568	 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2569	 */
2570
2571	/*
2572	 * 4. Enable the port PLL.
2573	 *
2574	 * The PLL enabling itself was already done before this function by
2575	 * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2576	 * configure the PLL to port mapping here.
2577	 */
2578	intel_ddi_enable_clock(encoder, crtc_state);
2579
2580	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2581	if (!intel_phy_is_tc(dev_priv, phy) ||
2582	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
2583		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2584		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2585								   dig_port->ddi_io_power_domain);
2586	}
2587
2588	/* 6. Program DP_MODE */
2589	icl_program_mg_dp_mode(dig_port, crtc_state);
2590
2591	/*
2592	 * 7. The rest of the below are substeps under the bspec's "Enable and
2593	 * Train Display Port" step.  Note that steps that are specific to
2594	 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2595	 * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2596	 * us when active_mst_links==0, so any steps designated for "single
2597	 * stream or multi-stream master transcoder" can just be performed
2598	 * unconditionally here.
2599	 */
2600
2601	/*
2602	 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2603	 * Transcoder.
2604	 */
2605	intel_ddi_enable_pipe_clock(encoder, crtc_state);
 
 
 
2606
2607	/*
2608	 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2609	 * Transport Select
2610	 */
2611	intel_ddi_config_transcoder_func(encoder, crtc_state);
2612
2613	/*
2614	 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2615	 * selected
2616	 *
2617	 * This will be handled by the intel_dp_start_link_train() farther
2618	 * down this function.
2619	 */
2620
2621	/* 7.e Configure voltage swing and related IO settings */
2622	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2623
2624	/*
2625	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2626	 * the used lanes of the DDI.
2627	 */
2628	intel_ddi_power_up_lanes(encoder, crtc_state);
2629
2630	/*
2631	 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2632	 */
2633	intel_ddi_mso_configure(crtc_state);
2634
2635	/*
2636	 * 7.g Configure and enable DDI_BUF_CTL
2637	 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2638	 *     after 500 us.
2639	 *
2640	 * We only configure what the register value will be here.  Actual
2641	 * enabling happens during link training farther down.
2642	 */
2643	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2644
2645	if (!is_mst)
2646		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2647
2648	intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2649	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
 
 
 
2650	/*
2651	 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2652	 * in the FEC_CONFIGURATION register to 1 before initiating link
2653	 * training
2654	 */
2655	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2656
2657	intel_dp_check_frl_training(intel_dp);
2658	intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2659
2660	/*
2661	 * 7.i Follow DisplayPort specification training sequence (see notes for
2662	 *     failure handling)
2663	 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2664	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2665	 *     (timeout after 800 us)
2666	 */
2667	intel_dp_start_link_train(intel_dp, crtc_state);
2668
2669	/* 7.k Set DP_TP_CTL link training to Normal */
2670	if (!is_trans_port_sync_mode(crtc_state))
2671		intel_dp_stop_link_train(intel_dp, crtc_state);
2672
2673	/* 7.l Configure and enable FEC if needed */
2674	intel_ddi_enable_fec(encoder, crtc_state);
2675	if (!crtc_state->bigjoiner)
2676		intel_dsc_enable(encoder, crtc_state);
 
2677}
2678
2679static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2680				  struct intel_encoder *encoder,
2681				  const struct intel_crtc_state *crtc_state,
2682				  const struct drm_connector_state *conn_state)
2683{
2684	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2685	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2686	enum port port = encoder->port;
2687	enum phy phy = intel_port_to_phy(dev_priv, port);
2688	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2689	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2690	int level = intel_ddi_dp_level(intel_dp);
2691
2692	if (DISPLAY_VER(dev_priv) < 11)
2693		drm_WARN_ON(&dev_priv->drm,
2694			    is_mst && (port == PORT_A || port == PORT_E));
2695	else
2696		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2697
2698	intel_dp_set_link_params(intel_dp,
2699				 crtc_state->port_clock,
2700				 crtc_state->lane_count);
2701
 
 
 
 
 
 
2702	intel_pps_on(intel_dp);
2703
2704	intel_ddi_enable_clock(encoder, crtc_state);
2705
2706	if (!intel_phy_is_tc(dev_priv, phy) ||
2707	    dig_port->tc_mode != TC_PORT_TBT_ALT) {
2708		drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2709		dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2710								   dig_port->ddi_io_power_domain);
2711	}
2712
2713	icl_program_mg_dp_mode(dig_port, crtc_state);
2714
2715	if (DISPLAY_VER(dev_priv) >= 11)
2716		icl_ddi_vswing_sequence(encoder, crtc_state, level);
2717	else if (IS_CANNONLAKE(dev_priv))
2718		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
2719	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2720		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
2721	else
2722		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2723
2724	intel_ddi_power_up_lanes(encoder, crtc_state);
2725
2726	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2727	if (!is_mst)
2728		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2729	intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2730	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2731					      true);
2732	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
 
 
2733	intel_dp_start_link_train(intel_dp, crtc_state);
2734	if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2735	    !is_trans_port_sync_mode(crtc_state))
2736		intel_dp_stop_link_train(intel_dp, crtc_state);
2737
2738	intel_ddi_enable_fec(encoder, crtc_state);
2739
2740	if (!is_mst)
2741		intel_ddi_enable_pipe_clock(encoder, crtc_state);
2742
2743	if (!crtc_state->bigjoiner)
2744		intel_dsc_enable(encoder, crtc_state);
2745}
2746
2747static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2748				    struct intel_encoder *encoder,
2749				    const struct intel_crtc_state *crtc_state,
2750				    const struct drm_connector_state *conn_state)
2751{
2752	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
2753
2754	if (DISPLAY_VER(dev_priv) >= 12)
 
 
 
 
 
 
 
 
 
 
2755		tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2756	else
2757		hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2758
2759	/* MST will call a setting of MSA after an allocating of Virtual Channel
2760	 * from MST encoder pre_enable callback.
2761	 */
2762	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2763		intel_ddi_set_dp_msa(crtc_state, conn_state);
2764
2765		intel_dp_set_m_n(crtc_state, M1_N1);
2766	}
2767}
2768
2769static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2770				      struct intel_encoder *encoder,
2771				      const struct intel_crtc_state *crtc_state,
2772				      const struct drm_connector_state *conn_state)
2773{
2774	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2775	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2776	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2777
2778	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2779	intel_ddi_enable_clock(encoder, crtc_state);
2780
2781	drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2782	dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2783							   dig_port->ddi_io_power_domain);
2784
2785	icl_program_mg_dp_mode(dig_port, crtc_state);
2786
2787	intel_ddi_enable_pipe_clock(encoder, crtc_state);
2788
2789	dig_port->set_infoframes(encoder,
2790				 crtc_state->has_infoframe,
2791				 crtc_state, conn_state);
2792}
2793
2794static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2795				 struct intel_encoder *encoder,
2796				 const struct intel_crtc_state *crtc_state,
2797				 const struct drm_connector_state *conn_state)
2798{
2799	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2800	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2801	enum pipe pipe = crtc->pipe;
2802
2803	/*
2804	 * When called from DP MST code:
2805	 * - conn_state will be NULL
2806	 * - encoder will be the main encoder (ie. mst->primary)
2807	 * - the main connector associated with this port
2808	 *   won't be active or linked to a crtc
2809	 * - crtc_state will be the state of the first stream to
2810	 *   be activated on this port, and it may not be the same
2811	 *   stream that will be deactivated last, but each stream
2812	 *   should have a state that is identical when it comes to
2813	 *   the DP link parameteres
2814	 */
2815
2816	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2817
2818	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2819
2820	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2821		intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2822					  conn_state);
2823	} else {
2824		struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2825
2826		intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2827					conn_state);
2828
2829		/* FIXME precompute everything properly */
2830		if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
 
2831			dig_port->set_infoframes(encoder,
2832						 crtc_state->has_infoframe,
2833						 crtc_state, conn_state);
2834	}
2835}
2836
2837static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2838				  const struct intel_crtc_state *crtc_state)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2839{
2840	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2841	enum port port = encoder->port;
2842	bool wait = false;
2843	u32 val;
2844
 
2845	val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2846	if (val & DDI_BUF_CTL_ENABLE) {
2847		val &= ~DDI_BUF_CTL_ENABLE;
2848		intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2849		wait = true;
 
 
2850	}
2851
 
 
 
 
2852	if (intel_crtc_has_dp_encoder(crtc_state)) {
2853		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2854		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2855		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2856		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2857	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2858
2859	/* Disable FEC in DP Sink */
2860	intel_ddi_disable_fec_state(encoder, crtc_state);
2861
2862	if (wait)
2863		intel_wait_ddi_buf_idle(dev_priv, port);
2864}
2865
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2866static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2867				      struct intel_encoder *encoder,
2868				      const struct intel_crtc_state *old_crtc_state,
2869				      const struct drm_connector_state *old_conn_state)
2870{
2871	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2872	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2873	struct intel_dp *intel_dp = &dig_port->dp;
 
2874	bool is_mst = intel_crtc_has_type(old_crtc_state,
2875					  INTEL_OUTPUT_DP_MST);
2876	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2877
2878	if (!is_mst)
2879		intel_dp_set_infoframes(encoder, false,
2880					old_crtc_state, old_conn_state);
2881
2882	/*
2883	 * Power down sink before disabling the port, otherwise we end
2884	 * up getting interrupts from the sink on detecting link loss.
2885	 */
2886	intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2887
2888	if (DISPLAY_VER(dev_priv) >= 12) {
2889		if (is_mst) {
2890			enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2891			u32 val;
2892
2893			val = intel_de_read(dev_priv,
2894					    TRANS_DDI_FUNC_CTL(cpu_transcoder));
2895			val &= ~(TGL_TRANS_DDI_PORT_MASK |
2896				 TRANS_DDI_MODE_SELECT_MASK);
2897			intel_de_write(dev_priv,
2898				       TRANS_DDI_FUNC_CTL(cpu_transcoder),
2899				       val);
2900		}
2901	} else {
2902		if (!is_mst)
2903			intel_ddi_disable_pipe_clock(old_crtc_state);
2904	}
2905
2906	intel_disable_ddi_buf(encoder, old_crtc_state);
2907
 
 
2908	/*
2909	 * From TGL spec: "If single stream or multi-stream master transcoder:
2910	 * Configure Transcoder Clock select to direct no clock to the
2911	 * transcoder"
2912	 */
2913	if (DISPLAY_VER(dev_priv) >= 12)
2914		intel_ddi_disable_pipe_clock(old_crtc_state);
2915
2916	intel_pps_vdd_on(intel_dp);
2917	intel_pps_off(intel_dp);
2918
2919	if (!intel_phy_is_tc(dev_priv, phy) ||
2920	    dig_port->tc_mode != TC_PORT_TBT_ALT)
 
2921		intel_display_power_put(dev_priv,
2922					dig_port->ddi_io_power_domain,
2923					fetch_and_zero(&dig_port->ddi_io_wakeref));
2924
2925	intel_ddi_disable_clock(encoder);
 
 
 
 
 
2926}
2927
2928static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2929					struct intel_encoder *encoder,
2930					const struct intel_crtc_state *old_crtc_state,
2931					const struct drm_connector_state *old_conn_state)
2932{
2933	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2934	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2935	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 
2936
2937	dig_port->set_infoframes(encoder, false,
2938				 old_crtc_state, old_conn_state);
2939
2940	intel_ddi_disable_pipe_clock(old_crtc_state);
 
2941
2942	intel_disable_ddi_buf(encoder, old_crtc_state);
2943
2944	intel_display_power_put(dev_priv,
2945				dig_port->ddi_io_power_domain,
2946				fetch_and_zero(&dig_port->ddi_io_wakeref));
 
 
 
 
 
2947
2948	intel_ddi_disable_clock(encoder);
2949
2950	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2951}
2952
2953static void intel_ddi_post_disable(struct intel_atomic_state *state,
2954				   struct intel_encoder *encoder,
2955				   const struct intel_crtc_state *old_crtc_state,
2956				   const struct drm_connector_state *old_conn_state)
2957{
2958	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2959	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2960	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2961	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2962
2963	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2964		intel_crtc_vblank_off(old_crtc_state);
2965
2966		intel_disable_pipe(old_crtc_state);
2967
2968		intel_vrr_disable(old_crtc_state);
2969
2970		intel_ddi_disable_transcoder_func(old_crtc_state);
2971
2972		intel_dsc_disable(old_crtc_state);
2973
2974		if (DISPLAY_VER(dev_priv) >= 9)
2975			skl_scaler_disable(old_crtc_state);
2976		else
2977			ilk_pfit_disable(old_crtc_state);
2978	}
2979
2980	if (old_crtc_state->bigjoiner_linked_crtc) {
2981		struct intel_atomic_state *state =
2982			to_intel_atomic_state(old_crtc_state->uapi.state);
2983		struct intel_crtc *slave =
2984			old_crtc_state->bigjoiner_linked_crtc;
2985		const struct intel_crtc_state *old_slave_crtc_state =
2986			intel_atomic_get_old_crtc_state(state, slave);
2987
2988		intel_crtc_vblank_off(old_slave_crtc_state);
2989
2990		intel_dsc_disable(old_slave_crtc_state);
2991		skl_scaler_disable(old_slave_crtc_state);
2992	}
2993
2994	/*
2995	 * When called from DP MST code:
2996	 * - old_conn_state will be NULL
2997	 * - encoder will be the main encoder (ie. mst->primary)
2998	 * - the main connector associated with this port
2999	 *   won't be active or linked to a crtc
3000	 * - old_crtc_state will be the state of the last stream to
3001	 *   be deactivated on this port, and it may not be the same
3002	 *   stream that was activated last, but each stream
3003	 *   should have a state that is identical when it comes to
3004	 *   the DP link parameteres
3005	 */
3006
3007	if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3008		intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3009					    old_conn_state);
3010	else
3011		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3012					  old_conn_state);
3013
3014	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3015		intel_display_power_put(dev_priv,
3016					intel_ddi_main_link_aux_domain(dig_port),
3017					fetch_and_zero(&dig_port->aux_wakeref));
3018
3019	if (is_tc_port)
3020		intel_tc_port_put_link(dig_port);
3021}
3022
3023void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3024				struct intel_encoder *encoder,
3025				const struct intel_crtc_state *old_crtc_state,
3026				const struct drm_connector_state *old_conn_state)
3027{
3028	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3029	u32 val;
3030
3031	/*
3032	 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3033	 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3034	 * step 13 is the correct place for it. Step 18 is where it was
3035	 * originally before the BUN.
3036	 */
3037	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3038	val &= ~FDI_RX_ENABLE;
3039	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3040
3041	intel_disable_ddi_buf(encoder, old_crtc_state);
3042	intel_ddi_disable_clock(encoder);
3043
3044	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3045	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3046	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3047	intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3048
3049	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3050	val &= ~FDI_PCDCLK;
3051	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3052
3053	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3054	val &= ~FDI_RX_PLL_ENABLE;
3055	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3056}
3057
3058static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3059					    struct intel_encoder *encoder,
3060					    const struct intel_crtc_state *crtc_state)
3061{
3062	const struct drm_connector_state *conn_state;
3063	struct drm_connector *conn;
3064	int i;
3065
3066	if (!crtc_state->sync_mode_slaves_mask)
3067		return;
3068
3069	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3070		struct intel_encoder *slave_encoder =
3071			to_intel_encoder(conn_state->best_encoder);
3072		struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3073		const struct intel_crtc_state *slave_crtc_state;
3074
3075		if (!slave_crtc)
3076			continue;
3077
3078		slave_crtc_state =
3079			intel_atomic_get_new_crtc_state(state, slave_crtc);
3080
3081		if (slave_crtc_state->master_transcoder !=
3082		    crtc_state->cpu_transcoder)
3083			continue;
3084
3085		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
3086					 slave_crtc_state);
3087	}
3088
3089	usleep_range(200, 400);
3090
3091	intel_dp_stop_link_train(enc_to_intel_dp(encoder),
3092				 crtc_state);
3093}
3094
3095static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3096				struct intel_encoder *encoder,
3097				const struct intel_crtc_state *crtc_state,
3098				const struct drm_connector_state *conn_state)
3099{
3100	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3101	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3102	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3103	enum port port = encoder->port;
3104
3105	if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3106		intel_dp_stop_link_train(intel_dp, crtc_state);
3107
 
3108	intel_edp_backlight_on(crtc_state, conn_state);
3109	intel_psr_enable(intel_dp, crtc_state, conn_state);
3110
3111	if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
3112		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3113
3114	intel_edp_drrs_enable(intel_dp, crtc_state);
3115
3116	if (crtc_state->has_audio)
3117		intel_audio_codec_enable(encoder, crtc_state, conn_state);
3118
3119	trans_port_sync_stop_link_train(state, encoder, crtc_state);
3120}
3121
 
 
 
 
 
 
 
 
 
3122static i915_reg_t
3123gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3124			       enum port port)
3125{
3126	static const enum transcoder trans[] = {
3127		[PORT_A] = TRANSCODER_EDP,
3128		[PORT_B] = TRANSCODER_A,
3129		[PORT_C] = TRANSCODER_B,
3130		[PORT_D] = TRANSCODER_C,
3131		[PORT_E] = TRANSCODER_A,
3132	};
3133
3134	drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3135
3136	if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3137		port = PORT_A;
3138
3139	return CHICKEN_TRANS(trans[port]);
3140}
3141
3142static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3143				  struct intel_encoder *encoder,
3144				  const struct intel_crtc_state *crtc_state,
3145				  const struct drm_connector_state *conn_state)
3146{
3147	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3148	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3149	struct drm_connector *connector = conn_state->connector;
3150	int level = intel_ddi_hdmi_level(encoder, crtc_state);
3151	enum port port = encoder->port;
 
 
3152
3153	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3154					       crtc_state->hdmi_high_tmds_clock_ratio,
3155					       crtc_state->hdmi_scrambling))
3156		drm_dbg_kms(&dev_priv->drm,
3157			    "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3158			    connector->base.id, connector->name);
3159
3160	if (DISPLAY_VER(dev_priv) >= 12)
3161		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3162	else if (DISPLAY_VER(dev_priv) == 11)
3163		icl_ddi_vswing_sequence(encoder, crtc_state, level);
3164	else if (IS_CANNONLAKE(dev_priv))
3165		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3166	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3167		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3168	else
3169		intel_prepare_hdmi_ddi_buffers(encoder, level);
3170
3171	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
3172		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 
 
3173
3174	/* Display WA #1143: skl,kbl,cfl */
3175	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3176		/*
3177		 * For some reason these chicken bits have been
3178		 * stuffed into a transcoder register, event though
3179		 * the bits affect a specific DDI port rather than
3180		 * a specific transcoder.
3181		 */
3182		i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3183		u32 val;
3184
3185		val = intel_de_read(dev_priv, reg);
3186
3187		if (port == PORT_E)
3188			val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3189				DDIE_TRAINING_OVERRIDE_VALUE;
3190		else
3191			val |= DDI_TRAINING_OVERRIDE_ENABLE |
3192				DDI_TRAINING_OVERRIDE_VALUE;
3193
3194		intel_de_write(dev_priv, reg, val);
3195		intel_de_posting_read(dev_priv, reg);
3196
3197		udelay(1);
3198
3199		if (port == PORT_E)
3200			val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3201				 DDIE_TRAINING_OVERRIDE_VALUE);
3202		else
3203			val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3204				 DDI_TRAINING_OVERRIDE_VALUE);
3205
3206		intel_de_write(dev_priv, reg, val);
3207	}
3208
3209	intel_ddi_power_up_lanes(encoder, crtc_state);
3210
3211	/* In HDMI/DVI mode, the port width, and swing/emphasis values
3212	 * are ignored so nothing special needs to be done besides
3213	 * enabling the port.
3214	 *
3215	 * On ADL_P the PHY link rate and lane count must be programmed but
3216	 * these are both 0 for HDMI.
 
 
 
 
3217	 */
3218	intel_de_write(dev_priv, DDI_BUF_CTL(port),
3219		       dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
 
 
3220
3221	if (crtc_state->has_audio)
3222		intel_audio_codec_enable(encoder, crtc_state, conn_state);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3223}
3224
3225static void intel_enable_ddi(struct intel_atomic_state *state,
3226			     struct intel_encoder *encoder,
3227			     const struct intel_crtc_state *crtc_state,
3228			     const struct drm_connector_state *conn_state)
3229{
3230	drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3231
3232	if (!crtc_state->bigjoiner_slave)
3233		intel_ddi_enable_transcoder_func(encoder, crtc_state);
3234
3235	intel_vrr_enable(encoder, crtc_state);
 
3236
3237	intel_enable_pipe(crtc_state);
 
 
3238
3239	intel_crtc_vblank_on(crtc_state);
3240
3241	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3242		intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3243	else
3244		intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3245
3246	/* Enable hdcp if it's desired */
3247	if (conn_state->content_protection ==
3248	    DRM_MODE_CONTENT_PROTECTION_DESIRED)
3249		intel_hdcp_enable(to_intel_connector(conn_state->connector),
3250				  crtc_state,
3251				  (u8)conn_state->hdcp_content_type);
3252}
3253
3254static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3255				 struct intel_encoder *encoder,
3256				 const struct intel_crtc_state *old_crtc_state,
3257				 const struct drm_connector_state *old_conn_state)
3258{
3259	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 
3260
3261	intel_dp->link_trained = false;
3262
3263	if (old_crtc_state->has_audio)
3264		intel_audio_codec_disable(encoder,
3265					  old_crtc_state, old_conn_state);
3266
3267	intel_edp_drrs_disable(intel_dp, old_crtc_state);
3268	intel_psr_disable(intel_dp, old_crtc_state);
3269	intel_edp_backlight_off(old_conn_state);
3270	/* Disable the decompression in DP Sink */
3271	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3272					      false);
3273	/* Disable Ignore_MSA bit in DP Sink */
3274	intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3275						      false);
3276}
3277
3278static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3279				   struct intel_encoder *encoder,
3280				   const struct intel_crtc_state *old_crtc_state,
3281				   const struct drm_connector_state *old_conn_state)
3282{
3283	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3284	struct drm_connector *connector = old_conn_state->connector;
3285
3286	if (old_crtc_state->has_audio)
3287		intel_audio_codec_disable(encoder,
3288					  old_crtc_state, old_conn_state);
3289
3290	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3291					       false, false))
3292		drm_dbg_kms(&i915->drm,
3293			    "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3294			    connector->base.id, connector->name);
3295}
3296
3297static void intel_disable_ddi(struct intel_atomic_state *state,
3298			      struct intel_encoder *encoder,
3299			      const struct intel_crtc_state *old_crtc_state,
3300			      const struct drm_connector_state *old_conn_state)
3301{
 
 
3302	intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3303
3304	if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3305		intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3306				       old_conn_state);
3307	else
3308		intel_disable_ddi_dp(state, encoder, old_crtc_state,
3309				     old_conn_state);
3310}
3311
3312static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3313				     struct intel_encoder *encoder,
3314				     const struct intel_crtc_state *crtc_state,
3315				     const struct drm_connector_state *conn_state)
3316{
3317	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3318
3319	intel_ddi_set_dp_msa(crtc_state, conn_state);
3320
3321	intel_psr_update(intel_dp, crtc_state, conn_state);
3322	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3323	intel_edp_drrs_update(intel_dp, crtc_state);
3324
3325	intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
 
3326}
3327
3328void intel_ddi_update_pipe(struct intel_atomic_state *state,
3329			   struct intel_encoder *encoder,
3330			   const struct intel_crtc_state *crtc_state,
3331			   const struct drm_connector_state *conn_state)
3332{
3333
3334	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3335	    !intel_encoder_is_mst(encoder))
3336		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3337					 conn_state);
3338
3339	intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3340}
3341
3342static void
3343intel_ddi_update_prepare(struct intel_atomic_state *state,
3344			 struct intel_encoder *encoder,
3345			 struct intel_crtc *crtc)
3346{
 
3347	struct intel_crtc_state *crtc_state =
3348		crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3349	int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3350
3351	drm_WARN_ON(state->base.dev, crtc && crtc->active);
3352
3353	intel_tc_port_get_link(enc_to_dig_port(encoder),
3354		               required_lanes);
3355	if (crtc_state && crtc_state->hw.active)
3356		intel_update_active_dpll(state, crtc, encoder);
3357}
3358
3359static void
3360intel_ddi_update_complete(struct intel_atomic_state *state,
3361			  struct intel_encoder *encoder,
3362			  struct intel_crtc *crtc)
3363{
3364	intel_tc_port_put_link(enc_to_dig_port(encoder));
3365}
3366
3367static void
3368intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3369			 struct intel_encoder *encoder,
3370			 const struct intel_crtc_state *crtc_state,
3371			 const struct drm_connector_state *conn_state)
3372{
3373	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3374	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3375	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3376	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3377
3378	if (is_tc_port)
3379		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
 
3380
3381	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3382		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3383		dig_port->aux_wakeref =
3384			intel_display_power_get(dev_priv,
3385						intel_ddi_main_link_aux_domain(dig_port));
3386	}
3387
3388	if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
 
 
3389		/*
3390		 * Program the lane count for static/dynamic connections on
3391		 * Type-C ports.  Skip this step for TBT.
3392		 */
3393		intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3394	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3395		bxt_ddi_phy_set_lane_optim_mask(encoder,
3396						crtc_state->lane_lat_optim_mask);
3397}
3398
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3399static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3400					   const struct intel_crtc_state *crtc_state)
3401{
3402	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 
3403	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3404	enum port port = encoder->port;
3405	u32 dp_tp_ctl, ddi_buf_ctl;
3406	bool wait = false;
3407
3408	dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3409
3410	if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3411		ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3412		if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3413			intel_de_write(dev_priv, DDI_BUF_CTL(port),
3414				       ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3415			wait = true;
3416		}
3417
3418		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3419		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3420		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3421		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3422
3423		if (wait)
3424			intel_wait_ddi_buf_idle(dev_priv, port);
3425	}
3426
3427	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3428	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3429		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3430	} else {
3431		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3432		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3433			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3434	}
3435	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3436	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3437
 
 
 
 
3438	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3439	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3440	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3441
3442	intel_wait_ddi_buf_active(dev_priv, port);
3443}
3444
3445static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3446				     const struct intel_crtc_state *crtc_state,
3447				     u8 dp_train_pat)
3448{
3449	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3450	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3451	u32 temp;
3452
3453	temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3454
3455	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3456	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3457	case DP_TRAINING_PATTERN_DISABLE:
3458		temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3459		break;
3460	case DP_TRAINING_PATTERN_1:
3461		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3462		break;
3463	case DP_TRAINING_PATTERN_2:
3464		temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3465		break;
3466	case DP_TRAINING_PATTERN_3:
3467		temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3468		break;
3469	case DP_TRAINING_PATTERN_4:
3470		temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3471		break;
3472	}
3473
3474	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3475}
3476
3477static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3478					  const struct intel_crtc_state *crtc_state)
3479{
3480	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3481	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3482	enum port port = encoder->port;
3483	u32 val;
3484
3485	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3486	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3487	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3488	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3489
3490	/*
3491	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3492	 * reason we need to set idle transmission mode is to work around a HW
3493	 * issue where we enable the pipe while not in idle link-training mode.
3494	 * In this case there is requirement to wait for a minimum number of
3495	 * idle patterns to be sent.
3496	 */
3497	if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3498		return;
3499
3500	if (intel_de_wait_for_set(dev_priv,
3501				  dp_tp_status_reg(encoder, crtc_state),
3502				  DP_TP_STATUS_IDLE_DONE, 1))
3503		drm_err(&dev_priv->drm,
3504			"Timed out waiting for DP idle patterns\n");
3505}
3506
3507static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3508				       enum transcoder cpu_transcoder)
3509{
3510	if (cpu_transcoder == TRANSCODER_EDP)
3511		return false;
3512
3513	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3514		return false;
3515
3516	return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3517		AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3518}
3519
3520void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3521					 struct intel_crtc_state *crtc_state)
3522{
3523	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3524		crtc_state->min_voltage_level = 2;
3525	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3526		crtc_state->min_voltage_level = 3;
3527	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3528		crtc_state->min_voltage_level = 1;
3529	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3530		crtc_state->min_voltage_level = 2;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3531}
3532
3533static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3534						     enum transcoder cpu_transcoder)
3535{
3536	u32 master_select;
3537
3538	if (DISPLAY_VER(dev_priv) >= 11) {
3539		u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3540
3541		if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3542			return INVALID_TRANSCODER;
3543
3544		master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3545	} else {
3546		u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3547
3548		if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3549			return INVALID_TRANSCODER;
3550
3551		master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3552	}
3553
3554	if (master_select == 0)
3555		return TRANSCODER_EDP;
3556	else
3557		return master_select - 1;
3558}
3559
3560static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3561{
3562	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3563	u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3564		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3565	enum transcoder cpu_transcoder;
3566
3567	crtc_state->master_transcoder =
3568		bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3569
3570	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3571		enum intel_display_power_domain power_domain;
3572		intel_wakeref_t trans_wakeref;
3573
3574		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3575		trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3576								   power_domain);
3577
3578		if (!trans_wakeref)
3579			continue;
3580
3581		if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3582		    crtc_state->cpu_transcoder)
3583			crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3584
3585		intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3586	}
3587
3588	drm_WARN_ON(&dev_priv->drm,
3589		    crtc_state->master_transcoder != INVALID_TRANSCODER &&
3590		    crtc_state->sync_mode_slaves_mask);
3591}
3592
3593static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3594				    struct intel_crtc_state *pipe_config)
3595{
3596	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3597	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
3598	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3599	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3600	u32 temp, flags = 0;
3601
3602	temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3603	if (temp & TRANS_DDI_PHSYNC)
3604		flags |= DRM_MODE_FLAG_PHSYNC;
3605	else
3606		flags |= DRM_MODE_FLAG_NHSYNC;
3607	if (temp & TRANS_DDI_PVSYNC)
3608		flags |= DRM_MODE_FLAG_PVSYNC;
3609	else
3610		flags |= DRM_MODE_FLAG_NVSYNC;
3611
3612	pipe_config->hw.adjusted_mode.flags |= flags;
3613
3614	switch (temp & TRANS_DDI_BPC_MASK) {
3615	case TRANS_DDI_BPC_6:
3616		pipe_config->pipe_bpp = 18;
3617		break;
3618	case TRANS_DDI_BPC_8:
3619		pipe_config->pipe_bpp = 24;
3620		break;
3621	case TRANS_DDI_BPC_10:
3622		pipe_config->pipe_bpp = 30;
3623		break;
3624	case TRANS_DDI_BPC_12:
3625		pipe_config->pipe_bpp = 36;
3626		break;
3627	default:
3628		break;
3629	}
3630
3631	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3632	case TRANS_DDI_MODE_SELECT_HDMI:
3633		pipe_config->has_hdmi_sink = true;
3634
3635		pipe_config->infoframes.enable |=
3636			intel_hdmi_infoframes_enabled(encoder, pipe_config);
3637
3638		if (pipe_config->infoframes.enable)
3639			pipe_config->has_infoframe = true;
3640
3641		if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3642			pipe_config->hdmi_scrambling = true;
3643		if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3644			pipe_config->hdmi_high_tmds_clock_ratio = true;
3645		fallthrough;
3646	case TRANS_DDI_MODE_SELECT_DVI:
3647		pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3648		pipe_config->lane_count = 4;
3649		break;
3650	case TRANS_DDI_MODE_SELECT_FDI:
3651		pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 
3652		break;
3653	case TRANS_DDI_MODE_SELECT_DP_SST:
3654		if (encoder->type == INTEL_OUTPUT_EDP)
3655			pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3656		else
3657			pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3658		pipe_config->lane_count =
3659			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3660		intel_dp_get_m_n(intel_crtc, pipe_config);
3661
3662		if (DISPLAY_VER(dev_priv) >= 11) {
3663			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
 
 
 
 
 
 
3664
 
3665			pipe_config->fec_enable =
3666				intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3667
3668			drm_dbg_kms(&dev_priv->drm,
3669				    "[ENCODER:%d:%s] Fec status: %u\n",
3670				    encoder->base.base.id, encoder->base.name,
3671				    pipe_config->fec_enable);
3672		}
3673
3674		if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3675			pipe_config->infoframes.enable |=
3676				intel_lspcon_infoframes_enabled(encoder, pipe_config);
3677		else
3678			pipe_config->infoframes.enable |=
3679				intel_hdmi_infoframes_enabled(encoder, pipe_config);
3680		break;
 
 
 
 
 
 
 
 
 
 
3681	case TRANS_DDI_MODE_SELECT_DP_MST:
3682		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3683		pipe_config->lane_count =
3684			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3685
3686		if (DISPLAY_VER(dev_priv) >= 12)
3687			pipe_config->mst_master_transcoder =
3688					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3689
3690		intel_dp_get_m_n(intel_crtc, pipe_config);
 
 
 
 
 
 
3691
3692		pipe_config->infoframes.enable |=
3693			intel_hdmi_infoframes_enabled(encoder, pipe_config);
3694		break;
3695	default:
3696		break;
3697	}
3698}
3699
3700static void intel_ddi_get_config(struct intel_encoder *encoder,
3701				 struct intel_crtc_state *pipe_config)
3702{
3703	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3704	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3705
3706	/* XXX: DSI transcoder paranoia */
3707	if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3708		return;
3709
3710	if (pipe_config->bigjoiner_slave) {
3711		/* read out pipe settings from master */
3712		enum transcoder save = pipe_config->cpu_transcoder;
3713
3714		/* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
3715		WARN_ON(pipe_config->output_types);
3716		pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
3717		intel_ddi_read_func_ctl(encoder, pipe_config);
3718		pipe_config->cpu_transcoder = save;
3719	} else {
3720		intel_ddi_read_func_ctl(encoder, pipe_config);
3721	}
3722
3723	intel_ddi_mso_get_config(encoder, pipe_config);
3724
3725	pipe_config->has_audio =
3726		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3727
3728	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3729	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3730		/*
3731		 * This is a big fat ugly hack.
3732		 *
3733		 * Some machines in UEFI boot mode provide us a VBT that has 18
3734		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3735		 * unknown we fail to light up. Yet the same BIOS boots up with
3736		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3737		 * max, not what it tells us to use.
3738		 *
3739		 * Note: This will still be broken if the eDP panel is not lit
3740		 * up by the BIOS, and thus we can't get the mode at module
3741		 * load.
3742		 */
3743		drm_dbg_kms(&dev_priv->drm,
3744			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3745			    pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3746		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3747	}
3748
3749	if (!pipe_config->bigjoiner_slave)
3750		ddi_dotclock_get(pipe_config);
3751
3752	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3753		pipe_config->lane_lat_optim_mask =
3754			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3755
3756	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3757
3758	intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3759
3760	intel_read_infoframe(encoder, pipe_config,
3761			     HDMI_INFOFRAME_TYPE_AVI,
3762			     &pipe_config->infoframes.avi);
3763	intel_read_infoframe(encoder, pipe_config,
3764			     HDMI_INFOFRAME_TYPE_SPD,
3765			     &pipe_config->infoframes.spd);
3766	intel_read_infoframe(encoder, pipe_config,
3767			     HDMI_INFOFRAME_TYPE_VENDOR,
3768			     &pipe_config->infoframes.hdmi);
3769	intel_read_infoframe(encoder, pipe_config,
3770			     HDMI_INFOFRAME_TYPE_DRM,
3771			     &pipe_config->infoframes.drm);
3772
3773	if (DISPLAY_VER(dev_priv) >= 8)
3774		bdw_get_trans_port_sync_config(pipe_config);
3775
 
 
3776	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3777	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3778
3779	intel_psr_get_config(encoder, pipe_config);
3780}
3781
3782void intel_ddi_get_clock(struct intel_encoder *encoder,
3783			 struct intel_crtc_state *crtc_state,
3784			 struct intel_shared_dpll *pll)
3785{
3786	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3787	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3788	struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3789	bool pll_active;
3790
3791	if (drm_WARN_ON(&i915->drm, !pll))
3792		return;
3793
3794	port_dpll->pll = pll;
3795	pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3796	drm_WARN_ON(&i915->drm, !pll_active);
3797
3798	icl_set_active_port_dpll(crtc_state, port_dpll_id);
3799
3800	crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3801						     &crtc_state->dpll_hw_state);
3802}
3803
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3804static void adls_ddi_get_config(struct intel_encoder *encoder,
3805				struct intel_crtc_state *crtc_state)
3806{
3807	intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3808	intel_ddi_get_config(encoder, crtc_state);
3809}
3810
3811static void rkl_ddi_get_config(struct intel_encoder *encoder,
3812			       struct intel_crtc_state *crtc_state)
3813{
3814	intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3815	intel_ddi_get_config(encoder, crtc_state);
3816}
3817
3818static void dg1_ddi_get_config(struct intel_encoder *encoder,
3819			       struct intel_crtc_state *crtc_state)
3820{
3821	intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3822	intel_ddi_get_config(encoder, crtc_state);
3823}
3824
3825static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3826				     struct intel_crtc_state *crtc_state)
3827{
3828	intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3829	intel_ddi_get_config(encoder, crtc_state);
3830}
3831
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3832static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3833				 struct intel_crtc_state *crtc_state,
3834				 struct intel_shared_dpll *pll)
3835{
3836	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3837	enum icl_port_dpll_id port_dpll_id;
3838	struct icl_port_dpll *port_dpll;
3839	bool pll_active;
3840
3841	if (drm_WARN_ON(&i915->drm, !pll))
3842		return;
3843
3844	if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3845		port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3846	else
3847		port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3848
3849	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3850
3851	port_dpll->pll = pll;
3852	pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3853	drm_WARN_ON(&i915->drm, !pll_active);
3854
3855	icl_set_active_port_dpll(crtc_state, port_dpll_id);
3856
3857	if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3858		crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3859	else
3860		crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3861							     &crtc_state->dpll_hw_state);
3862}
3863
3864static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3865				  struct intel_crtc_state *crtc_state)
3866{
3867	icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3868	intel_ddi_get_config(encoder, crtc_state);
3869}
3870
3871static void cnl_ddi_get_config(struct intel_encoder *encoder,
3872			       struct intel_crtc_state *crtc_state)
3873{
3874	intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
3875	intel_ddi_get_config(encoder, crtc_state);
3876}
3877
3878static void bxt_ddi_get_config(struct intel_encoder *encoder,
3879			       struct intel_crtc_state *crtc_state)
3880{
3881	intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3882	intel_ddi_get_config(encoder, crtc_state);
3883}
3884
3885static void skl_ddi_get_config(struct intel_encoder *encoder,
3886			       struct intel_crtc_state *crtc_state)
3887{
3888	intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3889	intel_ddi_get_config(encoder, crtc_state);
3890}
3891
3892void hsw_ddi_get_config(struct intel_encoder *encoder,
3893			struct intel_crtc_state *crtc_state)
3894{
3895	intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3896	intel_ddi_get_config(encoder, crtc_state);
3897}
3898
3899static void intel_ddi_sync_state(struct intel_encoder *encoder,
3900				 const struct intel_crtc_state *crtc_state)
3901{
3902	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3903	enum phy phy = intel_port_to_phy(i915, encoder->port);
3904
3905	if (intel_phy_is_tc(i915, phy))
3906		intel_tc_port_sanitize(enc_to_dig_port(encoder));
 
3907
3908	if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
3909		intel_dp_sync_state(encoder, crtc_state);
3910}
3911
3912static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3913					    struct intel_crtc_state *crtc_state)
3914{
3915	if (intel_crtc_has_dp_encoder(crtc_state))
3916		return intel_dp_initial_fastset_check(encoder, crtc_state);
 
3917
3918	return true;
 
 
 
 
 
 
 
 
 
 
 
3919}
3920
3921static enum intel_output_type
3922intel_ddi_compute_output_type(struct intel_encoder *encoder,
3923			      struct intel_crtc_state *crtc_state,
3924			      struct drm_connector_state *conn_state)
3925{
3926	switch (conn_state->connector->connector_type) {
3927	case DRM_MODE_CONNECTOR_HDMIA:
3928		return INTEL_OUTPUT_HDMI;
3929	case DRM_MODE_CONNECTOR_eDP:
3930		return INTEL_OUTPUT_EDP;
3931	case DRM_MODE_CONNECTOR_DisplayPort:
3932		return INTEL_OUTPUT_DP;
3933	default:
3934		MISSING_CASE(conn_state->connector->connector_type);
3935		return INTEL_OUTPUT_UNUSED;
3936	}
3937}
3938
3939static int intel_ddi_compute_config(struct intel_encoder *encoder,
3940				    struct intel_crtc_state *pipe_config,
3941				    struct drm_connector_state *conn_state)
3942{
3943	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3944	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3945	enum port port = encoder->port;
3946	int ret;
3947
3948	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3949		pipe_config->cpu_transcoder = TRANSCODER_EDP;
3950
3951	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
 
 
 
3952		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3953	} else {
3954		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3955	}
3956
3957	if (ret)
3958		return ret;
3959
3960	if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3961	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
3962		pipe_config->pch_pfit.force_thru =
3963			pipe_config->pch_pfit.enabled ||
3964			pipe_config->crc_enabled;
3965
3966	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3967		pipe_config->lane_lat_optim_mask =
3968			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3969
3970	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3971
3972	return 0;
3973}
3974
3975static bool mode_equal(const struct drm_display_mode *mode1,
3976		       const struct drm_display_mode *mode2)
3977{
3978	return drm_mode_match(mode1, mode2,
3979			      DRM_MODE_MATCH_TIMINGS |
3980			      DRM_MODE_MATCH_FLAGS |
3981			      DRM_MODE_MATCH_3D_FLAGS) &&
3982		mode1->clock == mode2->clock; /* we want an exact match */
3983}
3984
3985static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3986		      const struct intel_link_m_n *m_n_2)
3987{
3988	return m_n_1->tu == m_n_2->tu &&
3989		m_n_1->gmch_m == m_n_2->gmch_m &&
3990		m_n_1->gmch_n == m_n_2->gmch_n &&
3991		m_n_1->link_m == m_n_2->link_m &&
3992		m_n_1->link_n == m_n_2->link_n;
3993}
3994
3995static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3996				       const struct intel_crtc_state *crtc_state2)
3997{
 
 
 
 
3998	return crtc_state1->hw.active && crtc_state2->hw.active &&
 
3999		crtc_state1->output_types == crtc_state2->output_types &&
4000		crtc_state1->output_format == crtc_state2->output_format &&
4001		crtc_state1->lane_count == crtc_state2->lane_count &&
4002		crtc_state1->port_clock == crtc_state2->port_clock &&
4003		mode_equal(&crtc_state1->hw.adjusted_mode,
4004			   &crtc_state2->hw.adjusted_mode) &&
4005		m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4006}
4007
4008static u8
4009intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4010				int tile_group_id)
4011{
4012	struct drm_connector *connector;
4013	const struct drm_connector_state *conn_state;
4014	struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4015	struct intel_atomic_state *state =
4016		to_intel_atomic_state(ref_crtc_state->uapi.state);
4017	u8 transcoders = 0;
4018	int i;
4019
4020	/*
4021	 * We don't enable port sync on BDW due to missing w/as and
4022	 * due to not having adjusted the modeset sequence appropriately.
4023	 */
4024	if (DISPLAY_VER(dev_priv) < 9)
4025		return 0;
4026
4027	if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4028		return 0;
4029
4030	for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4031		struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4032		const struct intel_crtc_state *crtc_state;
4033
4034		if (!crtc)
4035			continue;
4036
4037		if (!connector->has_tile ||
4038		    connector->tile_group->id !=
4039		    tile_group_id)
4040			continue;
4041		crtc_state = intel_atomic_get_new_crtc_state(state,
4042							     crtc);
4043		if (!crtcs_port_sync_compatible(ref_crtc_state,
4044						crtc_state))
4045			continue;
4046		transcoders |= BIT(crtc_state->cpu_transcoder);
4047	}
4048
4049	return transcoders;
4050}
4051
4052static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4053					 struct intel_crtc_state *crtc_state,
4054					 struct drm_connector_state *conn_state)
4055{
4056	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4057	struct drm_connector *connector = conn_state->connector;
4058	u8 port_sync_transcoders = 0;
4059
4060	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4061		    encoder->base.base.id, encoder->base.name,
4062		    crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4063
4064	if (connector->has_tile)
4065		port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4066									connector->tile_group->id);
4067
4068	/*
4069	 * EDP Transcoders cannot be ensalved
4070	 * make them a master always when present
4071	 */
4072	if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4073		crtc_state->master_transcoder = TRANSCODER_EDP;
4074	else
4075		crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4076
4077	if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4078		crtc_state->master_transcoder = INVALID_TRANSCODER;
4079		crtc_state->sync_mode_slaves_mask =
4080			port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4081	}
4082
4083	return 0;
4084}
4085
4086static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4087{
4088	struct drm_i915_private *i915 = to_i915(encoder->dev);
4089	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
 
4090
4091	intel_dp_encoder_flush_work(encoder);
 
 
4092	intel_display_power_flush_work(i915);
4093
4094	drm_encoder_cleanup(encoder);
4095	if (dig_port)
4096		kfree(dig_port->hdcp_port_data.streams);
4097	kfree(dig_port);
4098}
4099
4100static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4101{
 
4102	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
 
 
4103
4104	intel_dp->reset_link_params = true;
4105
4106	intel_pps_encoder_reset(intel_dp);
 
 
 
 
 
 
 
 
 
 
 
 
4107}
4108
4109static const struct drm_encoder_funcs intel_ddi_funcs = {
4110	.reset = intel_ddi_encoder_reset,
4111	.destroy = intel_ddi_encoder_destroy,
 
4112};
4113
4114static struct intel_connector *
4115intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4116{
4117	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4118	struct intel_connector *connector;
4119	enum port port = dig_port->base.port;
4120
4121	connector = intel_connector_alloc();
4122	if (!connector)
4123		return NULL;
4124
4125	dig_port->dp.output_reg = DDI_BUF_CTL(port);
4126	dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
 
 
 
4127	dig_port->dp.set_link_train = intel_ddi_set_link_train;
4128	dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4129
4130	if (DISPLAY_VER(dev_priv) >= 12)
4131		dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4132	else if (DISPLAY_VER(dev_priv) >= 11)
4133		dig_port->dp.set_signal_levels = icl_set_signal_levels;
4134	else if (IS_CANNONLAKE(dev_priv))
4135		dig_port->dp.set_signal_levels = cnl_set_signal_levels;
4136	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4137		dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4138	else
4139		dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4140
4141	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4142	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4143
4144	if (!intel_dp_init_connector(dig_port, connector)) {
4145		kfree(connector);
4146		return NULL;
4147	}
4148
 
 
 
 
 
 
 
 
 
 
 
 
 
4149	return connector;
4150}
4151
4152static int modeset_pipe(struct drm_crtc *crtc,
4153			struct drm_modeset_acquire_ctx *ctx)
4154{
4155	struct drm_atomic_state *state;
4156	struct drm_crtc_state *crtc_state;
4157	int ret;
4158
4159	state = drm_atomic_state_alloc(crtc->dev);
4160	if (!state)
4161		return -ENOMEM;
4162
4163	state->acquire_ctx = ctx;
 
4164
4165	crtc_state = drm_atomic_get_crtc_state(state, crtc);
4166	if (IS_ERR(crtc_state)) {
4167		ret = PTR_ERR(crtc_state);
4168		goto out;
4169	}
4170
4171	crtc_state->connectors_changed = true;
4172
4173	ret = drm_atomic_commit(state);
4174out:
4175	drm_atomic_state_put(state);
4176
4177	return ret;
4178}
4179
4180static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4181				 struct drm_modeset_acquire_ctx *ctx)
4182{
4183	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4184	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4185	struct intel_connector *connector = hdmi->attached_connector;
4186	struct i2c_adapter *adapter =
4187		intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4188	struct drm_connector_state *conn_state;
4189	struct intel_crtc_state *crtc_state;
4190	struct intel_crtc *crtc;
4191	u8 config;
4192	int ret;
4193
4194	if (!connector || connector->base.status != connector_status_connected)
4195		return 0;
4196
4197	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4198			       ctx);
4199	if (ret)
4200		return ret;
4201
4202	conn_state = connector->base.state;
4203
4204	crtc = to_intel_crtc(conn_state->crtc);
4205	if (!crtc)
4206		return 0;
4207
4208	ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4209	if (ret)
4210		return ret;
4211
4212	crtc_state = to_intel_crtc_state(crtc->base.state);
4213
4214	drm_WARN_ON(&dev_priv->drm,
4215		    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4216
4217	if (!crtc_state->hw.active)
4218		return 0;
4219
4220	if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4221	    !crtc_state->hdmi_scrambling)
4222		return 0;
4223
4224	if (conn_state->commit &&
4225	    !try_wait_for_completion(&conn_state->commit->hw_done))
4226		return 0;
4227
4228	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4229	if (ret < 0) {
4230		drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4231			ret);
4232		return 0;
4233	}
4234
4235	if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4236	    crtc_state->hdmi_high_tmds_clock_ratio &&
4237	    !!(config & SCDC_SCRAMBLING_ENABLE) ==
4238	    crtc_state->hdmi_scrambling)
4239		return 0;
4240
4241	/*
4242	 * HDMI 2.0 says that one should not send scrambled data
4243	 * prior to configuring the sink scrambling, and that
4244	 * TMDS clock/data transmission should be suspended when
4245	 * changing the TMDS clock rate in the sink. So let's
4246	 * just do a full modeset here, even though some sinks
4247	 * would be perfectly happy if were to just reconfigure
4248	 * the SCDC settings on the fly.
4249	 */
4250	return modeset_pipe(&crtc->base, ctx);
4251}
4252
4253static enum intel_hotplug_state
4254intel_ddi_hotplug(struct intel_encoder *encoder,
4255		  struct intel_connector *connector)
4256{
4257	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4258	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4259	struct intel_dp *intel_dp = &dig_port->dp;
4260	enum phy phy = intel_port_to_phy(i915, encoder->port);
4261	bool is_tc = intel_phy_is_tc(i915, phy);
4262	struct drm_modeset_acquire_ctx ctx;
4263	enum intel_hotplug_state state;
4264	int ret;
4265
4266	if (intel_dp->compliance.test_active &&
4267	    intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4268		intel_dp_phy_test(encoder);
4269		/* just do the PHY test and nothing else */
4270		return INTEL_HOTPLUG_UNCHANGED;
4271	}
4272
4273	state = intel_encoder_hotplug(encoder, connector);
4274
4275	drm_modeset_acquire_init(&ctx, 0);
4276
4277	for (;;) {
4278		if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4279			ret = intel_hdmi_reset_link(encoder, &ctx);
4280		else
4281			ret = intel_dp_retrain_link(encoder, &ctx);
4282
4283		if (ret == -EDEADLK) {
4284			drm_modeset_backoff(&ctx);
4285			continue;
4286		}
4287
4288		break;
4289	}
4290
4291	drm_modeset_drop_locks(&ctx);
4292	drm_modeset_acquire_fini(&ctx);
4293	drm_WARN(encoder->base.dev, ret,
4294		 "Acquiring modeset locks failed with %i\n", ret);
4295
4296	/*
4297	 * Unpowered type-c dongles can take some time to boot and be
4298	 * responsible, so here giving some time to those dongles to power up
4299	 * and then retrying the probe.
4300	 *
4301	 * On many platforms the HDMI live state signal is known to be
4302	 * unreliable, so we can't use it to detect if a sink is connected or
4303	 * not. Instead we detect if it's connected based on whether we can
4304	 * read the EDID or not. That in turn has a problem during disconnect,
4305	 * since the HPD interrupt may be raised before the DDC lines get
4306	 * disconnected (due to how the required length of DDC vs. HPD
4307	 * connector pins are specified) and so we'll still be able to get a
4308	 * valid EDID. To solve this schedule another detection cycle if this
4309	 * time around we didn't detect any change in the sink's connection
4310	 * status.
4311	 *
4312	 * Type-c connectors which get their HPD signal deasserted then
4313	 * reasserted, without unplugging/replugging the sink from the
4314	 * connector, introduce a delay until the AUX channel communication
4315	 * becomes functional. Retry the detection for 5 seconds on type-c
4316	 * connectors to account for this delay.
4317	 */
4318	if (state == INTEL_HOTPLUG_UNCHANGED &&
4319	    connector->hotplug_retries < (is_tc ? 5 : 1) &&
4320	    !dig_port->dp.is_mst)
4321		state = INTEL_HOTPLUG_RETRY;
4322
4323	return state;
4324}
4325
4326static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4327{
4328	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4329	u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4330
4331	return intel_de_read(dev_priv, SDEISR) & bit;
4332}
4333
4334static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4335{
4336	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4337	u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4338
4339	return intel_de_read(dev_priv, DEISR) & bit;
4340}
4341
4342static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4343{
4344	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4345	u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4346
4347	return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4348}
4349
4350static struct intel_connector *
4351intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4352{
4353	struct intel_connector *connector;
4354	enum port port = dig_port->base.port;
4355
4356	connector = intel_connector_alloc();
4357	if (!connector)
4358		return NULL;
4359
4360	dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4361	intel_hdmi_init_connector(dig_port, connector);
4362
4363	return connector;
4364}
4365
4366static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4367{
4368	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4369
4370	if (dig_port->base.port != PORT_A)
4371		return false;
4372
4373	if (dig_port->saved_port_bits & DDI_A_4_LANES)
4374		return false;
4375
4376	/* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4377	 *                     supported configuration
4378	 */
4379	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4380		return true;
4381
4382	/* Cannonlake: Most of SKUs don't support DDI_E, and the only
4383	 *             one who does also have a full A/E split called
4384	 *             DDI_F what makes DDI_E useless. However for this
4385	 *             case let's trust VBT info.
4386	 */
4387	if (IS_CANNONLAKE(dev_priv) &&
4388	    !intel_bios_is_port_present(dev_priv, PORT_E))
4389		return true;
4390
4391	return false;
4392}
4393
4394static int
4395intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4396{
4397	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4398	enum port port = dig_port->base.port;
4399	int max_lanes = 4;
4400
4401	if (DISPLAY_VER(dev_priv) >= 11)
4402		return max_lanes;
4403
4404	if (port == PORT_A || port == PORT_E) {
4405		if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4406			max_lanes = port == PORT_A ? 4 : 0;
4407		else
4408			/* Both A and E share 2 lanes */
4409			max_lanes = 2;
4410	}
4411
4412	/*
4413	 * Some BIOS might fail to set this bit on port A if eDP
4414	 * wasn't lit up at boot.  Force this bit set when needed
4415	 * so we use the proper lane count for our calculations.
4416	 */
4417	if (intel_ddi_a_force_4_lanes(dig_port)) {
4418		drm_dbg_kms(&dev_priv->drm,
4419			    "Forcing DDI_A_4_LANES for port A\n");
4420		dig_port->saved_port_bits |= DDI_A_4_LANES;
4421		max_lanes = 4;
4422	}
4423
4424	return max_lanes;
4425}
4426
4427static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4428{
4429	return i915->hti_state & HDPORT_ENABLED &&
4430	       i915->hti_state & HDPORT_DDI_USED(phy);
4431}
4432
4433static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4434				  enum port port)
4435{
4436	if (port >= PORT_D_XELPD)
4437		return HPD_PORT_D + port - PORT_D_XELPD;
4438	else if (port >= PORT_TC1)
4439		return HPD_PORT_TC1 + port - PORT_TC1;
4440	else
4441		return HPD_PORT_A + port - PORT_A;
4442}
4443
4444static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4445				enum port port)
4446{
4447	if (port >= PORT_TC1)
4448		return HPD_PORT_C + port - PORT_TC1;
4449	else
4450		return HPD_PORT_A + port - PORT_A;
4451}
4452
4453static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4454				enum port port)
4455{
4456	if (port >= PORT_TC1)
4457		return HPD_PORT_TC1 + port - PORT_TC1;
4458	else
4459		return HPD_PORT_A + port - PORT_A;
4460}
4461
4462static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4463				enum port port)
4464{
4465	if (HAS_PCH_TGP(dev_priv))
4466		return tgl_hpd_pin(dev_priv, port);
4467
4468	if (port >= PORT_TC1)
4469		return HPD_PORT_C + port - PORT_TC1;
4470	else
4471		return HPD_PORT_A + port - PORT_A;
4472}
4473
4474static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4475				enum port port)
4476{
4477	if (port >= PORT_C)
4478		return HPD_PORT_TC1 + port - PORT_C;
4479	else
4480		return HPD_PORT_A + port - PORT_A;
4481}
4482
4483static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4484				enum port port)
4485{
4486	if (port == PORT_D)
4487		return HPD_PORT_A;
4488
4489	if (HAS_PCH_MCC(dev_priv))
4490		return icl_hpd_pin(dev_priv, port);
4491
4492	return HPD_PORT_A + port - PORT_A;
4493}
4494
4495static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
4496				enum port port)
4497{
4498	if (port == PORT_F)
4499		return HPD_PORT_E;
4500
4501	return HPD_PORT_A + port - PORT_A;
4502}
4503
4504static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4505{
4506	if (HAS_PCH_TGP(dev_priv))
4507		return icl_hpd_pin(dev_priv, port);
4508
4509	return HPD_PORT_A + port - PORT_A;
4510}
4511
4512static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4513{
4514	if (DISPLAY_VER(i915) >= 12)
4515		return port >= PORT_TC1;
4516	else if (DISPLAY_VER(i915) >= 11)
4517		return port >= PORT_C;
4518	else
4519		return false;
4520}
4521
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4522#define port_tc_name(port) ((port) - PORT_TC1 + '1')
4523#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4524
4525void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4526{
4527	struct intel_digital_port *dig_port;
4528	struct intel_encoder *encoder;
4529	const struct intel_bios_encoder_data *devdata;
4530	bool init_hdmi, init_dp;
4531	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4532
4533	/*
4534	 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4535	 * have taken over some of the PHYs and made them unavailable to the
4536	 * driver.  In that case we should skip initializing the corresponding
4537	 * outputs.
4538	 */
4539	if (hti_uses_phy(dev_priv, phy)) {
4540		drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4541			    port_name(port), phy_name(phy));
4542		return;
4543	}
4544
4545	devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4546	if (!devdata) {
4547		drm_dbg_kms(&dev_priv->drm,
4548			    "VBT says port %c is not present\n",
4549			    port_name(port));
4550		return;
4551	}
4552
4553	init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4554		intel_bios_encoder_supports_hdmi(devdata);
4555	init_dp = intel_bios_encoder_supports_dp(devdata);
4556
4557	if (intel_bios_is_lspcon_present(dev_priv, port)) {
4558		/*
4559		 * Lspcon device needs to be driven with DP connector
4560		 * with special detection sequence. So make sure DP
4561		 * is initialized before lspcon.
4562		 */
4563		init_dp = true;
4564		init_hdmi = false;
4565		drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4566			    port_name(port));
4567	}
4568
4569	if (!init_dp && !init_hdmi) {
4570		drm_dbg_kms(&dev_priv->drm,
4571			    "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4572			    port_name(port));
4573		return;
4574	}
4575
 
 
 
 
 
 
 
4576	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4577	if (!dig_port)
4578		return;
4579
 
 
4580	encoder = &dig_port->base;
4581	encoder->devdata = devdata;
4582
4583	if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4584		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4585				 DRM_MODE_ENCODER_TMDS,
4586				 "DDI %c/PHY %c",
4587				 port_name(port - PORT_D_XELPD + PORT_D),
4588				 phy_name(phy));
4589	} else if (DISPLAY_VER(dev_priv) >= 12) {
4590		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4591
4592		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4593				 DRM_MODE_ENCODER_TMDS,
4594				 "DDI %s%c/PHY %s%c",
4595				 port >= PORT_TC1 ? "TC" : "",
4596				 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4597				 tc_port != TC_PORT_NONE ? "TC" : "",
4598				 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4599	} else if (DISPLAY_VER(dev_priv) >= 11) {
4600		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4601
4602		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4603				 DRM_MODE_ENCODER_TMDS,
4604				 "DDI %c%s/PHY %s%c",
4605				 port_name(port),
4606				 port >= PORT_C ? " (TC)" : "",
4607				 tc_port != TC_PORT_NONE ? "TC" : "",
4608				 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4609	} else {
4610		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4611				 DRM_MODE_ENCODER_TMDS,
4612				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4613	}
4614
4615	mutex_init(&dig_port->hdcp_mutex);
4616	dig_port->num_hdcp_streams = 0;
4617
4618	encoder->hotplug = intel_ddi_hotplug;
4619	encoder->compute_output_type = intel_ddi_compute_output_type;
4620	encoder->compute_config = intel_ddi_compute_config;
4621	encoder->compute_config_late = intel_ddi_compute_config_late;
4622	encoder->enable = intel_enable_ddi;
4623	encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4624	encoder->pre_enable = intel_ddi_pre_enable;
4625	encoder->disable = intel_disable_ddi;
 
4626	encoder->post_disable = intel_ddi_post_disable;
4627	encoder->update_pipe = intel_ddi_update_pipe;
 
 
4628	encoder->get_hw_state = intel_ddi_get_hw_state;
4629	encoder->sync_state = intel_ddi_sync_state;
4630	encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4631	encoder->suspend = intel_dp_encoder_suspend;
4632	encoder->shutdown = intel_dp_encoder_shutdown;
4633	encoder->get_power_domains = intel_ddi_get_power_domains;
4634
4635	encoder->type = INTEL_OUTPUT_DDI;
4636	encoder->power_domain = intel_port_to_power_domain(port);
4637	encoder->port = port;
4638	encoder->cloneable = 0;
4639	encoder->pipe_mask = ~0;
4640
4641	if (IS_ALDERLAKE_S(dev_priv)) {
 
 
 
 
 
 
 
 
 
4642		encoder->enable_clock = adls_ddi_enable_clock;
4643		encoder->disable_clock = adls_ddi_disable_clock;
4644		encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4645		encoder->get_config = adls_ddi_get_config;
4646	} else if (IS_ROCKETLAKE(dev_priv)) {
4647		encoder->enable_clock = rkl_ddi_enable_clock;
4648		encoder->disable_clock = rkl_ddi_disable_clock;
4649		encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4650		encoder->get_config = rkl_ddi_get_config;
4651	} else if (IS_DG1(dev_priv)) {
4652		encoder->enable_clock = dg1_ddi_enable_clock;
4653		encoder->disable_clock = dg1_ddi_disable_clock;
4654		encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4655		encoder->get_config = dg1_ddi_get_config;
4656	} else if (IS_JSL_EHL(dev_priv)) {
4657		if (intel_ddi_is_tc(dev_priv, port)) {
4658			encoder->enable_clock = jsl_ddi_tc_enable_clock;
4659			encoder->disable_clock = jsl_ddi_tc_disable_clock;
4660			encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
 
4661			encoder->get_config = icl_ddi_combo_get_config;
4662		} else {
4663			encoder->enable_clock = icl_ddi_combo_enable_clock;
4664			encoder->disable_clock = icl_ddi_combo_disable_clock;
4665			encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4666			encoder->get_config = icl_ddi_combo_get_config;
4667		}
4668	} else if (DISPLAY_VER(dev_priv) >= 11) {
4669		if (intel_ddi_is_tc(dev_priv, port)) {
4670			encoder->enable_clock = icl_ddi_tc_enable_clock;
4671			encoder->disable_clock = icl_ddi_tc_disable_clock;
4672			encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
 
4673			encoder->get_config = icl_ddi_tc_get_config;
4674		} else {
4675			encoder->enable_clock = icl_ddi_combo_enable_clock;
4676			encoder->disable_clock = icl_ddi_combo_disable_clock;
4677			encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4678			encoder->get_config = icl_ddi_combo_get_config;
4679		}
4680	} else if (IS_CANNONLAKE(dev_priv)) {
4681		encoder->enable_clock = cnl_ddi_enable_clock;
4682		encoder->disable_clock = cnl_ddi_disable_clock;
4683		encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
4684		encoder->get_config = cnl_ddi_get_config;
4685	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4686		/* BXT/GLK have fixed PLL->port mapping */
4687		encoder->get_config = bxt_ddi_get_config;
4688	} else if (DISPLAY_VER(dev_priv) == 9) {
4689		encoder->enable_clock = skl_ddi_enable_clock;
4690		encoder->disable_clock = skl_ddi_disable_clock;
4691		encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4692		encoder->get_config = skl_ddi_get_config;
4693	} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4694		encoder->enable_clock = hsw_ddi_enable_clock;
4695		encoder->disable_clock = hsw_ddi_disable_clock;
4696		encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4697		encoder->get_config = hsw_ddi_get_config;
4698	}
4699
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4700	if (DISPLAY_VER(dev_priv) >= 13)
4701		encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4702	else if (IS_DG1(dev_priv))
4703		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4704	else if (IS_ROCKETLAKE(dev_priv))
4705		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4706	else if (DISPLAY_VER(dev_priv) >= 12)
4707		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4708	else if (IS_JSL_EHL(dev_priv))
4709		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4710	else if (DISPLAY_VER(dev_priv) == 11)
4711		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4712	else if (IS_CANNONLAKE(dev_priv))
4713		encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
4714	else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4715		encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4716	else
4717		encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4718
4719	if (DISPLAY_VER(dev_priv) >= 11)
4720		dig_port->saved_port_bits =
4721			intel_de_read(dev_priv, DDI_BUF_CTL(port))
4722			& DDI_BUF_PORT_REVERSAL;
4723	else
4724		dig_port->saved_port_bits =
4725			intel_de_read(dev_priv, DDI_BUF_CTL(port))
4726			& (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4727
4728	if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4729		dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4730
4731	dig_port->dp.output_reg = INVALID_MMIO_REG;
4732	dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4733	dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 
 
 
 
 
4734
4735	if (intel_phy_is_tc(dev_priv, phy)) {
4736		bool is_legacy =
4737			!intel_bios_encoder_supports_typec_usb(devdata) &&
4738			!intel_bios_encoder_supports_tbt(devdata);
4739
4740		intel_tc_port_init(dig_port, is_legacy);
4741
4742		encoder->update_prepare = intel_ddi_update_prepare;
4743		encoder->update_complete = intel_ddi_update_complete;
4744	}
4745
4746	drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4747	dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4748					      port - PORT_A;
4749
4750	if (init_dp) {
4751		if (!intel_ddi_init_dp_connector(dig_port))
4752			goto err;
 
 
 
4753
4754		dig_port->hpd_pulse = intel_dp_hpd_pulse;
 
4755
4756		if (dig_port->dp.mso_link_count)
4757			encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4758	}
4759
4760	/* In theory we don't need the encoder->type check, but leave it just in
4761	 * case we have some really bad VBTs... */
4762	if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4763		if (!intel_ddi_init_hdmi_connector(dig_port))
4764			goto err;
4765	}
4766
 
 
 
4767	if (DISPLAY_VER(dev_priv) >= 11) {
4768		if (intel_phy_is_tc(dev_priv, phy))
4769			dig_port->connected = intel_tc_port_connected;
4770		else
4771			dig_port->connected = lpt_digital_port_connected;
4772	} else if (DISPLAY_VER(dev_priv) >= 8) {
4773		if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4774		    IS_BROXTON(dev_priv))
 
 
 
4775			dig_port->connected = bdw_digital_port_connected;
4776		else
4777			dig_port->connected = lpt_digital_port_connected;
4778	} else {
4779		if (port == PORT_A)
4780			dig_port->connected = hsw_digital_port_connected;
4781		else
4782			dig_port->connected = lpt_digital_port_connected;
4783	}
4784
4785	intel_infoframe_init(dig_port);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4786
4787	return;
4788
4789err:
4790	drm_encoder_cleanup(&encoder->base);
4791	kfree(dig_port);
4792}