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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
5 *
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 *
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
10 *
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
16 *
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
20 *
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
24 */
25
26#undef DEBUG
27#undef DEBUG_HARD
28#undef USE_CTRL_O_SYSRQ
29
30#include <linux/module.h>
31#include <linux/tty.h>
32
33#include <linux/tty_flip.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/fcntl.h>
37#include <linux/mm.h>
38#include <linux/kernel.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41#include <linux/console.h>
42#include <linux/adb.h>
43#include <linux/pmu.h>
44#include <linux/bitops.h>
45#include <linux/sysrq.h>
46#include <linux/mutex.h>
47#include <linux/of_address.h>
48#include <linux/of_irq.h>
49#include <asm/sections.h>
50#include <linux/io.h>
51#include <asm/irq.h>
52
53#ifdef CONFIG_PPC_PMAC
54#include <asm/prom.h>
55#include <asm/machdep.h>
56#include <asm/pmac_feature.h>
57#include <asm/dbdma.h>
58#include <asm/macio.h>
59#else
60#include <linux/platform_device.h>
61#define of_machine_is_compatible(x) (0)
62#endif
63
64#include <linux/serial.h>
65#include <linux/serial_core.h>
66
67#include "pmac_zilog.h"
68
69/* Not yet implemented */
70#undef HAS_DBDMA
71
72static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
73MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
74MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
75MODULE_LICENSE("GPL");
76
77#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
78#define PMACZILOG_MAJOR TTY_MAJOR
79#define PMACZILOG_MINOR 64
80#define PMACZILOG_NAME "ttyS"
81#else
82#define PMACZILOG_MAJOR 204
83#define PMACZILOG_MINOR 192
84#define PMACZILOG_NAME "ttyPZ"
85#endif
86
87#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
88#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
89#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
90
91/*
92 * For the sake of early serial console, we can do a pre-probe
93 * (optional) of the ports at rather early boot time.
94 */
95static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
96static int pmz_ports_count;
97
98static struct uart_driver pmz_uart_reg = {
99 .owner = THIS_MODULE,
100 .driver_name = PMACZILOG_NAME,
101 .dev_name = PMACZILOG_NAME,
102 .major = PMACZILOG_MAJOR,
103 .minor = PMACZILOG_MINOR,
104};
105
106
107/*
108 * Load all registers to reprogram the port
109 * This function must only be called when the TX is not busy. The UART
110 * port lock must be held and local interrupts disabled.
111 */
112static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
113{
114 int i;
115
116 /* Let pending transmits finish. */
117 for (i = 0; i < 1000; i++) {
118 unsigned char stat = read_zsreg(uap, R1);
119 if (stat & ALL_SNT)
120 break;
121 udelay(100);
122 }
123
124 ZS_CLEARERR(uap);
125 zssync(uap);
126 ZS_CLEARFIFO(uap);
127 zssync(uap);
128 ZS_CLEARERR(uap);
129
130 /* Disable all interrupts. */
131 write_zsreg(uap, R1,
132 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
133
134 /* Set parity, sync config, stop bits, and clock divisor. */
135 write_zsreg(uap, R4, regs[R4]);
136
137 /* Set misc. TX/RX control bits. */
138 write_zsreg(uap, R10, regs[R10]);
139
140 /* Set TX/RX controls sans the enable bits. */
141 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
142 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
143
144 /* now set R7 "prime" on ESCC */
145 write_zsreg(uap, R15, regs[R15] | EN85C30);
146 write_zsreg(uap, R7, regs[R7P]);
147
148 /* make sure we use R7 "non-prime" on ESCC */
149 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
150
151 /* Synchronous mode config. */
152 write_zsreg(uap, R6, regs[R6]);
153 write_zsreg(uap, R7, regs[R7]);
154
155 /* Disable baud generator. */
156 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
157
158 /* Clock mode control. */
159 write_zsreg(uap, R11, regs[R11]);
160
161 /* Lower and upper byte of baud rate generator divisor. */
162 write_zsreg(uap, R12, regs[R12]);
163 write_zsreg(uap, R13, regs[R13]);
164
165 /* Now rewrite R14, with BRENAB (if set). */
166 write_zsreg(uap, R14, regs[R14]);
167
168 /* Reset external status interrupts. */
169 write_zsreg(uap, R0, RES_EXT_INT);
170 write_zsreg(uap, R0, RES_EXT_INT);
171
172 /* Rewrite R3/R5, this time without enables masked. */
173 write_zsreg(uap, R3, regs[R3]);
174 write_zsreg(uap, R5, regs[R5]);
175
176 /* Rewrite R1, this time without IRQ enabled masked. */
177 write_zsreg(uap, R1, regs[R1]);
178
179 /* Enable interrupts */
180 write_zsreg(uap, R9, regs[R9]);
181}
182
183/*
184 * We do like sunzilog to avoid disrupting pending Tx
185 * Reprogram the Zilog channel HW registers with the copies found in the
186 * software state struct. If the transmitter is busy, we defer this update
187 * until the next TX complete interrupt. Else, we do it right now.
188 *
189 * The UART port lock must be held and local interrupts disabled.
190 */
191static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
192{
193 if (!ZS_REGS_HELD(uap)) {
194 if (ZS_TX_ACTIVE(uap)) {
195 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
196 } else {
197 pmz_debug("pmz: maybe_update_regs: updating\n");
198 pmz_load_zsregs(uap, uap->curregs);
199 }
200 }
201}
202
203static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
204{
205 if (enable) {
206 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
207 if (!ZS_IS_EXTCLK(uap))
208 uap->curregs[1] |= EXT_INT_ENAB;
209 } else {
210 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
211 }
212 write_zsreg(uap, R1, uap->curregs[1]);
213}
214
215static bool pmz_receive_chars(struct uart_pmac_port *uap)
216 __must_hold(&uap->port.lock)
217{
218 struct tty_port *port;
219 unsigned char ch, r1, drop, flag;
220 int loops = 0;
221
222 /* Sanity check, make sure the old bug is no longer happening */
223 if (uap->port.state == NULL) {
224 WARN_ON(1);
225 (void)read_zsdata(uap);
226 return false;
227 }
228 port = &uap->port.state->port;
229
230 while (1) {
231 drop = 0;
232
233 r1 = read_zsreg(uap, R1);
234 ch = read_zsdata(uap);
235
236 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
237 write_zsreg(uap, R0, ERR_RES);
238 zssync(uap);
239 }
240
241 ch &= uap->parity_mask;
242 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
243 uap->flags &= ~PMACZILOG_FLAG_BREAK;
244 }
245
246#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
247#ifdef USE_CTRL_O_SYSRQ
248 /* Handle the SysRq ^O Hack */
249 if (ch == '\x0f') {
250 uap->port.sysrq = jiffies + HZ*5;
251 goto next_char;
252 }
253#endif /* USE_CTRL_O_SYSRQ */
254 if (uap->port.sysrq) {
255 int swallow;
256 spin_unlock(&uap->port.lock);
257 swallow = uart_handle_sysrq_char(&uap->port, ch);
258 spin_lock(&uap->port.lock);
259 if (swallow)
260 goto next_char;
261 }
262#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
263
264 /* A real serial line, record the character and status. */
265 if (drop)
266 goto next_char;
267
268 flag = TTY_NORMAL;
269 uap->port.icount.rx++;
270
271 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
272 if (r1 & BRK_ABRT) {
273 pmz_debug("pmz: got break !\n");
274 r1 &= ~(PAR_ERR | CRC_ERR);
275 uap->port.icount.brk++;
276 if (uart_handle_break(&uap->port))
277 goto next_char;
278 }
279 else if (r1 & PAR_ERR)
280 uap->port.icount.parity++;
281 else if (r1 & CRC_ERR)
282 uap->port.icount.frame++;
283 if (r1 & Rx_OVR)
284 uap->port.icount.overrun++;
285 r1 &= uap->port.read_status_mask;
286 if (r1 & BRK_ABRT)
287 flag = TTY_BREAK;
288 else if (r1 & PAR_ERR)
289 flag = TTY_PARITY;
290 else if (r1 & CRC_ERR)
291 flag = TTY_FRAME;
292 }
293
294 if (uap->port.ignore_status_mask == 0xff ||
295 (r1 & uap->port.ignore_status_mask) == 0) {
296 tty_insert_flip_char(port, ch, flag);
297 }
298 if (r1 & Rx_OVR)
299 tty_insert_flip_char(port, 0, TTY_OVERRUN);
300 next_char:
301 /* We can get stuck in an infinite loop getting char 0 when the
302 * line is in a wrong HW state, we break that here.
303 * When that happens, I disable the receive side of the driver.
304 * Note that what I've been experiencing is a real irq loop where
305 * I'm getting flooded regardless of the actual port speed.
306 * Something strange is going on with the HW
307 */
308 if ((++loops) > 1000)
309 goto flood;
310 ch = read_zsreg(uap, R0);
311 if (!(ch & Rx_CH_AV))
312 break;
313 }
314
315 return true;
316 flood:
317 pmz_interrupt_control(uap, 0);
318 pmz_error("pmz: rx irq flood !\n");
319 return true;
320}
321
322static void pmz_status_handle(struct uart_pmac_port *uap)
323{
324 unsigned char status;
325
326 status = read_zsreg(uap, R0);
327 write_zsreg(uap, R0, RES_EXT_INT);
328 zssync(uap);
329
330 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
331 if (status & SYNC_HUNT)
332 uap->port.icount.dsr++;
333
334 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
335 * But it does not tell us which bit has changed, we have to keep
336 * track of this ourselves.
337 * The CTS input is inverted for some reason. -- paulus
338 */
339 if ((status ^ uap->prev_status) & DCD)
340 uart_handle_dcd_change(&uap->port,
341 (status & DCD));
342 if ((status ^ uap->prev_status) & CTS)
343 uart_handle_cts_change(&uap->port,
344 !(status & CTS));
345
346 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
347 }
348
349 if (status & BRK_ABRT)
350 uap->flags |= PMACZILOG_FLAG_BREAK;
351
352 uap->prev_status = status;
353}
354
355static void pmz_transmit_chars(struct uart_pmac_port *uap)
356{
357 struct circ_buf *xmit;
358
359 if (ZS_IS_CONS(uap)) {
360 unsigned char status = read_zsreg(uap, R0);
361
362 /* TX still busy? Just wait for the next TX done interrupt.
363 *
364 * It can occur because of how we do serial console writes. It would
365 * be nice to transmit console writes just like we normally would for
366 * a TTY line. (ie. buffered and TX interrupt driven). That is not
367 * easy because console writes cannot sleep. One solution might be
368 * to poll on enough port->xmit space becoming free. -DaveM
369 */
370 if (!(status & Tx_BUF_EMP))
371 return;
372 }
373
374 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
375
376 if (ZS_REGS_HELD(uap)) {
377 pmz_load_zsregs(uap, uap->curregs);
378 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
379 }
380
381 if (ZS_TX_STOPPED(uap)) {
382 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
383 goto ack_tx_int;
384 }
385
386 /* Under some circumstances, we see interrupts reported for
387 * a closed channel. The interrupt mask in R1 is clear, but
388 * R3 still signals the interrupts and we see them when taking
389 * an interrupt for the other channel (this could be a qemu
390 * bug but since the ESCC doc doesn't specify precsiely whether
391 * R3 interrup status bits are masked by R1 interrupt enable
392 * bits, better safe than sorry). --BenH.
393 */
394 if (!ZS_IS_OPEN(uap))
395 goto ack_tx_int;
396
397 if (uap->port.x_char) {
398 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
399 write_zsdata(uap, uap->port.x_char);
400 zssync(uap);
401 uap->port.icount.tx++;
402 uap->port.x_char = 0;
403 return;
404 }
405
406 if (uap->port.state == NULL)
407 goto ack_tx_int;
408 xmit = &uap->port.state->xmit;
409 if (uart_circ_empty(xmit)) {
410 uart_write_wakeup(&uap->port);
411 goto ack_tx_int;
412 }
413 if (uart_tx_stopped(&uap->port))
414 goto ack_tx_int;
415
416 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
417 write_zsdata(uap, xmit->buf[xmit->tail]);
418 zssync(uap);
419
420 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
421 uap->port.icount.tx++;
422
423 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
424 uart_write_wakeup(&uap->port);
425
426 return;
427
428ack_tx_int:
429 write_zsreg(uap, R0, RES_Tx_P);
430 zssync(uap);
431}
432
433/* Hrm... we register that twice, fixme later.... */
434static irqreturn_t pmz_interrupt(int irq, void *dev_id)
435{
436 struct uart_pmac_port *uap = dev_id;
437 struct uart_pmac_port *uap_a;
438 struct uart_pmac_port *uap_b;
439 int rc = IRQ_NONE;
440 bool push;
441 u8 r3;
442
443 uap_a = pmz_get_port_A(uap);
444 uap_b = uap_a->mate;
445
446 spin_lock(&uap_a->port.lock);
447 r3 = read_zsreg(uap_a, R3);
448
449#ifdef DEBUG_HARD
450 pmz_debug("irq, r3: %x\n", r3);
451#endif
452 /* Channel A */
453 push = false;
454 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
455 if (!ZS_IS_OPEN(uap_a)) {
456 pmz_debug("ChanA interrupt while not open !\n");
457 goto skip_a;
458 }
459 write_zsreg(uap_a, R0, RES_H_IUS);
460 zssync(uap_a);
461 if (r3 & CHAEXT)
462 pmz_status_handle(uap_a);
463 if (r3 & CHARxIP)
464 push = pmz_receive_chars(uap_a);
465 if (r3 & CHATxIP)
466 pmz_transmit_chars(uap_a);
467 rc = IRQ_HANDLED;
468 }
469 skip_a:
470 spin_unlock(&uap_a->port.lock);
471 if (push)
472 tty_flip_buffer_push(&uap->port.state->port);
473
474 if (!uap_b)
475 goto out;
476
477 spin_lock(&uap_b->port.lock);
478 push = false;
479 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
480 if (!ZS_IS_OPEN(uap_b)) {
481 pmz_debug("ChanB interrupt while not open !\n");
482 goto skip_b;
483 }
484 write_zsreg(uap_b, R0, RES_H_IUS);
485 zssync(uap_b);
486 if (r3 & CHBEXT)
487 pmz_status_handle(uap_b);
488 if (r3 & CHBRxIP)
489 push = pmz_receive_chars(uap_b);
490 if (r3 & CHBTxIP)
491 pmz_transmit_chars(uap_b);
492 rc = IRQ_HANDLED;
493 }
494 skip_b:
495 spin_unlock(&uap_b->port.lock);
496 if (push)
497 tty_flip_buffer_push(&uap->port.state->port);
498
499 out:
500 return rc;
501}
502
503/*
504 * Peek the status register, lock not held by caller
505 */
506static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
507{
508 unsigned long flags;
509 u8 status;
510
511 spin_lock_irqsave(&uap->port.lock, flags);
512 status = read_zsreg(uap, R0);
513 spin_unlock_irqrestore(&uap->port.lock, flags);
514
515 return status;
516}
517
518/*
519 * Check if transmitter is empty
520 * The port lock is not held.
521 */
522static unsigned int pmz_tx_empty(struct uart_port *port)
523{
524 unsigned char status;
525
526 status = pmz_peek_status(to_pmz(port));
527 if (status & Tx_BUF_EMP)
528 return TIOCSER_TEMT;
529 return 0;
530}
531
532/*
533 * Set Modem Control (RTS & DTR) bits
534 * The port lock is held and interrupts are disabled.
535 * Note: Shall we really filter out RTS on external ports or
536 * should that be dealt at higher level only ?
537 */
538static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
539{
540 struct uart_pmac_port *uap = to_pmz(port);
541 unsigned char set_bits, clear_bits;
542
543 /* Do nothing for irda for now... */
544 if (ZS_IS_IRDA(uap))
545 return;
546 /* We get called during boot with a port not up yet */
547 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
548 return;
549
550 set_bits = clear_bits = 0;
551
552 if (ZS_IS_INTMODEM(uap)) {
553 if (mctrl & TIOCM_RTS)
554 set_bits |= RTS;
555 else
556 clear_bits |= RTS;
557 }
558 if (mctrl & TIOCM_DTR)
559 set_bits |= DTR;
560 else
561 clear_bits |= DTR;
562
563 /* NOTE: Not subject to 'transmitter active' rule. */
564 uap->curregs[R5] |= set_bits;
565 uap->curregs[R5] &= ~clear_bits;
566
567 write_zsreg(uap, R5, uap->curregs[R5]);
568 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
569 set_bits, clear_bits, uap->curregs[R5]);
570 zssync(uap);
571}
572
573/*
574 * Get Modem Control bits (only the input ones, the core will
575 * or that with a cached value of the control ones)
576 * The port lock is held and interrupts are disabled.
577 */
578static unsigned int pmz_get_mctrl(struct uart_port *port)
579{
580 struct uart_pmac_port *uap = to_pmz(port);
581 unsigned char status;
582 unsigned int ret;
583
584 status = read_zsreg(uap, R0);
585
586 ret = 0;
587 if (status & DCD)
588 ret |= TIOCM_CAR;
589 if (status & SYNC_HUNT)
590 ret |= TIOCM_DSR;
591 if (!(status & CTS))
592 ret |= TIOCM_CTS;
593
594 return ret;
595}
596
597/*
598 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
599 * though for DMA, we will have to do a bit more.
600 * The port lock is held and interrupts are disabled.
601 */
602static void pmz_stop_tx(struct uart_port *port)
603{
604 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
605}
606
607/*
608 * Kick the Tx side.
609 * The port lock is held and interrupts are disabled.
610 */
611static void pmz_start_tx(struct uart_port *port)
612{
613 struct uart_pmac_port *uap = to_pmz(port);
614 unsigned char status;
615
616 pmz_debug("pmz: start_tx()\n");
617
618 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
619 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
620
621 status = read_zsreg(uap, R0);
622
623 /* TX busy? Just wait for the TX done interrupt. */
624 if (!(status & Tx_BUF_EMP))
625 return;
626
627 /* Send the first character to jump-start the TX done
628 * IRQ sending engine.
629 */
630 if (port->x_char) {
631 write_zsdata(uap, port->x_char);
632 zssync(uap);
633 port->icount.tx++;
634 port->x_char = 0;
635 } else {
636 struct circ_buf *xmit = &port->state->xmit;
637
638 if (uart_circ_empty(xmit))
639 goto out;
640 write_zsdata(uap, xmit->buf[xmit->tail]);
641 zssync(uap);
642 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
643 port->icount.tx++;
644
645 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
646 uart_write_wakeup(&uap->port);
647 }
648 out:
649 pmz_debug("pmz: start_tx() done.\n");
650}
651
652/*
653 * Stop Rx side, basically disable emitting of
654 * Rx interrupts on the port. We don't disable the rx
655 * side of the chip proper though
656 * The port lock is held.
657 */
658static void pmz_stop_rx(struct uart_port *port)
659{
660 struct uart_pmac_port *uap = to_pmz(port);
661
662 pmz_debug("pmz: stop_rx()()\n");
663
664 /* Disable all RX interrupts. */
665 uap->curregs[R1] &= ~RxINT_MASK;
666 pmz_maybe_update_regs(uap);
667
668 pmz_debug("pmz: stop_rx() done.\n");
669}
670
671/*
672 * Enable modem status change interrupts
673 * The port lock is held.
674 */
675static void pmz_enable_ms(struct uart_port *port)
676{
677 struct uart_pmac_port *uap = to_pmz(port);
678 unsigned char new_reg;
679
680 if (ZS_IS_IRDA(uap))
681 return;
682 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
683 if (new_reg != uap->curregs[R15]) {
684 uap->curregs[R15] = new_reg;
685
686 /* NOTE: Not subject to 'transmitter active' rule. */
687 write_zsreg(uap, R15, uap->curregs[R15]);
688 }
689}
690
691/*
692 * Control break state emission
693 * The port lock is not held.
694 */
695static void pmz_break_ctl(struct uart_port *port, int break_state)
696{
697 struct uart_pmac_port *uap = to_pmz(port);
698 unsigned char set_bits, clear_bits, new_reg;
699 unsigned long flags;
700
701 set_bits = clear_bits = 0;
702
703 if (break_state)
704 set_bits |= SND_BRK;
705 else
706 clear_bits |= SND_BRK;
707
708 spin_lock_irqsave(&port->lock, flags);
709
710 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
711 if (new_reg != uap->curregs[R5]) {
712 uap->curregs[R5] = new_reg;
713 write_zsreg(uap, R5, uap->curregs[R5]);
714 }
715
716 spin_unlock_irqrestore(&port->lock, flags);
717}
718
719#ifdef CONFIG_PPC_PMAC
720
721/*
722 * Turn power on or off to the SCC and associated stuff
723 * (port drivers, modem, IR port, etc.)
724 * Returns the number of milliseconds we should wait before
725 * trying to use the port.
726 */
727static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
728{
729 int delay = 0;
730 int rc;
731
732 if (state) {
733 rc = pmac_call_feature(
734 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
735 pmz_debug("port power on result: %d\n", rc);
736 if (ZS_IS_INTMODEM(uap)) {
737 rc = pmac_call_feature(
738 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
739 delay = 2500; /* wait for 2.5s before using */
740 pmz_debug("modem power result: %d\n", rc);
741 }
742 } else {
743 /* TODO: Make that depend on a timer, don't power down
744 * immediately
745 */
746 if (ZS_IS_INTMODEM(uap)) {
747 rc = pmac_call_feature(
748 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
749 pmz_debug("port power off result: %d\n", rc);
750 }
751 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
752 }
753 return delay;
754}
755
756#else
757
758static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
759{
760 return 0;
761}
762
763#endif /* !CONFIG_PPC_PMAC */
764
765/*
766 * FixZeroBug....Works around a bug in the SCC receiving channel.
767 * Inspired from Darwin code, 15 Sept. 2000 -DanM
768 *
769 * The following sequence prevents a problem that is seen with O'Hare ASICs
770 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
771 * at the input to the receiver becomes 'stuck' and locks up the receiver.
772 * This problem can occur as a result of a zero bit at the receiver input
773 * coincident with any of the following events:
774 *
775 * The SCC is initialized (hardware or software).
776 * A framing error is detected.
777 * The clocking option changes from synchronous or X1 asynchronous
778 * clocking to X16, X32, or X64 asynchronous clocking.
779 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
780 *
781 * This workaround attempts to recover from the lockup condition by placing
782 * the SCC in synchronous loopback mode with a fast clock before programming
783 * any of the asynchronous modes.
784 */
785static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
786{
787 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
788 zssync(uap);
789 udelay(10);
790 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
791 zssync(uap);
792
793 write_zsreg(uap, 4, X1CLK | MONSYNC);
794 write_zsreg(uap, 3, Rx8);
795 write_zsreg(uap, 5, Tx8 | RTS);
796 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
797 write_zsreg(uap, 11, RCBR | TCBR);
798 write_zsreg(uap, 12, 0);
799 write_zsreg(uap, 13, 0);
800 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
801 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
802 write_zsreg(uap, 3, Rx8 | RxENABLE);
803 write_zsreg(uap, 0, RES_EXT_INT);
804 write_zsreg(uap, 0, RES_EXT_INT);
805 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
806
807 /* The channel should be OK now, but it is probably receiving
808 * loopback garbage.
809 * Switch to asynchronous mode, disable the receiver,
810 * and discard everything in the receive buffer.
811 */
812 write_zsreg(uap, 9, NV);
813 write_zsreg(uap, 4, X16CLK | SB_MASK);
814 write_zsreg(uap, 3, Rx8);
815
816 while (read_zsreg(uap, 0) & Rx_CH_AV) {
817 (void)read_zsreg(uap, 8);
818 write_zsreg(uap, 0, RES_EXT_INT);
819 write_zsreg(uap, 0, ERR_RES);
820 }
821}
822
823/*
824 * Real startup routine, powers up the hardware and sets up
825 * the SCC. Returns a delay in ms where you need to wait before
826 * actually using the port, this is typically the internal modem
827 * powerup delay. This routine expect the lock to be taken.
828 */
829static int __pmz_startup(struct uart_pmac_port *uap)
830{
831 int pwr_delay = 0;
832
833 memset(&uap->curregs, 0, sizeof(uap->curregs));
834
835 /* Power up the SCC & underlying hardware (modem/irda) */
836 pwr_delay = pmz_set_scc_power(uap, 1);
837
838 /* Nice buggy HW ... */
839 pmz_fix_zero_bug_scc(uap);
840
841 /* Reset the channel */
842 uap->curregs[R9] = 0;
843 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
844 zssync(uap);
845 udelay(10);
846 write_zsreg(uap, 9, 0);
847 zssync(uap);
848
849 /* Clear the interrupt registers */
850 write_zsreg(uap, R1, 0);
851 write_zsreg(uap, R0, ERR_RES);
852 write_zsreg(uap, R0, ERR_RES);
853 write_zsreg(uap, R0, RES_H_IUS);
854 write_zsreg(uap, R0, RES_H_IUS);
855
856 /* Setup some valid baud rate */
857 uap->curregs[R4] = X16CLK | SB1;
858 uap->curregs[R3] = Rx8;
859 uap->curregs[R5] = Tx8 | RTS;
860 if (!ZS_IS_IRDA(uap))
861 uap->curregs[R5] |= DTR;
862 uap->curregs[R12] = 0;
863 uap->curregs[R13] = 0;
864 uap->curregs[R14] = BRENAB;
865
866 /* Clear handshaking, enable BREAK interrupts */
867 uap->curregs[R15] = BRKIE;
868
869 /* Master interrupt enable */
870 uap->curregs[R9] |= NV | MIE;
871
872 pmz_load_zsregs(uap, uap->curregs);
873
874 /* Enable receiver and transmitter. */
875 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
876 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
877
878 /* Remember status for DCD/CTS changes */
879 uap->prev_status = read_zsreg(uap, R0);
880
881 return pwr_delay;
882}
883
884static void pmz_irda_reset(struct uart_pmac_port *uap)
885{
886 unsigned long flags;
887
888 spin_lock_irqsave(&uap->port.lock, flags);
889 uap->curregs[R5] |= DTR;
890 write_zsreg(uap, R5, uap->curregs[R5]);
891 zssync(uap);
892 spin_unlock_irqrestore(&uap->port.lock, flags);
893 msleep(110);
894
895 spin_lock_irqsave(&uap->port.lock, flags);
896 uap->curregs[R5] &= ~DTR;
897 write_zsreg(uap, R5, uap->curregs[R5]);
898 zssync(uap);
899 spin_unlock_irqrestore(&uap->port.lock, flags);
900 msleep(10);
901}
902
903/*
904 * This is the "normal" startup routine, using the above one
905 * wrapped with the lock and doing a schedule delay
906 */
907static int pmz_startup(struct uart_port *port)
908{
909 struct uart_pmac_port *uap = to_pmz(port);
910 unsigned long flags;
911 int pwr_delay = 0;
912
913 pmz_debug("pmz: startup()\n");
914
915 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
916
917 /* A console is never powered down. Else, power up and
918 * initialize the chip
919 */
920 if (!ZS_IS_CONS(uap)) {
921 spin_lock_irqsave(&port->lock, flags);
922 pwr_delay = __pmz_startup(uap);
923 spin_unlock_irqrestore(&port->lock, flags);
924 }
925 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
926 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
927 uap->irq_name, uap)) {
928 pmz_error("Unable to register zs interrupt handler.\n");
929 pmz_set_scc_power(uap, 0);
930 return -ENXIO;
931 }
932
933 /* Right now, we deal with delay by blocking here, I'll be
934 * smarter later on
935 */
936 if (pwr_delay != 0) {
937 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
938 msleep(pwr_delay);
939 }
940
941 /* IrDA reset is done now */
942 if (ZS_IS_IRDA(uap))
943 pmz_irda_reset(uap);
944
945 /* Enable interrupt requests for the channel */
946 spin_lock_irqsave(&port->lock, flags);
947 pmz_interrupt_control(uap, 1);
948 spin_unlock_irqrestore(&port->lock, flags);
949
950 pmz_debug("pmz: startup() done.\n");
951
952 return 0;
953}
954
955static void pmz_shutdown(struct uart_port *port)
956{
957 struct uart_pmac_port *uap = to_pmz(port);
958 unsigned long flags;
959
960 pmz_debug("pmz: shutdown()\n");
961
962 spin_lock_irqsave(&port->lock, flags);
963
964 /* Disable interrupt requests for the channel */
965 pmz_interrupt_control(uap, 0);
966
967 if (!ZS_IS_CONS(uap)) {
968 /* Disable receiver and transmitter */
969 uap->curregs[R3] &= ~RxENABLE;
970 uap->curregs[R5] &= ~TxENABLE;
971
972 /* Disable break assertion */
973 uap->curregs[R5] &= ~SND_BRK;
974 pmz_maybe_update_regs(uap);
975 }
976
977 spin_unlock_irqrestore(&port->lock, flags);
978
979 /* Release interrupt handler */
980 free_irq(uap->port.irq, uap);
981
982 spin_lock_irqsave(&port->lock, flags);
983
984 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
985
986 if (!ZS_IS_CONS(uap))
987 pmz_set_scc_power(uap, 0); /* Shut the chip down */
988
989 spin_unlock_irqrestore(&port->lock, flags);
990
991 pmz_debug("pmz: shutdown() done.\n");
992}
993
994/* Shared by TTY driver and serial console setup. The port lock is held
995 * and local interrupts are disabled.
996 */
997static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
998 unsigned int iflag, unsigned long baud)
999{
1000 int brg;
1001
1002 /* Switch to external clocking for IrDA high clock rates. That
1003 * code could be re-used for Midi interfaces with different
1004 * multipliers
1005 */
1006 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1007 uap->curregs[R4] = X1CLK;
1008 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1009 uap->curregs[R14] = 0; /* BRG off */
1010 uap->curregs[R12] = 0;
1011 uap->curregs[R13] = 0;
1012 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1013 } else {
1014 switch (baud) {
1015 case ZS_CLOCK/16: /* 230400 */
1016 uap->curregs[R4] = X16CLK;
1017 uap->curregs[R11] = 0;
1018 uap->curregs[R14] = 0;
1019 break;
1020 case ZS_CLOCK/32: /* 115200 */
1021 uap->curregs[R4] = X32CLK;
1022 uap->curregs[R11] = 0;
1023 uap->curregs[R14] = 0;
1024 break;
1025 default:
1026 uap->curregs[R4] = X16CLK;
1027 uap->curregs[R11] = TCBR | RCBR;
1028 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1029 uap->curregs[R12] = (brg & 255);
1030 uap->curregs[R13] = ((brg >> 8) & 255);
1031 uap->curregs[R14] = BRENAB;
1032 }
1033 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1034 }
1035
1036 /* Character size, stop bits, and parity. */
1037 uap->curregs[3] &= ~RxN_MASK;
1038 uap->curregs[5] &= ~TxN_MASK;
1039
1040 switch (cflag & CSIZE) {
1041 case CS5:
1042 uap->curregs[3] |= Rx5;
1043 uap->curregs[5] |= Tx5;
1044 uap->parity_mask = 0x1f;
1045 break;
1046 case CS6:
1047 uap->curregs[3] |= Rx6;
1048 uap->curregs[5] |= Tx6;
1049 uap->parity_mask = 0x3f;
1050 break;
1051 case CS7:
1052 uap->curregs[3] |= Rx7;
1053 uap->curregs[5] |= Tx7;
1054 uap->parity_mask = 0x7f;
1055 break;
1056 case CS8:
1057 default:
1058 uap->curregs[3] |= Rx8;
1059 uap->curregs[5] |= Tx8;
1060 uap->parity_mask = 0xff;
1061 break;
1062 }
1063 uap->curregs[4] &= ~(SB_MASK);
1064 if (cflag & CSTOPB)
1065 uap->curregs[4] |= SB2;
1066 else
1067 uap->curregs[4] |= SB1;
1068 if (cflag & PARENB)
1069 uap->curregs[4] |= PAR_ENAB;
1070 else
1071 uap->curregs[4] &= ~PAR_ENAB;
1072 if (!(cflag & PARODD))
1073 uap->curregs[4] |= PAR_EVEN;
1074 else
1075 uap->curregs[4] &= ~PAR_EVEN;
1076
1077 uap->port.read_status_mask = Rx_OVR;
1078 if (iflag & INPCK)
1079 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1080 if (iflag & (IGNBRK | BRKINT | PARMRK))
1081 uap->port.read_status_mask |= BRK_ABRT;
1082
1083 uap->port.ignore_status_mask = 0;
1084 if (iflag & IGNPAR)
1085 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1086 if (iflag & IGNBRK) {
1087 uap->port.ignore_status_mask |= BRK_ABRT;
1088 if (iflag & IGNPAR)
1089 uap->port.ignore_status_mask |= Rx_OVR;
1090 }
1091
1092 if ((cflag & CREAD) == 0)
1093 uap->port.ignore_status_mask = 0xff;
1094}
1095
1096
1097/*
1098 * Set the irda codec on the imac to the specified baud rate.
1099 */
1100static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1101{
1102 u8 cmdbyte;
1103 int t, version;
1104
1105 switch (*baud) {
1106 /* SIR modes */
1107 case 2400:
1108 cmdbyte = 0x53;
1109 break;
1110 case 4800:
1111 cmdbyte = 0x52;
1112 break;
1113 case 9600:
1114 cmdbyte = 0x51;
1115 break;
1116 case 19200:
1117 cmdbyte = 0x50;
1118 break;
1119 case 38400:
1120 cmdbyte = 0x4f;
1121 break;
1122 case 57600:
1123 cmdbyte = 0x4e;
1124 break;
1125 case 115200:
1126 cmdbyte = 0x4d;
1127 break;
1128 /* The FIR modes aren't really supported at this point, how
1129 * do we select the speed ? via the FCR on KeyLargo ?
1130 */
1131 case 1152000:
1132 cmdbyte = 0;
1133 break;
1134 case 4000000:
1135 cmdbyte = 0;
1136 break;
1137 default: /* 9600 */
1138 cmdbyte = 0x51;
1139 *baud = 9600;
1140 break;
1141 }
1142
1143 /* Wait for transmitter to drain */
1144 t = 10000;
1145 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1146 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1147 if (--t <= 0) {
1148 pmz_error("transmitter didn't drain\n");
1149 return;
1150 }
1151 udelay(10);
1152 }
1153
1154 /* Drain the receiver too */
1155 t = 100;
1156 (void)read_zsdata(uap);
1157 (void)read_zsdata(uap);
1158 (void)read_zsdata(uap);
1159 mdelay(10);
1160 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1161 read_zsdata(uap);
1162 mdelay(10);
1163 if (--t <= 0) {
1164 pmz_error("receiver didn't drain\n");
1165 return;
1166 }
1167 }
1168
1169 /* Switch to command mode */
1170 uap->curregs[R5] |= DTR;
1171 write_zsreg(uap, R5, uap->curregs[R5]);
1172 zssync(uap);
1173 mdelay(1);
1174
1175 /* Switch SCC to 19200 */
1176 pmz_convert_to_zs(uap, CS8, 0, 19200);
1177 pmz_load_zsregs(uap, uap->curregs);
1178 mdelay(1);
1179
1180 /* Write get_version command byte */
1181 write_zsdata(uap, 1);
1182 t = 5000;
1183 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1184 if (--t <= 0) {
1185 pmz_error("irda_setup timed out on get_version byte\n");
1186 goto out;
1187 }
1188 udelay(10);
1189 }
1190 version = read_zsdata(uap);
1191
1192 if (version < 4) {
1193 pmz_info("IrDA: dongle version %d not supported\n", version);
1194 goto out;
1195 }
1196
1197 /* Send speed mode */
1198 write_zsdata(uap, cmdbyte);
1199 t = 5000;
1200 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1201 if (--t <= 0) {
1202 pmz_error("irda_setup timed out on speed mode byte\n");
1203 goto out;
1204 }
1205 udelay(10);
1206 }
1207 t = read_zsdata(uap);
1208 if (t != cmdbyte)
1209 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1210
1211 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1212 *baud, version);
1213
1214 (void)read_zsdata(uap);
1215 (void)read_zsdata(uap);
1216 (void)read_zsdata(uap);
1217
1218 out:
1219 /* Switch back to data mode */
1220 uap->curregs[R5] &= ~DTR;
1221 write_zsreg(uap, R5, uap->curregs[R5]);
1222 zssync(uap);
1223
1224 (void)read_zsdata(uap);
1225 (void)read_zsdata(uap);
1226 (void)read_zsdata(uap);
1227}
1228
1229
1230static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1231 struct ktermios *old)
1232{
1233 struct uart_pmac_port *uap = to_pmz(port);
1234 unsigned long baud;
1235
1236 pmz_debug("pmz: set_termios()\n");
1237
1238 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1239
1240 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1241 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1242 * about the FIR mode and high speed modes. So these are unused. For
1243 * implementing proper support for these, we should probably add some
1244 * DMA as well, at least on the Rx side, which isn't a simple thing
1245 * at this point.
1246 */
1247 if (ZS_IS_IRDA(uap)) {
1248 /* Calc baud rate */
1249 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1250 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1251 /* Cet the irda codec to the right rate */
1252 pmz_irda_setup(uap, &baud);
1253 /* Set final baud rate */
1254 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1255 pmz_load_zsregs(uap, uap->curregs);
1256 zssync(uap);
1257 } else {
1258 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1259 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1260 /* Make sure modem status interrupts are correctly configured */
1261 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1262 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1263 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1264 } else {
1265 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1266 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1267 }
1268
1269 /* Load registers to the chip */
1270 pmz_maybe_update_regs(uap);
1271 }
1272 uart_update_timeout(port, termios->c_cflag, baud);
1273
1274 pmz_debug("pmz: set_termios() done.\n");
1275}
1276
1277/* The port lock is not held. */
1278static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1279 struct ktermios *old)
1280{
1281 struct uart_pmac_port *uap = to_pmz(port);
1282 unsigned long flags;
1283
1284 spin_lock_irqsave(&port->lock, flags);
1285
1286 /* Disable IRQs on the port */
1287 pmz_interrupt_control(uap, 0);
1288
1289 /* Setup new port configuration */
1290 __pmz_set_termios(port, termios, old);
1291
1292 /* Re-enable IRQs on the port */
1293 if (ZS_IS_OPEN(uap))
1294 pmz_interrupt_control(uap, 1);
1295
1296 spin_unlock_irqrestore(&port->lock, flags);
1297}
1298
1299static const char *pmz_type(struct uart_port *port)
1300{
1301 struct uart_pmac_port *uap = to_pmz(port);
1302
1303 if (ZS_IS_IRDA(uap))
1304 return "Z85c30 ESCC - Infrared port";
1305 else if (ZS_IS_INTMODEM(uap))
1306 return "Z85c30 ESCC - Internal modem";
1307 return "Z85c30 ESCC - Serial port";
1308}
1309
1310/* We do not request/release mappings of the registers here, this
1311 * happens at early serial probe time.
1312 */
1313static void pmz_release_port(struct uart_port *port)
1314{
1315}
1316
1317static int pmz_request_port(struct uart_port *port)
1318{
1319 return 0;
1320}
1321
1322/* These do not need to do anything interesting either. */
1323static void pmz_config_port(struct uart_port *port, int flags)
1324{
1325}
1326
1327/* We do not support letting the user mess with the divisor, IRQ, etc. */
1328static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1329{
1330 return -EINVAL;
1331}
1332
1333#ifdef CONFIG_CONSOLE_POLL
1334
1335static int pmz_poll_get_char(struct uart_port *port)
1336{
1337 struct uart_pmac_port *uap =
1338 container_of(port, struct uart_pmac_port, port);
1339 int tries = 2;
1340
1341 while (tries) {
1342 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1343 return read_zsdata(uap);
1344 if (tries--)
1345 udelay(5);
1346 }
1347
1348 return NO_POLL_CHAR;
1349}
1350
1351static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1352{
1353 struct uart_pmac_port *uap =
1354 container_of(port, struct uart_pmac_port, port);
1355
1356 /* Wait for the transmit buffer to empty. */
1357 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1358 udelay(5);
1359 write_zsdata(uap, c);
1360}
1361
1362#endif /* CONFIG_CONSOLE_POLL */
1363
1364static const struct uart_ops pmz_pops = {
1365 .tx_empty = pmz_tx_empty,
1366 .set_mctrl = pmz_set_mctrl,
1367 .get_mctrl = pmz_get_mctrl,
1368 .stop_tx = pmz_stop_tx,
1369 .start_tx = pmz_start_tx,
1370 .stop_rx = pmz_stop_rx,
1371 .enable_ms = pmz_enable_ms,
1372 .break_ctl = pmz_break_ctl,
1373 .startup = pmz_startup,
1374 .shutdown = pmz_shutdown,
1375 .set_termios = pmz_set_termios,
1376 .type = pmz_type,
1377 .release_port = pmz_release_port,
1378 .request_port = pmz_request_port,
1379 .config_port = pmz_config_port,
1380 .verify_port = pmz_verify_port,
1381#ifdef CONFIG_CONSOLE_POLL
1382 .poll_get_char = pmz_poll_get_char,
1383 .poll_put_char = pmz_poll_put_char,
1384#endif
1385};
1386
1387#ifdef CONFIG_PPC_PMAC
1388
1389/*
1390 * Setup one port structure after probing, HW is down at this point,
1391 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1392 * register our console before uart_add_one_port() is called
1393 */
1394static int __init pmz_init_port(struct uart_pmac_port *uap)
1395{
1396 struct device_node *np = uap->node;
1397 const char *conn;
1398 const struct slot_names_prop {
1399 int count;
1400 char name[1];
1401 } *slots;
1402 int len;
1403 struct resource r_ports, r_rxdma, r_txdma;
1404
1405 /*
1406 * Request & map chip registers
1407 */
1408 if (of_address_to_resource(np, 0, &r_ports))
1409 return -ENODEV;
1410 uap->port.mapbase = r_ports.start;
1411 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1412
1413 uap->control_reg = uap->port.membase;
1414 uap->data_reg = uap->control_reg + 0x10;
1415
1416 /*
1417 * Request & map DBDMA registers
1418 */
1419#ifdef HAS_DBDMA
1420 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1421 of_address_to_resource(np, 2, &r_rxdma) == 0)
1422 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1423#else
1424 memset(&r_txdma, 0, sizeof(struct resource));
1425 memset(&r_rxdma, 0, sizeof(struct resource));
1426#endif
1427 if (ZS_HAS_DMA(uap)) {
1428 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1429 if (uap->tx_dma_regs == NULL) {
1430 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1431 goto no_dma;
1432 }
1433 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1434 if (uap->rx_dma_regs == NULL) {
1435 iounmap(uap->tx_dma_regs);
1436 uap->tx_dma_regs = NULL;
1437 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1438 goto no_dma;
1439 }
1440 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1441 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1442 }
1443no_dma:
1444
1445 /*
1446 * Detect port type
1447 */
1448 if (of_device_is_compatible(np, "cobalt"))
1449 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1450 conn = of_get_property(np, "AAPL,connector", &len);
1451 if (conn && (strcmp(conn, "infrared") == 0))
1452 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1453 uap->port_type = PMAC_SCC_ASYNC;
1454 /* 1999 Powerbook G3 has slot-names property instead */
1455 slots = of_get_property(np, "slot-names", &len);
1456 if (slots && slots->count > 0) {
1457 if (strcmp(slots->name, "IrDA") == 0)
1458 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1459 else if (strcmp(slots->name, "Modem") == 0)
1460 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1461 }
1462 if (ZS_IS_IRDA(uap))
1463 uap->port_type = PMAC_SCC_IRDA;
1464 if (ZS_IS_INTMODEM(uap)) {
1465 struct device_node* i2c_modem =
1466 of_find_node_by_name(NULL, "i2c-modem");
1467 if (i2c_modem) {
1468 const char* mid =
1469 of_get_property(i2c_modem, "modem-id", NULL);
1470 if (mid) switch(*mid) {
1471 case 0x04 :
1472 case 0x05 :
1473 case 0x07 :
1474 case 0x08 :
1475 case 0x0b :
1476 case 0x0c :
1477 uap->port_type = PMAC_SCC_I2S1;
1478 }
1479 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1480 mid ? (*mid) : 0);
1481 of_node_put(i2c_modem);
1482 } else {
1483 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1484 }
1485 }
1486
1487 /*
1488 * Init remaining bits of "port" structure
1489 */
1490 uap->port.iotype = UPIO_MEM;
1491 uap->port.irq = irq_of_parse_and_map(np, 0);
1492 uap->port.uartclk = ZS_CLOCK;
1493 uap->port.fifosize = 1;
1494 uap->port.ops = &pmz_pops;
1495 uap->port.type = PORT_PMAC_ZILOG;
1496 uap->port.flags = 0;
1497
1498 /*
1499 * Fixup for the port on Gatwick for which the device-tree has
1500 * missing interrupts. Normally, the macio_dev would contain
1501 * fixed up interrupt info, but we use the device-tree directly
1502 * here due to early probing so we need the fixup too.
1503 */
1504 if (uap->port.irq == 0 &&
1505 np->parent && np->parent->parent &&
1506 of_device_is_compatible(np->parent->parent, "gatwick")) {
1507 /* IRQs on gatwick are offset by 64 */
1508 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1509 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1510 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1511 }
1512
1513 /* Setup some valid baud rate information in the register
1514 * shadows so we don't write crap there before baud rate is
1515 * first initialized.
1516 */
1517 pmz_convert_to_zs(uap, CS8, 0, 9600);
1518
1519 return 0;
1520}
1521
1522/*
1523 * Get rid of a port on module removal
1524 */
1525static void pmz_dispose_port(struct uart_pmac_port *uap)
1526{
1527 struct device_node *np;
1528
1529 np = uap->node;
1530 iounmap(uap->rx_dma_regs);
1531 iounmap(uap->tx_dma_regs);
1532 iounmap(uap->control_reg);
1533 uap->node = NULL;
1534 of_node_put(np);
1535 memset(uap, 0, sizeof(struct uart_pmac_port));
1536}
1537
1538/*
1539 * Called upon match with an escc node in the device-tree.
1540 */
1541static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1542{
1543 struct uart_pmac_port *uap;
1544 int i;
1545
1546 /* Iterate the pmz_ports array to find a matching entry
1547 */
1548 for (i = 0; i < MAX_ZS_PORTS; i++)
1549 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1550 break;
1551 if (i >= MAX_ZS_PORTS)
1552 return -ENODEV;
1553
1554
1555 uap = &pmz_ports[i];
1556 uap->dev = mdev;
1557 uap->port.dev = &mdev->ofdev.dev;
1558 dev_set_drvdata(&mdev->ofdev.dev, uap);
1559
1560 /* We still activate the port even when failing to request resources
1561 * to work around bugs in ancient Apple device-trees
1562 */
1563 if (macio_request_resources(uap->dev, "pmac_zilog"))
1564 printk(KERN_WARNING "%pOFn: Failed to request resource"
1565 ", port still active\n",
1566 uap->node);
1567 else
1568 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1569
1570 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1571}
1572
1573/*
1574 * That one should not be called, macio isn't really a hotswap device,
1575 * we don't expect one of those serial ports to go away...
1576 */
1577static int pmz_detach(struct macio_dev *mdev)
1578{
1579 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1580
1581 if (!uap)
1582 return -ENODEV;
1583
1584 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1585
1586 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1587 macio_release_resources(uap->dev);
1588 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1589 }
1590 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1591 uap->dev = NULL;
1592 uap->port.dev = NULL;
1593
1594 return 0;
1595}
1596
1597
1598static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1599{
1600 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1601
1602 if (uap == NULL) {
1603 printk("HRM... pmz_suspend with NULL uap\n");
1604 return 0;
1605 }
1606
1607 uart_suspend_port(&pmz_uart_reg, &uap->port);
1608
1609 return 0;
1610}
1611
1612
1613static int pmz_resume(struct macio_dev *mdev)
1614{
1615 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1616
1617 if (uap == NULL)
1618 return 0;
1619
1620 uart_resume_port(&pmz_uart_reg, &uap->port);
1621
1622 return 0;
1623}
1624
1625/*
1626 * Probe all ports in the system and build the ports array, we register
1627 * with the serial layer later, so we get a proper struct device which
1628 * allows the tty to attach properly. This is later than it used to be
1629 * but the tty layer really wants it that way.
1630 */
1631static int __init pmz_probe(void)
1632{
1633 struct device_node *node_p, *node_a, *node_b, *np;
1634 int count = 0;
1635 int rc;
1636
1637 /*
1638 * Find all escc chips in the system
1639 */
1640 for_each_node_by_name(node_p, "escc") {
1641 /*
1642 * First get channel A/B node pointers
1643 *
1644 * TODO: Add routines with proper locking to do that...
1645 */
1646 node_a = node_b = NULL;
1647 for_each_child_of_node(node_p, np) {
1648 if (of_node_name_prefix(np, "ch-a"))
1649 node_a = of_node_get(np);
1650 else if (of_node_name_prefix(np, "ch-b"))
1651 node_b = of_node_get(np);
1652 }
1653 if (!node_a && !node_b) {
1654 of_node_put(node_a);
1655 of_node_put(node_b);
1656 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1657 (!node_a) ? 'a' : 'b', node_p);
1658 continue;
1659 }
1660
1661 /*
1662 * Fill basic fields in the port structures
1663 */
1664 if (node_b != NULL) {
1665 pmz_ports[count].mate = &pmz_ports[count+1];
1666 pmz_ports[count+1].mate = &pmz_ports[count];
1667 }
1668 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1669 pmz_ports[count].node = node_a;
1670 pmz_ports[count+1].node = node_b;
1671 pmz_ports[count].port.line = count;
1672 pmz_ports[count+1].port.line = count+1;
1673
1674 /*
1675 * Setup the ports for real
1676 */
1677 rc = pmz_init_port(&pmz_ports[count]);
1678 if (rc == 0 && node_b != NULL)
1679 rc = pmz_init_port(&pmz_ports[count+1]);
1680 if (rc != 0) {
1681 of_node_put(node_a);
1682 of_node_put(node_b);
1683 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1684 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1685 continue;
1686 }
1687 count += 2;
1688 }
1689 pmz_ports_count = count;
1690
1691 return 0;
1692}
1693
1694#else
1695
1696/* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
1697 * tree to obtain the device_nodes needed to start the console before the
1698 * macio driver. On Macs without OpenFirmware, global platform_devices take
1699 * the place of those device_nodes.
1700 */
1701extern struct platform_device scc_a_pdev, scc_b_pdev;
1702
1703static int __init pmz_init_port(struct uart_pmac_port *uap)
1704{
1705 struct resource *r_ports, *r_irq;
1706
1707 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1708 r_irq = platform_get_resource(uap->pdev, IORESOURCE_IRQ, 0);
1709 if (!r_ports || !r_irq)
1710 return -ENODEV;
1711
1712 uap->port.mapbase = r_ports->start;
1713 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1714 uap->port.iotype = UPIO_MEM;
1715 uap->port.irq = r_irq->start;
1716 uap->port.uartclk = ZS_CLOCK;
1717 uap->port.fifosize = 1;
1718 uap->port.ops = &pmz_pops;
1719 uap->port.type = PORT_PMAC_ZILOG;
1720 uap->port.flags = 0;
1721
1722 uap->control_reg = uap->port.membase;
1723 uap->data_reg = uap->control_reg + 4;
1724 uap->port_type = 0;
1725 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1726
1727 pmz_convert_to_zs(uap, CS8, 0, 9600);
1728
1729 return 0;
1730}
1731
1732static int __init pmz_probe(void)
1733{
1734 int err;
1735
1736 pmz_ports_count = 0;
1737
1738 pmz_ports[0].port.line = 0;
1739 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1740 pmz_ports[0].pdev = &scc_a_pdev;
1741 err = pmz_init_port(&pmz_ports[0]);
1742 if (err)
1743 return err;
1744 pmz_ports_count++;
1745
1746 pmz_ports[0].mate = &pmz_ports[1];
1747 pmz_ports[1].mate = &pmz_ports[0];
1748 pmz_ports[1].port.line = 1;
1749 pmz_ports[1].flags = 0;
1750 pmz_ports[1].pdev = &scc_b_pdev;
1751 err = pmz_init_port(&pmz_ports[1]);
1752 if (err)
1753 return err;
1754 pmz_ports_count++;
1755
1756 return 0;
1757}
1758
1759static void pmz_dispose_port(struct uart_pmac_port *uap)
1760{
1761 memset(uap, 0, sizeof(struct uart_pmac_port));
1762}
1763
1764static int __init pmz_attach(struct platform_device *pdev)
1765{
1766 struct uart_pmac_port *uap;
1767 int i;
1768
1769 /* Iterate the pmz_ports array to find a matching entry */
1770 for (i = 0; i < pmz_ports_count; i++)
1771 if (pmz_ports[i].pdev == pdev)
1772 break;
1773 if (i >= pmz_ports_count)
1774 return -ENODEV;
1775
1776 uap = &pmz_ports[i];
1777 uap->port.dev = &pdev->dev;
1778 platform_set_drvdata(pdev, uap);
1779
1780 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1781}
1782
1783static int __exit pmz_detach(struct platform_device *pdev)
1784{
1785 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1786
1787 if (!uap)
1788 return -ENODEV;
1789
1790 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1791
1792 uap->port.dev = NULL;
1793
1794 return 0;
1795}
1796
1797#endif /* !CONFIG_PPC_PMAC */
1798
1799#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1800
1801static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1802static int __init pmz_console_setup(struct console *co, char *options);
1803
1804static struct console pmz_console = {
1805 .name = PMACZILOG_NAME,
1806 .write = pmz_console_write,
1807 .device = uart_console_device,
1808 .setup = pmz_console_setup,
1809 .flags = CON_PRINTBUFFER,
1810 .index = -1,
1811 .data = &pmz_uart_reg,
1812};
1813
1814#define PMACZILOG_CONSOLE &pmz_console
1815#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1816#define PMACZILOG_CONSOLE (NULL)
1817#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1818
1819/*
1820 * Register the driver, console driver and ports with the serial
1821 * core
1822 */
1823static int __init pmz_register(void)
1824{
1825 pmz_uart_reg.nr = pmz_ports_count;
1826 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1827
1828 /*
1829 * Register this driver with the serial core
1830 */
1831 return uart_register_driver(&pmz_uart_reg);
1832}
1833
1834#ifdef CONFIG_PPC_PMAC
1835
1836static const struct of_device_id pmz_match[] =
1837{
1838 {
1839 .name = "ch-a",
1840 },
1841 {
1842 .name = "ch-b",
1843 },
1844 {},
1845};
1846MODULE_DEVICE_TABLE (of, pmz_match);
1847
1848static struct macio_driver pmz_driver = {
1849 .driver = {
1850 .name = "pmac_zilog",
1851 .owner = THIS_MODULE,
1852 .of_match_table = pmz_match,
1853 },
1854 .probe = pmz_attach,
1855 .remove = pmz_detach,
1856 .suspend = pmz_suspend,
1857 .resume = pmz_resume,
1858};
1859
1860#else
1861
1862static struct platform_driver pmz_driver = {
1863 .remove = __exit_p(pmz_detach),
1864 .driver = {
1865 .name = "scc",
1866 },
1867};
1868
1869#endif /* !CONFIG_PPC_PMAC */
1870
1871static int __init init_pmz(void)
1872{
1873 int rc, i;
1874 printk(KERN_INFO "%s\n", version);
1875
1876 /*
1877 * First, we need to do a direct OF-based probe pass. We
1878 * do that because we want serial console up before the
1879 * macio stuffs calls us back, and since that makes it
1880 * easier to pass the proper number of channels to
1881 * uart_register_driver()
1882 */
1883 if (pmz_ports_count == 0)
1884 pmz_probe();
1885
1886 /*
1887 * Bail early if no port found
1888 */
1889 if (pmz_ports_count == 0)
1890 return -ENODEV;
1891
1892 /*
1893 * Now we register with the serial layer
1894 */
1895 rc = pmz_register();
1896 if (rc) {
1897 printk(KERN_ERR
1898 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1899 "pmac_zilog: Did another serial driver already claim the minors?\n");
1900 /* effectively "pmz_unprobe()" */
1901 for (i=0; i < pmz_ports_count; i++)
1902 pmz_dispose_port(&pmz_ports[i]);
1903 return rc;
1904 }
1905
1906 /*
1907 * Then we register the macio driver itself
1908 */
1909#ifdef CONFIG_PPC_PMAC
1910 return macio_register_driver(&pmz_driver);
1911#else
1912 return platform_driver_probe(&pmz_driver, pmz_attach);
1913#endif
1914}
1915
1916static void __exit exit_pmz(void)
1917{
1918 int i;
1919
1920#ifdef CONFIG_PPC_PMAC
1921 /* Get rid of macio-driver (detach from macio) */
1922 macio_unregister_driver(&pmz_driver);
1923#else
1924 platform_driver_unregister(&pmz_driver);
1925#endif
1926
1927 for (i = 0; i < pmz_ports_count; i++) {
1928 struct uart_pmac_port *uport = &pmz_ports[i];
1929#ifdef CONFIG_PPC_PMAC
1930 if (uport->node != NULL)
1931 pmz_dispose_port(uport);
1932#else
1933 if (uport->pdev != NULL)
1934 pmz_dispose_port(uport);
1935#endif
1936 }
1937 /* Unregister UART driver */
1938 uart_unregister_driver(&pmz_uart_reg);
1939}
1940
1941#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1942
1943static void pmz_console_putchar(struct uart_port *port, int ch)
1944{
1945 struct uart_pmac_port *uap =
1946 container_of(port, struct uart_pmac_port, port);
1947
1948 /* Wait for the transmit buffer to empty. */
1949 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1950 udelay(5);
1951 write_zsdata(uap, ch);
1952}
1953
1954/*
1955 * Print a string to the serial port trying not to disturb
1956 * any possible real use of the port...
1957 */
1958static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1959{
1960 struct uart_pmac_port *uap = &pmz_ports[con->index];
1961 unsigned long flags;
1962
1963 spin_lock_irqsave(&uap->port.lock, flags);
1964
1965 /* Turn of interrupts and enable the transmitter. */
1966 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1967 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1968
1969 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1970
1971 /* Restore the values in the registers. */
1972 write_zsreg(uap, R1, uap->curregs[1]);
1973 /* Don't disable the transmitter. */
1974
1975 spin_unlock_irqrestore(&uap->port.lock, flags);
1976}
1977
1978/*
1979 * Setup the serial console
1980 */
1981static int __init pmz_console_setup(struct console *co, char *options)
1982{
1983 struct uart_pmac_port *uap;
1984 struct uart_port *port;
1985 int baud = 38400;
1986 int bits = 8;
1987 int parity = 'n';
1988 int flow = 'n';
1989 unsigned long pwr_delay;
1990
1991 /*
1992 * XServe's default to 57600 bps
1993 */
1994 if (of_machine_is_compatible("RackMac1,1")
1995 || of_machine_is_compatible("RackMac1,2")
1996 || of_machine_is_compatible("MacRISC4"))
1997 baud = 57600;
1998
1999 /*
2000 * Check whether an invalid uart number has been specified, and
2001 * if so, search for the first available port that does have
2002 * console support.
2003 */
2004 if (co->index >= pmz_ports_count)
2005 co->index = 0;
2006 uap = &pmz_ports[co->index];
2007#ifdef CONFIG_PPC_PMAC
2008 if (uap->node == NULL)
2009 return -ENODEV;
2010#else
2011 if (uap->pdev == NULL)
2012 return -ENODEV;
2013#endif
2014 port = &uap->port;
2015
2016 /*
2017 * Mark port as beeing a console
2018 */
2019 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2020
2021 /*
2022 * Temporary fix for uart layer who didn't setup the spinlock yet
2023 */
2024 spin_lock_init(&port->lock);
2025
2026 /*
2027 * Enable the hardware
2028 */
2029 pwr_delay = __pmz_startup(uap);
2030 if (pwr_delay)
2031 mdelay(pwr_delay);
2032
2033 if (options)
2034 uart_parse_options(options, &baud, &parity, &bits, &flow);
2035
2036 return uart_set_options(port, co, baud, parity, bits, flow);
2037}
2038
2039static int __init pmz_console_init(void)
2040{
2041 /* Probe ports */
2042 pmz_probe();
2043
2044 if (pmz_ports_count == 0)
2045 return -ENODEV;
2046
2047 /* TODO: Autoprobe console based on OF */
2048 /* pmz_console.index = i; */
2049 register_console(&pmz_console);
2050
2051 return 0;
2052
2053}
2054console_initcall(pmz_console_init);
2055#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2056
2057module_init(init_pmz);
2058module_exit(exit_pmz);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
5 *
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 *
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
10 *
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
16 *
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
20 *
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
24 */
25
26#undef DEBUG
27#undef USE_CTRL_O_SYSRQ
28
29#include <linux/module.h>
30#include <linux/tty.h>
31
32#include <linux/tty_flip.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/mm.h>
37#include <linux/kernel.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/adb.h>
42#include <linux/pmu.h>
43#include <linux/bitops.h>
44#include <linux/sysrq.h>
45#include <linux/mutex.h>
46#include <linux/of_address.h>
47#include <linux/of_irq.h>
48#include <asm/sections.h>
49#include <linux/io.h>
50#include <asm/irq.h>
51
52#ifdef CONFIG_PPC_PMAC
53#include <asm/machdep.h>
54#include <asm/pmac_feature.h>
55#include <asm/macio.h>
56#else
57#include <linux/platform_device.h>
58#define of_machine_is_compatible(x) (0)
59#endif
60
61#include <linux/serial.h>
62#include <linux/serial_core.h>
63
64#include "pmac_zilog.h"
65
66MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
67MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
68MODULE_LICENSE("GPL");
69
70#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
71#define PMACZILOG_MAJOR TTY_MAJOR
72#define PMACZILOG_MINOR 64
73#define PMACZILOG_NAME "ttyS"
74#else
75#define PMACZILOG_MAJOR 204
76#define PMACZILOG_MINOR 192
77#define PMACZILOG_NAME "ttyPZ"
78#endif
79
80#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
81#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
82#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
83
84/*
85 * For the sake of early serial console, we can do a pre-probe
86 * (optional) of the ports at rather early boot time.
87 */
88static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
89static int pmz_ports_count;
90
91static struct uart_driver pmz_uart_reg = {
92 .owner = THIS_MODULE,
93 .driver_name = PMACZILOG_NAME,
94 .dev_name = PMACZILOG_NAME,
95 .major = PMACZILOG_MAJOR,
96 .minor = PMACZILOG_MINOR,
97};
98
99
100/*
101 * Load all registers to reprogram the port
102 * This function must only be called when the TX is not busy. The UART
103 * port lock must be held and local interrupts disabled.
104 */
105static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
106{
107 int i;
108
109 /* Let pending transmits finish. */
110 for (i = 0; i < 1000; i++) {
111 unsigned char stat = read_zsreg(uap, R1);
112 if (stat & ALL_SNT)
113 break;
114 udelay(100);
115 }
116
117 ZS_CLEARERR(uap);
118 zssync(uap);
119 ZS_CLEARFIFO(uap);
120 zssync(uap);
121 ZS_CLEARERR(uap);
122
123 /* Disable all interrupts. */
124 write_zsreg(uap, R1,
125 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
126
127 /* Set parity, sync config, stop bits, and clock divisor. */
128 write_zsreg(uap, R4, regs[R4]);
129
130 /* Set misc. TX/RX control bits. */
131 write_zsreg(uap, R10, regs[R10]);
132
133 /* Set TX/RX controls sans the enable bits. */
134 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
136
137 /* now set R7 "prime" on ESCC */
138 write_zsreg(uap, R15, regs[R15] | EN85C30);
139 write_zsreg(uap, R7, regs[R7P]);
140
141 /* make sure we use R7 "non-prime" on ESCC */
142 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
143
144 /* Synchronous mode config. */
145 write_zsreg(uap, R6, regs[R6]);
146 write_zsreg(uap, R7, regs[R7]);
147
148 /* Disable baud generator. */
149 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
150
151 /* Clock mode control. */
152 write_zsreg(uap, R11, regs[R11]);
153
154 /* Lower and upper byte of baud rate generator divisor. */
155 write_zsreg(uap, R12, regs[R12]);
156 write_zsreg(uap, R13, regs[R13]);
157
158 /* Now rewrite R14, with BRENAB (if set). */
159 write_zsreg(uap, R14, regs[R14]);
160
161 /* Reset external status interrupts. */
162 write_zsreg(uap, R0, RES_EXT_INT);
163 write_zsreg(uap, R0, RES_EXT_INT);
164
165 /* Rewrite R3/R5, this time without enables masked. */
166 write_zsreg(uap, R3, regs[R3]);
167 write_zsreg(uap, R5, regs[R5]);
168
169 /* Rewrite R1, this time without IRQ enabled masked. */
170 write_zsreg(uap, R1, regs[R1]);
171
172 /* Enable interrupts */
173 write_zsreg(uap, R9, regs[R9]);
174}
175
176/*
177 * We do like sunzilog to avoid disrupting pending Tx
178 * Reprogram the Zilog channel HW registers with the copies found in the
179 * software state struct. If the transmitter is busy, we defer this update
180 * until the next TX complete interrupt. Else, we do it right now.
181 *
182 * The UART port lock must be held and local interrupts disabled.
183 */
184static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
185{
186 if (!ZS_REGS_HELD(uap)) {
187 if (ZS_TX_ACTIVE(uap)) {
188 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
189 } else {
190 pmz_debug("pmz: maybe_update_regs: updating\n");
191 pmz_load_zsregs(uap, uap->curregs);
192 }
193 }
194}
195
196static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
197{
198 if (enable) {
199 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
200 if (!ZS_IS_EXTCLK(uap))
201 uap->curregs[1] |= EXT_INT_ENAB;
202 } else {
203 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
204 }
205 write_zsreg(uap, R1, uap->curregs[1]);
206}
207
208static bool pmz_receive_chars(struct uart_pmac_port *uap)
209 __must_hold(&uap->port.lock)
210{
211 struct tty_port *port;
212 unsigned char ch, r1, drop, flag;
213
214 /* Sanity check, make sure the old bug is no longer happening */
215 if (uap->port.state == NULL) {
216 WARN_ON(1);
217 (void)read_zsdata(uap);
218 return false;
219 }
220 port = &uap->port.state->port;
221
222 while (1) {
223 drop = 0;
224
225 r1 = read_zsreg(uap, R1);
226 ch = read_zsdata(uap);
227
228 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
229 write_zsreg(uap, R0, ERR_RES);
230 zssync(uap);
231 }
232
233 ch &= uap->parity_mask;
234 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
235 uap->flags &= ~PMACZILOG_FLAG_BREAK;
236 }
237
238#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
239#ifdef USE_CTRL_O_SYSRQ
240 /* Handle the SysRq ^O Hack */
241 if (ch == '\x0f') {
242 uap->port.sysrq = jiffies + HZ*5;
243 goto next_char;
244 }
245#endif /* USE_CTRL_O_SYSRQ */
246 if (uap->port.sysrq) {
247 int swallow;
248 uart_port_unlock(&uap->port);
249 swallow = uart_handle_sysrq_char(&uap->port, ch);
250 uart_port_lock(&uap->port);
251 if (swallow)
252 goto next_char;
253 }
254#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
255
256 /* A real serial line, record the character and status. */
257 if (drop)
258 goto next_char;
259
260 flag = TTY_NORMAL;
261 uap->port.icount.rx++;
262
263 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
264 if (r1 & BRK_ABRT) {
265 pmz_debug("pmz: got break !\n");
266 r1 &= ~(PAR_ERR | CRC_ERR);
267 uap->port.icount.brk++;
268 if (uart_handle_break(&uap->port))
269 goto next_char;
270 }
271 else if (r1 & PAR_ERR)
272 uap->port.icount.parity++;
273 else if (r1 & CRC_ERR)
274 uap->port.icount.frame++;
275 if (r1 & Rx_OVR)
276 uap->port.icount.overrun++;
277 r1 &= uap->port.read_status_mask;
278 if (r1 & BRK_ABRT)
279 flag = TTY_BREAK;
280 else if (r1 & PAR_ERR)
281 flag = TTY_PARITY;
282 else if (r1 & CRC_ERR)
283 flag = TTY_FRAME;
284 }
285
286 if (uap->port.ignore_status_mask == 0xff ||
287 (r1 & uap->port.ignore_status_mask) == 0) {
288 tty_insert_flip_char(port, ch, flag);
289 }
290 if (r1 & Rx_OVR)
291 tty_insert_flip_char(port, 0, TTY_OVERRUN);
292 next_char:
293 ch = read_zsreg(uap, R0);
294 if (!(ch & Rx_CH_AV))
295 break;
296 }
297
298 return true;
299}
300
301static void pmz_status_handle(struct uart_pmac_port *uap)
302{
303 unsigned char status;
304
305 status = read_zsreg(uap, R0);
306 write_zsreg(uap, R0, RES_EXT_INT);
307 zssync(uap);
308
309 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
310 if (status & SYNC_HUNT)
311 uap->port.icount.dsr++;
312
313 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
314 * But it does not tell us which bit has changed, we have to keep
315 * track of this ourselves.
316 * The CTS input is inverted for some reason. -- paulus
317 */
318 if ((status ^ uap->prev_status) & DCD)
319 uart_handle_dcd_change(&uap->port,
320 (status & DCD));
321 if ((status ^ uap->prev_status) & CTS)
322 uart_handle_cts_change(&uap->port,
323 !(status & CTS));
324
325 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
326 }
327
328 if (status & BRK_ABRT)
329 uap->flags |= PMACZILOG_FLAG_BREAK;
330
331 uap->prev_status = status;
332}
333
334static void pmz_transmit_chars(struct uart_pmac_port *uap)
335{
336 struct circ_buf *xmit;
337
338 if (ZS_IS_CONS(uap)) {
339 unsigned char status = read_zsreg(uap, R0);
340
341 /* TX still busy? Just wait for the next TX done interrupt.
342 *
343 * It can occur because of how we do serial console writes. It would
344 * be nice to transmit console writes just like we normally would for
345 * a TTY line. (ie. buffered and TX interrupt driven). That is not
346 * easy because console writes cannot sleep. One solution might be
347 * to poll on enough port->xmit space becoming free. -DaveM
348 */
349 if (!(status & Tx_BUF_EMP))
350 return;
351 }
352
353 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
354
355 if (ZS_REGS_HELD(uap)) {
356 pmz_load_zsregs(uap, uap->curregs);
357 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
358 }
359
360 if (ZS_TX_STOPPED(uap)) {
361 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
362 goto ack_tx_int;
363 }
364
365 /* Under some circumstances, we see interrupts reported for
366 * a closed channel. The interrupt mask in R1 is clear, but
367 * R3 still signals the interrupts and we see them when taking
368 * an interrupt for the other channel (this could be a qemu
369 * bug but since the ESCC doc doesn't specify precsiely whether
370 * R3 interrup status bits are masked by R1 interrupt enable
371 * bits, better safe than sorry). --BenH.
372 */
373 if (!ZS_IS_OPEN(uap))
374 goto ack_tx_int;
375
376 if (uap->port.x_char) {
377 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
378 write_zsdata(uap, uap->port.x_char);
379 zssync(uap);
380 uap->port.icount.tx++;
381 uap->port.x_char = 0;
382 return;
383 }
384
385 if (uap->port.state == NULL)
386 goto ack_tx_int;
387 xmit = &uap->port.state->xmit;
388 if (uart_circ_empty(xmit)) {
389 uart_write_wakeup(&uap->port);
390 goto ack_tx_int;
391 }
392 if (uart_tx_stopped(&uap->port))
393 goto ack_tx_int;
394
395 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
396 write_zsdata(uap, xmit->buf[xmit->tail]);
397 zssync(uap);
398
399 uart_xmit_advance(&uap->port, 1);
400
401 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
402 uart_write_wakeup(&uap->port);
403
404 return;
405
406ack_tx_int:
407 write_zsreg(uap, R0, RES_Tx_P);
408 zssync(uap);
409}
410
411/* Hrm... we register that twice, fixme later.... */
412static irqreturn_t pmz_interrupt(int irq, void *dev_id)
413{
414 struct uart_pmac_port *uap = dev_id;
415 struct uart_pmac_port *uap_a;
416 struct uart_pmac_port *uap_b;
417 int rc = IRQ_NONE;
418 bool push;
419 u8 r3;
420
421 uap_a = pmz_get_port_A(uap);
422 uap_b = uap_a->mate;
423
424 uart_port_lock(&uap_a->port);
425 r3 = read_zsreg(uap_a, R3);
426
427 /* Channel A */
428 push = false;
429 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
430 if (!ZS_IS_OPEN(uap_a)) {
431 pmz_debug("ChanA interrupt while not open !\n");
432 goto skip_a;
433 }
434 write_zsreg(uap_a, R0, RES_H_IUS);
435 zssync(uap_a);
436 if (r3 & CHAEXT)
437 pmz_status_handle(uap_a);
438 if (r3 & CHARxIP)
439 push = pmz_receive_chars(uap_a);
440 if (r3 & CHATxIP)
441 pmz_transmit_chars(uap_a);
442 rc = IRQ_HANDLED;
443 }
444 skip_a:
445 uart_port_unlock(&uap_a->port);
446 if (push)
447 tty_flip_buffer_push(&uap->port.state->port);
448
449 if (!uap_b)
450 goto out;
451
452 uart_port_lock(&uap_b->port);
453 push = false;
454 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
455 if (!ZS_IS_OPEN(uap_b)) {
456 pmz_debug("ChanB interrupt while not open !\n");
457 goto skip_b;
458 }
459 write_zsreg(uap_b, R0, RES_H_IUS);
460 zssync(uap_b);
461 if (r3 & CHBEXT)
462 pmz_status_handle(uap_b);
463 if (r3 & CHBRxIP)
464 push = pmz_receive_chars(uap_b);
465 if (r3 & CHBTxIP)
466 pmz_transmit_chars(uap_b);
467 rc = IRQ_HANDLED;
468 }
469 skip_b:
470 uart_port_unlock(&uap_b->port);
471 if (push)
472 tty_flip_buffer_push(&uap->port.state->port);
473
474 out:
475 return rc;
476}
477
478/*
479 * Peek the status register, lock not held by caller
480 */
481static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
482{
483 unsigned long flags;
484 u8 status;
485
486 uart_port_lock_irqsave(&uap->port, &flags);
487 status = read_zsreg(uap, R0);
488 uart_port_unlock_irqrestore(&uap->port, flags);
489
490 return status;
491}
492
493/*
494 * Check if transmitter is empty
495 * The port lock is not held.
496 */
497static unsigned int pmz_tx_empty(struct uart_port *port)
498{
499 unsigned char status;
500
501 status = pmz_peek_status(to_pmz(port));
502 if (status & Tx_BUF_EMP)
503 return TIOCSER_TEMT;
504 return 0;
505}
506
507/*
508 * Set Modem Control (RTS & DTR) bits
509 * The port lock is held and interrupts are disabled.
510 * Note: Shall we really filter out RTS on external ports or
511 * should that be dealt at higher level only ?
512 */
513static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
514{
515 struct uart_pmac_port *uap = to_pmz(port);
516 unsigned char set_bits, clear_bits;
517
518 /* Do nothing for irda for now... */
519 if (ZS_IS_IRDA(uap))
520 return;
521 /* We get called during boot with a port not up yet */
522 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
523 return;
524
525 set_bits = clear_bits = 0;
526
527 if (ZS_IS_INTMODEM(uap)) {
528 if (mctrl & TIOCM_RTS)
529 set_bits |= RTS;
530 else
531 clear_bits |= RTS;
532 }
533 if (mctrl & TIOCM_DTR)
534 set_bits |= DTR;
535 else
536 clear_bits |= DTR;
537
538 /* NOTE: Not subject to 'transmitter active' rule. */
539 uap->curregs[R5] |= set_bits;
540 uap->curregs[R5] &= ~clear_bits;
541
542 write_zsreg(uap, R5, uap->curregs[R5]);
543 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
544 set_bits, clear_bits, uap->curregs[R5]);
545 zssync(uap);
546}
547
548/*
549 * Get Modem Control bits (only the input ones, the core will
550 * or that with a cached value of the control ones)
551 * The port lock is held and interrupts are disabled.
552 */
553static unsigned int pmz_get_mctrl(struct uart_port *port)
554{
555 struct uart_pmac_port *uap = to_pmz(port);
556 unsigned char status;
557 unsigned int ret;
558
559 status = read_zsreg(uap, R0);
560
561 ret = 0;
562 if (status & DCD)
563 ret |= TIOCM_CAR;
564 if (status & SYNC_HUNT)
565 ret |= TIOCM_DSR;
566 if (!(status & CTS))
567 ret |= TIOCM_CTS;
568
569 return ret;
570}
571
572/*
573 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
574 * though for DMA, we will have to do a bit more.
575 * The port lock is held and interrupts are disabled.
576 */
577static void pmz_stop_tx(struct uart_port *port)
578{
579 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
580}
581
582/*
583 * Kick the Tx side.
584 * The port lock is held and interrupts are disabled.
585 */
586static void pmz_start_tx(struct uart_port *port)
587{
588 struct uart_pmac_port *uap = to_pmz(port);
589 unsigned char status;
590
591 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
592 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
593
594 status = read_zsreg(uap, R0);
595
596 /* TX busy? Just wait for the TX done interrupt. */
597 if (!(status & Tx_BUF_EMP))
598 return;
599
600 /* Send the first character to jump-start the TX done
601 * IRQ sending engine.
602 */
603 if (port->x_char) {
604 write_zsdata(uap, port->x_char);
605 zssync(uap);
606 port->icount.tx++;
607 port->x_char = 0;
608 } else {
609 struct circ_buf *xmit = &port->state->xmit;
610
611 if (uart_circ_empty(xmit))
612 return;
613 write_zsdata(uap, xmit->buf[xmit->tail]);
614 zssync(uap);
615 uart_xmit_advance(port, 1);
616
617 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
618 uart_write_wakeup(&uap->port);
619 }
620}
621
622/*
623 * Stop Rx side, basically disable emitting of
624 * Rx interrupts on the port. We don't disable the rx
625 * side of the chip proper though
626 * The port lock is held.
627 */
628static void pmz_stop_rx(struct uart_port *port)
629{
630 struct uart_pmac_port *uap = to_pmz(port);
631
632 /* Disable all RX interrupts. */
633 uap->curregs[R1] &= ~RxINT_MASK;
634 pmz_maybe_update_regs(uap);
635}
636
637/*
638 * Enable modem status change interrupts
639 * The port lock is held.
640 */
641static void pmz_enable_ms(struct uart_port *port)
642{
643 struct uart_pmac_port *uap = to_pmz(port);
644 unsigned char new_reg;
645
646 if (ZS_IS_IRDA(uap))
647 return;
648 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
649 if (new_reg != uap->curregs[R15]) {
650 uap->curregs[R15] = new_reg;
651
652 /* NOTE: Not subject to 'transmitter active' rule. */
653 write_zsreg(uap, R15, uap->curregs[R15]);
654 }
655}
656
657/*
658 * Control break state emission
659 * The port lock is not held.
660 */
661static void pmz_break_ctl(struct uart_port *port, int break_state)
662{
663 struct uart_pmac_port *uap = to_pmz(port);
664 unsigned char set_bits, clear_bits, new_reg;
665 unsigned long flags;
666
667 set_bits = clear_bits = 0;
668
669 if (break_state)
670 set_bits |= SND_BRK;
671 else
672 clear_bits |= SND_BRK;
673
674 uart_port_lock_irqsave(port, &flags);
675
676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
677 if (new_reg != uap->curregs[R5]) {
678 uap->curregs[R5] = new_reg;
679 write_zsreg(uap, R5, uap->curregs[R5]);
680 }
681
682 uart_port_unlock_irqrestore(port, flags);
683}
684
685#ifdef CONFIG_PPC_PMAC
686
687/*
688 * Turn power on or off to the SCC and associated stuff
689 * (port drivers, modem, IR port, etc.)
690 * Returns the number of milliseconds we should wait before
691 * trying to use the port.
692 */
693static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
694{
695 int delay = 0;
696 int rc;
697
698 if (state) {
699 rc = pmac_call_feature(
700 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
701 pmz_debug("port power on result: %d\n", rc);
702 if (ZS_IS_INTMODEM(uap)) {
703 rc = pmac_call_feature(
704 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
705 delay = 2500; /* wait for 2.5s before using */
706 pmz_debug("modem power result: %d\n", rc);
707 }
708 } else {
709 /* TODO: Make that depend on a timer, don't power down
710 * immediately
711 */
712 if (ZS_IS_INTMODEM(uap)) {
713 rc = pmac_call_feature(
714 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
715 pmz_debug("port power off result: %d\n", rc);
716 }
717 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
718 }
719 return delay;
720}
721
722#else
723
724static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
725{
726 return 0;
727}
728
729#endif /* !CONFIG_PPC_PMAC */
730
731/*
732 * FixZeroBug....Works around a bug in the SCC receiving channel.
733 * Inspired from Darwin code, 15 Sept. 2000 -DanM
734 *
735 * The following sequence prevents a problem that is seen with O'Hare ASICs
736 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
737 * at the input to the receiver becomes 'stuck' and locks up the receiver.
738 * This problem can occur as a result of a zero bit at the receiver input
739 * coincident with any of the following events:
740 *
741 * The SCC is initialized (hardware or software).
742 * A framing error is detected.
743 * The clocking option changes from synchronous or X1 asynchronous
744 * clocking to X16, X32, or X64 asynchronous clocking.
745 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
746 *
747 * This workaround attempts to recover from the lockup condition by placing
748 * the SCC in synchronous loopback mode with a fast clock before programming
749 * any of the asynchronous modes.
750 */
751static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
752{
753 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
754 zssync(uap);
755 udelay(10);
756 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
757 zssync(uap);
758
759 write_zsreg(uap, 4, X1CLK | MONSYNC);
760 write_zsreg(uap, 3, Rx8);
761 write_zsreg(uap, 5, Tx8 | RTS);
762 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
763 write_zsreg(uap, 11, RCBR | TCBR);
764 write_zsreg(uap, 12, 0);
765 write_zsreg(uap, 13, 0);
766 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
767 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
768 write_zsreg(uap, 3, Rx8 | RxENABLE);
769 write_zsreg(uap, 0, RES_EXT_INT);
770 write_zsreg(uap, 0, RES_EXT_INT);
771 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
772
773 /* The channel should be OK now, but it is probably receiving
774 * loopback garbage.
775 * Switch to asynchronous mode, disable the receiver,
776 * and discard everything in the receive buffer.
777 */
778 write_zsreg(uap, 9, NV);
779 write_zsreg(uap, 4, X16CLK | SB_MASK);
780 write_zsreg(uap, 3, Rx8);
781
782 while (read_zsreg(uap, 0) & Rx_CH_AV) {
783 (void)read_zsreg(uap, 8);
784 write_zsreg(uap, 0, RES_EXT_INT);
785 write_zsreg(uap, 0, ERR_RES);
786 }
787}
788
789/*
790 * Real startup routine, powers up the hardware and sets up
791 * the SCC. Returns a delay in ms where you need to wait before
792 * actually using the port, this is typically the internal modem
793 * powerup delay. This routine expect the lock to be taken.
794 */
795static int __pmz_startup(struct uart_pmac_port *uap)
796{
797 int pwr_delay = 0;
798
799 memset(&uap->curregs, 0, sizeof(uap->curregs));
800
801 /* Power up the SCC & underlying hardware (modem/irda) */
802 pwr_delay = pmz_set_scc_power(uap, 1);
803
804 /* Nice buggy HW ... */
805 pmz_fix_zero_bug_scc(uap);
806
807 /* Reset the channel */
808 uap->curregs[R9] = 0;
809 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
810 zssync(uap);
811 udelay(10);
812 write_zsreg(uap, 9, 0);
813 zssync(uap);
814
815 /* Clear the interrupt registers */
816 write_zsreg(uap, R1, 0);
817 write_zsreg(uap, R0, ERR_RES);
818 write_zsreg(uap, R0, ERR_RES);
819 write_zsreg(uap, R0, RES_H_IUS);
820 write_zsreg(uap, R0, RES_H_IUS);
821
822 /* Setup some valid baud rate */
823 uap->curregs[R4] = X16CLK | SB1;
824 uap->curregs[R3] = Rx8;
825 uap->curregs[R5] = Tx8 | RTS;
826 if (!ZS_IS_IRDA(uap))
827 uap->curregs[R5] |= DTR;
828 uap->curregs[R12] = 0;
829 uap->curregs[R13] = 0;
830 uap->curregs[R14] = BRENAB;
831
832 /* Clear handshaking, enable BREAK interrupts */
833 uap->curregs[R15] = BRKIE;
834
835 /* Master interrupt enable */
836 uap->curregs[R9] |= NV | MIE;
837
838 pmz_load_zsregs(uap, uap->curregs);
839
840 /* Enable receiver and transmitter. */
841 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
842 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
843
844 /* Remember status for DCD/CTS changes */
845 uap->prev_status = read_zsreg(uap, R0);
846
847 return pwr_delay;
848}
849
850static void pmz_irda_reset(struct uart_pmac_port *uap)
851{
852 unsigned long flags;
853
854 uart_port_lock_irqsave(&uap->port, &flags);
855 uap->curregs[R5] |= DTR;
856 write_zsreg(uap, R5, uap->curregs[R5]);
857 zssync(uap);
858 uart_port_unlock_irqrestore(&uap->port, flags);
859 msleep(110);
860
861 uart_port_lock_irqsave(&uap->port, &flags);
862 uap->curregs[R5] &= ~DTR;
863 write_zsreg(uap, R5, uap->curregs[R5]);
864 zssync(uap);
865 uart_port_unlock_irqrestore(&uap->port, flags);
866 msleep(10);
867}
868
869/*
870 * This is the "normal" startup routine, using the above one
871 * wrapped with the lock and doing a schedule delay
872 */
873static int pmz_startup(struct uart_port *port)
874{
875 struct uart_pmac_port *uap = to_pmz(port);
876 unsigned long flags;
877 int pwr_delay = 0;
878
879 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
880
881 /* A console is never powered down. Else, power up and
882 * initialize the chip
883 */
884 if (!ZS_IS_CONS(uap)) {
885 uart_port_lock_irqsave(port, &flags);
886 pwr_delay = __pmz_startup(uap);
887 uart_port_unlock_irqrestore(port, flags);
888 }
889 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
890 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
891 uap->irq_name, uap)) {
892 pmz_error("Unable to register zs interrupt handler.\n");
893 pmz_set_scc_power(uap, 0);
894 return -ENXIO;
895 }
896
897 /* Right now, we deal with delay by blocking here, I'll be
898 * smarter later on
899 */
900 if (pwr_delay != 0) {
901 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
902 msleep(pwr_delay);
903 }
904
905 /* IrDA reset is done now */
906 if (ZS_IS_IRDA(uap))
907 pmz_irda_reset(uap);
908
909 /* Enable interrupt requests for the channel */
910 uart_port_lock_irqsave(port, &flags);
911 pmz_interrupt_control(uap, 1);
912 uart_port_unlock_irqrestore(port, flags);
913
914 return 0;
915}
916
917static void pmz_shutdown(struct uart_port *port)
918{
919 struct uart_pmac_port *uap = to_pmz(port);
920 unsigned long flags;
921
922 uart_port_lock_irqsave(port, &flags);
923
924 /* Disable interrupt requests for the channel */
925 pmz_interrupt_control(uap, 0);
926
927 if (!ZS_IS_CONS(uap)) {
928 /* Disable receiver and transmitter */
929 uap->curregs[R3] &= ~RxENABLE;
930 uap->curregs[R5] &= ~TxENABLE;
931
932 /* Disable break assertion */
933 uap->curregs[R5] &= ~SND_BRK;
934 pmz_maybe_update_regs(uap);
935 }
936
937 uart_port_unlock_irqrestore(port, flags);
938
939 /* Release interrupt handler */
940 free_irq(uap->port.irq, uap);
941
942 uart_port_lock_irqsave(port, &flags);
943
944 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
945
946 if (!ZS_IS_CONS(uap))
947 pmz_set_scc_power(uap, 0); /* Shut the chip down */
948
949 uart_port_unlock_irqrestore(port, flags);
950}
951
952/* Shared by TTY driver and serial console setup. The port lock is held
953 * and local interrupts are disabled.
954 */
955static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
956 unsigned int iflag, unsigned long baud)
957{
958 int brg;
959
960 /* Switch to external clocking for IrDA high clock rates. That
961 * code could be re-used for Midi interfaces with different
962 * multipliers
963 */
964 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
965 uap->curregs[R4] = X1CLK;
966 uap->curregs[R11] = RCTRxCP | TCTRxCP;
967 uap->curregs[R14] = 0; /* BRG off */
968 uap->curregs[R12] = 0;
969 uap->curregs[R13] = 0;
970 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
971 } else {
972 switch (baud) {
973 case ZS_CLOCK/16: /* 230400 */
974 uap->curregs[R4] = X16CLK;
975 uap->curregs[R11] = 0;
976 uap->curregs[R14] = 0;
977 break;
978 case ZS_CLOCK/32: /* 115200 */
979 uap->curregs[R4] = X32CLK;
980 uap->curregs[R11] = 0;
981 uap->curregs[R14] = 0;
982 break;
983 default:
984 uap->curregs[R4] = X16CLK;
985 uap->curregs[R11] = TCBR | RCBR;
986 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
987 uap->curregs[R12] = (brg & 255);
988 uap->curregs[R13] = ((brg >> 8) & 255);
989 uap->curregs[R14] = BRENAB;
990 }
991 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
992 }
993
994 /* Character size, stop bits, and parity. */
995 uap->curregs[3] &= ~RxN_MASK;
996 uap->curregs[5] &= ~TxN_MASK;
997
998 switch (cflag & CSIZE) {
999 case CS5:
1000 uap->curregs[3] |= Rx5;
1001 uap->curregs[5] |= Tx5;
1002 uap->parity_mask = 0x1f;
1003 break;
1004 case CS6:
1005 uap->curregs[3] |= Rx6;
1006 uap->curregs[5] |= Tx6;
1007 uap->parity_mask = 0x3f;
1008 break;
1009 case CS7:
1010 uap->curregs[3] |= Rx7;
1011 uap->curregs[5] |= Tx7;
1012 uap->parity_mask = 0x7f;
1013 break;
1014 case CS8:
1015 default:
1016 uap->curregs[3] |= Rx8;
1017 uap->curregs[5] |= Tx8;
1018 uap->parity_mask = 0xff;
1019 break;
1020 }
1021 uap->curregs[4] &= ~(SB_MASK);
1022 if (cflag & CSTOPB)
1023 uap->curregs[4] |= SB2;
1024 else
1025 uap->curregs[4] |= SB1;
1026 if (cflag & PARENB)
1027 uap->curregs[4] |= PAR_ENAB;
1028 else
1029 uap->curregs[4] &= ~PAR_ENAB;
1030 if (!(cflag & PARODD))
1031 uap->curregs[4] |= PAR_EVEN;
1032 else
1033 uap->curregs[4] &= ~PAR_EVEN;
1034
1035 uap->port.read_status_mask = Rx_OVR;
1036 if (iflag & INPCK)
1037 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1038 if (iflag & (IGNBRK | BRKINT | PARMRK))
1039 uap->port.read_status_mask |= BRK_ABRT;
1040
1041 uap->port.ignore_status_mask = 0;
1042 if (iflag & IGNPAR)
1043 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1044 if (iflag & IGNBRK) {
1045 uap->port.ignore_status_mask |= BRK_ABRT;
1046 if (iflag & IGNPAR)
1047 uap->port.ignore_status_mask |= Rx_OVR;
1048 }
1049
1050 if ((cflag & CREAD) == 0)
1051 uap->port.ignore_status_mask = 0xff;
1052}
1053
1054
1055/*
1056 * Set the irda codec on the imac to the specified baud rate.
1057 */
1058static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1059{
1060 u8 cmdbyte;
1061 int t, version;
1062
1063 switch (*baud) {
1064 /* SIR modes */
1065 case 2400:
1066 cmdbyte = 0x53;
1067 break;
1068 case 4800:
1069 cmdbyte = 0x52;
1070 break;
1071 case 9600:
1072 cmdbyte = 0x51;
1073 break;
1074 case 19200:
1075 cmdbyte = 0x50;
1076 break;
1077 case 38400:
1078 cmdbyte = 0x4f;
1079 break;
1080 case 57600:
1081 cmdbyte = 0x4e;
1082 break;
1083 case 115200:
1084 cmdbyte = 0x4d;
1085 break;
1086 /* The FIR modes aren't really supported at this point, how
1087 * do we select the speed ? via the FCR on KeyLargo ?
1088 */
1089 case 1152000:
1090 cmdbyte = 0;
1091 break;
1092 case 4000000:
1093 cmdbyte = 0;
1094 break;
1095 default: /* 9600 */
1096 cmdbyte = 0x51;
1097 *baud = 9600;
1098 break;
1099 }
1100
1101 /* Wait for transmitter to drain */
1102 t = 10000;
1103 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1104 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1105 if (--t <= 0) {
1106 pmz_error("transmitter didn't drain\n");
1107 return;
1108 }
1109 udelay(10);
1110 }
1111
1112 /* Drain the receiver too */
1113 t = 100;
1114 (void)read_zsdata(uap);
1115 (void)read_zsdata(uap);
1116 (void)read_zsdata(uap);
1117 mdelay(10);
1118 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1119 read_zsdata(uap);
1120 mdelay(10);
1121 if (--t <= 0) {
1122 pmz_error("receiver didn't drain\n");
1123 return;
1124 }
1125 }
1126
1127 /* Switch to command mode */
1128 uap->curregs[R5] |= DTR;
1129 write_zsreg(uap, R5, uap->curregs[R5]);
1130 zssync(uap);
1131 mdelay(1);
1132
1133 /* Switch SCC to 19200 */
1134 pmz_convert_to_zs(uap, CS8, 0, 19200);
1135 pmz_load_zsregs(uap, uap->curregs);
1136 mdelay(1);
1137
1138 /* Write get_version command byte */
1139 write_zsdata(uap, 1);
1140 t = 5000;
1141 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1142 if (--t <= 0) {
1143 pmz_error("irda_setup timed out on get_version byte\n");
1144 goto out;
1145 }
1146 udelay(10);
1147 }
1148 version = read_zsdata(uap);
1149
1150 if (version < 4) {
1151 pmz_info("IrDA: dongle version %d not supported\n", version);
1152 goto out;
1153 }
1154
1155 /* Send speed mode */
1156 write_zsdata(uap, cmdbyte);
1157 t = 5000;
1158 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1159 if (--t <= 0) {
1160 pmz_error("irda_setup timed out on speed mode byte\n");
1161 goto out;
1162 }
1163 udelay(10);
1164 }
1165 t = read_zsdata(uap);
1166 if (t != cmdbyte)
1167 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1168
1169 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1170 *baud, version);
1171
1172 (void)read_zsdata(uap);
1173 (void)read_zsdata(uap);
1174 (void)read_zsdata(uap);
1175
1176 out:
1177 /* Switch back to data mode */
1178 uap->curregs[R5] &= ~DTR;
1179 write_zsreg(uap, R5, uap->curregs[R5]);
1180 zssync(uap);
1181
1182 (void)read_zsdata(uap);
1183 (void)read_zsdata(uap);
1184 (void)read_zsdata(uap);
1185}
1186
1187
1188static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1189 const struct ktermios *old)
1190{
1191 struct uart_pmac_port *uap = to_pmz(port);
1192 unsigned long baud;
1193
1194 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1195 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1196 * about the FIR mode and high speed modes. So these are unused. For
1197 * implementing proper support for these, we should probably add some
1198 * DMA as well, at least on the Rx side, which isn't a simple thing
1199 * at this point.
1200 */
1201 if (ZS_IS_IRDA(uap)) {
1202 /* Calc baud rate */
1203 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1204 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1205 /* Cet the irda codec to the right rate */
1206 pmz_irda_setup(uap, &baud);
1207 /* Set final baud rate */
1208 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1209 pmz_load_zsregs(uap, uap->curregs);
1210 zssync(uap);
1211 } else {
1212 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1213 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1214 /* Make sure modem status interrupts are correctly configured */
1215 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1216 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1217 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1218 } else {
1219 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1220 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1221 }
1222
1223 /* Load registers to the chip */
1224 pmz_maybe_update_regs(uap);
1225 }
1226 uart_update_timeout(port, termios->c_cflag, baud);
1227}
1228
1229/* The port lock is not held. */
1230static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1231 const struct ktermios *old)
1232{
1233 struct uart_pmac_port *uap = to_pmz(port);
1234 unsigned long flags;
1235
1236 uart_port_lock_irqsave(port, &flags);
1237
1238 /* Disable IRQs on the port */
1239 pmz_interrupt_control(uap, 0);
1240
1241 /* Setup new port configuration */
1242 __pmz_set_termios(port, termios, old);
1243
1244 /* Re-enable IRQs on the port */
1245 if (ZS_IS_OPEN(uap))
1246 pmz_interrupt_control(uap, 1);
1247
1248 uart_port_unlock_irqrestore(port, flags);
1249}
1250
1251static const char *pmz_type(struct uart_port *port)
1252{
1253 struct uart_pmac_port *uap = to_pmz(port);
1254
1255 if (ZS_IS_IRDA(uap))
1256 return "Z85c30 ESCC - Infrared port";
1257 else if (ZS_IS_INTMODEM(uap))
1258 return "Z85c30 ESCC - Internal modem";
1259 return "Z85c30 ESCC - Serial port";
1260}
1261
1262/* We do not request/release mappings of the registers here, this
1263 * happens at early serial probe time.
1264 */
1265static void pmz_release_port(struct uart_port *port)
1266{
1267}
1268
1269static int pmz_request_port(struct uart_port *port)
1270{
1271 return 0;
1272}
1273
1274/* These do not need to do anything interesting either. */
1275static void pmz_config_port(struct uart_port *port, int flags)
1276{
1277}
1278
1279/* We do not support letting the user mess with the divisor, IRQ, etc. */
1280static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1281{
1282 return -EINVAL;
1283}
1284
1285#ifdef CONFIG_CONSOLE_POLL
1286
1287static int pmz_poll_get_char(struct uart_port *port)
1288{
1289 struct uart_pmac_port *uap =
1290 container_of(port, struct uart_pmac_port, port);
1291 int tries = 2;
1292
1293 while (tries) {
1294 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1295 return read_zsdata(uap);
1296 if (tries--)
1297 udelay(5);
1298 }
1299
1300 return NO_POLL_CHAR;
1301}
1302
1303static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1304{
1305 struct uart_pmac_port *uap =
1306 container_of(port, struct uart_pmac_port, port);
1307
1308 /* Wait for the transmit buffer to empty. */
1309 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1310 udelay(5);
1311 write_zsdata(uap, c);
1312}
1313
1314#endif /* CONFIG_CONSOLE_POLL */
1315
1316static const struct uart_ops pmz_pops = {
1317 .tx_empty = pmz_tx_empty,
1318 .set_mctrl = pmz_set_mctrl,
1319 .get_mctrl = pmz_get_mctrl,
1320 .stop_tx = pmz_stop_tx,
1321 .start_tx = pmz_start_tx,
1322 .stop_rx = pmz_stop_rx,
1323 .enable_ms = pmz_enable_ms,
1324 .break_ctl = pmz_break_ctl,
1325 .startup = pmz_startup,
1326 .shutdown = pmz_shutdown,
1327 .set_termios = pmz_set_termios,
1328 .type = pmz_type,
1329 .release_port = pmz_release_port,
1330 .request_port = pmz_request_port,
1331 .config_port = pmz_config_port,
1332 .verify_port = pmz_verify_port,
1333#ifdef CONFIG_CONSOLE_POLL
1334 .poll_get_char = pmz_poll_get_char,
1335 .poll_put_char = pmz_poll_put_char,
1336#endif
1337};
1338
1339#ifdef CONFIG_PPC_PMAC
1340
1341/*
1342 * Setup one port structure after probing, HW is down at this point,
1343 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1344 * register our console before uart_add_one_port() is called
1345 */
1346static int __init pmz_init_port(struct uart_pmac_port *uap)
1347{
1348 struct device_node *np = uap->node;
1349 const char *conn;
1350 const struct slot_names_prop {
1351 int count;
1352 char name[1];
1353 } *slots;
1354 int len;
1355 struct resource r_ports;
1356
1357 /*
1358 * Request & map chip registers
1359 */
1360 if (of_address_to_resource(np, 0, &r_ports))
1361 return -ENODEV;
1362 uap->port.mapbase = r_ports.start;
1363 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1364
1365 uap->control_reg = uap->port.membase;
1366 uap->data_reg = uap->control_reg + 0x10;
1367
1368 /*
1369 * Detect port type
1370 */
1371 if (of_device_is_compatible(np, "cobalt"))
1372 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1373 conn = of_get_property(np, "AAPL,connector", &len);
1374 if (conn && (strcmp(conn, "infrared") == 0))
1375 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1376 uap->port_type = PMAC_SCC_ASYNC;
1377 /* 1999 Powerbook G3 has slot-names property instead */
1378 slots = of_get_property(np, "slot-names", &len);
1379 if (slots && slots->count > 0) {
1380 if (strcmp(slots->name, "IrDA") == 0)
1381 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1382 else if (strcmp(slots->name, "Modem") == 0)
1383 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1384 }
1385 if (ZS_IS_IRDA(uap))
1386 uap->port_type = PMAC_SCC_IRDA;
1387 if (ZS_IS_INTMODEM(uap)) {
1388 struct device_node* i2c_modem =
1389 of_find_node_by_name(NULL, "i2c-modem");
1390 if (i2c_modem) {
1391 const char* mid =
1392 of_get_property(i2c_modem, "modem-id", NULL);
1393 if (mid) switch(*mid) {
1394 case 0x04 :
1395 case 0x05 :
1396 case 0x07 :
1397 case 0x08 :
1398 case 0x0b :
1399 case 0x0c :
1400 uap->port_type = PMAC_SCC_I2S1;
1401 }
1402 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1403 mid ? (*mid) : 0);
1404 of_node_put(i2c_modem);
1405 } else {
1406 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1407 }
1408 }
1409
1410 /*
1411 * Init remaining bits of "port" structure
1412 */
1413 uap->port.iotype = UPIO_MEM;
1414 uap->port.irq = irq_of_parse_and_map(np, 0);
1415 uap->port.uartclk = ZS_CLOCK;
1416 uap->port.fifosize = 1;
1417 uap->port.ops = &pmz_pops;
1418 uap->port.type = PORT_PMAC_ZILOG;
1419 uap->port.flags = 0;
1420
1421 /*
1422 * Fixup for the port on Gatwick for which the device-tree has
1423 * missing interrupts. Normally, the macio_dev would contain
1424 * fixed up interrupt info, but we use the device-tree directly
1425 * here due to early probing so we need the fixup too.
1426 */
1427 if (uap->port.irq == 0 &&
1428 np->parent && np->parent->parent &&
1429 of_device_is_compatible(np->parent->parent, "gatwick")) {
1430 /* IRQs on gatwick are offset by 64 */
1431 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1432 }
1433
1434 /* Setup some valid baud rate information in the register
1435 * shadows so we don't write crap there before baud rate is
1436 * first initialized.
1437 */
1438 pmz_convert_to_zs(uap, CS8, 0, 9600);
1439
1440 return 0;
1441}
1442
1443/*
1444 * Get rid of a port on module removal
1445 */
1446static void pmz_dispose_port(struct uart_pmac_port *uap)
1447{
1448 struct device_node *np;
1449
1450 np = uap->node;
1451 iounmap(uap->control_reg);
1452 uap->node = NULL;
1453 of_node_put(np);
1454 memset(uap, 0, sizeof(struct uart_pmac_port));
1455}
1456
1457/*
1458 * Called upon match with an escc node in the device-tree.
1459 */
1460static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1461{
1462 struct uart_pmac_port *uap;
1463 int i;
1464
1465 /* Iterate the pmz_ports array to find a matching entry
1466 */
1467 for (i = 0; i < MAX_ZS_PORTS; i++)
1468 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1469 break;
1470 if (i >= MAX_ZS_PORTS)
1471 return -ENODEV;
1472
1473
1474 uap = &pmz_ports[i];
1475 uap->dev = mdev;
1476 uap->port.dev = &mdev->ofdev.dev;
1477 dev_set_drvdata(&mdev->ofdev.dev, uap);
1478
1479 /* We still activate the port even when failing to request resources
1480 * to work around bugs in ancient Apple device-trees
1481 */
1482 if (macio_request_resources(uap->dev, "pmac_zilog"))
1483 printk(KERN_WARNING "%pOFn: Failed to request resource"
1484 ", port still active\n",
1485 uap->node);
1486 else
1487 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1488
1489 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1490}
1491
1492/*
1493 * That one should not be called, macio isn't really a hotswap device,
1494 * we don't expect one of those serial ports to go away...
1495 */
1496static void pmz_detach(struct macio_dev *mdev)
1497{
1498 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1499
1500 if (!uap)
1501 return;
1502
1503 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1504
1505 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1506 macio_release_resources(uap->dev);
1507 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1508 }
1509 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1510 uap->dev = NULL;
1511 uap->port.dev = NULL;
1512}
1513
1514static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1515{
1516 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1517
1518 if (uap == NULL) {
1519 printk("HRM... pmz_suspend with NULL uap\n");
1520 return 0;
1521 }
1522
1523 uart_suspend_port(&pmz_uart_reg, &uap->port);
1524
1525 return 0;
1526}
1527
1528
1529static int pmz_resume(struct macio_dev *mdev)
1530{
1531 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1532
1533 if (uap == NULL)
1534 return 0;
1535
1536 uart_resume_port(&pmz_uart_reg, &uap->port);
1537
1538 return 0;
1539}
1540
1541/*
1542 * Probe all ports in the system and build the ports array, we register
1543 * with the serial layer later, so we get a proper struct device which
1544 * allows the tty to attach properly. This is later than it used to be
1545 * but the tty layer really wants it that way.
1546 */
1547static int __init pmz_probe(void)
1548{
1549 struct device_node *node_p, *node_a, *node_b, *np;
1550 int count = 0;
1551 int rc;
1552
1553 /*
1554 * Find all escc chips in the system
1555 */
1556 for_each_node_by_name(node_p, "escc") {
1557 /*
1558 * First get channel A/B node pointers
1559 *
1560 * TODO: Add routines with proper locking to do that...
1561 */
1562 node_a = node_b = NULL;
1563 for_each_child_of_node(node_p, np) {
1564 if (of_node_name_prefix(np, "ch-a"))
1565 node_a = of_node_get(np);
1566 else if (of_node_name_prefix(np, "ch-b"))
1567 node_b = of_node_get(np);
1568 }
1569 if (!node_a && !node_b) {
1570 of_node_put(node_a);
1571 of_node_put(node_b);
1572 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1573 (!node_a) ? 'a' : 'b', node_p);
1574 continue;
1575 }
1576
1577 /*
1578 * Fill basic fields in the port structures
1579 */
1580 if (node_b != NULL) {
1581 pmz_ports[count].mate = &pmz_ports[count+1];
1582 pmz_ports[count+1].mate = &pmz_ports[count];
1583 }
1584 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1585 pmz_ports[count].node = node_a;
1586 pmz_ports[count+1].node = node_b;
1587 pmz_ports[count].port.line = count;
1588 pmz_ports[count+1].port.line = count+1;
1589
1590 /*
1591 * Setup the ports for real
1592 */
1593 rc = pmz_init_port(&pmz_ports[count]);
1594 if (rc == 0 && node_b != NULL)
1595 rc = pmz_init_port(&pmz_ports[count+1]);
1596 if (rc != 0) {
1597 of_node_put(node_a);
1598 of_node_put(node_b);
1599 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1600 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1601 continue;
1602 }
1603 count += 2;
1604 }
1605 pmz_ports_count = count;
1606
1607 return 0;
1608}
1609
1610#else
1611
1612/* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
1613 * tree to obtain the device_nodes needed to start the console before the
1614 * macio driver. On Macs without OpenFirmware, global platform_devices take
1615 * the place of those device_nodes.
1616 */
1617extern struct platform_device scc_a_pdev, scc_b_pdev;
1618
1619static int __init pmz_init_port(struct uart_pmac_port *uap)
1620{
1621 struct resource *r_ports;
1622 int irq;
1623
1624 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1625 if (!r_ports)
1626 return -ENODEV;
1627
1628 irq = platform_get_irq(uap->pdev, 0);
1629 if (irq < 0)
1630 return irq;
1631
1632 uap->port.mapbase = r_ports->start;
1633 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1634 uap->port.iotype = UPIO_MEM;
1635 uap->port.irq = irq;
1636 uap->port.uartclk = ZS_CLOCK;
1637 uap->port.fifosize = 1;
1638 uap->port.ops = &pmz_pops;
1639 uap->port.type = PORT_PMAC_ZILOG;
1640 uap->port.flags = 0;
1641
1642 uap->control_reg = uap->port.membase;
1643 uap->data_reg = uap->control_reg + 4;
1644 uap->port_type = 0;
1645 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1646
1647 pmz_convert_to_zs(uap, CS8, 0, 9600);
1648
1649 return 0;
1650}
1651
1652static int __init pmz_probe(void)
1653{
1654 int err;
1655
1656 pmz_ports_count = 0;
1657
1658 pmz_ports[0].port.line = 0;
1659 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1660 pmz_ports[0].pdev = &scc_a_pdev;
1661 err = pmz_init_port(&pmz_ports[0]);
1662 if (err)
1663 return err;
1664 pmz_ports_count++;
1665
1666 pmz_ports[0].mate = &pmz_ports[1];
1667 pmz_ports[1].mate = &pmz_ports[0];
1668 pmz_ports[1].port.line = 1;
1669 pmz_ports[1].flags = 0;
1670 pmz_ports[1].pdev = &scc_b_pdev;
1671 err = pmz_init_port(&pmz_ports[1]);
1672 if (err)
1673 return err;
1674 pmz_ports_count++;
1675
1676 return 0;
1677}
1678
1679static void pmz_dispose_port(struct uart_pmac_port *uap)
1680{
1681 memset(uap, 0, sizeof(struct uart_pmac_port));
1682}
1683
1684static int __init pmz_attach(struct platform_device *pdev)
1685{
1686 struct uart_pmac_port *uap;
1687 int i;
1688
1689 /* Iterate the pmz_ports array to find a matching entry */
1690 for (i = 0; i < pmz_ports_count; i++)
1691 if (pmz_ports[i].pdev == pdev)
1692 break;
1693 if (i >= pmz_ports_count)
1694 return -ENODEV;
1695
1696 uap = &pmz_ports[i];
1697 uap->port.dev = &pdev->dev;
1698 platform_set_drvdata(pdev, uap);
1699
1700 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1701}
1702
1703static void __exit pmz_detach(struct platform_device *pdev)
1704{
1705 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1706
1707 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1708
1709 uap->port.dev = NULL;
1710}
1711
1712#endif /* !CONFIG_PPC_PMAC */
1713
1714#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1715
1716static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1717static int __init pmz_console_setup(struct console *co, char *options);
1718
1719static struct console pmz_console = {
1720 .name = PMACZILOG_NAME,
1721 .write = pmz_console_write,
1722 .device = uart_console_device,
1723 .setup = pmz_console_setup,
1724 .flags = CON_PRINTBUFFER,
1725 .index = -1,
1726 .data = &pmz_uart_reg,
1727};
1728
1729#define PMACZILOG_CONSOLE &pmz_console
1730#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1731#define PMACZILOG_CONSOLE (NULL)
1732#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1733
1734/*
1735 * Register the driver, console driver and ports with the serial
1736 * core
1737 */
1738static int __init pmz_register(void)
1739{
1740 pmz_uart_reg.nr = pmz_ports_count;
1741 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1742
1743 /*
1744 * Register this driver with the serial core
1745 */
1746 return uart_register_driver(&pmz_uart_reg);
1747}
1748
1749#ifdef CONFIG_PPC_PMAC
1750
1751static const struct of_device_id pmz_match[] =
1752{
1753 {
1754 .name = "ch-a",
1755 },
1756 {
1757 .name = "ch-b",
1758 },
1759 {},
1760};
1761MODULE_DEVICE_TABLE (of, pmz_match);
1762
1763static struct macio_driver pmz_driver = {
1764 .driver = {
1765 .name = "pmac_zilog",
1766 .owner = THIS_MODULE,
1767 .of_match_table = pmz_match,
1768 },
1769 .probe = pmz_attach,
1770 .remove = pmz_detach,
1771 .suspend = pmz_suspend,
1772 .resume = pmz_resume,
1773};
1774
1775#else
1776
1777static struct platform_driver pmz_driver = {
1778 .remove_new = __exit_p(pmz_detach),
1779 .driver = {
1780 .name = "scc",
1781 },
1782};
1783
1784#endif /* !CONFIG_PPC_PMAC */
1785
1786static int __init init_pmz(void)
1787{
1788 int rc, i;
1789
1790 /*
1791 * First, we need to do a direct OF-based probe pass. We
1792 * do that because we want serial console up before the
1793 * macio stuffs calls us back, and since that makes it
1794 * easier to pass the proper number of channels to
1795 * uart_register_driver()
1796 */
1797 if (pmz_ports_count == 0)
1798 pmz_probe();
1799
1800 /*
1801 * Bail early if no port found
1802 */
1803 if (pmz_ports_count == 0)
1804 return -ENODEV;
1805
1806 /*
1807 * Now we register with the serial layer
1808 */
1809 rc = pmz_register();
1810 if (rc) {
1811 printk(KERN_ERR
1812 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1813 "pmac_zilog: Did another serial driver already claim the minors?\n");
1814 /* effectively "pmz_unprobe()" */
1815 for (i=0; i < pmz_ports_count; i++)
1816 pmz_dispose_port(&pmz_ports[i]);
1817 return rc;
1818 }
1819
1820 /*
1821 * Then we register the macio driver itself
1822 */
1823#ifdef CONFIG_PPC_PMAC
1824 return macio_register_driver(&pmz_driver);
1825#else
1826 return platform_driver_probe(&pmz_driver, pmz_attach);
1827#endif
1828}
1829
1830static void __exit exit_pmz(void)
1831{
1832 int i;
1833
1834#ifdef CONFIG_PPC_PMAC
1835 /* Get rid of macio-driver (detach from macio) */
1836 macio_unregister_driver(&pmz_driver);
1837#else
1838 platform_driver_unregister(&pmz_driver);
1839#endif
1840
1841 for (i = 0; i < pmz_ports_count; i++) {
1842 struct uart_pmac_port *uport = &pmz_ports[i];
1843#ifdef CONFIG_PPC_PMAC
1844 if (uport->node != NULL)
1845 pmz_dispose_port(uport);
1846#else
1847 if (uport->pdev != NULL)
1848 pmz_dispose_port(uport);
1849#endif
1850 }
1851 /* Unregister UART driver */
1852 uart_unregister_driver(&pmz_uart_reg);
1853}
1854
1855#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1856
1857static void pmz_console_putchar(struct uart_port *port, unsigned char ch)
1858{
1859 struct uart_pmac_port *uap =
1860 container_of(port, struct uart_pmac_port, port);
1861
1862 /* Wait for the transmit buffer to empty. */
1863 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1864 udelay(5);
1865 write_zsdata(uap, ch);
1866}
1867
1868/*
1869 * Print a string to the serial port trying not to disturb
1870 * any possible real use of the port...
1871 */
1872static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1873{
1874 struct uart_pmac_port *uap = &pmz_ports[con->index];
1875 unsigned long flags;
1876
1877 uart_port_lock_irqsave(&uap->port, &flags);
1878
1879 /* Turn of interrupts and enable the transmitter. */
1880 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1881 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1882
1883 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1884
1885 /* Restore the values in the registers. */
1886 write_zsreg(uap, R1, uap->curregs[1]);
1887 /* Don't disable the transmitter. */
1888
1889 uart_port_unlock_irqrestore(&uap->port, flags);
1890}
1891
1892/*
1893 * Setup the serial console
1894 */
1895static int __init pmz_console_setup(struct console *co, char *options)
1896{
1897 struct uart_pmac_port *uap;
1898 struct uart_port *port;
1899 int baud = 38400;
1900 int bits = 8;
1901 int parity = 'n';
1902 int flow = 'n';
1903 unsigned long pwr_delay;
1904
1905 /*
1906 * XServe's default to 57600 bps
1907 */
1908 if (of_machine_is_compatible("RackMac1,1")
1909 || of_machine_is_compatible("RackMac1,2")
1910 || of_machine_is_compatible("MacRISC4"))
1911 baud = 57600;
1912
1913 /*
1914 * Check whether an invalid uart number has been specified, and
1915 * if so, search for the first available port that does have
1916 * console support.
1917 */
1918 if (co->index >= pmz_ports_count)
1919 co->index = 0;
1920 uap = &pmz_ports[co->index];
1921#ifdef CONFIG_PPC_PMAC
1922 if (uap->node == NULL)
1923 return -ENODEV;
1924#else
1925 if (uap->pdev == NULL)
1926 return -ENODEV;
1927#endif
1928 port = &uap->port;
1929
1930 /*
1931 * Mark port as beeing a console
1932 */
1933 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1934
1935 /*
1936 * Temporary fix for uart layer who didn't setup the spinlock yet
1937 */
1938 spin_lock_init(&port->lock);
1939
1940 /*
1941 * Enable the hardware
1942 */
1943 pwr_delay = __pmz_startup(uap);
1944 if (pwr_delay)
1945 mdelay(pwr_delay);
1946
1947 if (options)
1948 uart_parse_options(options, &baud, &parity, &bits, &flow);
1949
1950 return uart_set_options(port, co, baud, parity, bits, flow);
1951}
1952
1953static int __init pmz_console_init(void)
1954{
1955 /* Probe ports */
1956 pmz_probe();
1957
1958 if (pmz_ports_count == 0)
1959 return -ENODEV;
1960
1961 /* TODO: Autoprobe console based on OF */
1962 /* pmz_console.index = i; */
1963 register_console(&pmz_console);
1964
1965 return 0;
1966
1967}
1968console_initcall(pmz_console_init);
1969#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1970
1971module_init(init_pmz);
1972module_exit(exit_pmz);