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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Actions Semi Owl family serial console
4 *
5 * Copyright 2013 Actions Semi Inc.
6 * Author: Actions Semi, Inc.
7 *
8 * Copyright (c) 2016-2017 Andreas Färber
9 */
10
11#include <linux/clk.h>
12#include <linux/console.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/serial.h>
20#include <linux/serial_core.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23
24#define OWL_UART_PORT_NUM 7
25#define OWL_UART_DEV_NAME "ttyOWL"
26
27#define OWL_UART_CTL 0x000
28#define OWL_UART_RXDAT 0x004
29#define OWL_UART_TXDAT 0x008
30#define OWL_UART_STAT 0x00c
31
32#define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)
33#define OWL_UART_CTL_DWLS_5BITS (0x0 << 0)
34#define OWL_UART_CTL_DWLS_6BITS (0x1 << 0)
35#define OWL_UART_CTL_DWLS_7BITS (0x2 << 0)
36#define OWL_UART_CTL_DWLS_8BITS (0x3 << 0)
37#define OWL_UART_CTL_STPS_2BITS BIT(2)
38#define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)
39#define OWL_UART_CTL_PRS_NONE (0x0 << 4)
40#define OWL_UART_CTL_PRS_ODD (0x4 << 4)
41#define OWL_UART_CTL_PRS_MARK (0x5 << 4)
42#define OWL_UART_CTL_PRS_EVEN (0x6 << 4)
43#define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
44#define OWL_UART_CTL_AFE BIT(12)
45#define OWL_UART_CTL_TRFS_TX BIT(14)
46#define OWL_UART_CTL_EN BIT(15)
47#define OWL_UART_CTL_RXDE BIT(16)
48#define OWL_UART_CTL_TXDE BIT(17)
49#define OWL_UART_CTL_RXIE BIT(18)
50#define OWL_UART_CTL_TXIE BIT(19)
51#define OWL_UART_CTL_LBEN BIT(20)
52
53#define OWL_UART_STAT_RIP BIT(0)
54#define OWL_UART_STAT_TIP BIT(1)
55#define OWL_UART_STAT_RXER BIT(2)
56#define OWL_UART_STAT_TFER BIT(3)
57#define OWL_UART_STAT_RXST BIT(4)
58#define OWL_UART_STAT_RFEM BIT(5)
59#define OWL_UART_STAT_TFFU BIT(6)
60#define OWL_UART_STAT_CTSS BIT(7)
61#define OWL_UART_STAT_RTSS BIT(8)
62#define OWL_UART_STAT_TFES BIT(10)
63#define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)
64#define OWL_UART_STAT_UTBB BIT(17)
65
66#define OWL_UART_POLL_USEC 5
67#define OWL_UART_TIMEOUT_USEC 10000
68
69static struct uart_driver owl_uart_driver;
70
71struct owl_uart_info {
72 unsigned int tx_fifosize;
73};
74
75struct owl_uart_port {
76 struct uart_port port;
77 struct clk *clk;
78};
79
80#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
81
82static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
83
84static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
85{
86 writel(val, port->membase + off);
87}
88
89static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
90{
91 return readl(port->membase + off);
92}
93
94static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
95{
96 u32 ctl;
97
98 ctl = owl_uart_read(port, OWL_UART_CTL);
99
100 if (mctrl & TIOCM_LOOP)
101 ctl |= OWL_UART_CTL_LBEN;
102 else
103 ctl &= ~OWL_UART_CTL_LBEN;
104
105 owl_uart_write(port, ctl, OWL_UART_CTL);
106}
107
108static unsigned int owl_uart_get_mctrl(struct uart_port *port)
109{
110 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
111 u32 stat, ctl;
112
113 ctl = owl_uart_read(port, OWL_UART_CTL);
114 stat = owl_uart_read(port, OWL_UART_STAT);
115 if (stat & OWL_UART_STAT_RTSS)
116 mctrl |= TIOCM_RTS;
117 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
118 mctrl |= TIOCM_CTS;
119 return mctrl;
120}
121
122static unsigned int owl_uart_tx_empty(struct uart_port *port)
123{
124 unsigned long flags;
125 u32 val;
126 unsigned int ret;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 val = owl_uart_read(port, OWL_UART_STAT);
131 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
132
133 spin_unlock_irqrestore(&port->lock, flags);
134
135 return ret;
136}
137
138static void owl_uart_stop_rx(struct uart_port *port)
139{
140 u32 val;
141
142 val = owl_uart_read(port, OWL_UART_CTL);
143 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
144 owl_uart_write(port, val, OWL_UART_CTL);
145
146 val = owl_uart_read(port, OWL_UART_STAT);
147 val |= OWL_UART_STAT_RIP;
148 owl_uart_write(port, val, OWL_UART_STAT);
149}
150
151static void owl_uart_stop_tx(struct uart_port *port)
152{
153 u32 val;
154
155 val = owl_uart_read(port, OWL_UART_CTL);
156 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
157 owl_uart_write(port, val, OWL_UART_CTL);
158
159 val = owl_uart_read(port, OWL_UART_STAT);
160 val |= OWL_UART_STAT_TIP;
161 owl_uart_write(port, val, OWL_UART_STAT);
162}
163
164static void owl_uart_start_tx(struct uart_port *port)
165{
166 u32 val;
167
168 if (uart_tx_stopped(port)) {
169 owl_uart_stop_tx(port);
170 return;
171 }
172
173 val = owl_uart_read(port, OWL_UART_STAT);
174 val |= OWL_UART_STAT_TIP;
175 owl_uart_write(port, val, OWL_UART_STAT);
176
177 val = owl_uart_read(port, OWL_UART_CTL);
178 val |= OWL_UART_CTL_TXIE;
179 owl_uart_write(port, val, OWL_UART_CTL);
180}
181
182static void owl_uart_send_chars(struct uart_port *port)
183{
184 struct circ_buf *xmit = &port->state->xmit;
185 unsigned int ch;
186
187 if (uart_tx_stopped(port))
188 return;
189
190 if (port->x_char) {
191 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
192 cpu_relax();
193 owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
194 port->icount.tx++;
195 port->x_char = 0;
196 }
197
198 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
199 if (uart_circ_empty(xmit))
200 break;
201
202 ch = xmit->buf[xmit->tail];
203 owl_uart_write(port, ch, OWL_UART_TXDAT);
204 xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
205 port->icount.tx++;
206 }
207
208 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
209 uart_write_wakeup(port);
210
211 if (uart_circ_empty(xmit))
212 owl_uart_stop_tx(port);
213}
214
215static void owl_uart_receive_chars(struct uart_port *port)
216{
217 u32 stat, val;
218
219 val = owl_uart_read(port, OWL_UART_CTL);
220 val &= ~OWL_UART_CTL_TRFS_TX;
221 owl_uart_write(port, val, OWL_UART_CTL);
222
223 stat = owl_uart_read(port, OWL_UART_STAT);
224 while (!(stat & OWL_UART_STAT_RFEM)) {
225 char flag = TTY_NORMAL;
226
227 if (stat & OWL_UART_STAT_RXER)
228 port->icount.overrun++;
229
230 if (stat & OWL_UART_STAT_RXST) {
231 /* We are not able to distinguish the error type. */
232 port->icount.brk++;
233 port->icount.frame++;
234
235 stat &= port->read_status_mask;
236 if (stat & OWL_UART_STAT_RXST)
237 flag = TTY_PARITY;
238 } else
239 port->icount.rx++;
240
241 val = owl_uart_read(port, OWL_UART_RXDAT);
242 val &= 0xff;
243
244 if ((stat & port->ignore_status_mask) == 0)
245 tty_insert_flip_char(&port->state->port, val, flag);
246
247 stat = owl_uart_read(port, OWL_UART_STAT);
248 }
249
250 tty_flip_buffer_push(&port->state->port);
251}
252
253static irqreturn_t owl_uart_irq(int irq, void *dev_id)
254{
255 struct uart_port *port = dev_id;
256 unsigned long flags;
257 u32 stat;
258
259 spin_lock_irqsave(&port->lock, flags);
260
261 stat = owl_uart_read(port, OWL_UART_STAT);
262
263 if (stat & OWL_UART_STAT_RIP)
264 owl_uart_receive_chars(port);
265
266 if (stat & OWL_UART_STAT_TIP)
267 owl_uart_send_chars(port);
268
269 stat = owl_uart_read(port, OWL_UART_STAT);
270 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
271 owl_uart_write(port, stat, OWL_UART_STAT);
272
273 spin_unlock_irqrestore(&port->lock, flags);
274
275 return IRQ_HANDLED;
276}
277
278static void owl_uart_shutdown(struct uart_port *port)
279{
280 u32 val;
281 unsigned long flags;
282
283 spin_lock_irqsave(&port->lock, flags);
284
285 val = owl_uart_read(port, OWL_UART_CTL);
286 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
287 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
288 owl_uart_write(port, val, OWL_UART_CTL);
289
290 spin_unlock_irqrestore(&port->lock, flags);
291
292 free_irq(port->irq, port);
293}
294
295static int owl_uart_startup(struct uart_port *port)
296{
297 u32 val;
298 unsigned long flags;
299 int ret;
300
301 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
302 "owl-uart", port);
303 if (ret)
304 return ret;
305
306 spin_lock_irqsave(&port->lock, flags);
307
308 val = owl_uart_read(port, OWL_UART_STAT);
309 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
310 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
311 owl_uart_write(port, val, OWL_UART_STAT);
312
313 val = owl_uart_read(port, OWL_UART_CTL);
314 val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
315 val |= OWL_UART_CTL_EN;
316 owl_uart_write(port, val, OWL_UART_CTL);
317
318 spin_unlock_irqrestore(&port->lock, flags);
319
320 return 0;
321}
322
323static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
324 unsigned long baud)
325{
326 clk_set_rate(owl_port->clk, baud * 8);
327}
328
329static void owl_uart_set_termios(struct uart_port *port,
330 struct ktermios *termios,
331 struct ktermios *old)
332{
333 struct owl_uart_port *owl_port = to_owl_uart_port(port);
334 unsigned int baud;
335 u32 ctl;
336 unsigned long flags;
337
338 spin_lock_irqsave(&port->lock, flags);
339
340 ctl = owl_uart_read(port, OWL_UART_CTL);
341
342 ctl &= ~OWL_UART_CTL_DWLS_MASK;
343 switch (termios->c_cflag & CSIZE) {
344 case CS5:
345 ctl |= OWL_UART_CTL_DWLS_5BITS;
346 break;
347 case CS6:
348 ctl |= OWL_UART_CTL_DWLS_6BITS;
349 break;
350 case CS7:
351 ctl |= OWL_UART_CTL_DWLS_7BITS;
352 break;
353 case CS8:
354 default:
355 ctl |= OWL_UART_CTL_DWLS_8BITS;
356 break;
357 }
358
359 if (termios->c_cflag & CSTOPB)
360 ctl |= OWL_UART_CTL_STPS_2BITS;
361 else
362 ctl &= ~OWL_UART_CTL_STPS_2BITS;
363
364 ctl &= ~OWL_UART_CTL_PRS_MASK;
365 if (termios->c_cflag & PARENB) {
366 if (termios->c_cflag & CMSPAR) {
367 if (termios->c_cflag & PARODD)
368 ctl |= OWL_UART_CTL_PRS_MARK;
369 else
370 ctl |= OWL_UART_CTL_PRS_SPACE;
371 } else if (termios->c_cflag & PARODD)
372 ctl |= OWL_UART_CTL_PRS_ODD;
373 else
374 ctl |= OWL_UART_CTL_PRS_EVEN;
375 } else
376 ctl |= OWL_UART_CTL_PRS_NONE;
377
378 if (termios->c_cflag & CRTSCTS)
379 ctl |= OWL_UART_CTL_AFE;
380 else
381 ctl &= ~OWL_UART_CTL_AFE;
382
383 owl_uart_write(port, ctl, OWL_UART_CTL);
384
385 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
386 owl_uart_change_baudrate(owl_port, baud);
387
388 /* Don't rewrite B0 */
389 if (tty_termios_baud_rate(termios))
390 tty_termios_encode_baud_rate(termios, baud, baud);
391
392 port->read_status_mask |= OWL_UART_STAT_RXER;
393 if (termios->c_iflag & INPCK)
394 port->read_status_mask |= OWL_UART_STAT_RXST;
395
396 uart_update_timeout(port, termios->c_cflag, baud);
397
398 spin_unlock_irqrestore(&port->lock, flags);
399}
400
401static void owl_uart_release_port(struct uart_port *port)
402{
403 struct platform_device *pdev = to_platform_device(port->dev);
404 struct resource *res;
405
406 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407 if (!res)
408 return;
409
410 if (port->flags & UPF_IOREMAP) {
411 devm_release_mem_region(port->dev, port->mapbase,
412 resource_size(res));
413 devm_iounmap(port->dev, port->membase);
414 port->membase = NULL;
415 }
416}
417
418static int owl_uart_request_port(struct uart_port *port)
419{
420 struct platform_device *pdev = to_platform_device(port->dev);
421 struct resource *res;
422
423 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
424 if (!res)
425 return -ENXIO;
426
427 if (!devm_request_mem_region(port->dev, port->mapbase,
428 resource_size(res), dev_name(port->dev)))
429 return -EBUSY;
430
431 if (port->flags & UPF_IOREMAP) {
432 port->membase = devm_ioremap(port->dev, port->mapbase,
433 resource_size(res));
434 if (!port->membase)
435 return -EBUSY;
436 }
437
438 return 0;
439}
440
441static const char *owl_uart_type(struct uart_port *port)
442{
443 return (port->type == PORT_OWL) ? "owl-uart" : NULL;
444}
445
446static int owl_uart_verify_port(struct uart_port *port,
447 struct serial_struct *ser)
448{
449 if (port->type != PORT_OWL)
450 return -EINVAL;
451
452 if (port->irq != ser->irq)
453 return -EINVAL;
454
455 return 0;
456}
457
458static void owl_uart_config_port(struct uart_port *port, int flags)
459{
460 if (flags & UART_CONFIG_TYPE) {
461 port->type = PORT_OWL;
462 owl_uart_request_port(port);
463 }
464}
465
466#ifdef CONFIG_CONSOLE_POLL
467
468static int owl_uart_poll_get_char(struct uart_port *port)
469{
470 if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)
471 return NO_POLL_CHAR;
472
473 return owl_uart_read(port, OWL_UART_RXDAT);
474}
475
476static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch)
477{
478 u32 reg;
479 int ret;
480
481 /* Wait while FIFO is full or timeout */
482 ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
483 !(reg & OWL_UART_STAT_TFFU),
484 OWL_UART_POLL_USEC,
485 OWL_UART_TIMEOUT_USEC);
486 if (ret == -ETIMEDOUT) {
487 dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
488 return;
489 }
490
491 owl_uart_write(port, ch, OWL_UART_TXDAT);
492}
493
494#endif /* CONFIG_CONSOLE_POLL */
495
496static const struct uart_ops owl_uart_ops = {
497 .set_mctrl = owl_uart_set_mctrl,
498 .get_mctrl = owl_uart_get_mctrl,
499 .tx_empty = owl_uart_tx_empty,
500 .start_tx = owl_uart_start_tx,
501 .stop_rx = owl_uart_stop_rx,
502 .stop_tx = owl_uart_stop_tx,
503 .startup = owl_uart_startup,
504 .shutdown = owl_uart_shutdown,
505 .set_termios = owl_uart_set_termios,
506 .type = owl_uart_type,
507 .config_port = owl_uart_config_port,
508 .request_port = owl_uart_request_port,
509 .release_port = owl_uart_release_port,
510 .verify_port = owl_uart_verify_port,
511#ifdef CONFIG_CONSOLE_POLL
512 .poll_get_char = owl_uart_poll_get_char,
513 .poll_put_char = owl_uart_poll_put_char,
514#endif
515};
516
517#ifdef CONFIG_SERIAL_OWL_CONSOLE
518
519static void owl_console_putchar(struct uart_port *port, int ch)
520{
521 if (!port->membase)
522 return;
523
524 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
525 cpu_relax();
526
527 owl_uart_write(port, ch, OWL_UART_TXDAT);
528}
529
530static void owl_uart_port_write(struct uart_port *port, const char *s,
531 u_int count)
532{
533 u32 old_ctl, val;
534 unsigned long flags;
535 int locked;
536
537 local_irq_save(flags);
538
539 if (port->sysrq)
540 locked = 0;
541 else if (oops_in_progress)
542 locked = spin_trylock(&port->lock);
543 else {
544 spin_lock(&port->lock);
545 locked = 1;
546 }
547
548 old_ctl = owl_uart_read(port, OWL_UART_CTL);
549 val = old_ctl | OWL_UART_CTL_TRFS_TX;
550 /* disable IRQ */
551 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
552 owl_uart_write(port, val, OWL_UART_CTL);
553
554 uart_console_write(port, s, count, owl_console_putchar);
555
556 /* wait until all contents have been sent out */
557 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
558 cpu_relax();
559
560 /* clear IRQ pending */
561 val = owl_uart_read(port, OWL_UART_STAT);
562 val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
563 owl_uart_write(port, val, OWL_UART_STAT);
564
565 owl_uart_write(port, old_ctl, OWL_UART_CTL);
566
567 if (locked)
568 spin_unlock(&port->lock);
569
570 local_irq_restore(flags);
571}
572
573static void owl_uart_console_write(struct console *co, const char *s,
574 u_int count)
575{
576 struct owl_uart_port *owl_port;
577
578 owl_port = owl_uart_ports[co->index];
579 if (!owl_port)
580 return;
581
582 owl_uart_port_write(&owl_port->port, s, count);
583}
584
585static int owl_uart_console_setup(struct console *co, char *options)
586{
587 struct owl_uart_port *owl_port;
588 int baud = 115200;
589 int bits = 8;
590 int parity = 'n';
591 int flow = 'n';
592
593 if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
594 return -EINVAL;
595
596 owl_port = owl_uart_ports[co->index];
597 if (!owl_port || !owl_port->port.membase)
598 return -ENODEV;
599
600 if (options)
601 uart_parse_options(options, &baud, &parity, &bits, &flow);
602
603 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
604}
605
606static struct console owl_uart_console = {
607 .name = OWL_UART_DEV_NAME,
608 .write = owl_uart_console_write,
609 .device = uart_console_device,
610 .setup = owl_uart_console_setup,
611 .flags = CON_PRINTBUFFER,
612 .index = -1,
613 .data = &owl_uart_driver,
614};
615
616static int __init owl_uart_console_init(void)
617{
618 register_console(&owl_uart_console);
619
620 return 0;
621}
622console_initcall(owl_uart_console_init);
623
624static void owl_uart_early_console_write(struct console *co,
625 const char *s,
626 u_int count)
627{
628 struct earlycon_device *dev = co->data;
629
630 owl_uart_port_write(&dev->port, s, count);
631}
632
633static int __init
634owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
635{
636 if (!device->port.membase)
637 return -ENODEV;
638
639 device->con->write = owl_uart_early_console_write;
640
641 return 0;
642}
643OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
644 owl_uart_early_console_setup);
645
646#define OWL_UART_CONSOLE (&owl_uart_console)
647#else
648#define OWL_UART_CONSOLE NULL
649#endif
650
651static struct uart_driver owl_uart_driver = {
652 .owner = THIS_MODULE,
653 .driver_name = "owl-uart",
654 .dev_name = OWL_UART_DEV_NAME,
655 .nr = OWL_UART_PORT_NUM,
656 .cons = OWL_UART_CONSOLE,
657};
658
659static const struct owl_uart_info owl_s500_info = {
660 .tx_fifosize = 16,
661};
662
663static const struct owl_uart_info owl_s900_info = {
664 .tx_fifosize = 32,
665};
666
667static const struct of_device_id owl_uart_dt_matches[] = {
668 { .compatible = "actions,s500-uart", .data = &owl_s500_info },
669 { .compatible = "actions,s900-uart", .data = &owl_s900_info },
670 { }
671};
672MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
673
674static int owl_uart_probe(struct platform_device *pdev)
675{
676 const struct of_device_id *match;
677 const struct owl_uart_info *info = NULL;
678 struct resource *res_mem;
679 struct owl_uart_port *owl_port;
680 int ret, irq;
681
682 if (pdev->dev.of_node) {
683 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
684 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
685 if (match)
686 info = match->data;
687 }
688
689 if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
690 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
691 return -EINVAL;
692 }
693
694 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
695 if (!res_mem) {
696 dev_err(&pdev->dev, "could not get mem\n");
697 return -ENODEV;
698 }
699
700 irq = platform_get_irq(pdev, 0);
701 if (irq < 0)
702 return irq;
703
704 if (owl_uart_ports[pdev->id]) {
705 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
706 return -EBUSY;
707 }
708
709 owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
710 if (!owl_port)
711 return -ENOMEM;
712
713 owl_port->clk = devm_clk_get(&pdev->dev, NULL);
714 if (IS_ERR(owl_port->clk)) {
715 dev_err(&pdev->dev, "could not get clk\n");
716 return PTR_ERR(owl_port->clk);
717 }
718
719 ret = clk_prepare_enable(owl_port->clk);
720 if (ret) {
721 dev_err(&pdev->dev, "could not enable clk\n");
722 return ret;
723 }
724
725 owl_port->port.dev = &pdev->dev;
726 owl_port->port.line = pdev->id;
727 owl_port->port.type = PORT_OWL;
728 owl_port->port.iotype = UPIO_MEM;
729 owl_port->port.mapbase = res_mem->start;
730 owl_port->port.irq = irq;
731 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
732 if (owl_port->port.uartclk == 0) {
733 dev_err(&pdev->dev, "clock rate is zero\n");
734 return -EINVAL;
735 }
736 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
737 owl_port->port.x_char = 0;
738 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
739 owl_port->port.ops = &owl_uart_ops;
740
741 owl_uart_ports[pdev->id] = owl_port;
742 platform_set_drvdata(pdev, owl_port);
743
744 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
745 if (ret)
746 owl_uart_ports[pdev->id] = NULL;
747
748 return ret;
749}
750
751static int owl_uart_remove(struct platform_device *pdev)
752{
753 struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
754
755 uart_remove_one_port(&owl_uart_driver, &owl_port->port);
756 owl_uart_ports[pdev->id] = NULL;
757 clk_disable_unprepare(owl_port->clk);
758
759 return 0;
760}
761
762static struct platform_driver owl_uart_platform_driver = {
763 .probe = owl_uart_probe,
764 .remove = owl_uart_remove,
765 .driver = {
766 .name = "owl-uart",
767 .of_match_table = owl_uart_dt_matches,
768 },
769};
770
771static int __init owl_uart_init(void)
772{
773 int ret;
774
775 ret = uart_register_driver(&owl_uart_driver);
776 if (ret)
777 return ret;
778
779 ret = platform_driver_register(&owl_uart_platform_driver);
780 if (ret)
781 uart_unregister_driver(&owl_uart_driver);
782
783 return ret;
784}
785
786static void __exit owl_uart_exit(void)
787{
788 platform_driver_unregister(&owl_uart_platform_driver);
789 uart_unregister_driver(&owl_uart_driver);
790}
791
792module_init(owl_uart_init);
793module_exit(owl_uart_exit);
794
795MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Actions Semi Owl family serial console
4 *
5 * Copyright 2013 Actions Semi Inc.
6 * Author: Actions Semi, Inc.
7 *
8 * Copyright (c) 2016-2017 Andreas Färber
9 */
10
11#include <linux/clk.h>
12#include <linux/console.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/serial.h>
20#include <linux/serial_core.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23
24#define OWL_UART_PORT_NUM 7
25#define OWL_UART_DEV_NAME "ttyOWL"
26
27#define OWL_UART_CTL 0x000
28#define OWL_UART_RXDAT 0x004
29#define OWL_UART_TXDAT 0x008
30#define OWL_UART_STAT 0x00c
31
32#define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)
33#define OWL_UART_CTL_DWLS_5BITS (0x0 << 0)
34#define OWL_UART_CTL_DWLS_6BITS (0x1 << 0)
35#define OWL_UART_CTL_DWLS_7BITS (0x2 << 0)
36#define OWL_UART_CTL_DWLS_8BITS (0x3 << 0)
37#define OWL_UART_CTL_STPS_2BITS BIT(2)
38#define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)
39#define OWL_UART_CTL_PRS_NONE (0x0 << 4)
40#define OWL_UART_CTL_PRS_ODD (0x4 << 4)
41#define OWL_UART_CTL_PRS_MARK (0x5 << 4)
42#define OWL_UART_CTL_PRS_EVEN (0x6 << 4)
43#define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
44#define OWL_UART_CTL_AFE BIT(12)
45#define OWL_UART_CTL_TRFS_TX BIT(14)
46#define OWL_UART_CTL_EN BIT(15)
47#define OWL_UART_CTL_RXDE BIT(16)
48#define OWL_UART_CTL_TXDE BIT(17)
49#define OWL_UART_CTL_RXIE BIT(18)
50#define OWL_UART_CTL_TXIE BIT(19)
51#define OWL_UART_CTL_LBEN BIT(20)
52
53#define OWL_UART_STAT_RIP BIT(0)
54#define OWL_UART_STAT_TIP BIT(1)
55#define OWL_UART_STAT_RXER BIT(2)
56#define OWL_UART_STAT_TFER BIT(3)
57#define OWL_UART_STAT_RXST BIT(4)
58#define OWL_UART_STAT_RFEM BIT(5)
59#define OWL_UART_STAT_TFFU BIT(6)
60#define OWL_UART_STAT_CTSS BIT(7)
61#define OWL_UART_STAT_RTSS BIT(8)
62#define OWL_UART_STAT_TFES BIT(10)
63#define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)
64#define OWL_UART_STAT_UTBB BIT(17)
65
66#define OWL_UART_POLL_USEC 5
67#define OWL_UART_TIMEOUT_USEC 10000
68
69static struct uart_driver owl_uart_driver;
70
71struct owl_uart_info {
72 unsigned int tx_fifosize;
73};
74
75struct owl_uart_port {
76 struct uart_port port;
77 struct clk *clk;
78};
79
80#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
81
82static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
83
84static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
85{
86 writel(val, port->membase + off);
87}
88
89static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
90{
91 return readl(port->membase + off);
92}
93
94static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
95{
96 u32 ctl;
97
98 ctl = owl_uart_read(port, OWL_UART_CTL);
99
100 if (mctrl & TIOCM_LOOP)
101 ctl |= OWL_UART_CTL_LBEN;
102 else
103 ctl &= ~OWL_UART_CTL_LBEN;
104
105 owl_uart_write(port, ctl, OWL_UART_CTL);
106}
107
108static unsigned int owl_uart_get_mctrl(struct uart_port *port)
109{
110 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
111 u32 stat, ctl;
112
113 ctl = owl_uart_read(port, OWL_UART_CTL);
114 stat = owl_uart_read(port, OWL_UART_STAT);
115 if (stat & OWL_UART_STAT_RTSS)
116 mctrl |= TIOCM_RTS;
117 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
118 mctrl |= TIOCM_CTS;
119 return mctrl;
120}
121
122static unsigned int owl_uart_tx_empty(struct uart_port *port)
123{
124 unsigned long flags;
125 u32 val;
126 unsigned int ret;
127
128 uart_port_lock_irqsave(port, &flags);
129
130 val = owl_uart_read(port, OWL_UART_STAT);
131 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
132
133 uart_port_unlock_irqrestore(port, flags);
134
135 return ret;
136}
137
138static void owl_uart_stop_rx(struct uart_port *port)
139{
140 u32 val;
141
142 val = owl_uart_read(port, OWL_UART_CTL);
143 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
144 owl_uart_write(port, val, OWL_UART_CTL);
145
146 val = owl_uart_read(port, OWL_UART_STAT);
147 val |= OWL_UART_STAT_RIP;
148 owl_uart_write(port, val, OWL_UART_STAT);
149}
150
151static void owl_uart_stop_tx(struct uart_port *port)
152{
153 u32 val;
154
155 val = owl_uart_read(port, OWL_UART_CTL);
156 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
157 owl_uart_write(port, val, OWL_UART_CTL);
158
159 val = owl_uart_read(port, OWL_UART_STAT);
160 val |= OWL_UART_STAT_TIP;
161 owl_uart_write(port, val, OWL_UART_STAT);
162}
163
164static void owl_uart_start_tx(struct uart_port *port)
165{
166 u32 val;
167
168 if (uart_tx_stopped(port)) {
169 owl_uart_stop_tx(port);
170 return;
171 }
172
173 val = owl_uart_read(port, OWL_UART_STAT);
174 val |= OWL_UART_STAT_TIP;
175 owl_uart_write(port, val, OWL_UART_STAT);
176
177 val = owl_uart_read(port, OWL_UART_CTL);
178 val |= OWL_UART_CTL_TXIE;
179 owl_uart_write(port, val, OWL_UART_CTL);
180}
181
182static void owl_uart_send_chars(struct uart_port *port)
183{
184 u8 ch;
185
186 uart_port_tx(port, ch,
187 !(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU),
188 owl_uart_write(port, ch, OWL_UART_TXDAT));
189}
190
191static void owl_uart_receive_chars(struct uart_port *port)
192{
193 u32 stat, val;
194
195 val = owl_uart_read(port, OWL_UART_CTL);
196 val &= ~OWL_UART_CTL_TRFS_TX;
197 owl_uart_write(port, val, OWL_UART_CTL);
198
199 stat = owl_uart_read(port, OWL_UART_STAT);
200 while (!(stat & OWL_UART_STAT_RFEM)) {
201 char flag = TTY_NORMAL;
202 bool sysrq;
203
204 if (stat & OWL_UART_STAT_RXER)
205 port->icount.overrun++;
206
207 if (stat & OWL_UART_STAT_RXST) {
208 /* We are not able to distinguish the error type. */
209 port->icount.brk++;
210 port->icount.frame++;
211
212 stat &= port->read_status_mask;
213 if (stat & OWL_UART_STAT_RXST)
214 flag = TTY_PARITY;
215 } else
216 port->icount.rx++;
217
218 val = owl_uart_read(port, OWL_UART_RXDAT);
219 val &= 0xff;
220
221 sysrq = uart_prepare_sysrq_char(port, val);
222
223 if (!sysrq && (stat & port->ignore_status_mask) == 0)
224 tty_insert_flip_char(&port->state->port, val, flag);
225
226 stat = owl_uart_read(port, OWL_UART_STAT);
227 }
228
229 tty_flip_buffer_push(&port->state->port);
230}
231
232static irqreturn_t owl_uart_irq(int irq, void *dev_id)
233{
234 struct uart_port *port = dev_id;
235 u32 stat;
236
237 uart_port_lock(port);
238
239 stat = owl_uart_read(port, OWL_UART_STAT);
240
241 if (stat & OWL_UART_STAT_RIP)
242 owl_uart_receive_chars(port);
243
244 if (stat & OWL_UART_STAT_TIP)
245 owl_uart_send_chars(port);
246
247 stat = owl_uart_read(port, OWL_UART_STAT);
248 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
249 owl_uart_write(port, stat, OWL_UART_STAT);
250
251 uart_unlock_and_check_sysrq(port);
252
253 return IRQ_HANDLED;
254}
255
256static void owl_uart_shutdown(struct uart_port *port)
257{
258 u32 val;
259 unsigned long flags;
260
261 uart_port_lock_irqsave(port, &flags);
262
263 val = owl_uart_read(port, OWL_UART_CTL);
264 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
265 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
266 owl_uart_write(port, val, OWL_UART_CTL);
267
268 uart_port_unlock_irqrestore(port, flags);
269
270 free_irq(port->irq, port);
271}
272
273static int owl_uart_startup(struct uart_port *port)
274{
275 u32 val;
276 unsigned long flags;
277 int ret;
278
279 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
280 "owl-uart", port);
281 if (ret)
282 return ret;
283
284 uart_port_lock_irqsave(port, &flags);
285
286 val = owl_uart_read(port, OWL_UART_STAT);
287 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
288 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
289 owl_uart_write(port, val, OWL_UART_STAT);
290
291 val = owl_uart_read(port, OWL_UART_CTL);
292 val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
293 val |= OWL_UART_CTL_EN;
294 owl_uart_write(port, val, OWL_UART_CTL);
295
296 uart_port_unlock_irqrestore(port, flags);
297
298 return 0;
299}
300
301static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
302 unsigned long baud)
303{
304 clk_set_rate(owl_port->clk, baud * 8);
305}
306
307static void owl_uart_set_termios(struct uart_port *port,
308 struct ktermios *termios,
309 const struct ktermios *old)
310{
311 struct owl_uart_port *owl_port = to_owl_uart_port(port);
312 unsigned int baud;
313 u32 ctl;
314 unsigned long flags;
315
316 uart_port_lock_irqsave(port, &flags);
317
318 ctl = owl_uart_read(port, OWL_UART_CTL);
319
320 ctl &= ~OWL_UART_CTL_DWLS_MASK;
321 switch (termios->c_cflag & CSIZE) {
322 case CS5:
323 ctl |= OWL_UART_CTL_DWLS_5BITS;
324 break;
325 case CS6:
326 ctl |= OWL_UART_CTL_DWLS_6BITS;
327 break;
328 case CS7:
329 ctl |= OWL_UART_CTL_DWLS_7BITS;
330 break;
331 case CS8:
332 default:
333 ctl |= OWL_UART_CTL_DWLS_8BITS;
334 break;
335 }
336
337 if (termios->c_cflag & CSTOPB)
338 ctl |= OWL_UART_CTL_STPS_2BITS;
339 else
340 ctl &= ~OWL_UART_CTL_STPS_2BITS;
341
342 ctl &= ~OWL_UART_CTL_PRS_MASK;
343 if (termios->c_cflag & PARENB) {
344 if (termios->c_cflag & CMSPAR) {
345 if (termios->c_cflag & PARODD)
346 ctl |= OWL_UART_CTL_PRS_MARK;
347 else
348 ctl |= OWL_UART_CTL_PRS_SPACE;
349 } else if (termios->c_cflag & PARODD)
350 ctl |= OWL_UART_CTL_PRS_ODD;
351 else
352 ctl |= OWL_UART_CTL_PRS_EVEN;
353 } else
354 ctl |= OWL_UART_CTL_PRS_NONE;
355
356 if (termios->c_cflag & CRTSCTS)
357 ctl |= OWL_UART_CTL_AFE;
358 else
359 ctl &= ~OWL_UART_CTL_AFE;
360
361 owl_uart_write(port, ctl, OWL_UART_CTL);
362
363 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
364 owl_uart_change_baudrate(owl_port, baud);
365
366 /* Don't rewrite B0 */
367 if (tty_termios_baud_rate(termios))
368 tty_termios_encode_baud_rate(termios, baud, baud);
369
370 port->read_status_mask |= OWL_UART_STAT_RXER;
371 if (termios->c_iflag & INPCK)
372 port->read_status_mask |= OWL_UART_STAT_RXST;
373
374 uart_update_timeout(port, termios->c_cflag, baud);
375
376 uart_port_unlock_irqrestore(port, flags);
377}
378
379static void owl_uart_release_port(struct uart_port *port)
380{
381 struct platform_device *pdev = to_platform_device(port->dev);
382 struct resource *res;
383
384 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385 if (!res)
386 return;
387
388 if (port->flags & UPF_IOREMAP) {
389 devm_release_mem_region(port->dev, port->mapbase,
390 resource_size(res));
391 devm_iounmap(port->dev, port->membase);
392 port->membase = NULL;
393 }
394}
395
396static int owl_uart_request_port(struct uart_port *port)
397{
398 struct platform_device *pdev = to_platform_device(port->dev);
399 struct resource *res;
400
401 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
402 if (!res)
403 return -ENXIO;
404
405 if (!devm_request_mem_region(port->dev, port->mapbase,
406 resource_size(res), dev_name(port->dev)))
407 return -EBUSY;
408
409 if (port->flags & UPF_IOREMAP) {
410 port->membase = devm_ioremap(port->dev, port->mapbase,
411 resource_size(res));
412 if (!port->membase)
413 return -EBUSY;
414 }
415
416 return 0;
417}
418
419static const char *owl_uart_type(struct uart_port *port)
420{
421 return (port->type == PORT_OWL) ? "owl-uart" : NULL;
422}
423
424static int owl_uart_verify_port(struct uart_port *port,
425 struct serial_struct *ser)
426{
427 if (port->type != PORT_OWL)
428 return -EINVAL;
429
430 if (port->irq != ser->irq)
431 return -EINVAL;
432
433 return 0;
434}
435
436static void owl_uart_config_port(struct uart_port *port, int flags)
437{
438 if (flags & UART_CONFIG_TYPE) {
439 port->type = PORT_OWL;
440 owl_uart_request_port(port);
441 }
442}
443
444#ifdef CONFIG_CONSOLE_POLL
445
446static int owl_uart_poll_get_char(struct uart_port *port)
447{
448 if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)
449 return NO_POLL_CHAR;
450
451 return owl_uart_read(port, OWL_UART_RXDAT);
452}
453
454static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch)
455{
456 u32 reg;
457 int ret;
458
459 /* Wait while FIFO is full or timeout */
460 ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
461 !(reg & OWL_UART_STAT_TFFU),
462 OWL_UART_POLL_USEC,
463 OWL_UART_TIMEOUT_USEC);
464 if (ret == -ETIMEDOUT) {
465 dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
466 return;
467 }
468
469 owl_uart_write(port, ch, OWL_UART_TXDAT);
470}
471
472#endif /* CONFIG_CONSOLE_POLL */
473
474static const struct uart_ops owl_uart_ops = {
475 .set_mctrl = owl_uart_set_mctrl,
476 .get_mctrl = owl_uart_get_mctrl,
477 .tx_empty = owl_uart_tx_empty,
478 .start_tx = owl_uart_start_tx,
479 .stop_rx = owl_uart_stop_rx,
480 .stop_tx = owl_uart_stop_tx,
481 .startup = owl_uart_startup,
482 .shutdown = owl_uart_shutdown,
483 .set_termios = owl_uart_set_termios,
484 .type = owl_uart_type,
485 .config_port = owl_uart_config_port,
486 .request_port = owl_uart_request_port,
487 .release_port = owl_uart_release_port,
488 .verify_port = owl_uart_verify_port,
489#ifdef CONFIG_CONSOLE_POLL
490 .poll_get_char = owl_uart_poll_get_char,
491 .poll_put_char = owl_uart_poll_put_char,
492#endif
493};
494
495#ifdef CONFIG_SERIAL_OWL_CONSOLE
496
497static void owl_console_putchar(struct uart_port *port, unsigned char ch)
498{
499 if (!port->membase)
500 return;
501
502 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
503 cpu_relax();
504
505 owl_uart_write(port, ch, OWL_UART_TXDAT);
506}
507
508static void owl_uart_port_write(struct uart_port *port, const char *s,
509 u_int count)
510{
511 u32 old_ctl, val;
512 unsigned long flags;
513 int locked = 1;
514
515 if (oops_in_progress)
516 locked = uart_port_trylock_irqsave(port, &flags);
517 else
518 uart_port_lock_irqsave(port, &flags);
519
520 old_ctl = owl_uart_read(port, OWL_UART_CTL);
521 val = old_ctl | OWL_UART_CTL_TRFS_TX;
522 /* disable IRQ */
523 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
524 owl_uart_write(port, val, OWL_UART_CTL);
525
526 uart_console_write(port, s, count, owl_console_putchar);
527
528 /* wait until all contents have been sent out */
529 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
530 cpu_relax();
531
532 /* clear IRQ pending */
533 val = owl_uart_read(port, OWL_UART_STAT);
534 val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
535 owl_uart_write(port, val, OWL_UART_STAT);
536
537 owl_uart_write(port, old_ctl, OWL_UART_CTL);
538
539 if (locked)
540 uart_port_unlock_irqrestore(port, flags);
541}
542
543static void owl_uart_console_write(struct console *co, const char *s,
544 u_int count)
545{
546 struct owl_uart_port *owl_port;
547
548 owl_port = owl_uart_ports[co->index];
549 if (!owl_port)
550 return;
551
552 owl_uart_port_write(&owl_port->port, s, count);
553}
554
555static int owl_uart_console_setup(struct console *co, char *options)
556{
557 struct owl_uart_port *owl_port;
558 int baud = 115200;
559 int bits = 8;
560 int parity = 'n';
561 int flow = 'n';
562
563 if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
564 return -EINVAL;
565
566 owl_port = owl_uart_ports[co->index];
567 if (!owl_port || !owl_port->port.membase)
568 return -ENODEV;
569
570 if (options)
571 uart_parse_options(options, &baud, &parity, &bits, &flow);
572
573 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
574}
575
576static struct console owl_uart_console = {
577 .name = OWL_UART_DEV_NAME,
578 .write = owl_uart_console_write,
579 .device = uart_console_device,
580 .setup = owl_uart_console_setup,
581 .flags = CON_PRINTBUFFER,
582 .index = -1,
583 .data = &owl_uart_driver,
584};
585
586static int __init owl_uart_console_init(void)
587{
588 register_console(&owl_uart_console);
589
590 return 0;
591}
592console_initcall(owl_uart_console_init);
593
594static void owl_uart_early_console_write(struct console *co,
595 const char *s,
596 u_int count)
597{
598 struct earlycon_device *dev = co->data;
599
600 owl_uart_port_write(&dev->port, s, count);
601}
602
603static int __init
604owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
605{
606 if (!device->port.membase)
607 return -ENODEV;
608
609 device->con->write = owl_uart_early_console_write;
610
611 return 0;
612}
613OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
614 owl_uart_early_console_setup);
615
616#define OWL_UART_CONSOLE (&owl_uart_console)
617#else
618#define OWL_UART_CONSOLE NULL
619#endif
620
621static struct uart_driver owl_uart_driver = {
622 .owner = THIS_MODULE,
623 .driver_name = "owl-uart",
624 .dev_name = OWL_UART_DEV_NAME,
625 .nr = OWL_UART_PORT_NUM,
626 .cons = OWL_UART_CONSOLE,
627};
628
629static const struct owl_uart_info owl_s500_info = {
630 .tx_fifosize = 16,
631};
632
633static const struct owl_uart_info owl_s900_info = {
634 .tx_fifosize = 32,
635};
636
637static const struct of_device_id owl_uart_dt_matches[] = {
638 { .compatible = "actions,s500-uart", .data = &owl_s500_info },
639 { .compatible = "actions,s900-uart", .data = &owl_s900_info },
640 { }
641};
642MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
643
644static int owl_uart_probe(struct platform_device *pdev)
645{
646 const struct of_device_id *match;
647 const struct owl_uart_info *info = NULL;
648 struct resource *res_mem;
649 struct owl_uart_port *owl_port;
650 int ret, irq;
651
652 if (pdev->dev.of_node) {
653 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
654 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
655 if (match)
656 info = match->data;
657 }
658
659 if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
660 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
661 return -EINVAL;
662 }
663
664 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
665 if (!res_mem) {
666 dev_err(&pdev->dev, "could not get mem\n");
667 return -ENODEV;
668 }
669
670 irq = platform_get_irq(pdev, 0);
671 if (irq < 0)
672 return irq;
673
674 if (owl_uart_ports[pdev->id]) {
675 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
676 return -EBUSY;
677 }
678
679 owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
680 if (!owl_port)
681 return -ENOMEM;
682
683 owl_port->clk = devm_clk_get(&pdev->dev, NULL);
684 if (IS_ERR(owl_port->clk)) {
685 dev_err(&pdev->dev, "could not get clk\n");
686 return PTR_ERR(owl_port->clk);
687 }
688
689 ret = clk_prepare_enable(owl_port->clk);
690 if (ret) {
691 dev_err(&pdev->dev, "could not enable clk\n");
692 return ret;
693 }
694
695 owl_port->port.dev = &pdev->dev;
696 owl_port->port.line = pdev->id;
697 owl_port->port.type = PORT_OWL;
698 owl_port->port.iotype = UPIO_MEM;
699 owl_port->port.mapbase = res_mem->start;
700 owl_port->port.irq = irq;
701 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
702 if (owl_port->port.uartclk == 0) {
703 dev_err(&pdev->dev, "clock rate is zero\n");
704 clk_disable_unprepare(owl_port->clk);
705 return -EINVAL;
706 }
707 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
708 owl_port->port.x_char = 0;
709 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
710 owl_port->port.ops = &owl_uart_ops;
711
712 owl_uart_ports[pdev->id] = owl_port;
713 platform_set_drvdata(pdev, owl_port);
714
715 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
716 if (ret)
717 owl_uart_ports[pdev->id] = NULL;
718
719 return ret;
720}
721
722static void owl_uart_remove(struct platform_device *pdev)
723{
724 struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
725
726 uart_remove_one_port(&owl_uart_driver, &owl_port->port);
727 owl_uart_ports[pdev->id] = NULL;
728 clk_disable_unprepare(owl_port->clk);
729}
730
731static struct platform_driver owl_uart_platform_driver = {
732 .probe = owl_uart_probe,
733 .remove_new = owl_uart_remove,
734 .driver = {
735 .name = "owl-uart",
736 .of_match_table = owl_uart_dt_matches,
737 },
738};
739
740static int __init owl_uart_init(void)
741{
742 int ret;
743
744 ret = uart_register_driver(&owl_uart_driver);
745 if (ret)
746 return ret;
747
748 ret = platform_driver_register(&owl_uart_platform_driver);
749 if (ret)
750 uart_unregister_driver(&owl_uart_driver);
751
752 return ret;
753}
754
755static void __exit owl_uart_exit(void)
756{
757 platform_driver_unregister(&owl_uart_platform_driver);
758 uart_unregister_driver(&owl_uart_driver);
759}
760
761module_init(owl_uart_init);
762module_exit(owl_uart_exit);
763
764MODULE_LICENSE("GPL");