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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/* Copyright 2013-2016 Freescale Semiconductor Inc.
3 * Copyright 2016 NXP
4 * Copyright 2020 NXP
5 */
6#ifndef _FSL_DPNI_CMD_H
7#define _FSL_DPNI_CMD_H
8
9#include "dpni.h"
10
11/* DPNI Version */
12#define DPNI_VER_MAJOR 7
13#define DPNI_VER_MINOR 0
14#define DPNI_CMD_BASE_VERSION 1
15#define DPNI_CMD_2ND_VERSION 2
16#define DPNI_CMD_ID_OFFSET 4
17
18#define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION)
19#define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_2ND_VERSION)
20
21#define DPNI_CMDID_OPEN DPNI_CMD(0x801)
22#define DPNI_CMDID_CLOSE DPNI_CMD(0x800)
23#define DPNI_CMDID_CREATE DPNI_CMD(0x901)
24#define DPNI_CMDID_DESTROY DPNI_CMD(0x900)
25#define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01)
26
27#define DPNI_CMDID_ENABLE DPNI_CMD(0x002)
28#define DPNI_CMDID_DISABLE DPNI_CMD(0x003)
29#define DPNI_CMDID_GET_ATTR DPNI_CMD(0x004)
30#define DPNI_CMDID_RESET DPNI_CMD(0x005)
31#define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006)
32
33#define DPNI_CMDID_SET_IRQ DPNI_CMD(0x010)
34#define DPNI_CMDID_GET_IRQ DPNI_CMD(0x011)
35#define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012)
36#define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013)
37#define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014)
38#define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015)
39#define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016)
40#define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017)
41
42#define DPNI_CMDID_SET_POOLS DPNI_CMD(0x200)
43#define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B)
44
45#define DPNI_CMDID_GET_QDID DPNI_CMD(0x210)
46#define DPNI_CMDID_GET_TX_DATA_OFFSET DPNI_CMD(0x212)
47#define DPNI_CMDID_GET_LINK_STATE DPNI_CMD(0x215)
48#define DPNI_CMDID_SET_MAX_FRAME_LENGTH DPNI_CMD(0x216)
49#define DPNI_CMDID_GET_MAX_FRAME_LENGTH DPNI_CMD(0x217)
50#define DPNI_CMDID_SET_LINK_CFG DPNI_CMD(0x21A)
51#define DPNI_CMDID_SET_TX_SHAPING DPNI_CMD_V2(0x21B)
52
53#define DPNI_CMDID_SET_MCAST_PROMISC DPNI_CMD(0x220)
54#define DPNI_CMDID_GET_MCAST_PROMISC DPNI_CMD(0x221)
55#define DPNI_CMDID_SET_UNICAST_PROMISC DPNI_CMD(0x222)
56#define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223)
57#define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224)
58#define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225)
59#define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD(0x226)
60#define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227)
61#define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228)
62
63#define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD(0x235)
64
65#define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230)
66#define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231)
67#define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232)
68
69#define DPNI_CMDID_SET_QOS_TBL DPNI_CMD(0x240)
70#define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD(0x241)
71#define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242)
72#define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243)
73#define DPNI_CMDID_ADD_FS_ENT DPNI_CMD(0x244)
74#define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245)
75#define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246)
76
77#define DPNI_CMDID_GET_STATISTICS DPNI_CMD(0x25D)
78#define DPNI_CMDID_GET_QUEUE DPNI_CMD(0x25F)
79#define DPNI_CMDID_SET_QUEUE DPNI_CMD(0x260)
80#define DPNI_CMDID_GET_TAILDROP DPNI_CMD(0x261)
81#define DPNI_CMDID_SET_TAILDROP DPNI_CMD(0x262)
82
83#define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263)
84
85#define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD(0x264)
86#define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD(0x265)
87
88#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266)
89#define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD(0x267)
90#define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD(0x268)
91#define DPNI_CMDID_SET_EARLY_DROP DPNI_CMD(0x269)
92#define DPNI_CMDID_GET_EARLY_DROP DPNI_CMD(0x26A)
93#define DPNI_CMDID_GET_OFFLOAD DPNI_CMD(0x26B)
94#define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C)
95
96#define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273)
97#define DPNI_CMDID_SET_RX_HASH_DIST DPNI_CMD(0x274)
98#define DPNI_CMDID_GET_LINK_CFG DPNI_CMD(0x278)
99
100#define DPNI_CMDID_SET_SINGLE_STEP_CFG DPNI_CMD(0x279)
101#define DPNI_CMDID_GET_SINGLE_STEP_CFG DPNI_CMD(0x27a)
102
103/* Macros for accessing command fields smaller than 1byte */
104#define DPNI_MASK(field) \
105 GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
106 DPNI_##field##_SHIFT)
107
108#define dpni_set_field(var, field, val) \
109 ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field)))
110#define dpni_get_field(var, field) \
111 (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT)
112
113struct dpni_cmd_open {
114 __le32 dpni_id;
115};
116
117#define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order))
118struct dpni_cmd_set_pools {
119 /* cmd word 0 */
120 u8 num_dpbp;
121 u8 backup_pool_mask;
122 __le16 pad;
123 /* cmd word 0..4 */
124 __le32 dpbp_id[DPNI_MAX_DPBP];
125 /* cmd word 4..6 */
126 __le16 buffer_size[DPNI_MAX_DPBP];
127};
128
129/* The enable indication is always the least significant bit */
130#define DPNI_ENABLE_SHIFT 0
131#define DPNI_ENABLE_SIZE 1
132
133struct dpni_rsp_is_enabled {
134 u8 enabled;
135};
136
137struct dpni_rsp_get_irq {
138 /* response word 0 */
139 __le32 irq_val;
140 __le32 pad;
141 /* response word 1 */
142 __le64 irq_addr;
143 /* response word 2 */
144 __le32 irq_num;
145 __le32 type;
146};
147
148struct dpni_cmd_set_irq_enable {
149 u8 enable;
150 u8 pad[3];
151 u8 irq_index;
152};
153
154struct dpni_cmd_get_irq_enable {
155 __le32 pad;
156 u8 irq_index;
157};
158
159struct dpni_rsp_get_irq_enable {
160 u8 enabled;
161};
162
163struct dpni_cmd_set_irq_mask {
164 __le32 mask;
165 u8 irq_index;
166};
167
168struct dpni_cmd_get_irq_mask {
169 __le32 pad;
170 u8 irq_index;
171};
172
173struct dpni_rsp_get_irq_mask {
174 __le32 mask;
175};
176
177struct dpni_cmd_get_irq_status {
178 __le32 status;
179 u8 irq_index;
180};
181
182struct dpni_rsp_get_irq_status {
183 __le32 status;
184};
185
186struct dpni_cmd_clear_irq_status {
187 __le32 status;
188 u8 irq_index;
189};
190
191struct dpni_rsp_get_attr {
192 /* response word 0 */
193 __le32 options;
194 u8 num_queues;
195 u8 num_tcs;
196 u8 mac_filter_entries;
197 u8 pad0;
198 /* response word 1 */
199 u8 vlan_filter_entries;
200 u8 pad1;
201 u8 qos_entries;
202 u8 pad2;
203 __le16 fs_entries;
204 __le16 pad3;
205 /* response word 2 */
206 u8 qos_key_size;
207 u8 fs_key_size;
208 __le16 wriop_version;
209};
210
211#define DPNI_ERROR_ACTION_SHIFT 0
212#define DPNI_ERROR_ACTION_SIZE 4
213#define DPNI_FRAME_ANN_SHIFT 4
214#define DPNI_FRAME_ANN_SIZE 1
215
216struct dpni_cmd_set_errors_behavior {
217 __le32 errors;
218 /* from least significant bit: error_action:4, set_frame_annotation:1 */
219 u8 flags;
220};
221
222/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation
223 * buffer layouts, but they all share the same parameters.
224 * If one of the functions changes, below structure needs to be split.
225 */
226
227#define DPNI_PASS_TS_SHIFT 0
228#define DPNI_PASS_TS_SIZE 1
229#define DPNI_PASS_PR_SHIFT 1
230#define DPNI_PASS_PR_SIZE 1
231#define DPNI_PASS_FS_SHIFT 2
232#define DPNI_PASS_FS_SIZE 1
233
234struct dpni_cmd_get_buffer_layout {
235 u8 qtype;
236};
237
238struct dpni_rsp_get_buffer_layout {
239 /* response word 0 */
240 u8 pad0[6];
241 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
242 u8 flags;
243 u8 pad1;
244 /* response word 1 */
245 __le16 private_data_size;
246 __le16 data_align;
247 __le16 head_room;
248 __le16 tail_room;
249};
250
251struct dpni_cmd_set_buffer_layout {
252 /* cmd word 0 */
253 u8 qtype;
254 u8 pad0[3];
255 __le16 options;
256 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
257 u8 flags;
258 u8 pad1;
259 /* cmd word 1 */
260 __le16 private_data_size;
261 __le16 data_align;
262 __le16 head_room;
263 __le16 tail_room;
264};
265
266struct dpni_cmd_set_offload {
267 u8 pad[3];
268 u8 dpni_offload;
269 __le32 config;
270};
271
272struct dpni_cmd_get_offload {
273 u8 pad[3];
274 u8 dpni_offload;
275};
276
277struct dpni_rsp_get_offload {
278 __le32 pad;
279 __le32 config;
280};
281
282struct dpni_cmd_get_qdid {
283 u8 qtype;
284};
285
286struct dpni_rsp_get_qdid {
287 __le16 qdid;
288};
289
290struct dpni_rsp_get_tx_data_offset {
291 __le16 data_offset;
292};
293
294struct dpni_cmd_get_statistics {
295 u8 page_number;
296};
297
298struct dpni_rsp_get_statistics {
299 __le64 counter[DPNI_STATISTICS_CNT];
300};
301
302struct dpni_cmd_link_cfg {
303 /* cmd word 0 */
304 __le64 pad0;
305 /* cmd word 1 */
306 __le32 rate;
307 __le32 pad1;
308 /* cmd word 2 */
309 __le64 options;
310};
311
312#define DPNI_LINK_STATE_SHIFT 0
313#define DPNI_LINK_STATE_SIZE 1
314
315struct dpni_rsp_get_link_state {
316 /* response word 0 */
317 __le32 pad0;
318 /* from LSB: up:1 */
319 u8 flags;
320 u8 pad1[3];
321 /* response word 1 */
322 __le32 rate;
323 __le32 pad2;
324 /* response word 2 */
325 __le64 options;
326};
327
328struct dpni_cmd_set_max_frame_length {
329 __le16 max_frame_length;
330};
331
332struct dpni_rsp_get_max_frame_length {
333 __le16 max_frame_length;
334};
335
336struct dpni_cmd_set_multicast_promisc {
337 u8 enable;
338};
339
340struct dpni_rsp_get_multicast_promisc {
341 u8 enabled;
342};
343
344struct dpni_cmd_set_unicast_promisc {
345 u8 enable;
346};
347
348struct dpni_rsp_get_unicast_promisc {
349 u8 enabled;
350};
351
352struct dpni_cmd_set_primary_mac_addr {
353 __le16 pad;
354 u8 mac_addr[6];
355};
356
357struct dpni_rsp_get_primary_mac_addr {
358 __le16 pad;
359 u8 mac_addr[6];
360};
361
362struct dpni_rsp_get_port_mac_addr {
363 __le16 pad;
364 u8 mac_addr[6];
365};
366
367struct dpni_cmd_add_mac_addr {
368 __le16 pad;
369 u8 mac_addr[6];
370};
371
372struct dpni_cmd_remove_mac_addr {
373 __le16 pad;
374 u8 mac_addr[6];
375};
376
377#define DPNI_UNICAST_FILTERS_SHIFT 0
378#define DPNI_UNICAST_FILTERS_SIZE 1
379#define DPNI_MULTICAST_FILTERS_SHIFT 1
380#define DPNI_MULTICAST_FILTERS_SIZE 1
381
382struct dpni_cmd_clear_mac_filters {
383 /* from LSB: unicast:1, multicast:1 */
384 u8 flags;
385};
386
387#define DPNI_DIST_MODE_SHIFT 0
388#define DPNI_DIST_MODE_SIZE 4
389#define DPNI_MISS_ACTION_SHIFT 4
390#define DPNI_MISS_ACTION_SIZE 4
391
392struct dpni_cmd_set_rx_tc_dist {
393 /* cmd word 0 */
394 __le16 dist_size;
395 u8 tc_id;
396 /* from LSB: dist_mode:4, miss_action:4 */
397 u8 flags;
398 __le16 pad0;
399 __le16 default_flow_id;
400 /* cmd word 1..5 */
401 __le64 pad1[5];
402 /* cmd word 6 */
403 __le64 key_cfg_iova;
404};
405
406/* dpni_set_rx_tc_dist extension (structure of the DMA-able memory at
407 * key_cfg_iova)
408 */
409struct dpni_mask_cfg {
410 u8 mask;
411 u8 offset;
412};
413
414#define DPNI_EFH_TYPE_SHIFT 0
415#define DPNI_EFH_TYPE_SIZE 4
416#define DPNI_EXTRACT_TYPE_SHIFT 0
417#define DPNI_EXTRACT_TYPE_SIZE 4
418
419struct dpni_dist_extract {
420 /* word 0 */
421 u8 prot;
422 /* EFH type stored in the 4 least significant bits */
423 u8 efh_type;
424 u8 size;
425 u8 offset;
426 __le32 field;
427 /* word 1 */
428 u8 hdr_index;
429 u8 constant;
430 u8 num_of_repeats;
431 u8 num_of_byte_masks;
432 /* Extraction type is stored in the 4 LSBs */
433 u8 extract_type;
434 u8 pad[3];
435 /* word 2 */
436 struct dpni_mask_cfg masks[4];
437};
438
439struct dpni_ext_set_rx_tc_dist {
440 /* extension word 0 */
441 u8 num_extracts;
442 u8 pad[7];
443 /* words 1..25 */
444 struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
445};
446
447struct dpni_cmd_get_queue {
448 u8 qtype;
449 u8 tc;
450 u8 index;
451};
452
453#define DPNI_DEST_TYPE_SHIFT 0
454#define DPNI_DEST_TYPE_SIZE 4
455#define DPNI_STASH_CTRL_SHIFT 6
456#define DPNI_STASH_CTRL_SIZE 1
457#define DPNI_HOLD_ACTIVE_SHIFT 7
458#define DPNI_HOLD_ACTIVE_SIZE 1
459
460struct dpni_rsp_get_queue {
461 /* response word 0 */
462 __le64 pad0;
463 /* response word 1 */
464 __le32 dest_id;
465 __le16 pad1;
466 u8 dest_prio;
467 /* From LSB: dest_type:4, pad:2, flc_stash_ctrl:1, hold_active:1 */
468 u8 flags;
469 /* response word 2 */
470 __le64 flc;
471 /* response word 3 */
472 __le64 user_context;
473 /* response word 4 */
474 __le32 fqid;
475 __le16 qdbin;
476};
477
478struct dpni_cmd_set_queue {
479 /* cmd word 0 */
480 u8 qtype;
481 u8 tc;
482 u8 index;
483 u8 options;
484 __le32 pad0;
485 /* cmd word 1 */
486 __le32 dest_id;
487 __le16 pad1;
488 u8 dest_prio;
489 u8 flags;
490 /* cmd word 2 */
491 __le64 flc;
492 /* cmd word 3 */
493 __le64 user_context;
494};
495
496struct dpni_cmd_set_taildrop {
497 /* cmd word 0 */
498 u8 congestion_point;
499 u8 qtype;
500 u8 tc;
501 u8 index;
502 __le32 pad0;
503 /* cmd word 1 */
504 /* Only least significant bit is relevant */
505 u8 enable;
506 u8 pad1;
507 u8 units;
508 u8 pad2;
509 __le32 threshold;
510};
511
512struct dpni_cmd_get_taildrop {
513 u8 congestion_point;
514 u8 qtype;
515 u8 tc;
516 u8 index;
517};
518
519struct dpni_rsp_get_taildrop {
520 /* cmd word 0 */
521 __le64 pad0;
522 /* cmd word 1 */
523 /* only least significant bit is relevant */
524 u8 enable;
525 u8 pad1;
526 u8 units;
527 u8 pad2;
528 __le32 threshold;
529};
530
531struct dpni_rsp_get_api_version {
532 __le16 major;
533 __le16 minor;
534};
535
536#define DPNI_RX_FS_DIST_ENABLE_SHIFT 0
537#define DPNI_RX_FS_DIST_ENABLE_SIZE 1
538struct dpni_cmd_set_rx_fs_dist {
539 __le16 dist_size;
540 u8 enable;
541 u8 tc;
542 __le16 miss_flow_id;
543 __le16 pad;
544 __le64 key_cfg_iova;
545};
546
547#define DPNI_RX_HASH_DIST_ENABLE_SHIFT 0
548#define DPNI_RX_HASH_DIST_ENABLE_SIZE 1
549struct dpni_cmd_set_rx_hash_dist {
550 __le16 dist_size;
551 u8 enable;
552 u8 tc;
553 __le32 pad;
554 __le64 key_cfg_iova;
555};
556
557struct dpni_cmd_add_fs_entry {
558 /* cmd word 0 */
559 __le16 options;
560 u8 tc_id;
561 u8 key_size;
562 __le16 index;
563 __le16 flow_id;
564 /* cmd word 1 */
565 __le64 key_iova;
566 /* cmd word 2 */
567 __le64 mask_iova;
568 /* cmd word 3 */
569 __le64 flc;
570};
571
572struct dpni_cmd_remove_fs_entry {
573 /* cmd word 0 */
574 __le16 pad0;
575 u8 tc_id;
576 u8 key_size;
577 __le32 pad1;
578 /* cmd word 1 */
579 __le64 key_iova;
580 /* cmd word 2 */
581 __le64 mask_iova;
582};
583
584#define DPNI_DISCARD_ON_MISS_SHIFT 0
585#define DPNI_DISCARD_ON_MISS_SIZE 1
586
587struct dpni_cmd_set_qos_table {
588 __le32 pad;
589 u8 default_tc;
590 /* only the LSB */
591 u8 discard_on_miss;
592 __le16 pad1[21];
593 __le64 key_cfg_iova;
594};
595
596struct dpni_cmd_add_qos_entry {
597 __le16 pad;
598 u8 tc_id;
599 u8 key_size;
600 __le16 index;
601 __le16 pad1;
602 __le64 key_iova;
603 __le64 mask_iova;
604};
605
606struct dpni_cmd_remove_qos_entry {
607 u8 pad[3];
608 u8 key_size;
609 __le32 pad1;
610 __le64 key_iova;
611 __le64 mask_iova;
612};
613
614#define DPNI_DEST_TYPE_SHIFT 0
615#define DPNI_DEST_TYPE_SIZE 4
616#define DPNI_CONG_UNITS_SHIFT 4
617#define DPNI_CONG_UNITS_SIZE 2
618
619struct dpni_cmd_set_congestion_notification {
620 /* cmd word 0 */
621 u8 qtype;
622 u8 tc;
623 u8 pad[6];
624 /* cmd word 1 */
625 __le32 dest_id;
626 __le16 notification_mode;
627 u8 dest_priority;
628 /* from LSB: dest_type: 4 units:2 */
629 u8 type_units;
630 /* cmd word 2 */
631 __le64 message_iova;
632 /* cmd word 3 */
633 __le64 message_ctx;
634 /* cmd word 4 */
635 __le32 threshold_entry;
636 __le32 threshold_exit;
637};
638
639#define DPNI_COUPLED_SHIFT 0
640#define DPNI_COUPLED_SIZE 1
641
642struct dpni_cmd_set_tx_shaping {
643 __le16 tx_cr_max_burst_size;
644 __le16 tx_er_max_burst_size;
645 __le32 pad;
646 __le32 tx_cr_rate_limit;
647 __le32 tx_er_rate_limit;
648 /* from LSB: coupled:1 */
649 u8 coupled;
650};
651
652#define DPNI_PTP_ENABLE_SHIFT 0
653#define DPNI_PTP_ENABLE_SIZE 1
654#define DPNI_PTP_CH_UPDATE_SHIFT 1
655#define DPNI_PTP_CH_UPDATE_SIZE 1
656
657struct dpni_cmd_single_step_cfg {
658 __le16 flags;
659 __le16 offset;
660 __le32 peer_delay;
661};
662
663struct dpni_rsp_single_step_cfg {
664 __le16 flags;
665 __le16 offset;
666 __le32 peer_delay;
667};
668
669struct dpni_cmd_enable_vlan_filter {
670 /* only the LSB */
671 u8 en;
672};
673
674struct dpni_cmd_vlan_id {
675 u8 flags;
676 u8 tc_id;
677 u8 flow_id;
678 u8 pad;
679 __le16 vlan_id;
680};
681
682#endif /* _FSL_DPNI_CMD_H */
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/* Copyright 2013-2016 Freescale Semiconductor Inc.
3 * Copyright 2016 NXP
4 * Copyright 2020 NXP
5 */
6#ifndef _FSL_DPNI_CMD_H
7#define _FSL_DPNI_CMD_H
8
9#include "dpni.h"
10
11/* DPNI Version */
12#define DPNI_VER_MAJOR 7
13#define DPNI_VER_MINOR 0
14#define DPNI_CMD_BASE_VERSION 1
15#define DPNI_CMD_2ND_VERSION 2
16#define DPNI_CMD_3RD_VERSION 3
17#define DPNI_CMD_ID_OFFSET 4
18
19#define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION)
20#define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_2ND_VERSION)
21#define DPNI_CMD_V3(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_3RD_VERSION)
22
23#define DPNI_CMDID_OPEN DPNI_CMD(0x801)
24#define DPNI_CMDID_CLOSE DPNI_CMD(0x800)
25#define DPNI_CMDID_CREATE DPNI_CMD(0x901)
26#define DPNI_CMDID_DESTROY DPNI_CMD(0x900)
27#define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01)
28
29#define DPNI_CMDID_ENABLE DPNI_CMD(0x002)
30#define DPNI_CMDID_DISABLE DPNI_CMD(0x003)
31#define DPNI_CMDID_GET_ATTR DPNI_CMD(0x004)
32#define DPNI_CMDID_RESET DPNI_CMD(0x005)
33#define DPNI_CMDID_IS_ENABLED DPNI_CMD(0x006)
34
35#define DPNI_CMDID_SET_IRQ DPNI_CMD(0x010)
36#define DPNI_CMDID_GET_IRQ DPNI_CMD(0x011)
37#define DPNI_CMDID_SET_IRQ_ENABLE DPNI_CMD(0x012)
38#define DPNI_CMDID_GET_IRQ_ENABLE DPNI_CMD(0x013)
39#define DPNI_CMDID_SET_IRQ_MASK DPNI_CMD(0x014)
40#define DPNI_CMDID_GET_IRQ_MASK DPNI_CMD(0x015)
41#define DPNI_CMDID_GET_IRQ_STATUS DPNI_CMD(0x016)
42#define DPNI_CMDID_CLEAR_IRQ_STATUS DPNI_CMD(0x017)
43
44#define DPNI_CMDID_SET_POOLS DPNI_CMD_V3(0x200)
45#define DPNI_CMDID_SET_ERRORS_BEHAVIOR DPNI_CMD(0x20B)
46
47#define DPNI_CMDID_GET_QDID DPNI_CMD(0x210)
48#define DPNI_CMDID_GET_TX_DATA_OFFSET DPNI_CMD(0x212)
49#define DPNI_CMDID_GET_LINK_STATE DPNI_CMD(0x215)
50#define DPNI_CMDID_SET_MAX_FRAME_LENGTH DPNI_CMD(0x216)
51#define DPNI_CMDID_GET_MAX_FRAME_LENGTH DPNI_CMD(0x217)
52#define DPNI_CMDID_SET_LINK_CFG DPNI_CMD(0x21A)
53#define DPNI_CMDID_SET_TX_SHAPING DPNI_CMD_V2(0x21B)
54
55#define DPNI_CMDID_SET_MCAST_PROMISC DPNI_CMD(0x220)
56#define DPNI_CMDID_GET_MCAST_PROMISC DPNI_CMD(0x221)
57#define DPNI_CMDID_SET_UNICAST_PROMISC DPNI_CMD(0x222)
58#define DPNI_CMDID_GET_UNICAST_PROMISC DPNI_CMD(0x223)
59#define DPNI_CMDID_SET_PRIM_MAC DPNI_CMD(0x224)
60#define DPNI_CMDID_GET_PRIM_MAC DPNI_CMD(0x225)
61#define DPNI_CMDID_ADD_MAC_ADDR DPNI_CMD(0x226)
62#define DPNI_CMDID_REMOVE_MAC_ADDR DPNI_CMD(0x227)
63#define DPNI_CMDID_CLR_MAC_FILTERS DPNI_CMD(0x228)
64
65#define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD(0x235)
66
67#define DPNI_CMDID_ENABLE_VLAN_FILTER DPNI_CMD(0x230)
68#define DPNI_CMDID_ADD_VLAN_ID DPNI_CMD_V2(0x231)
69#define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232)
70
71#define DPNI_CMDID_SET_QOS_TBL DPNI_CMD(0x240)
72#define DPNI_CMDID_ADD_QOS_ENT DPNI_CMD(0x241)
73#define DPNI_CMDID_REMOVE_QOS_ENT DPNI_CMD(0x242)
74#define DPNI_CMDID_CLR_QOS_TBL DPNI_CMD(0x243)
75#define DPNI_CMDID_ADD_FS_ENT DPNI_CMD(0x244)
76#define DPNI_CMDID_REMOVE_FS_ENT DPNI_CMD(0x245)
77#define DPNI_CMDID_CLR_FS_ENT DPNI_CMD(0x246)
78
79#define DPNI_CMDID_GET_STATISTICS DPNI_CMD(0x25D)
80#define DPNI_CMDID_GET_QUEUE DPNI_CMD(0x25F)
81#define DPNI_CMDID_SET_QUEUE DPNI_CMD(0x260)
82#define DPNI_CMDID_GET_TAILDROP DPNI_CMD(0x261)
83#define DPNI_CMDID_SET_TAILDROP DPNI_CMD(0x262)
84
85#define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263)
86
87#define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD(0x264)
88#define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD(0x265)
89
90#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266)
91#define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD(0x267)
92#define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD(0x268)
93#define DPNI_CMDID_SET_EARLY_DROP DPNI_CMD(0x269)
94#define DPNI_CMDID_GET_EARLY_DROP DPNI_CMD(0x26A)
95#define DPNI_CMDID_GET_OFFLOAD DPNI_CMD(0x26B)
96#define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C)
97
98#define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273)
99#define DPNI_CMDID_SET_RX_HASH_DIST DPNI_CMD(0x274)
100#define DPNI_CMDID_GET_LINK_CFG DPNI_CMD(0x278)
101
102#define DPNI_CMDID_SET_SINGLE_STEP_CFG DPNI_CMD(0x279)
103#define DPNI_CMDID_GET_SINGLE_STEP_CFG DPNI_CMD_V2(0x27a)
104
105/* Macros for accessing command fields smaller than 1byte */
106#define DPNI_MASK(field) \
107 GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
108 DPNI_##field##_SHIFT)
109
110#define dpni_set_field(var, field, val) \
111 ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field)))
112#define dpni_get_field(var, field) \
113 (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT)
114
115struct dpni_cmd_open {
116 __le32 dpni_id;
117};
118
119#define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order))
120
121struct dpni_cmd_pool {
122 __le16 dpbp_id;
123 u8 priority_mask;
124 u8 pad;
125};
126
127struct dpni_cmd_set_pools {
128 u8 num_dpbp;
129 u8 backup_pool_mask;
130 u8 pad;
131 u8 pool_options;
132 struct dpni_cmd_pool pool[DPNI_MAX_DPBP];
133 __le16 buffer_size[DPNI_MAX_DPBP];
134};
135
136/* The enable indication is always the least significant bit */
137#define DPNI_ENABLE_SHIFT 0
138#define DPNI_ENABLE_SIZE 1
139
140struct dpni_rsp_is_enabled {
141 u8 enabled;
142};
143
144struct dpni_rsp_get_irq {
145 /* response word 0 */
146 __le32 irq_val;
147 __le32 pad;
148 /* response word 1 */
149 __le64 irq_addr;
150 /* response word 2 */
151 __le32 irq_num;
152 __le32 type;
153};
154
155struct dpni_cmd_set_irq_enable {
156 u8 enable;
157 u8 pad[3];
158 u8 irq_index;
159};
160
161struct dpni_cmd_get_irq_enable {
162 __le32 pad;
163 u8 irq_index;
164};
165
166struct dpni_rsp_get_irq_enable {
167 u8 enabled;
168};
169
170struct dpni_cmd_set_irq_mask {
171 __le32 mask;
172 u8 irq_index;
173};
174
175struct dpni_cmd_get_irq_mask {
176 __le32 pad;
177 u8 irq_index;
178};
179
180struct dpni_rsp_get_irq_mask {
181 __le32 mask;
182};
183
184struct dpni_cmd_get_irq_status {
185 __le32 status;
186 u8 irq_index;
187};
188
189struct dpni_rsp_get_irq_status {
190 __le32 status;
191};
192
193struct dpni_cmd_clear_irq_status {
194 __le32 status;
195 u8 irq_index;
196};
197
198struct dpni_rsp_get_attr {
199 /* response word 0 */
200 __le32 options;
201 u8 num_queues;
202 u8 num_tcs;
203 u8 mac_filter_entries;
204 u8 pad0;
205 /* response word 1 */
206 u8 vlan_filter_entries;
207 u8 pad1;
208 u8 qos_entries;
209 u8 pad2;
210 __le16 fs_entries;
211 __le16 pad3;
212 /* response word 2 */
213 u8 qos_key_size;
214 u8 fs_key_size;
215 __le16 wriop_version;
216};
217
218#define DPNI_ERROR_ACTION_SHIFT 0
219#define DPNI_ERROR_ACTION_SIZE 4
220#define DPNI_FRAME_ANN_SHIFT 4
221#define DPNI_FRAME_ANN_SIZE 1
222
223struct dpni_cmd_set_errors_behavior {
224 __le32 errors;
225 /* from least significant bit: error_action:4, set_frame_annotation:1 */
226 u8 flags;
227};
228
229/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation
230 * buffer layouts, but they all share the same parameters.
231 * If one of the functions changes, below structure needs to be split.
232 */
233
234#define DPNI_PASS_TS_SHIFT 0
235#define DPNI_PASS_TS_SIZE 1
236#define DPNI_PASS_PR_SHIFT 1
237#define DPNI_PASS_PR_SIZE 1
238#define DPNI_PASS_FS_SHIFT 2
239#define DPNI_PASS_FS_SIZE 1
240
241struct dpni_cmd_get_buffer_layout {
242 u8 qtype;
243};
244
245struct dpni_rsp_get_buffer_layout {
246 /* response word 0 */
247 u8 pad0[6];
248 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
249 u8 flags;
250 u8 pad1;
251 /* response word 1 */
252 __le16 private_data_size;
253 __le16 data_align;
254 __le16 head_room;
255 __le16 tail_room;
256};
257
258struct dpni_cmd_set_buffer_layout {
259 /* cmd word 0 */
260 u8 qtype;
261 u8 pad0[3];
262 __le16 options;
263 /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
264 u8 flags;
265 u8 pad1;
266 /* cmd word 1 */
267 __le16 private_data_size;
268 __le16 data_align;
269 __le16 head_room;
270 __le16 tail_room;
271};
272
273struct dpni_cmd_set_offload {
274 u8 pad[3];
275 u8 dpni_offload;
276 __le32 config;
277};
278
279struct dpni_cmd_get_offload {
280 u8 pad[3];
281 u8 dpni_offload;
282};
283
284struct dpni_rsp_get_offload {
285 __le32 pad;
286 __le32 config;
287};
288
289struct dpni_cmd_get_qdid {
290 u8 qtype;
291};
292
293struct dpni_rsp_get_qdid {
294 __le16 qdid;
295};
296
297struct dpni_rsp_get_tx_data_offset {
298 __le16 data_offset;
299};
300
301struct dpni_cmd_get_statistics {
302 u8 page_number;
303};
304
305struct dpni_rsp_get_statistics {
306 __le64 counter[DPNI_STATISTICS_CNT];
307};
308
309struct dpni_cmd_link_cfg {
310 /* cmd word 0 */
311 __le64 pad0;
312 /* cmd word 1 */
313 __le32 rate;
314 __le32 pad1;
315 /* cmd word 2 */
316 __le64 options;
317};
318
319#define DPNI_LINK_STATE_SHIFT 0
320#define DPNI_LINK_STATE_SIZE 1
321
322struct dpni_rsp_get_link_state {
323 /* response word 0 */
324 __le32 pad0;
325 /* from LSB: up:1 */
326 u8 flags;
327 u8 pad1[3];
328 /* response word 1 */
329 __le32 rate;
330 __le32 pad2;
331 /* response word 2 */
332 __le64 options;
333};
334
335struct dpni_cmd_set_max_frame_length {
336 __le16 max_frame_length;
337};
338
339struct dpni_rsp_get_max_frame_length {
340 __le16 max_frame_length;
341};
342
343struct dpni_cmd_set_multicast_promisc {
344 u8 enable;
345};
346
347struct dpni_rsp_get_multicast_promisc {
348 u8 enabled;
349};
350
351struct dpni_cmd_set_unicast_promisc {
352 u8 enable;
353};
354
355struct dpni_rsp_get_unicast_promisc {
356 u8 enabled;
357};
358
359struct dpni_cmd_set_primary_mac_addr {
360 __le16 pad;
361 u8 mac_addr[6];
362};
363
364struct dpni_rsp_get_primary_mac_addr {
365 __le16 pad;
366 u8 mac_addr[6];
367};
368
369struct dpni_rsp_get_port_mac_addr {
370 __le16 pad;
371 u8 mac_addr[6];
372};
373
374struct dpni_cmd_add_mac_addr {
375 __le16 pad;
376 u8 mac_addr[6];
377};
378
379struct dpni_cmd_remove_mac_addr {
380 __le16 pad;
381 u8 mac_addr[6];
382};
383
384#define DPNI_UNICAST_FILTERS_SHIFT 0
385#define DPNI_UNICAST_FILTERS_SIZE 1
386#define DPNI_MULTICAST_FILTERS_SHIFT 1
387#define DPNI_MULTICAST_FILTERS_SIZE 1
388
389struct dpni_cmd_clear_mac_filters {
390 /* from LSB: unicast:1, multicast:1 */
391 u8 flags;
392};
393
394#define DPNI_DIST_MODE_SHIFT 0
395#define DPNI_DIST_MODE_SIZE 4
396#define DPNI_MISS_ACTION_SHIFT 4
397#define DPNI_MISS_ACTION_SIZE 4
398
399struct dpni_cmd_set_rx_tc_dist {
400 /* cmd word 0 */
401 __le16 dist_size;
402 u8 tc_id;
403 /* from LSB: dist_mode:4, miss_action:4 */
404 u8 flags;
405 __le16 pad0;
406 __le16 default_flow_id;
407 /* cmd word 1..5 */
408 __le64 pad1[5];
409 /* cmd word 6 */
410 __le64 key_cfg_iova;
411};
412
413/* dpni_set_rx_tc_dist extension (structure of the DMA-able memory at
414 * key_cfg_iova)
415 */
416struct dpni_mask_cfg {
417 u8 mask;
418 u8 offset;
419};
420
421#define DPNI_EFH_TYPE_SHIFT 0
422#define DPNI_EFH_TYPE_SIZE 4
423#define DPNI_EXTRACT_TYPE_SHIFT 0
424#define DPNI_EXTRACT_TYPE_SIZE 4
425
426struct dpni_dist_extract {
427 /* word 0 */
428 u8 prot;
429 /* EFH type stored in the 4 least significant bits */
430 u8 efh_type;
431 u8 size;
432 u8 offset;
433 __le32 field;
434 /* word 1 */
435 u8 hdr_index;
436 u8 constant;
437 u8 num_of_repeats;
438 u8 num_of_byte_masks;
439 /* Extraction type is stored in the 4 LSBs */
440 u8 extract_type;
441 u8 pad[3];
442 /* word 2 */
443 struct dpni_mask_cfg masks[4];
444};
445
446struct dpni_ext_set_rx_tc_dist {
447 /* extension word 0 */
448 u8 num_extracts;
449 u8 pad[7];
450 /* words 1..25 */
451 struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
452};
453
454struct dpni_cmd_get_queue {
455 u8 qtype;
456 u8 tc;
457 u8 index;
458};
459
460#define DPNI_DEST_TYPE_SHIFT 0
461#define DPNI_DEST_TYPE_SIZE 4
462#define DPNI_STASH_CTRL_SHIFT 6
463#define DPNI_STASH_CTRL_SIZE 1
464#define DPNI_HOLD_ACTIVE_SHIFT 7
465#define DPNI_HOLD_ACTIVE_SIZE 1
466
467struct dpni_rsp_get_queue {
468 /* response word 0 */
469 __le64 pad0;
470 /* response word 1 */
471 __le32 dest_id;
472 __le16 pad1;
473 u8 dest_prio;
474 /* From LSB: dest_type:4, pad:2, flc_stash_ctrl:1, hold_active:1 */
475 u8 flags;
476 /* response word 2 */
477 __le64 flc;
478 /* response word 3 */
479 __le64 user_context;
480 /* response word 4 */
481 __le32 fqid;
482 __le16 qdbin;
483};
484
485struct dpni_cmd_set_queue {
486 /* cmd word 0 */
487 u8 qtype;
488 u8 tc;
489 u8 index;
490 u8 options;
491 __le32 pad0;
492 /* cmd word 1 */
493 __le32 dest_id;
494 __le16 pad1;
495 u8 dest_prio;
496 u8 flags;
497 /* cmd word 2 */
498 __le64 flc;
499 /* cmd word 3 */
500 __le64 user_context;
501};
502
503struct dpni_cmd_set_taildrop {
504 /* cmd word 0 */
505 u8 congestion_point;
506 u8 qtype;
507 u8 tc;
508 u8 index;
509 __le32 pad0;
510 /* cmd word 1 */
511 /* Only least significant bit is relevant */
512 u8 enable;
513 u8 pad1;
514 u8 units;
515 u8 pad2;
516 __le32 threshold;
517};
518
519struct dpni_cmd_get_taildrop {
520 u8 congestion_point;
521 u8 qtype;
522 u8 tc;
523 u8 index;
524};
525
526struct dpni_rsp_get_taildrop {
527 /* cmd word 0 */
528 __le64 pad0;
529 /* cmd word 1 */
530 /* only least significant bit is relevant */
531 u8 enable;
532 u8 pad1;
533 u8 units;
534 u8 pad2;
535 __le32 threshold;
536};
537
538struct dpni_rsp_get_api_version {
539 __le16 major;
540 __le16 minor;
541};
542
543#define DPNI_RX_FS_DIST_ENABLE_SHIFT 0
544#define DPNI_RX_FS_DIST_ENABLE_SIZE 1
545struct dpni_cmd_set_rx_fs_dist {
546 __le16 dist_size;
547 u8 enable;
548 u8 tc;
549 __le16 miss_flow_id;
550 __le16 pad;
551 __le64 key_cfg_iova;
552};
553
554#define DPNI_RX_HASH_DIST_ENABLE_SHIFT 0
555#define DPNI_RX_HASH_DIST_ENABLE_SIZE 1
556struct dpni_cmd_set_rx_hash_dist {
557 __le16 dist_size;
558 u8 enable;
559 u8 tc;
560 __le32 pad;
561 __le64 key_cfg_iova;
562};
563
564struct dpni_cmd_add_fs_entry {
565 /* cmd word 0 */
566 __le16 options;
567 u8 tc_id;
568 u8 key_size;
569 __le16 index;
570 __le16 flow_id;
571 /* cmd word 1 */
572 __le64 key_iova;
573 /* cmd word 2 */
574 __le64 mask_iova;
575 /* cmd word 3 */
576 __le64 flc;
577};
578
579struct dpni_cmd_remove_fs_entry {
580 /* cmd word 0 */
581 __le16 pad0;
582 u8 tc_id;
583 u8 key_size;
584 __le32 pad1;
585 /* cmd word 1 */
586 __le64 key_iova;
587 /* cmd word 2 */
588 __le64 mask_iova;
589};
590
591#define DPNI_DISCARD_ON_MISS_SHIFT 0
592#define DPNI_DISCARD_ON_MISS_SIZE 1
593
594struct dpni_cmd_set_qos_table {
595 __le32 pad;
596 u8 default_tc;
597 /* only the LSB */
598 u8 discard_on_miss;
599 __le16 pad1[21];
600 __le64 key_cfg_iova;
601};
602
603struct dpni_cmd_add_qos_entry {
604 __le16 pad;
605 u8 tc_id;
606 u8 key_size;
607 __le16 index;
608 __le16 pad1;
609 __le64 key_iova;
610 __le64 mask_iova;
611};
612
613struct dpni_cmd_remove_qos_entry {
614 u8 pad[3];
615 u8 key_size;
616 __le32 pad1;
617 __le64 key_iova;
618 __le64 mask_iova;
619};
620
621#define DPNI_DEST_TYPE_SHIFT 0
622#define DPNI_DEST_TYPE_SIZE 4
623#define DPNI_CONG_UNITS_SHIFT 4
624#define DPNI_CONG_UNITS_SIZE 2
625
626struct dpni_cmd_set_congestion_notification {
627 /* cmd word 0 */
628 u8 qtype;
629 u8 tc;
630 u8 pad[6];
631 /* cmd word 1 */
632 __le32 dest_id;
633 __le16 notification_mode;
634 u8 dest_priority;
635 /* from LSB: dest_type: 4 units:2 */
636 u8 type_units;
637 /* cmd word 2 */
638 __le64 message_iova;
639 /* cmd word 3 */
640 __le64 message_ctx;
641 /* cmd word 4 */
642 __le32 threshold_entry;
643 __le32 threshold_exit;
644};
645
646#define DPNI_COUPLED_SHIFT 0
647#define DPNI_COUPLED_SIZE 1
648
649struct dpni_cmd_set_tx_shaping {
650 __le16 tx_cr_max_burst_size;
651 __le16 tx_er_max_burst_size;
652 __le32 pad;
653 __le32 tx_cr_rate_limit;
654 __le32 tx_er_rate_limit;
655 /* from LSB: coupled:1 */
656 u8 coupled;
657};
658
659#define DPNI_PTP_ENABLE_SHIFT 0
660#define DPNI_PTP_ENABLE_SIZE 1
661#define DPNI_PTP_CH_UPDATE_SHIFT 1
662#define DPNI_PTP_CH_UPDATE_SIZE 1
663
664struct dpni_cmd_single_step_cfg {
665 __le16 flags;
666 __le16 offset;
667 __le32 peer_delay;
668 __le32 ptp_onestep_reg_base;
669 __le32 pad0;
670};
671
672struct dpni_rsp_single_step_cfg {
673 __le16 flags;
674 __le16 offset;
675 __le32 peer_delay;
676 __le32 ptp_onestep_reg_base;
677 __le32 pad0;
678};
679
680struct dpni_cmd_enable_vlan_filter {
681 /* only the LSB */
682 u8 en;
683};
684
685struct dpni_cmd_vlan_id {
686 u8 flags;
687 u8 tc_id;
688 u8 flow_id;
689 u8 pad;
690 __le16 vlan_id;
691};
692
693#endif /* _FSL_DPNI_CMD_H */