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1perf-c2c(1)
2===========
3
4NAME
5----
6perf-c2c - Shared Data C2C/HITM Analyzer.
7
8SYNOPSIS
9--------
10[verse]
11'perf c2c record' [<options>] <command>
12'perf c2c record' [<options>] -- [<record command options>] <command>
13'perf c2c report' [<options>]
14
15DESCRIPTION
16-----------
17C2C stands for Cache To Cache.
18
19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20you to track down the cacheline contentions.
21
22On x86, the tool is based on load latency and precise store facility events
23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24with thresholding feature.
25
26These events provide:
27 - memory address of the access
28 - type of the access (load and store details)
29 - latency (in cycles) of the load access
30
31The c2c tool provide means to record this data and report back access details
32for cachelines with highest contention - highest number of HITM accesses.
33
34The basic workflow with this tool follows the standard record/report phase.
35User uses the record command to record events data and report command to
36display it.
37
38
39RECORD OPTIONS
40--------------
41-e::
42--event=::
43 Select the PMU event. Use 'perf c2c record -e list'
44 to list available events.
45
46-v::
47--verbose::
48 Be more verbose (show counter open errors, etc).
49
50-l::
51--ldlat::
52 Configure mem-loads latency. (x86 only)
53
54-k::
55--all-kernel::
56 Configure all used events to run in kernel space.
57
58-u::
59--all-user::
60 Configure all used events to run in user space.
61
62REPORT OPTIONS
63--------------
64-k::
65--vmlinux=<file>::
66 vmlinux pathname
67
68-v::
69--verbose::
70 Be more verbose (show counter open errors, etc).
71
72-i::
73--input::
74 Specify the input file to process.
75
76-N::
77--node-info::
78 Show extra node info in report (see NODE INFO section)
79
80-c::
81--coalesce::
82 Specify sorting fields for single cacheline display.
83 Following fields are available: tid,pid,iaddr,dso
84 (see COALESCE)
85
86-g::
87--call-graph::
88 Setup callchains parameters.
89 Please refer to perf-report man page for details.
90
91--stdio::
92 Force the stdio output (see STDIO OUTPUT)
93
94--stats::
95 Display only statistic tables and force stdio mode.
96
97--full-symbols::
98 Display full length of symbols.
99
100--no-source::
101 Do not display Source:Line column.
102
103--show-all::
104 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
105
106-f::
107--force::
108 Don't do ownership validation.
109
110-d::
111--display::
112 Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
113
114--stitch-lbr::
115 Show callgraph with stitched LBRs, which may have more complete
116 callgraph. The perf.data file must have been obtained using
117 perf c2c record --call-graph lbr.
118 Disabled by default. In common cases with call stack overflows,
119 it can recreate better call stacks than the default lbr call stack
120 output. But this approach is not full proof. There can be cases
121 where it creates incorrect call stacks from incorrect matches.
122 The known limitations include exception handing such as
123 setjmp/longjmp will have calls/returns not match.
124
125C2C RECORD
126----------
127The perf c2c record command setup options related to HITM cacheline analysis
128and calls standard perf record command.
129
130Following perf record options are configured by default:
131(check perf record man page for details)
132
133 -W,-d,--phys-data,--sample-cpu
134
135Unless specified otherwise with '-e' option, following events are monitored by
136default on x86:
137
138 cpu/mem-loads,ldlat=30/P
139 cpu/mem-stores/P
140
141and following on PowerPC:
142
143 cpu/mem-loads/
144 cpu/mem-stores/
145
146User can pass any 'perf record' option behind '--' mark, like (to enable
147callchains and system wide monitoring):
148
149 $ perf c2c record -- -g -a
150
151Please check RECORD OPTIONS section for specific c2c record options.
152
153C2C REPORT
154----------
155The perf c2c report command displays shared data analysis. It comes in two
156display modes: stdio and tui (default).
157
158The report command workflow is following:
159 - sort all the data based on the cacheline address
160 - store access details for each cacheline
161 - sort all cachelines based on user settings
162 - display data
163
164In general perf report output consist of 2 basic views:
165 1) most expensive cachelines list
166 2) offsets details for each cacheline
167
168For each cacheline in the 1) list we display following data:
169(Both stdio and TUI modes follow the same fields output)
170
171 Index
172 - zero based index to identify the cacheline
173
174 Cacheline
175 - cacheline address (hex number)
176
177 Rmt/Lcl Hitm
178 - cacheline percentage of all Remote/Local HITM accesses
179
180 LLC Load Hitm - Total, LclHitm, RmtHitm
181 - count of Total/Local/Remote load HITMs
182
183 Total records
184 - sum of all cachelines accesses
185
186 Total loads
187 - sum of all load accesses
188
189 Total stores
190 - sum of all store accesses
191
192 Store Reference - L1Hit, L1Miss
193 L1Hit - store accesses that hit L1
194 L1Miss - store accesses that missed L1
195
196 Core Load Hit - FB, L1, L2
197 - count of load hits in FB (Fill Buffer), L1 and L2 cache
198
199 LLC Load Hit - LlcHit, LclHitm
200 - count of LLC load accesses, includes LLC hits and LLC HITMs
201
202 RMT Load Hit - RmtHit, RmtHitm
203 - count of remote load accesses, includes remote hits and remote HITMs
204
205 Load Dram - Lcl, Rmt
206 - count of local and remote DRAM accesses
207
208For each offset in the 2) list we display following data:
209
210 HITM - Rmt, Lcl
211 - % of Remote/Local HITM accesses for given offset within cacheline
212
213 Store Refs - L1 Hit, L1 Miss
214 - % of store accesses that hit/missed L1 for given offset within cacheline
215
216 Data address - Offset
217 - offset address
218
219 Pid
220 - pid of the process responsible for the accesses
221
222 Tid
223 - tid of the process responsible for the accesses
224
225 Code address
226 - code address responsible for the accesses
227
228 cycles - rmt hitm, lcl hitm, load
229 - sum of cycles for given accesses - Remote/Local HITM and generic load
230
231 cpu cnt
232 - number of cpus that participated on the access
233
234 Symbol
235 - code symbol related to the 'Code address' value
236
237 Shared Object
238 - shared object name related to the 'Code address' value
239
240 Source:Line
241 - source information related to the 'Code address' value
242
243 Node
244 - nodes participating on the access (see NODE INFO section)
245
246NODE INFO
247---------
248The 'Node' field displays nodes that accesses given cacheline
249offset. Its output comes in 3 flavors:
250 - node IDs separated by ','
251 - node IDs with stats for each ID, in following format:
252 Node{cpus %hitms %stores}
253 - node IDs with list of affected CPUs in following format:
254 Node{cpu list}
255
256User can switch between above flavors with -N option or
257use 'n' key to interactively switch in TUI mode.
258
259COALESCE
260--------
261User can specify how to sort offsets for cacheline.
262
263Following fields are available and governs the final
264output fields set for caheline offsets output:
265
266 tid - coalesced by process TIDs
267 pid - coalesced by process PIDs
268 iaddr - coalesced by code address, following fields are displayed:
269 Code address, Code symbol, Shared Object, Source line
270 dso - coalesced by shared object
271
272By default the coalescing is setup with 'pid,iaddr'.
273
274STDIO OUTPUT
275------------
276The stdio output displays data on standard output.
277
278Following tables are displayed:
279 Trace Event Information
280 - overall statistics of memory accesses
281
282 Global Shared Cache Line Event Information
283 - overall statistics on shared cachelines
284
285 Shared Data Cache Line Table
286 - list of most expensive cachelines
287
288 Shared Cache Line Distribution Pareto
289 - list of all accessed offsets for each cacheline
290
291TUI OUTPUT
292----------
293The TUI output provides interactive interface to navigate
294through cachelines list and to display offset details.
295
296For details please refer to the help window by pressing '?' key.
297
298CREDITS
299-------
300Although Don Zickus, Dick Fowles and Joe Mario worked together
301to get this implemented, we got lots of early help from Arnaldo
302Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
303
304C2C BLOG
305--------
306Check Joe's blog on c2c tool for detailed use case explanation:
307 https://joemario.github.io/blog/2016/09/01/c2c-blog/
308
309SEE ALSO
310--------
311linkperf:perf-record[1], linkperf:perf-mem[1]
1perf-c2c(1)
2===========
3
4NAME
5----
6perf-c2c - Shared Data C2C/HITM Analyzer.
7
8SYNOPSIS
9--------
10[verse]
11'perf c2c record' [<options>] <command>
12'perf c2c record' [<options>] \-- [<record command options>] <command>
13'perf c2c report' [<options>]
14
15DESCRIPTION
16-----------
17C2C stands for Cache To Cache.
18
19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20you to track down the cacheline contentions.
21
22On Intel, the tool is based on load latency and precise store facility events
23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
25limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to
26sample load and store operations, therefore hardware and kernel support is
27required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
28statistical nature of Arm SPE sampling, not every memory operation will be
29sampled.
30
31These events provide:
32 - memory address of the access
33 - type of the access (load and store details)
34 - latency (in cycles) of the load access
35
36The c2c tool provide means to record this data and report back access details
37for cachelines with highest contention - highest number of HITM accesses.
38
39The basic workflow with this tool follows the standard record/report phase.
40User uses the record command to record events data and report command to
41display it.
42
43
44RECORD OPTIONS
45--------------
46-e::
47--event=::
48 Select the PMU event. Use 'perf c2c record -e list'
49 to list available events.
50
51-v::
52--verbose::
53 Be more verbose (show counter open errors, etc).
54
55-l::
56--ldlat::
57 Configure mem-loads latency. Supported on Intel and Arm64 processors
58 only. Ignored on other archs.
59
60-k::
61--all-kernel::
62 Configure all used events to run in kernel space.
63
64-u::
65--all-user::
66 Configure all used events to run in user space.
67
68REPORT OPTIONS
69--------------
70-k::
71--vmlinux=<file>::
72 vmlinux pathname
73
74-v::
75--verbose::
76 Be more verbose (show counter open errors, etc).
77
78-i::
79--input::
80 Specify the input file to process.
81
82-N::
83--node-info::
84 Show extra node info in report (see NODE INFO section)
85
86-c::
87--coalesce::
88 Specify sorting fields for single cacheline display.
89 Following fields are available: tid,pid,iaddr,dso
90 (see COALESCE)
91
92-g::
93--call-graph::
94 Setup callchains parameters.
95 Please refer to perf-report man page for details.
96
97--stdio::
98 Force the stdio output (see STDIO OUTPUT)
99
100--stats::
101 Display only statistic tables and force stdio mode.
102
103--full-symbols::
104 Display full length of symbols.
105
106--no-source::
107 Do not display Source:Line column.
108
109--show-all::
110 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
111
112-f::
113--force::
114 Don't do ownership validation.
115
116-d::
117--display::
118 Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display
119 and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode
120 as default.
121
122--stitch-lbr::
123 Show callgraph with stitched LBRs, which may have more complete
124 callgraph. The perf.data file must have been obtained using
125 perf c2c record --call-graph lbr.
126 Disabled by default. In common cases with call stack overflows,
127 it can recreate better call stacks than the default lbr call stack
128 output. But this approach is not foolproof. There can be cases
129 where it creates incorrect call stacks from incorrect matches.
130 The known limitations include exception handing such as
131 setjmp/longjmp will have calls/returns not match.
132
133--double-cl::
134 Group the detection of shared cacheline events into double cacheline
135 granularity. Some architectures have an Adjacent Cacheline Prefetch
136 feature, which causes cacheline sharing to behave like the cacheline
137 size is doubled.
138
139C2C RECORD
140----------
141The perf c2c record command setup options related to HITM cacheline analysis
142and calls standard perf record command.
143
144Following perf record options are configured by default:
145(check perf record man page for details)
146
147 -W,-d,--phys-data,--sample-cpu
148
149Unless specified otherwise with '-e' option, following events are monitored by
150default on Intel:
151
152 cpu/mem-loads,ldlat=30/P
153 cpu/mem-stores/P
154
155following on AMD:
156
157 ibs_op//
158
159and following on PowerPC:
160
161 cpu/mem-loads/
162 cpu/mem-stores/
163
164User can pass any 'perf record' option behind '--' mark, like (to enable
165callchains and system wide monitoring):
166
167 $ perf c2c record -- -g -a
168
169Please check RECORD OPTIONS section for specific c2c record options.
170
171C2C REPORT
172----------
173The perf c2c report command displays shared data analysis. It comes in two
174display modes: stdio and tui (default).
175
176The report command workflow is following:
177 - sort all the data based on the cacheline address
178 - store access details for each cacheline
179 - sort all cachelines based on user settings
180 - display data
181
182In general perf report output consist of 2 basic views:
183 1) most expensive cachelines list
184 2) offsets details for each cacheline
185
186For each cacheline in the 1) list we display following data:
187(Both stdio and TUI modes follow the same fields output)
188
189 Index
190 - zero based index to identify the cacheline
191
192 Cacheline
193 - cacheline address (hex number)
194
195 Rmt/Lcl Hitm (Display with HITM types)
196 - cacheline percentage of all Remote/Local HITM accesses
197
198 Peer Snoop (Display with peer type)
199 - cacheline percentage of all peer accesses
200
201 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
202 - count of Total/Local/Remote load HITMs
203
204 Load Peer - Total, Local, Remote (For display with peer type)
205 - count of Total/Local/Remote load from peer cache or DRAM
206
207 Total records
208 - sum of all cachelines accesses
209
210 Total loads
211 - sum of all load accesses
212
213 Total stores
214 - sum of all store accesses
215
216 Store Reference - L1Hit, L1Miss, N/A
217 L1Hit - store accesses that hit L1
218 L1Miss - store accesses that missed L1
219 N/A - store accesses with memory level is not available
220
221 Core Load Hit - FB, L1, L2
222 - count of load hits in FB (Fill Buffer), L1 and L2 cache
223
224 LLC Load Hit - LlcHit, LclHitm
225 - count of LLC load accesses, includes LLC hits and LLC HITMs
226
227 RMT Load Hit - RmtHit, RmtHitm
228 - count of remote load accesses, includes remote hits and remote HITMs;
229 on Arm neoverse cores, RmtHit is used to account remote accesses,
230 includes remote DRAM or any upward cache level in remote node
231
232 Load Dram - Lcl, Rmt
233 - count of local and remote DRAM accesses
234
235For each offset in the 2) list we display following data:
236
237 HITM - Rmt, Lcl (Display with HITM types)
238 - % of Remote/Local HITM accesses for given offset within cacheline
239
240 Peer Snoop - Rmt, Lcl (Display with peer type)
241 - % of Remote/Local peer accesses for given offset within cacheline
242
243 Store Refs - L1 Hit, L1 Miss, N/A
244 - % of store accesses that hit L1, missed L1 and N/A (no available) memory
245 level for given offset within cacheline
246
247 Data address - Offset
248 - offset address
249
250 Pid
251 - pid of the process responsible for the accesses
252
253 Tid
254 - tid of the process responsible for the accesses
255
256 Code address
257 - code address responsible for the accesses
258
259 cycles - rmt hitm, lcl hitm, load (Display with HITM types)
260 - sum of cycles for given accesses - Remote/Local HITM and generic load
261
262 cycles - rmt peer, lcl peer, load (Display with peer type)
263 - sum of cycles for given accesses - Remote/Local peer load and generic load
264
265 cpu cnt
266 - number of cpus that participated on the access
267
268 Symbol
269 - code symbol related to the 'Code address' value
270
271 Shared Object
272 - shared object name related to the 'Code address' value
273
274 Source:Line
275 - source information related to the 'Code address' value
276
277 Node
278 - nodes participating on the access (see NODE INFO section)
279
280NODE INFO
281---------
282The 'Node' field displays nodes that accesses given cacheline
283offset. Its output comes in 3 flavors:
284 - node IDs separated by ','
285 - node IDs with stats for each ID, in following format:
286 Node{cpus %hitms %stores} (Display with HITM types)
287 Node{cpus %peers %stores} (Display with peer type)
288 - node IDs with list of affected CPUs in following format:
289 Node{cpu list}
290
291User can switch between above flavors with -N option or
292use 'n' key to interactively switch in TUI mode.
293
294COALESCE
295--------
296User can specify how to sort offsets for cacheline.
297
298Following fields are available and governs the final
299output fields set for cacheline offsets output:
300
301 tid - coalesced by process TIDs
302 pid - coalesced by process PIDs
303 iaddr - coalesced by code address, following fields are displayed:
304 Code address, Code symbol, Shared Object, Source line
305 dso - coalesced by shared object
306
307By default the coalescing is setup with 'pid,iaddr'.
308
309STDIO OUTPUT
310------------
311The stdio output displays data on standard output.
312
313Following tables are displayed:
314 Trace Event Information
315 - overall statistics of memory accesses
316
317 Global Shared Cache Line Event Information
318 - overall statistics on shared cachelines
319
320 Shared Data Cache Line Table
321 - list of most expensive cachelines
322
323 Shared Cache Line Distribution Pareto
324 - list of all accessed offsets for each cacheline
325
326TUI OUTPUT
327----------
328The TUI output provides interactive interface to navigate
329through cachelines list and to display offset details.
330
331For details please refer to the help window by pressing '?' key.
332
333CREDITS
334-------
335Although Don Zickus, Dick Fowles and Joe Mario worked together
336to get this implemented, we got lots of early help from Arnaldo
337Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
338
339C2C BLOG
340--------
341Check Joe's blog on c2c tool for detailed use case explanation:
342 https://joemario.github.io/blog/2016/09/01/c2c-blog/
343
344SEE ALSO
345--------
346linkperf:perf-record[1], linkperf:perf-mem[1], linkperf:perf-arm-spe[1]