1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *   ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
   4 *
   5 *      Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
   6 *                              Pilo Chambert <pilo.c@wanadoo.fr>
   7 *
   8 *      Thanks to :        Anders Torger <torger@ludd.luth.se>,
   9 *                         Henk Hesselink <henk@anda.nl>
  10 *                         for writing the digi96-driver 
  11 *                         and RME for all informations.
  12 * 
  13 * ****************************************************************************
  14 * 
  15 * Note #1 "Sek'd models" ................................... martin 2002-12-07
  16 * 
  17 * Identical soundcards by Sek'd were labeled:
  18 * RME Digi 32     = Sek'd Prodif 32
  19 * RME Digi 32 Pro = Sek'd Prodif 96
  20 * RME Digi 32/8   = Sek'd Prodif Gold
  21 * 
  22 * ****************************************************************************
  23 * 
  24 * Note #2 "full duplex mode" ............................... martin 2002-12-07
  25 * 
  26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
  27 * in this mode. Rec data and play data are using the same buffer therefore. At
  28 * first you have got the playing bits in the buffer and then (after playing
  29 * them) they were overwitten by the captured sound of the CS8412/14. Both 
  30 * modes (play/record) are running harmonically hand in hand in the same buffer
  31 * and you have only one start bit plus one interrupt bit to control this 
  32 * paired action.
  33 * This is opposite to the latter rme96 where playing and capturing is totally
  34 * separated and so their full duplex mode is supported by alsa (using two 
  35 * start bits and two interrupts for two different buffers). 
  36 * But due to the wrong sequence of playing and capturing ALSA shows no solved
  37 * full duplex support for the rme32 at the moment. That's bad, but I'm not
  38 * able to solve it. Are you motivated enough to solve this problem now? Your
  39 * patch would be welcome!
  40 * 
  41 * ****************************************************************************
  42 *
  43 * "The story after the long seeking" -- tiwai
  44 *
  45 * Ok, the situation regarding the full duplex is now improved a bit.
  46 * In the fullduplex mode (given by the module parameter), the hardware buffer
  47 * is split to halves for read and write directions at the DMA pointer.
  48 * That is, the half above the current DMA pointer is used for write, and
  49 * the half below is used for read.  To mangle this strange behavior, an
  50 * software intermediate buffer is introduced.  This is, of course, not good
  51 * from the viewpoint of the data transfer efficiency.  However, this allows
  52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
  53 *
  54 * ****************************************************************************
  55 */
  56
  57
  58#include <linux/delay.h>
  59#include <linux/gfp.h>
  60#include <linux/init.h>
  61#include <linux/interrupt.h>
  62#include <linux/pci.h>
  63#include <linux/module.h>
  64#include <linux/io.h>
  65
  66#include <sound/core.h>
  67#include <sound/info.h>
  68#include <sound/control.h>
  69#include <sound/pcm.h>
  70#include <sound/pcm_params.h>
  71#include <sound/pcm-indirect.h>
  72#include <sound/asoundef.h>
  73#include <sound/initval.h>
  74
  75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
  76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
  77static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
  78static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
  79
  80module_param_array(index, int, NULL, 0444);
  81MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
  82module_param_array(id, charp, NULL, 0444);
  83MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
  84module_param_array(enable, bool, NULL, 0444);
  85MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
  86module_param_array(fullduplex, bool, NULL, 0444);
  87MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
  88MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
  89MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
  90MODULE_LICENSE("GPL");
  91
  92/* Defines for RME Digi32 series */
  93#define RME32_SPDIF_NCHANNELS 2
  94
  95/* Playback and capture buffer size */
  96#define RME32_BUFFER_SIZE 0x20000
  97
  98/* IO area size */
  99#define RME32_IO_SIZE 0x30000
 100
 101/* IO area offsets */
 102#define RME32_IO_DATA_BUFFER        0x0
 103#define RME32_IO_CONTROL_REGISTER   0x20000
 104#define RME32_IO_GET_POS            0x20000
 105#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
 106#define RME32_IO_RESET_POS          0x20100
 107
 108/* Write control register bits */
 109#define RME32_WCR_START     (1 << 0)    /* startbit */
 110#define RME32_WCR_MONO      (1 << 1)    /* 0=stereo, 1=mono
 111                                           Setting the whole card to mono
 112                                           doesn't seem to be very useful.
 113                                           A software-solution can handle 
 114                                           full-duplex with one direction in
 115                                           stereo and the other way in mono. 
 116                                           So, the hardware should work all 
 117                                           the time in stereo! */
 118#define RME32_WCR_MODE24    (1 << 2)    /* 0=16bit, 1=32bit */
 119#define RME32_WCR_SEL       (1 << 3)    /* 0=input on output, 1=normal playback/capture */
 120#define RME32_WCR_FREQ_0    (1 << 4)    /* frequency (play) */
 121#define RME32_WCR_FREQ_1    (1 << 5)
 122#define RME32_WCR_INP_0     (1 << 6)    /* input switch */
 123#define RME32_WCR_INP_1     (1 << 7)
 124#define RME32_WCR_RESET     (1 << 8)    /* Reset address */
 125#define RME32_WCR_MUTE      (1 << 9)    /* digital mute for output */
 126#define RME32_WCR_PRO       (1 << 10)   /* 1=professional, 0=consumer */
 127#define RME32_WCR_DS_BM     (1 << 11)	/* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
 128#define RME32_WCR_ADAT      (1 << 12)	/* Adat Mode (only Adat-Version) */
 129#define RME32_WCR_AUTOSYNC  (1 << 13)   /* AutoSync */
 130#define RME32_WCR_PD        (1 << 14)	/* DAC Reset (only PRO-Version) */
 131#define RME32_WCR_EMP       (1 << 15)	/* 1=Emphasis on (only PRO-Version) */
 132
 133#define RME32_WCR_BITPOS_FREQ_0 4
 134#define RME32_WCR_BITPOS_FREQ_1 5
 135#define RME32_WCR_BITPOS_INP_0 6
 136#define RME32_WCR_BITPOS_INP_1 7
 137
 138/* Read control register bits */
 139#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
 140#define RME32_RCR_LOCK      (1 << 23)   /* 1=locked, 0=not locked */
 141#define RME32_RCR_ERF       (1 << 26)   /* 1=Error, 0=no Error */
 142#define RME32_RCR_FREQ_0    (1 << 27)   /* CS841x frequency (record) */
 143#define RME32_RCR_FREQ_1    (1 << 28)
 144#define RME32_RCR_FREQ_2    (1 << 29)
 145#define RME32_RCR_KMODE     (1 << 30)   /* card mode: 1=PLL, 0=quartz */
 146#define RME32_RCR_IRQ       (1 << 31)   /* interrupt */
 147
 148#define RME32_RCR_BITPOS_F0 27
 149#define RME32_RCR_BITPOS_F1 28
 150#define RME32_RCR_BITPOS_F2 29
 151
 152/* Input types */
 153#define RME32_INPUT_OPTICAL 0
 154#define RME32_INPUT_COAXIAL 1
 155#define RME32_INPUT_INTERNAL 2
 156#define RME32_INPUT_XLR 3
 157
 158/* Clock modes */
 159#define RME32_CLOCKMODE_SLAVE 0
 160#define RME32_CLOCKMODE_MASTER_32 1
 161#define RME32_CLOCKMODE_MASTER_44 2
 162#define RME32_CLOCKMODE_MASTER_48 3
 163
 164/* Block sizes in bytes */
 165#define RME32_BLOCK_SIZE 8192
 166
 167/* Software intermediate buffer (max) size */
 168#define RME32_MID_BUFFER_SIZE (1024*1024)
 169
 170/* Hardware revisions */
 171#define RME32_32_REVISION 192
 172#define RME32_328_REVISION_OLD 100
 173#define RME32_328_REVISION_NEW 101
 174#define RME32_PRO_REVISION_WITH_8412 192
 175#define RME32_PRO_REVISION_WITH_8414 150
 176
 177
 178struct rme32 {
 179	spinlock_t lock;
 180	int irq;
 181	unsigned long port;
 182	void __iomem *iobase;
 183
 184	u32 wcreg;		/* cached write control register value */
 185	u32 wcreg_spdif;	/* S/PDIF setup */
 186	u32 wcreg_spdif_stream;	/* S/PDIF setup (temporary) */
 187	u32 rcreg;		/* cached read control register value */
 188
 189	u8 rev;			/* card revision number */
 190
 191	struct snd_pcm_substream *playback_substream;
 192	struct snd_pcm_substream *capture_substream;
 193
 194	int playback_frlog;	/* log2 of framesize */
 195	int capture_frlog;
 196
 197	size_t playback_periodsize;	/* in bytes, zero if not used */
 198	size_t capture_periodsize;	/* in bytes, zero if not used */
 199
 200	unsigned int fullduplex_mode;
 201	int running;
 202
 203	struct snd_pcm_indirect playback_pcm;
 204	struct snd_pcm_indirect capture_pcm;
 205
 206	struct snd_card *card;
 207	struct snd_pcm *spdif_pcm;
 208	struct snd_pcm *adat_pcm;
 209	struct pci_dev *pci;
 210	struct snd_kcontrol *spdif_ctl;
 211};
 212
 213static const struct pci_device_id snd_rme32_ids[] = {
 214	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
 215	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
 216	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
 217	{0,}
 218};
 219
 220MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
 221
 222#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
 223#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
 224
 225static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
 226
 227static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
 228
 229static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
 230
 231static void snd_rme32_proc_init(struct rme32 * rme32);
 232
 233static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
 234
 235static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
 236{
 237	return (readl(rme32->iobase + RME32_IO_GET_POS)
 238		& RME32_RCR_AUDIO_ADDR_MASK);
 239}
 240
 241/* silence callback for halfduplex mode */
 242static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
 243				      int channel, unsigned long pos,
 244				      unsigned long count)
 245{
 246	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 247
 248	memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
 249	return 0;
 250}
 251
 252/* copy callback for halfduplex mode */
 253static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
 254				   int channel, unsigned long pos,
 255				   void __user *src, unsigned long count)
 256{
 257	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 258
 259	if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
 260				src, count))
 261		return -EFAULT;
 262	return 0;
 263}
 264
 265static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
 266					  int channel, unsigned long pos,
 267					  void *src, unsigned long count)
 268{
 269	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 270
 271	memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
 272	return 0;
 273}
 274
 275/* copy callback for halfduplex mode */
 276static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
 277				  int channel, unsigned long pos,
 278				  void __user *dst, unsigned long count)
 279{
 280	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 281
 282	if (copy_to_user_fromio(dst,
 283			    rme32->iobase + RME32_IO_DATA_BUFFER + pos,
 284			    count))
 285		return -EFAULT;
 286	return 0;
 287}
 288
 289static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
 290					 int channel, unsigned long pos,
 291					 void *dst, unsigned long count)
 292{
 293	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 294
 295	memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
 296	return 0;
 297}
 298
 299/*
 300 * SPDIF I/O capabilities (half-duplex mode)
 301 */
 302static const struct snd_pcm_hardware snd_rme32_spdif_info = {
 303	.info =		(SNDRV_PCM_INFO_MMAP_IOMEM |
 304			 SNDRV_PCM_INFO_MMAP_VALID |
 305			 SNDRV_PCM_INFO_INTERLEAVED | 
 306			 SNDRV_PCM_INFO_PAUSE |
 307			 SNDRV_PCM_INFO_SYNC_START |
 308			 SNDRV_PCM_INFO_SYNC_APPLPTR),
 309	.formats =	(SNDRV_PCM_FMTBIT_S16_LE | 
 310			 SNDRV_PCM_FMTBIT_S32_LE),
 311	.rates =	(SNDRV_PCM_RATE_32000 |
 312			 SNDRV_PCM_RATE_44100 | 
 313			 SNDRV_PCM_RATE_48000),
 314	.rate_min =	32000,
 315	.rate_max =	48000,
 316	.channels_min =	2,
 317	.channels_max =	2,
 318	.buffer_bytes_max = RME32_BUFFER_SIZE,
 319	.period_bytes_min = RME32_BLOCK_SIZE,
 320	.period_bytes_max = RME32_BLOCK_SIZE,
 321	.periods_min =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 322	.periods_max =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 323	.fifo_size =	0,
 324};
 325
 326/*
 327 * ADAT I/O capabilities (half-duplex mode)
 328 */
 329static const struct snd_pcm_hardware snd_rme32_adat_info =
 330{
 331	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
 332			      SNDRV_PCM_INFO_MMAP_VALID |
 333			      SNDRV_PCM_INFO_INTERLEAVED |
 334			      SNDRV_PCM_INFO_PAUSE |
 335			      SNDRV_PCM_INFO_SYNC_START |
 336			      SNDRV_PCM_INFO_SYNC_APPLPTR),
 337	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
 338	.rates =             (SNDRV_PCM_RATE_44100 | 
 339			      SNDRV_PCM_RATE_48000),
 340	.rate_min =          44100,
 341	.rate_max =          48000,
 342	.channels_min =      8,
 343	.channels_max =	     8,
 344	.buffer_bytes_max =  RME32_BUFFER_SIZE,
 345	.period_bytes_min =  RME32_BLOCK_SIZE,
 346	.period_bytes_max =  RME32_BLOCK_SIZE,
 347	.periods_min =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 348	.periods_max =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 349	.fifo_size =	    0,
 350};
 351
 352/*
 353 * SPDIF I/O capabilities (full-duplex mode)
 354 */
 355static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
 356	.info =		(SNDRV_PCM_INFO_MMAP |
 357			 SNDRV_PCM_INFO_MMAP_VALID |
 358			 SNDRV_PCM_INFO_INTERLEAVED | 
 359			 SNDRV_PCM_INFO_PAUSE |
 360			 SNDRV_PCM_INFO_SYNC_START |
 361			 SNDRV_PCM_INFO_SYNC_APPLPTR),
 362	.formats =	(SNDRV_PCM_FMTBIT_S16_LE | 
 363			 SNDRV_PCM_FMTBIT_S32_LE),
 364	.rates =	(SNDRV_PCM_RATE_32000 |
 365			 SNDRV_PCM_RATE_44100 | 
 366			 SNDRV_PCM_RATE_48000),
 367	.rate_min =	32000,
 368	.rate_max =	48000,
 369	.channels_min =	2,
 370	.channels_max =	2,
 371	.buffer_bytes_max = RME32_MID_BUFFER_SIZE,
 372	.period_bytes_min = RME32_BLOCK_SIZE,
 373	.period_bytes_max = RME32_BLOCK_SIZE,
 374	.periods_min =	2,
 375	.periods_max =	RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
 376	.fifo_size =	0,
 377};
 378
 379/*
 380 * ADAT I/O capabilities (full-duplex mode)
 381 */
 382static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
 383{
 384	.info =		     (SNDRV_PCM_INFO_MMAP |
 385			      SNDRV_PCM_INFO_MMAP_VALID |
 386			      SNDRV_PCM_INFO_INTERLEAVED |
 387			      SNDRV_PCM_INFO_PAUSE |
 388			      SNDRV_PCM_INFO_SYNC_START |
 389			      SNDRV_PCM_INFO_SYNC_APPLPTR),
 390	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
 391	.rates =             (SNDRV_PCM_RATE_44100 | 
 392			      SNDRV_PCM_RATE_48000),
 393	.rate_min =          44100,
 394	.rate_max =          48000,
 395	.channels_min =      8,
 396	.channels_max =	     8,
 397	.buffer_bytes_max =  RME32_MID_BUFFER_SIZE,
 398	.period_bytes_min =  RME32_BLOCK_SIZE,
 399	.period_bytes_max =  RME32_BLOCK_SIZE,
 400	.periods_min =	    2,
 401	.periods_max =	    RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
 402	.fifo_size =	    0,
 403};
 404
 405static void snd_rme32_reset_dac(struct rme32 *rme32)
 406{
 407        writel(rme32->wcreg | RME32_WCR_PD,
 408               rme32->iobase + RME32_IO_CONTROL_REGISTER);
 409        writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 410}
 411
 412static int snd_rme32_playback_getrate(struct rme32 * rme32)
 413{
 414	int rate;
 415
 416	rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
 417	       (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
 418	switch (rate) {
 419	case 1:
 420		rate = 32000;
 421		break;
 422	case 2:
 423		rate = 44100;
 424		break;
 425	case 3:
 426		rate = 48000;
 427		break;
 428	default:
 429		return -1;
 430	}
 431	return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
 432}
 433
 434static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
 435{
 436	int n;
 437
 438	*is_adat = 0;
 439	if (rme32->rcreg & RME32_RCR_LOCK) { 
 440                /* ADAT rate */
 441                *is_adat = 1;
 442	}
 443	if (rme32->rcreg & RME32_RCR_ERF) {
 444		return -1;
 445	}
 446
 447        /* S/PDIF rate */
 448	n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
 449		(((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
 450		(((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
 451
 452	if (RME32_PRO_WITH_8414(rme32))
 453		switch (n) {	/* supporting the CS8414 */
 454		case 0:
 455		case 1:
 456		case 2:
 457			return -1;
 458		case 3:
 459			return 96000;
 460		case 4:
 461			return 88200;
 462		case 5:
 463			return 48000;
 464		case 6:
 465			return 44100;
 466		case 7:
 467			return 32000;
 468		default:
 469			return -1;
 470		} 
 471	else
 472		switch (n) {	/* supporting the CS8412 */
 473		case 0:
 474			return -1;
 475		case 1:
 476			return 48000;
 477		case 2:
 478			return 44100;
 479		case 3:
 480			return 32000;
 481		case 4:
 482			return 48000;
 483		case 5:
 484			return 44100;
 485		case 6:
 486			return 44056;
 487		case 7:
 488			return 32000;
 489		default:
 490			break;
 491		}
 492	return -1;
 493}
 494
 495static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
 496{
 497        int ds;
 498
 499        ds = rme32->wcreg & RME32_WCR_DS_BM;
 500	switch (rate) {
 501	case 32000:
 502		rme32->wcreg &= ~RME32_WCR_DS_BM;
 503		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
 504			~RME32_WCR_FREQ_1;
 505		break;
 506	case 44100:
 507		rme32->wcreg &= ~RME32_WCR_DS_BM;
 508		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 
 509			~RME32_WCR_FREQ_0;
 510		break;
 511	case 48000:
 512		rme32->wcreg &= ~RME32_WCR_DS_BM;
 513		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
 514			RME32_WCR_FREQ_1;
 515		break;
 516	case 64000:
 517		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
 518			return -EINVAL;
 519		rme32->wcreg |= RME32_WCR_DS_BM;
 520		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
 521			~RME32_WCR_FREQ_1;
 522		break;
 523	case 88200:
 524		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
 525			return -EINVAL;
 526		rme32->wcreg |= RME32_WCR_DS_BM;
 527		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 
 528			~RME32_WCR_FREQ_0;
 529		break;
 530	case 96000:
 531		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
 532			return -EINVAL;
 533		rme32->wcreg |= RME32_WCR_DS_BM;
 534		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
 535			RME32_WCR_FREQ_1;
 536		break;
 537	default:
 538		return -EINVAL;
 539	}
 540        if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
 541            (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
 542        {
 543                /* change to/from double-speed: reset the DAC (if available) */
 544                snd_rme32_reset_dac(rme32);
 545        } else {
 546                writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 547	}
 548	return 0;
 549}
 550
 551static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
 552{
 553	switch (mode) {
 554	case RME32_CLOCKMODE_SLAVE:
 555		/* AutoSync */
 556		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 
 557			~RME32_WCR_FREQ_1;
 558		break;
 559	case RME32_CLOCKMODE_MASTER_32:
 560		/* Internal 32.0kHz */
 561		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
 562			~RME32_WCR_FREQ_1;
 563		break;
 564	case RME32_CLOCKMODE_MASTER_44:
 565		/* Internal 44.1kHz */
 566		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 
 567			RME32_WCR_FREQ_1;
 568		break;
 569	case RME32_CLOCKMODE_MASTER_48:
 570		/* Internal 48.0kHz */
 571		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
 572			RME32_WCR_FREQ_1;
 573		break;
 574	default:
 575		return -EINVAL;
 576	}
 577	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 578	return 0;
 579}
 580
 581static int snd_rme32_getclockmode(struct rme32 * rme32)
 582{
 583	return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
 584	    (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
 585}
 586
 587static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
 588{
 589	switch (type) {
 590	case RME32_INPUT_OPTICAL:
 591		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 
 592			~RME32_WCR_INP_1;
 593		break;
 594	case RME32_INPUT_COAXIAL:
 595		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 
 596			~RME32_WCR_INP_1;
 597		break;
 598	case RME32_INPUT_INTERNAL:
 599		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 
 600			RME32_WCR_INP_1;
 601		break;
 602	case RME32_INPUT_XLR:
 603		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 
 604			RME32_WCR_INP_1;
 605		break;
 606	default:
 607		return -EINVAL;
 608	}
 609	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 610	return 0;
 611}
 612
 613static int snd_rme32_getinputtype(struct rme32 * rme32)
 614{
 615	return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
 616	    (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
 617}
 618
 619static void
 620snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
 621{
 622	int frlog;
 623
 624	if (n_channels == 2) {
 625		frlog = 1;
 626	} else {
 627		/* assume 8 channels */
 628		frlog = 3;
 629	}
 630	if (is_playback) {
 631		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
 632		rme32->playback_frlog = frlog;
 633	} else {
 634		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
 635		rme32->capture_frlog = frlog;
 636	}
 637}
 638
 639static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
 640{
 641	switch (format) {
 642	case SNDRV_PCM_FORMAT_S16_LE:
 643		rme32->wcreg &= ~RME32_WCR_MODE24;
 644		break;
 645	case SNDRV_PCM_FORMAT_S32_LE:
 646		rme32->wcreg |= RME32_WCR_MODE24;
 647		break;
 648	default:
 649		return -EINVAL;
 650	}
 651	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 652	return 0;
 653}
 654
 655static int
 656snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
 657			     struct snd_pcm_hw_params *params)
 658{
 659	int err, rate, dummy;
 660	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 661	struct snd_pcm_runtime *runtime = substream->runtime;
 662
 663	if (!rme32->fullduplex_mode) {
 664		runtime->dma_area = (void __force *)(rme32->iobase +
 665						     RME32_IO_DATA_BUFFER);
 666		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
 667		runtime->dma_bytes = RME32_BUFFER_SIZE;
 668	}
 669
 670	spin_lock_irq(&rme32->lock);
 671	rate = 0;
 672	if (rme32->rcreg & RME32_RCR_KMODE)
 673		rate = snd_rme32_capture_getrate(rme32, &dummy);
 674	if (rate > 0) {
 675		/* AutoSync */
 676		if ((int)params_rate(params) != rate) {
 677			spin_unlock_irq(&rme32->lock);
 678			return -EIO;
 679		}
 680	} else {
 681		err = snd_rme32_playback_setrate(rme32, params_rate(params));
 682		if (err < 0) {
 683			spin_unlock_irq(&rme32->lock);
 684			return err;
 685		}
 686	}
 687	err = snd_rme32_setformat(rme32, params_format(params));
 688	if (err < 0) {
 689		spin_unlock_irq(&rme32->lock);
 690		return err;
 691	}
 692
 693	snd_rme32_setframelog(rme32, params_channels(params), 1);
 694	if (rme32->capture_periodsize != 0) {
 695		if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
 696			spin_unlock_irq(&rme32->lock);
 697			return -EBUSY;
 698		}
 699	}
 700	rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
 701	/* S/PDIF setup */
 702	if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
 703		rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
 704		rme32->wcreg |= rme32->wcreg_spdif_stream;
 705		writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 706	}
 707	spin_unlock_irq(&rme32->lock);
 708
 709	return 0;
 710}
 711
 712static int
 713snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
 714			    struct snd_pcm_hw_params *params)
 715{
 716	int err, isadat, rate;
 717	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 718	struct snd_pcm_runtime *runtime = substream->runtime;
 719
 720	if (!rme32->fullduplex_mode) {
 721		runtime->dma_area = (void __force *)rme32->iobase +
 722					RME32_IO_DATA_BUFFER;
 723		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
 724		runtime->dma_bytes = RME32_BUFFER_SIZE;
 725	}
 726
 727	spin_lock_irq(&rme32->lock);
 728	/* enable AutoSync for record-preparing */
 729	rme32->wcreg |= RME32_WCR_AUTOSYNC;
 730	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 731
 732	err = snd_rme32_setformat(rme32, params_format(params));
 733	if (err < 0) {
 734		spin_unlock_irq(&rme32->lock);
 735		return err;
 736	}
 737	err = snd_rme32_playback_setrate(rme32, params_rate(params));
 738	if (err < 0) {
 739		spin_unlock_irq(&rme32->lock);
 740		return err;
 741	}
 742	rate = snd_rme32_capture_getrate(rme32, &isadat);
 743	if (rate > 0) {
 744                if ((int)params_rate(params) != rate) {
 745			spin_unlock_irq(&rme32->lock);
 746                        return -EIO;                    
 747                }
 748                if ((isadat && runtime->hw.channels_min == 2) ||
 749                    (!isadat && runtime->hw.channels_min == 8)) {
 750			spin_unlock_irq(&rme32->lock);
 751                        return -EIO;
 752                }
 753	}
 754	/* AutoSync off for recording */
 755	rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
 756	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 757
 758	snd_rme32_setframelog(rme32, params_channels(params), 0);
 759	if (rme32->playback_periodsize != 0) {
 760		if (params_period_size(params) << rme32->capture_frlog !=
 761		    rme32->playback_periodsize) {
 762			spin_unlock_irq(&rme32->lock);
 763			return -EBUSY;
 764		}
 765	}
 766	rme32->capture_periodsize =
 767	    params_period_size(params) << rme32->capture_frlog;
 768	spin_unlock_irq(&rme32->lock);
 769
 770	return 0;
 771}
 772
 773static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
 774{
 775	if (!from_pause) {
 776		writel(0, rme32->iobase + RME32_IO_RESET_POS);
 777	}
 778
 779	rme32->wcreg |= RME32_WCR_START;
 780	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 781}
 782
 783static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
 784{
 785	/*
 786	 * Check if there is an unconfirmed IRQ, if so confirm it, or else
 787	 * the hardware will not stop generating interrupts
 788	 */
 789	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
 790	if (rme32->rcreg & RME32_RCR_IRQ) {
 791		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
 792	}
 793	rme32->wcreg &= ~RME32_WCR_START;
 794	if (rme32->wcreg & RME32_WCR_SEL)
 795		rme32->wcreg |= RME32_WCR_MUTE;
 796	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 797	if (! to_pause)
 798		writel(0, rme32->iobase + RME32_IO_RESET_POS);
 799}
 800
 801static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
 802{
 803	struct rme32 *rme32 = (struct rme32 *) dev_id;
 804
 805	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
 806	if (!(rme32->rcreg & RME32_RCR_IRQ)) {
 807		return IRQ_NONE;
 808	} else {
 809		if (rme32->capture_substream) {
 810			snd_pcm_period_elapsed(rme32->capture_substream);
 811		}
 812		if (rme32->playback_substream) {
 813			snd_pcm_period_elapsed(rme32->playback_substream);
 814		}
 815		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
 816	}
 817	return IRQ_HANDLED;
 818}
 819
 820static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
 821
 822static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
 823	.count = ARRAY_SIZE(period_bytes),
 824	.list = period_bytes,
 825	.mask = 0
 826};
 827
 828static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
 829{
 830	if (! rme32->fullduplex_mode) {
 831		snd_pcm_hw_constraint_single(runtime,
 832					     SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 833					     RME32_BUFFER_SIZE);
 834		snd_pcm_hw_constraint_list(runtime, 0,
 835					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 836					   &hw_constraints_period_bytes);
 837	}
 838}
 839
 840static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
 841{
 842	int rate, dummy;
 843	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 844	struct snd_pcm_runtime *runtime = substream->runtime;
 845
 846	snd_pcm_set_sync(substream);
 847
 848	spin_lock_irq(&rme32->lock);
 849	if (rme32->playback_substream != NULL) {
 850		spin_unlock_irq(&rme32->lock);
 851		return -EBUSY;
 852	}
 853	rme32->wcreg &= ~RME32_WCR_ADAT;
 854	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 855	rme32->playback_substream = substream;
 856	spin_unlock_irq(&rme32->lock);
 857
 858	if (rme32->fullduplex_mode)
 859		runtime->hw = snd_rme32_spdif_fd_info;
 860	else
 861		runtime->hw = snd_rme32_spdif_info;
 862	if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
 863		runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
 864		runtime->hw.rate_max = 96000;
 865	}
 866	rate = 0;
 867	if (rme32->rcreg & RME32_RCR_KMODE)
 868		rate = snd_rme32_capture_getrate(rme32, &dummy);
 869	if (rate > 0) {
 870		/* AutoSync */
 871		runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 872		runtime->hw.rate_min = rate;
 873		runtime->hw.rate_max = rate;
 874	}       
 875
 876	snd_rme32_set_buffer_constraint(rme32, runtime);
 877
 878	rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
 879	rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
 880	snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
 881		       SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
 882	return 0;
 883}
 884
 885static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
 886{
 887	int isadat, rate;
 888	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 889	struct snd_pcm_runtime *runtime = substream->runtime;
 890
 891	snd_pcm_set_sync(substream);
 892
 893	spin_lock_irq(&rme32->lock);
 894        if (rme32->capture_substream != NULL) {
 895		spin_unlock_irq(&rme32->lock);
 896                return -EBUSY;
 897        }
 898	rme32->capture_substream = substream;
 899	spin_unlock_irq(&rme32->lock);
 900
 901	if (rme32->fullduplex_mode)
 902		runtime->hw = snd_rme32_spdif_fd_info;
 903	else
 904		runtime->hw = snd_rme32_spdif_info;
 905	if (RME32_PRO_WITH_8414(rme32)) {
 906		runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
 907		runtime->hw.rate_max = 96000;
 908	}
 909	rate = snd_rme32_capture_getrate(rme32, &isadat);
 910	if (rate > 0) {
 911		if (isadat) {
 912			return -EIO;
 913		}
 914		runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 915		runtime->hw.rate_min = rate;
 916		runtime->hw.rate_max = rate;
 917	}
 918
 919	snd_rme32_set_buffer_constraint(rme32, runtime);
 920
 921	return 0;
 922}
 923
 924static int
 925snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
 926{
 927	int rate, dummy;
 928	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 929	struct snd_pcm_runtime *runtime = substream->runtime;
 930	
 931	snd_pcm_set_sync(substream);
 932
 933	spin_lock_irq(&rme32->lock);	
 934        if (rme32->playback_substream != NULL) {
 935		spin_unlock_irq(&rme32->lock);
 936                return -EBUSY;
 937        }
 938	rme32->wcreg |= RME32_WCR_ADAT;
 939	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 940	rme32->playback_substream = substream;
 941	spin_unlock_irq(&rme32->lock);
 942	
 943	if (rme32->fullduplex_mode)
 944		runtime->hw = snd_rme32_adat_fd_info;
 945	else
 946		runtime->hw = snd_rme32_adat_info;
 947	rate = 0;
 948	if (rme32->rcreg & RME32_RCR_KMODE)
 949		rate = snd_rme32_capture_getrate(rme32, &dummy);
 950	if (rate > 0) {
 951                /* AutoSync */
 952                runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 953                runtime->hw.rate_min = rate;
 954                runtime->hw.rate_max = rate;
 955	}        
 956
 957	snd_rme32_set_buffer_constraint(rme32, runtime);
 958	return 0;
 959}
 960
 961static int
 962snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
 963{
 964	int isadat, rate;
 965	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 966	struct snd_pcm_runtime *runtime = substream->runtime;
 967
 968	if (rme32->fullduplex_mode)
 969		runtime->hw = snd_rme32_adat_fd_info;
 970	else
 971		runtime->hw = snd_rme32_adat_info;
 972	rate = snd_rme32_capture_getrate(rme32, &isadat);
 973	if (rate > 0) {
 974		if (!isadat) {
 975			return -EIO;
 976		}
 977                runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 978                runtime->hw.rate_min = rate;
 979                runtime->hw.rate_max = rate;
 980        }
 981
 982	snd_pcm_set_sync(substream);
 983        
 984	spin_lock_irq(&rme32->lock);	
 985	if (rme32->capture_substream != NULL) {
 986		spin_unlock_irq(&rme32->lock);
 987		return -EBUSY;
 988        }
 989	rme32->capture_substream = substream;
 990	spin_unlock_irq(&rme32->lock);
 991
 992	snd_rme32_set_buffer_constraint(rme32, runtime);
 993	return 0;
 994}
 995
 996static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
 997{
 998	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 999	int spdif = 0;
1000
1001	spin_lock_irq(&rme32->lock);
1002	rme32->playback_substream = NULL;
1003	rme32->playback_periodsize = 0;
1004	spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1005	spin_unlock_irq(&rme32->lock);
1006	if (spdif) {
1007		rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1008		snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1009			       SNDRV_CTL_EVENT_MASK_INFO,
1010			       &rme32->spdif_ctl->id);
1011	}
1012	return 0;
1013}
1014
1015static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1016{
1017	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1018
1019	spin_lock_irq(&rme32->lock);
1020	rme32->capture_substream = NULL;
1021	rme32->capture_periodsize = 0;
1022	spin_unlock_irq(&rme32->lock);
1023	return 0;
1024}
1025
1026static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1027{
1028	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1029
1030	spin_lock_irq(&rme32->lock);
1031	if (rme32->fullduplex_mode) {
1032		memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1033		rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1034		rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1035	} else {
1036		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1037	}
1038	if (rme32->wcreg & RME32_WCR_SEL)
1039		rme32->wcreg &= ~RME32_WCR_MUTE;
1040	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1041	spin_unlock_irq(&rme32->lock);
1042	return 0;
1043}
1044
1045static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1046{
1047	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1048
1049	spin_lock_irq(&rme32->lock);
1050	if (rme32->fullduplex_mode) {
1051		memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1052		rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1053		rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1054		rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1055	} else {
1056		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1057	}
1058	spin_unlock_irq(&rme32->lock);
1059	return 0;
1060}
1061
1062static int
1063snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1064{
1065	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1066	struct snd_pcm_substream *s;
1067
1068	spin_lock(&rme32->lock);
1069	snd_pcm_group_for_each_entry(s, substream) {
1070		if (s != rme32->playback_substream &&
1071		    s != rme32->capture_substream)
1072			continue;
1073		switch (cmd) {
1074		case SNDRV_PCM_TRIGGER_START:
1075			rme32->running |= (1 << s->stream);
1076			if (rme32->fullduplex_mode) {
1077				/* remember the current DMA position */
1078				if (s == rme32->playback_substream) {
1079					rme32->playback_pcm.hw_io =
1080					rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1081				} else {
1082					rme32->capture_pcm.hw_io =
1083					rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1084				}
1085			}
1086			break;
1087		case SNDRV_PCM_TRIGGER_STOP:
1088			rme32->running &= ~(1 << s->stream);
1089			break;
1090		}
1091		snd_pcm_trigger_done(s, substream);
1092	}
1093	
1094	switch (cmd) {
1095	case SNDRV_PCM_TRIGGER_START:
1096		if (rme32->running && ! RME32_ISWORKING(rme32))
1097			snd_rme32_pcm_start(rme32, 0);
1098		break;
1099	case SNDRV_PCM_TRIGGER_STOP:
1100		if (! rme32->running && RME32_ISWORKING(rme32))
1101			snd_rme32_pcm_stop(rme32, 0);
1102		break;
1103	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1104		if (rme32->running && RME32_ISWORKING(rme32))
1105			snd_rme32_pcm_stop(rme32, 1);
1106		break;
1107	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108		if (rme32->running && ! RME32_ISWORKING(rme32))
1109			snd_rme32_pcm_start(rme32, 1);
1110		break;
1111	}
1112	spin_unlock(&rme32->lock);
1113	return 0;
1114}
1115
1116/* pointer callback for halfduplex mode */
1117static snd_pcm_uframes_t
1118snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1119{
1120	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1121	return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1122}
1123
1124static snd_pcm_uframes_t
1125snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1126{
1127	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1128	return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1129}
1130
1131
1132/* ack and pointer callbacks for fullduplex mode */
1133static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1134				    struct snd_pcm_indirect *rec, size_t bytes)
1135{
1136	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1137	memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1138		    substream->runtime->dma_area + rec->sw_data, bytes);
1139}
1140
1141static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1142{
1143	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1144	struct snd_pcm_indirect *rec, *cprec;
1145
1146	rec = &rme32->playback_pcm;
1147	cprec = &rme32->capture_pcm;
1148	spin_lock(&rme32->lock);
1149	rec->hw_queue_size = RME32_BUFFER_SIZE;
1150	if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1151		rec->hw_queue_size -= cprec->hw_ready;
1152	spin_unlock(&rme32->lock);
1153	return snd_pcm_indirect_playback_transfer(substream, rec,
1154						  snd_rme32_pb_trans_copy);
1155}
1156
1157static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1158				    struct snd_pcm_indirect *rec, size_t bytes)
1159{
1160	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1161	memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1162		      rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1163		      bytes);
1164}
1165
1166static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1167{
1168	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1169	return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1170						 snd_rme32_cp_trans_copy);
1171}
1172
1173static snd_pcm_uframes_t
1174snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1175{
1176	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1177	return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1178						 snd_rme32_pcm_byteptr(rme32));
1179}
1180
1181static snd_pcm_uframes_t
1182snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1183{
1184	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1185	return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1186						snd_rme32_pcm_byteptr(rme32));
1187}
1188
1189/* for halfduplex mode */
1190static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1191	.open =		snd_rme32_playback_spdif_open,
1192	.close =	snd_rme32_playback_close,
1193	.hw_params =	snd_rme32_playback_hw_params,
1194	.prepare =	snd_rme32_playback_prepare,
1195	.trigger =	snd_rme32_pcm_trigger,
1196	.pointer =	snd_rme32_playback_pointer,
1197	.copy_user =	snd_rme32_playback_copy,
1198	.copy_kernel =	snd_rme32_playback_copy_kernel,
1199	.fill_silence =	snd_rme32_playback_silence,
1200	.mmap =		snd_pcm_lib_mmap_iomem,
1201};
1202
1203static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1204	.open =		snd_rme32_capture_spdif_open,
1205	.close =	snd_rme32_capture_close,
1206	.hw_params =	snd_rme32_capture_hw_params,
1207	.prepare =	snd_rme32_capture_prepare,
1208	.trigger =	snd_rme32_pcm_trigger,
1209	.pointer =	snd_rme32_capture_pointer,
1210	.copy_user =	snd_rme32_capture_copy,
1211	.copy_kernel =	snd_rme32_capture_copy_kernel,
1212	.mmap =		snd_pcm_lib_mmap_iomem,
1213};
1214
1215static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1216	.open =		snd_rme32_playback_adat_open,
1217	.close =	snd_rme32_playback_close,
1218	.hw_params =	snd_rme32_playback_hw_params,
1219	.prepare =	snd_rme32_playback_prepare,
1220	.trigger =	snd_rme32_pcm_trigger,
1221	.pointer =	snd_rme32_playback_pointer,
1222	.copy_user =	snd_rme32_playback_copy,
1223	.copy_kernel =	snd_rme32_playback_copy_kernel,
1224	.fill_silence =	snd_rme32_playback_silence,
1225	.mmap =		snd_pcm_lib_mmap_iomem,
1226};
1227
1228static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1229	.open =		snd_rme32_capture_adat_open,
1230	.close =	snd_rme32_capture_close,
1231	.hw_params =	snd_rme32_capture_hw_params,
1232	.prepare =	snd_rme32_capture_prepare,
1233	.trigger =	snd_rme32_pcm_trigger,
1234	.pointer =	snd_rme32_capture_pointer,
1235	.copy_user =	snd_rme32_capture_copy,
1236	.copy_kernel =	snd_rme32_capture_copy_kernel,
1237	.mmap =		snd_pcm_lib_mmap_iomem,
1238};
1239
1240/* for fullduplex mode */
1241static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1242	.open =		snd_rme32_playback_spdif_open,
1243	.close =	snd_rme32_playback_close,
1244	.hw_params =	snd_rme32_playback_hw_params,
1245	.prepare =	snd_rme32_playback_prepare,
1246	.trigger =	snd_rme32_pcm_trigger,
1247	.pointer =	snd_rme32_playback_fd_pointer,
1248	.ack =		snd_rme32_playback_fd_ack,
1249};
1250
1251static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1252	.open =		snd_rme32_capture_spdif_open,
1253	.close =	snd_rme32_capture_close,
1254	.hw_params =	snd_rme32_capture_hw_params,
1255	.prepare =	snd_rme32_capture_prepare,
1256	.trigger =	snd_rme32_pcm_trigger,
1257	.pointer =	snd_rme32_capture_fd_pointer,
1258	.ack =		snd_rme32_capture_fd_ack,
1259};
1260
1261static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1262	.open =		snd_rme32_playback_adat_open,
1263	.close =	snd_rme32_playback_close,
1264	.hw_params =	snd_rme32_playback_hw_params,
1265	.prepare =	snd_rme32_playback_prepare,
1266	.trigger =	snd_rme32_pcm_trigger,
1267	.pointer =	snd_rme32_playback_fd_pointer,
1268	.ack =		snd_rme32_playback_fd_ack,
1269};
1270
1271static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1272	.open =		snd_rme32_capture_adat_open,
1273	.close =	snd_rme32_capture_close,
1274	.hw_params =	snd_rme32_capture_hw_params,
1275	.prepare =	snd_rme32_capture_prepare,
1276	.trigger =	snd_rme32_pcm_trigger,
1277	.pointer =	snd_rme32_capture_fd_pointer,
1278	.ack =		snd_rme32_capture_fd_ack,
1279};
1280
1281static void snd_rme32_free(void *private_data)
1282{
1283	struct rme32 *rme32 = (struct rme32 *) private_data;
1284
1285	if (rme32 == NULL) {
1286		return;
1287	}
1288	if (rme32->irq >= 0) {
1289		snd_rme32_pcm_stop(rme32, 0);
1290		free_irq(rme32->irq, (void *) rme32);
1291		rme32->irq = -1;
1292	}
1293	if (rme32->iobase) {
1294		iounmap(rme32->iobase);
1295		rme32->iobase = NULL;
1296	}
1297	if (rme32->port) {
1298		pci_release_regions(rme32->pci);
1299		rme32->port = 0;
1300	}
1301	pci_disable_device(rme32->pci);
1302}
1303
1304static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1305{
1306	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1307	rme32->spdif_pcm = NULL;
1308}
1309
1310static void
1311snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1312{
1313	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1314	rme32->adat_pcm = NULL;
1315}
1316
1317static int snd_rme32_create(struct rme32 *rme32)
1318{
1319	struct pci_dev *pci = rme32->pci;
1320	int err;
1321
1322	rme32->irq = -1;
1323	spin_lock_init(&rme32->lock);
1324
1325	err = pci_enable_device(pci);
1326	if (err < 0)
1327		return err;
1328
1329	err = pci_request_regions(pci, "RME32");
1330	if (err < 0)
1331		return err;
1332	rme32->port = pci_resource_start(rme32->pci, 0);
1333
1334	rme32->iobase = ioremap(rme32->port, RME32_IO_SIZE);
1335	if (!rme32->iobase) {
1336		dev_err(rme32->card->dev,
1337			"unable to remap memory region 0x%lx-0x%lx\n",
1338			   rme32->port, rme32->port + RME32_IO_SIZE - 1);
1339		return -ENOMEM;
1340	}
1341
1342	if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1343			KBUILD_MODNAME, rme32)) {
1344		dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
1345		return -EBUSY;
1346	}
1347	rme32->irq = pci->irq;
1348	rme32->card->sync_irq = rme32->irq;
1349
1350	/* read the card's revision number */
1351	pci_read_config_byte(pci, 8, &rme32->rev);
1352
1353	/* set up ALSA pcm device for S/PDIF */
1354	err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm);
1355	if (err < 0)
1356		return err;
1357	rme32->spdif_pcm->private_data = rme32;
1358	rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1359	strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1360	if (rme32->fullduplex_mode) {
1361		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1362				&snd_rme32_playback_spdif_fd_ops);
1363		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1364				&snd_rme32_capture_spdif_fd_ops);
1365		snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1366					       NULL, 0, RME32_MID_BUFFER_SIZE);
1367		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1368	} else {
1369		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1370				&snd_rme32_playback_spdif_ops);
1371		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1372				&snd_rme32_capture_spdif_ops);
1373		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1374	}
1375
1376	/* set up ALSA pcm device for ADAT */
1377	if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1378	    (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1379		/* ADAT is not available on DIGI32 and DIGI32 Pro */
1380		rme32->adat_pcm = NULL;
1381	}
1382	else {
1383		err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1384				  1, 1, &rme32->adat_pcm);
1385		if (err < 0)
1386			return err;
1387		rme32->adat_pcm->private_data = rme32;
1388		rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1389		strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1390		if (rme32->fullduplex_mode) {
1391			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 
1392					&snd_rme32_playback_adat_fd_ops);
1393			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 
1394					&snd_rme32_capture_adat_fd_ops);
1395			snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1396						       NULL,
1397						       0, RME32_MID_BUFFER_SIZE);
1398			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1399		} else {
1400			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 
1401					&snd_rme32_playback_adat_ops);
1402			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 
1403					&snd_rme32_capture_adat_ops);
1404			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1405		}
1406	}
1407
1408
1409	rme32->playback_periodsize = 0;
1410	rme32->capture_periodsize = 0;
1411
1412	/* make sure playback/capture is stopped, if by some reason active */
1413	snd_rme32_pcm_stop(rme32, 0);
1414
1415        /* reset DAC */
1416        snd_rme32_reset_dac(rme32);
1417
1418	/* reset buffer pointer */
1419	writel(0, rme32->iobase + RME32_IO_RESET_POS);
1420
1421	/* set default values in registers */
1422	rme32->wcreg = RME32_WCR_SEL |	 /* normal playback */
1423		RME32_WCR_INP_0 | /* input select */
1424		RME32_WCR_MUTE;	 /* muting on */
1425	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1426
1427
1428	/* init switch interface */
1429	err = snd_rme32_create_switches(rme32->card, rme32);
1430	if (err < 0)
1431		return err;
1432
1433	/* init proc interface */
1434	snd_rme32_proc_init(rme32);
1435
1436	rme32->capture_substream = NULL;
1437	rme32->playback_substream = NULL;
1438
1439	return 0;
1440}
1441
1442/*
1443 * proc interface
1444 */
1445
1446static void
1447snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1448{
1449	int n;
1450	struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1451
1452	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1453
1454	snd_iprintf(buffer, rme32->card->longname);
1455	snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1456
1457	snd_iprintf(buffer, "\nGeneral settings\n");
1458	if (rme32->fullduplex_mode)
1459		snd_iprintf(buffer, "  Full-duplex mode\n");
1460	else
1461		snd_iprintf(buffer, "  Half-duplex mode\n");
1462	if (RME32_PRO_WITH_8414(rme32)) {
1463		snd_iprintf(buffer, "  receiver: CS8414\n");
1464	} else {
1465		snd_iprintf(buffer, "  receiver: CS8412\n");
1466	}
1467	if (rme32->wcreg & RME32_WCR_MODE24) {
1468		snd_iprintf(buffer, "  format: 24 bit");
1469	} else {
1470		snd_iprintf(buffer, "  format: 16 bit");
1471	}
1472	if (rme32->wcreg & RME32_WCR_MONO) {
1473		snd_iprintf(buffer, ", Mono\n");
1474	} else {
1475		snd_iprintf(buffer, ", Stereo\n");
1476	}
1477
1478	snd_iprintf(buffer, "\nInput settings\n");
1479	switch (snd_rme32_getinputtype(rme32)) {
1480	case RME32_INPUT_OPTICAL:
1481		snd_iprintf(buffer, "  input: optical");
1482		break;
1483	case RME32_INPUT_COAXIAL:
1484		snd_iprintf(buffer, "  input: coaxial");
1485		break;
1486	case RME32_INPUT_INTERNAL:
1487		snd_iprintf(buffer, "  input: internal");
1488		break;
1489	case RME32_INPUT_XLR:
1490		snd_iprintf(buffer, "  input: XLR");
1491		break;
1492	}
1493	if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1494		snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1495	} else {
1496		if (n) {
1497			snd_iprintf(buffer, " (8 channels)\n");
1498		} else {
1499			snd_iprintf(buffer, " (2 channels)\n");
1500		}
1501		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1502			    snd_rme32_capture_getrate(rme32, &n));
1503	}
1504
1505	snd_iprintf(buffer, "\nOutput settings\n");
1506	if (rme32->wcreg & RME32_WCR_SEL) {
1507		snd_iprintf(buffer, "  output signal: normal playback");
1508	} else {
1509		snd_iprintf(buffer, "  output signal: same as input");
1510	}
1511	if (rme32->wcreg & RME32_WCR_MUTE) {
1512		snd_iprintf(buffer, " (muted)\n");
1513	} else {
1514		snd_iprintf(buffer, "\n");
1515	}
1516
1517	/* master output frequency */
1518	if (!
1519	    ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1520	     && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1521		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1522			    snd_rme32_playback_getrate(rme32));
1523	}
1524	if (rme32->rcreg & RME32_RCR_KMODE) {
1525		snd_iprintf(buffer, "  sample clock source: AutoSync\n");
1526	} else {
1527		snd_iprintf(buffer, "  sample clock source: Internal\n");
1528	}
1529	if (rme32->wcreg & RME32_WCR_PRO) {
1530		snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1531	} else {
1532		snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1533	}
1534	if (rme32->wcreg & RME32_WCR_EMP) {
1535		snd_iprintf(buffer, "  emphasis: on\n");
1536	} else {
1537		snd_iprintf(buffer, "  emphasis: off\n");
1538	}
1539}
1540
1541static void snd_rme32_proc_init(struct rme32 *rme32)
1542{
1543	snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
1544}
1545
1546/*
1547 * control interface
1548 */
1549
1550#define snd_rme32_info_loopback_control		snd_ctl_boolean_mono_info
1551
1552static int
1553snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1554			       struct snd_ctl_elem_value *ucontrol)
1555{
1556	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1557
1558	spin_lock_irq(&rme32->lock);
1559	ucontrol->value.integer.value[0] =
1560	    rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1561	spin_unlock_irq(&rme32->lock);
1562	return 0;
1563}
1564static int
1565snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1566			       struct snd_ctl_elem_value *ucontrol)
1567{
1568	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1569	unsigned int val;
1570	int change;
1571
1572	val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1573	spin_lock_irq(&rme32->lock);
1574	val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1575	change = val != rme32->wcreg;
1576	if (ucontrol->value.integer.value[0])
1577		val &= ~RME32_WCR_MUTE;
1578	else
1579		val |= RME32_WCR_MUTE;
1580	rme32->wcreg = val;
1581	writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1582	spin_unlock_irq(&rme32->lock);
1583	return change;
1584}
1585
1586static int
1587snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1588				 struct snd_ctl_elem_info *uinfo)
1589{
1590	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1591	static const char * const texts[4] = {
1592		"Optical", "Coaxial", "Internal", "XLR"
1593	};
1594	int num_items;
1595
1596	switch (rme32->pci->device) {
1597	case PCI_DEVICE_ID_RME_DIGI32:
1598	case PCI_DEVICE_ID_RME_DIGI32_8:
1599		num_items = 3;
1600		break;
1601	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1602		num_items = 4;
1603		break;
1604	default:
1605		snd_BUG();
1606		return -EINVAL;
1607	}
1608	return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1609}
1610static int
1611snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1612				struct snd_ctl_elem_value *ucontrol)
1613{
1614	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1615	unsigned int items = 3;
1616
1617	spin_lock_irq(&rme32->lock);
1618	ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1619
1620	switch (rme32->pci->device) {
1621	case PCI_DEVICE_ID_RME_DIGI32:
1622	case PCI_DEVICE_ID_RME_DIGI32_8:
1623		items = 3;
1624		break;
1625	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1626		items = 4;
1627		break;
1628	default:
1629		snd_BUG();
1630		break;
1631	}
1632	if (ucontrol->value.enumerated.item[0] >= items) {
1633		ucontrol->value.enumerated.item[0] = items - 1;
1634	}
1635
1636	spin_unlock_irq(&rme32->lock);
1637	return 0;
1638}
1639static int
1640snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1641				struct snd_ctl_elem_value *ucontrol)
1642{
1643	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1644	unsigned int val;
1645	int change, items = 3;
1646
1647	switch (rme32->pci->device) {
1648	case PCI_DEVICE_ID_RME_DIGI32:
1649	case PCI_DEVICE_ID_RME_DIGI32_8:
1650		items = 3;
1651		break;
1652	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1653		items = 4;
1654		break;
1655	default:
1656		snd_BUG();
1657		break;
1658	}
1659	val = ucontrol->value.enumerated.item[0] % items;
1660
1661	spin_lock_irq(&rme32->lock);
1662	change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1663	snd_rme32_setinputtype(rme32, val);
1664	spin_unlock_irq(&rme32->lock);
1665	return change;
1666}
1667
1668static int
1669snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1670				 struct snd_ctl_elem_info *uinfo)
1671{
1672	static const char * const texts[4] = { "AutoSync",
1673				  "Internal 32.0kHz", 
1674				  "Internal 44.1kHz", 
1675				  "Internal 48.0kHz" };
1676
1677	return snd_ctl_enum_info(uinfo, 1, 4, texts);
1678}
1679static int
1680snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1681				struct snd_ctl_elem_value *ucontrol)
1682{
1683	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1684
1685	spin_lock_irq(&rme32->lock);
1686	ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1687	spin_unlock_irq(&rme32->lock);
1688	return 0;
1689}
1690static int
1691snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1692				struct snd_ctl_elem_value *ucontrol)
1693{
1694	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1695	unsigned int val;
1696	int change;
1697
1698	val = ucontrol->value.enumerated.item[0] % 3;
1699	spin_lock_irq(&rme32->lock);
1700	change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1701	snd_rme32_setclockmode(rme32, val);
1702	spin_unlock_irq(&rme32->lock);
1703	return change;
1704}
1705
1706static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1707{
1708	u32 val = 0;
1709	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1710	if (val & RME32_WCR_PRO)
1711		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1712	else
1713		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1714	return val;
1715}
1716
1717static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1718{
1719	aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1720	if (val & RME32_WCR_PRO)
1721		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1722	else
1723		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1724}
1725
1726static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1727					struct snd_ctl_elem_info *uinfo)
1728{
1729	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1730	uinfo->count = 1;
1731	return 0;
1732}
1733
1734static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1735				       struct snd_ctl_elem_value *ucontrol)
1736{
1737	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1738
1739	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1740				 rme32->wcreg_spdif);
1741	return 0;
1742}
1743
1744static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1745				       struct snd_ctl_elem_value *ucontrol)
1746{
1747	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1748	int change;
1749	u32 val;
1750
1751	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1752	spin_lock_irq(&rme32->lock);
1753	change = val != rme32->wcreg_spdif;
1754	rme32->wcreg_spdif = val;
1755	spin_unlock_irq(&rme32->lock);
1756	return change;
1757}
1758
1759static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1760					       struct snd_ctl_elem_info *uinfo)
1761{
1762	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1763	uinfo->count = 1;
1764	return 0;
1765}
1766
1767static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1768					      struct snd_ctl_elem_value *
1769					      ucontrol)
1770{
1771	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1772
1773	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1774				 rme32->wcreg_spdif_stream);
1775	return 0;
1776}
1777
1778static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1779					      struct snd_ctl_elem_value *
1780					      ucontrol)
1781{
1782	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1783	int change;
1784	u32 val;
1785
1786	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1787	spin_lock_irq(&rme32->lock);
1788	change = val != rme32->wcreg_spdif_stream;
1789	rme32->wcreg_spdif_stream = val;
1790	rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1791	rme32->wcreg |= val;
1792	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1793	spin_unlock_irq(&rme32->lock);
1794	return change;
1795}
1796
1797static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1798					     struct snd_ctl_elem_info *uinfo)
1799{
1800	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1801	uinfo->count = 1;
1802	return 0;
1803}
1804
1805static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1806					    struct snd_ctl_elem_value *
1807					    ucontrol)
1808{
1809	ucontrol->value.iec958.status[0] = kcontrol->private_value;
1810	return 0;
1811}
1812
1813static const struct snd_kcontrol_new snd_rme32_controls[] = {
1814	{
1815		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1816		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1817		.info =	snd_rme32_control_spdif_info,
1818		.get =	snd_rme32_control_spdif_get,
1819		.put =	snd_rme32_control_spdif_put
1820	},
1821	{
1822		.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1823		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1824		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1825		.info =	snd_rme32_control_spdif_stream_info,
1826		.get =	snd_rme32_control_spdif_stream_get,
1827		.put =	snd_rme32_control_spdif_stream_put
1828	},
1829	{
1830		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1831		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1832		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1833		.info =	snd_rme32_control_spdif_mask_info,
1834		.get =	snd_rme32_control_spdif_mask_get,
1835		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1836	},
1837	{
1838		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1839		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1840		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1841		.info =	snd_rme32_control_spdif_mask_info,
1842		.get =	snd_rme32_control_spdif_mask_get,
1843		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1844	},
1845	{
1846		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1847		.name =	"Input Connector",
1848		.info =	snd_rme32_info_inputtype_control,
1849		.get =	snd_rme32_get_inputtype_control,
1850		.put =	snd_rme32_put_inputtype_control
1851	},
1852	{
1853		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1854		.name =	"Loopback Input",
1855		.info =	snd_rme32_info_loopback_control,
1856		.get =	snd_rme32_get_loopback_control,
1857		.put =	snd_rme32_put_loopback_control
1858	},
1859	{
1860		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1861		.name =	"Sample Clock Source",
1862		.info =	snd_rme32_info_clockmode_control,
1863		.get =	snd_rme32_get_clockmode_control,
1864		.put =	snd_rme32_put_clockmode_control
1865	}
1866};
1867
1868static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1869{
1870	int idx, err;
1871	struct snd_kcontrol *kctl;
1872
1873	for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1874		kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32);
1875		err = snd_ctl_add(card, kctl);
1876		if (err < 0)
1877			return err;
1878		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
1879			rme32->spdif_ctl = kctl;
1880	}
1881
1882	return 0;
1883}
1884
1885/*
1886 * Card initialisation
1887 */
1888
1889static void snd_rme32_card_free(struct snd_card *card)
1890{
1891	snd_rme32_free(card->private_data);
1892}
1893
1894static int
1895snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1896{
1897	static int dev;
1898	struct rme32 *rme32;
1899	struct snd_card *card;
1900	int err;
1901
1902	if (dev >= SNDRV_CARDS) {
1903		return -ENODEV;
1904	}
1905	if (!enable[dev]) {
1906		dev++;
1907		return -ENOENT;
1908	}
1909
1910	err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1911			   sizeof(struct rme32), &card);
1912	if (err < 0)
1913		return err;
1914	card->private_free = snd_rme32_card_free;
1915	rme32 = (struct rme32 *) card->private_data;
1916	rme32->card = card;
1917	rme32->pci = pci;
1918        if (fullduplex[dev])
1919		rme32->fullduplex_mode = 1;
1920	err = snd_rme32_create(rme32);
1921	if (err < 0) {
1922		snd_card_free(card);
1923		return err;
1924	}
1925
1926	strcpy(card->driver, "Digi32");
1927	switch (rme32->pci->device) {
1928	case PCI_DEVICE_ID_RME_DIGI32:
1929		strcpy(card->shortname, "RME Digi32");
1930		break;
1931	case PCI_DEVICE_ID_RME_DIGI32_8:
1932		strcpy(card->shortname, "RME Digi32/8");
1933		break;
1934	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1935		strcpy(card->shortname, "RME Digi32 PRO");
1936		break;
1937	}
1938	sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1939		card->shortname, rme32->rev, rme32->port, rme32->irq);
1940
1941	err = snd_card_register(card);
1942	if (err < 0) {
1943		snd_card_free(card);
1944		return err;
1945	}
1946	pci_set_drvdata(pci, card);
1947	dev++;
1948	return 0;
1949}
1950
1951static void snd_rme32_remove(struct pci_dev *pci)
 
1952{
1953	snd_card_free(pci_get_drvdata(pci));
1954}
1955
1956static struct pci_driver rme32_driver = {
1957	.name =		KBUILD_MODNAME,
1958	.id_table =	snd_rme32_ids,
1959	.probe =	snd_rme32_probe,
1960	.remove =	snd_rme32_remove,
1961};
1962
1963module_pci_driver(rme32_driver);