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1/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
28#include <uapi/drm/i915_drm.h>
29
30#include "intel_step.h"
31
32#include "display/intel_display.h"
33
34#include "gt/intel_engine_types.h"
35#include "gt/intel_context_types.h"
36#include "gt/intel_sseu.h"
37
38struct drm_printer;
39struct drm_i915_private;
40
41/* Keep in gen based order, and chronological order within a gen */
42enum intel_platform {
43 INTEL_PLATFORM_UNINITIALIZED = 0,
44 /* gen2 */
45 INTEL_I830,
46 INTEL_I845G,
47 INTEL_I85X,
48 INTEL_I865G,
49 /* gen3 */
50 INTEL_I915G,
51 INTEL_I915GM,
52 INTEL_I945G,
53 INTEL_I945GM,
54 INTEL_G33,
55 INTEL_PINEVIEW,
56 /* gen4 */
57 INTEL_I965G,
58 INTEL_I965GM,
59 INTEL_G45,
60 INTEL_GM45,
61 /* gen5 */
62 INTEL_IRONLAKE,
63 /* gen6 */
64 INTEL_SANDYBRIDGE,
65 /* gen7 */
66 INTEL_IVYBRIDGE,
67 INTEL_VALLEYVIEW,
68 INTEL_HASWELL,
69 /* gen8 */
70 INTEL_BROADWELL,
71 INTEL_CHERRYVIEW,
72 /* gen9 */
73 INTEL_SKYLAKE,
74 INTEL_BROXTON,
75 INTEL_KABYLAKE,
76 INTEL_GEMINILAKE,
77 INTEL_COFFEELAKE,
78 INTEL_COMETLAKE,
79 /* gen10 */
80 INTEL_CANNONLAKE,
81 /* gen11 */
82 INTEL_ICELAKE,
83 INTEL_ELKHARTLAKE,
84 INTEL_JASPERLAKE,
85 /* gen12 */
86 INTEL_TIGERLAKE,
87 INTEL_ROCKETLAKE,
88 INTEL_DG1,
89 INTEL_ALDERLAKE_S,
90 INTEL_ALDERLAKE_P,
91 INTEL_MAX_PLATFORMS
92};
93
94/*
95 * Subplatform bits share the same namespace per parent platform. In other words
96 * it is fine for the same bit to be used on multiple parent platforms.
97 */
98
99#define INTEL_SUBPLATFORM_BITS (2)
100#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
101
102/* HSW/BDW/SKL/KBL/CFL */
103#define INTEL_SUBPLATFORM_ULT (0)
104#define INTEL_SUBPLATFORM_ULX (1)
105
106/* CNL/ICL */
107#define INTEL_SUBPLATFORM_PORTF (0)
108
109enum intel_ppgtt_type {
110 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
111 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
112 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
113};
114
115#define DEV_INFO_FOR_EACH_FLAG(func) \
116 func(is_mobile); \
117 func(is_lp); \
118 func(require_force_probe); \
119 func(is_dgfx); \
120 /* Keep has_* in alphabetical order */ \
121 func(has_64bit_reloc); \
122 func(gpu_reset_clobbers_display); \
123 func(has_reset_engine); \
124 func(has_global_mocs); \
125 func(has_gt_uc); \
126 func(has_l3_dpf); \
127 func(has_llc); \
128 func(has_logical_ring_contexts); \
129 func(has_logical_ring_elsq); \
130 func(has_master_unit_irq); \
131 func(has_pooled_eu); \
132 func(has_rc6); \
133 func(has_rc6p); \
134 func(has_rps); \
135 func(has_runtime_pm); \
136 func(has_snoop); \
137 func(has_coherent_ggtt); \
138 func(unfenced_needs_alignment); \
139 func(hws_needs_physical);
140
141#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
142 /* Keep in alphabetical order */ \
143 func(cursor_needs_physical); \
144 func(has_dmc); \
145 func(has_ddi); \
146 func(has_dp_mst); \
147 func(has_dsb); \
148 func(has_dsc); \
149 func(has_fbc); \
150 func(has_fpga_dbg); \
151 func(has_gmch); \
152 func(has_hdcp); \
153 func(has_hotplug); \
154 func(has_hti); \
155 func(has_ipc); \
156 func(has_modular_fia); \
157 func(has_overlay); \
158 func(has_psr); \
159 func(has_psr_hw_tracking); \
160 func(overlay_needs_physical); \
161 func(supports_tv);
162
163struct intel_device_info {
164 u8 graphics_ver;
165 u8 media_ver;
166
167 u8 gt; /* GT number, 0 if undefined */
168 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
169
170 enum intel_platform platform;
171
172 unsigned int dma_mask_size; /* available DMA address bits */
173
174 enum intel_ppgtt_type ppgtt_type;
175 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
176
177 unsigned int page_sizes; /* page sizes supported by the HW */
178
179 u32 memory_regions; /* regions supported by the HW */
180
181 u32 display_mmio_offset;
182
183 u8 pipe_mask;
184 u8 cpu_transcoder_mask;
185
186 u8 abox_mask;
187
188 u8 has_cdclk_crawl; /* does support CDCLK crawling */
189
190#define DEFINE_FLAG(name) u8 name:1
191 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
192#undef DEFINE_FLAG
193
194 struct {
195 u8 ver;
196
197#define DEFINE_FLAG(name) u8 name:1
198 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
199#undef DEFINE_FLAG
200 } display;
201
202 struct {
203 u16 size; /* in blocks */
204 u8 slice_mask;
205 } dbuf;
206
207 /* Register offsets for the various display pipes and transcoders */
208 int pipe_offsets[I915_MAX_TRANSCODERS];
209 int trans_offsets[I915_MAX_TRANSCODERS];
210 int cursor_offsets[I915_MAX_PIPES];
211
212 struct color_luts {
213 u32 degamma_lut_size;
214 u32 gamma_lut_size;
215 u32 degamma_lut_tests;
216 u32 gamma_lut_tests;
217 } color;
218};
219
220struct intel_runtime_info {
221 /*
222 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
223 * into single runtime conditionals, and also to provide groundwork
224 * for future per platform, or per SKU build optimizations.
225 *
226 * Array can be extended when necessary if the corresponding
227 * BUILD_BUG_ON is hit.
228 */
229 u32 platform_mask[2];
230
231 u16 device_id;
232
233 u8 num_sprites[I915_MAX_PIPES];
234 u8 num_scalers[I915_MAX_PIPES];
235
236 u32 rawclk_freq;
237
238 struct intel_step_info step;
239};
240
241struct intel_driver_caps {
242 unsigned int scheduler;
243 bool has_logical_contexts:1;
244};
245
246const char *intel_platform_name(enum intel_platform platform);
247
248void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
249void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
250
251void intel_device_info_print_static(const struct intel_device_info *info,
252 struct drm_printer *p);
253void intel_device_info_print_runtime(const struct intel_runtime_info *info,
254 struct drm_printer *p);
255
256void intel_driver_caps_print(const struct intel_driver_caps *caps,
257 struct drm_printer *p);
258
259#endif
1/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
28#include <uapi/drm/i915_drm.h>
29
30#include "intel_step.h"
31
32#include "gt/intel_engine_types.h"
33#include "gt/intel_context_types.h"
34#include "gt/intel_sseu.h"
35
36#include "gem/i915_gem_object_types.h"
37
38struct drm_printer;
39struct drm_i915_private;
40struct intel_gt_definition;
41
42/* Keep in gen based order, and chronological order within a gen */
43enum intel_platform {
44 INTEL_PLATFORM_UNINITIALIZED = 0,
45 /* gen2 */
46 INTEL_I830,
47 INTEL_I845G,
48 INTEL_I85X,
49 INTEL_I865G,
50 /* gen3 */
51 INTEL_I915G,
52 INTEL_I915GM,
53 INTEL_I945G,
54 INTEL_I945GM,
55 INTEL_G33,
56 INTEL_PINEVIEW,
57 /* gen4 */
58 INTEL_I965G,
59 INTEL_I965GM,
60 INTEL_G45,
61 INTEL_GM45,
62 /* gen5 */
63 INTEL_IRONLAKE,
64 /* gen6 */
65 INTEL_SANDYBRIDGE,
66 /* gen7 */
67 INTEL_IVYBRIDGE,
68 INTEL_VALLEYVIEW,
69 INTEL_HASWELL,
70 /* gen8 */
71 INTEL_BROADWELL,
72 INTEL_CHERRYVIEW,
73 /* gen9 */
74 INTEL_SKYLAKE,
75 INTEL_BROXTON,
76 INTEL_KABYLAKE,
77 INTEL_GEMINILAKE,
78 INTEL_COFFEELAKE,
79 INTEL_COMETLAKE,
80 /* gen11 */
81 INTEL_ICELAKE,
82 INTEL_ELKHARTLAKE,
83 INTEL_JASPERLAKE,
84 /* gen12 */
85 INTEL_TIGERLAKE,
86 INTEL_ROCKETLAKE,
87 INTEL_DG1,
88 INTEL_ALDERLAKE_S,
89 INTEL_ALDERLAKE_P,
90 INTEL_XEHPSDV,
91 INTEL_DG2,
92 INTEL_PONTEVECCHIO,
93 INTEL_METEORLAKE,
94 INTEL_MAX_PLATFORMS
95};
96
97/*
98 * Subplatform bits share the same namespace per parent platform. In other words
99 * it is fine for the same bit to be used on multiple parent platforms.
100 */
101
102#define INTEL_SUBPLATFORM_BITS (3)
103#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
104
105/* HSW/BDW/SKL/KBL/CFL */
106#define INTEL_SUBPLATFORM_ULT (0)
107#define INTEL_SUBPLATFORM_ULX (1)
108
109/* ICL */
110#define INTEL_SUBPLATFORM_PORTF (0)
111
112/* TGL */
113#define INTEL_SUBPLATFORM_UY (0)
114
115/* DG2 */
116#define INTEL_SUBPLATFORM_G10 0
117#define INTEL_SUBPLATFORM_G11 1
118#define INTEL_SUBPLATFORM_G12 2
119
120/* ADL */
121#define INTEL_SUBPLATFORM_RPL 0
122
123/* ADL-P */
124/*
125 * As #define INTEL_SUBPLATFORM_RPL 0 will apply
126 * here too, SUBPLATFORM_N will have different
127 * bit set
128 */
129#define INTEL_SUBPLATFORM_N 1
130#define INTEL_SUBPLATFORM_RPLU 2
131
132enum intel_ppgtt_type {
133 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
134 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
135 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
136};
137
138#define DEV_INFO_FOR_EACH_FLAG(func) \
139 func(is_mobile); \
140 func(is_lp); \
141 func(require_force_probe); \
142 func(is_dgfx); \
143 /* Keep has_* in alphabetical order */ \
144 func(has_64bit_reloc); \
145 func(has_64k_pages); \
146 func(gpu_reset_clobbers_display); \
147 func(has_reset_engine); \
148 func(has_3d_pipeline); \
149 func(has_flat_ccs); \
150 func(has_global_mocs); \
151 func(has_gmd_id); \
152 func(has_gt_uc); \
153 func(has_heci_pxp); \
154 func(has_heci_gscfi); \
155 func(has_guc_deprivilege); \
156 func(has_guc_tlb_invalidation); \
157 func(has_l3_ccs_read); \
158 func(has_l3_dpf); \
159 func(has_llc); \
160 func(has_logical_ring_contexts); \
161 func(has_logical_ring_elsq); \
162 func(has_media_ratio_mode); \
163 func(has_mslice_steering); \
164 func(has_oa_bpc_reporting); \
165 func(has_oa_slice_contrib_limits); \
166 func(has_oam); \
167 func(has_one_eu_per_fuse_bit); \
168 func(has_pxp); \
169 func(has_rc6); \
170 func(has_rc6p); \
171 func(has_rps); \
172 func(has_runtime_pm); \
173 func(has_snoop); \
174 func(has_coherent_ggtt); \
175 func(tuning_thread_rr_after_dep); \
176 func(unfenced_needs_alignment); \
177 func(hws_needs_physical);
178
179struct intel_ip_version {
180 u8 ver;
181 u8 rel;
182 u8 step;
183};
184
185struct intel_runtime_info {
186 /*
187 * Single "graphics" IP version that represents
188 * render, compute and copy behavior.
189 */
190 struct {
191 struct intel_ip_version ip;
192 } graphics;
193 struct {
194 struct intel_ip_version ip;
195 } media;
196
197 /*
198 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
199 * single runtime conditionals, and also to provide groundwork for
200 * future per platform, or per SKU build optimizations.
201 *
202 * Array can be extended when necessary if the corresponding
203 * BUILD_BUG_ON is hit.
204 */
205 u32 platform_mask[2];
206
207 u16 device_id;
208
209 u32 rawclk_freq;
210
211 struct intel_step_info step;
212
213 unsigned int page_sizes; /* page sizes supported by the HW */
214
215 enum intel_ppgtt_type ppgtt_type;
216 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
217
218 bool has_pooled_eu;
219};
220
221struct intel_device_info {
222 enum intel_platform platform;
223
224 unsigned int dma_mask_size; /* available DMA address bits */
225
226 const struct intel_gt_definition *extra_gt_list;
227
228 u8 gt; /* GT number, 0 if undefined */
229
230 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
231 u32 memory_regions; /* regions supported by the HW */
232
233#define DEFINE_FLAG(name) u8 name:1
234 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
235#undef DEFINE_FLAG
236
237 /*
238 * Initial runtime info. Do not access outside of i915_driver_create().
239 */
240 const struct intel_runtime_info __runtime;
241
242 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
243 u32 max_pat_index;
244};
245
246struct intel_driver_caps {
247 unsigned int scheduler;
248 bool has_logical_contexts:1;
249};
250
251const char *intel_platform_name(enum intel_platform platform);
252
253void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id,
254 const struct intel_device_info *match_info);
255void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
256void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
257
258void intel_device_info_print(const struct intel_device_info *info,
259 const struct intel_runtime_info *runtime,
260 struct drm_printer *p);
261
262void intel_driver_caps_print(const struct intel_driver_caps *caps,
263 struct drm_printer *p);
264
265#endif