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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30#include <linux/export.h>
31#include <linux/i2c-algo-bit.h>
32#include <linux/i2c.h>
33
34#include <drm/drm_hdcp.h>
35
36#include "i915_drv.h"
37#include "intel_de.h"
38#include "intel_display_types.h"
39#include "intel_gmbus.h"
40
41struct gmbus_pin {
42 const char *name;
43 enum i915_gpio gpio;
44};
45
46/* Map gmbus pin pairs to names and registers. */
47static const struct gmbus_pin gmbus_pins[] = {
48 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
50 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
51 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
52 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
53 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
54};
55
56static const struct gmbus_pin gmbus_pins_bdw[] = {
57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
58 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
59 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
60 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
61};
62
63static const struct gmbus_pin gmbus_pins_skl[] = {
64 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
65 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
66 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
67};
68
69static const struct gmbus_pin gmbus_pins_bxt[] = {
70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
73};
74
75static const struct gmbus_pin gmbus_pins_cnp[] = {
76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
80};
81
82static const struct gmbus_pin gmbus_pins_icp[] = {
83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
85 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
86 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
87 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
88 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
89 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
90 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
91 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
92};
93
94static const struct gmbus_pin gmbus_pins_dg1[] = {
95 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
96 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
97 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
98 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
99};
100
101/* pin is expected to be valid */
102static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
103 unsigned int pin)
104{
105 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
106 return &gmbus_pins_dg1[pin];
107 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
108 return &gmbus_pins_icp[pin];
109 else if (HAS_PCH_CNP(dev_priv))
110 return &gmbus_pins_cnp[pin];
111 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
112 return &gmbus_pins_bxt[pin];
113 else if (DISPLAY_VER(dev_priv) == 9)
114 return &gmbus_pins_skl[pin];
115 else if (IS_BROADWELL(dev_priv))
116 return &gmbus_pins_bdw[pin];
117 else
118 return &gmbus_pins[pin];
119}
120
121bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
122 unsigned int pin)
123{
124 unsigned int size;
125
126 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
127 size = ARRAY_SIZE(gmbus_pins_dg1);
128 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
129 size = ARRAY_SIZE(gmbus_pins_icp);
130 else if (HAS_PCH_CNP(dev_priv))
131 size = ARRAY_SIZE(gmbus_pins_cnp);
132 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
133 size = ARRAY_SIZE(gmbus_pins_bxt);
134 else if (DISPLAY_VER(dev_priv) == 9)
135 size = ARRAY_SIZE(gmbus_pins_skl);
136 else if (IS_BROADWELL(dev_priv))
137 size = ARRAY_SIZE(gmbus_pins_bdw);
138 else
139 size = ARRAY_SIZE(gmbus_pins);
140
141 return pin < size && get_gmbus_pin(dev_priv, pin)->name;
142}
143
144/* Intel GPIO access functions */
145
146#define I2C_RISEFALL_TIME 10
147
148static inline struct intel_gmbus *
149to_intel_gmbus(struct i2c_adapter *i2c)
150{
151 return container_of(i2c, struct intel_gmbus, adapter);
152}
153
154void
155intel_gmbus_reset(struct drm_i915_private *dev_priv)
156{
157 intel_de_write(dev_priv, GMBUS0, 0);
158 intel_de_write(dev_priv, GMBUS4, 0);
159}
160
161static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
162 bool enable)
163{
164 u32 val;
165
166 /* When using bit bashing for I2C, this bit needs to be set to 1 */
167 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
168 if (!enable)
169 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
170 else
171 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
172 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
173}
174
175static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
176 bool enable)
177{
178 u32 val;
179
180 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
181 if (!enable)
182 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
183 else
184 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
185 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
186}
187
188static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
189 bool enable)
190{
191 u32 val;
192
193 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
194 if (!enable)
195 val |= BXT_GMBUS_GATING_DIS;
196 else
197 val &= ~BXT_GMBUS_GATING_DIS;
198 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
199}
200
201static u32 get_reserved(struct intel_gmbus *bus)
202{
203 struct drm_i915_private *i915 = bus->dev_priv;
204 struct intel_uncore *uncore = &i915->uncore;
205 u32 reserved = 0;
206
207 /* On most chips, these bits must be preserved in software. */
208 if (!IS_I830(i915) && !IS_I845G(i915))
209 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
210 (GPIO_DATA_PULLUP_DISABLE |
211 GPIO_CLOCK_PULLUP_DISABLE);
212
213 return reserved;
214}
215
216static int get_clock(void *data)
217{
218 struct intel_gmbus *bus = data;
219 struct intel_uncore *uncore = &bus->dev_priv->uncore;
220 u32 reserved = get_reserved(bus);
221
222 intel_uncore_write_notrace(uncore,
223 bus->gpio_reg,
224 reserved | GPIO_CLOCK_DIR_MASK);
225 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
226
227 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
228 GPIO_CLOCK_VAL_IN) != 0;
229}
230
231static int get_data(void *data)
232{
233 struct intel_gmbus *bus = data;
234 struct intel_uncore *uncore = &bus->dev_priv->uncore;
235 u32 reserved = get_reserved(bus);
236
237 intel_uncore_write_notrace(uncore,
238 bus->gpio_reg,
239 reserved | GPIO_DATA_DIR_MASK);
240 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
241
242 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
243 GPIO_DATA_VAL_IN) != 0;
244}
245
246static void set_clock(void *data, int state_high)
247{
248 struct intel_gmbus *bus = data;
249 struct intel_uncore *uncore = &bus->dev_priv->uncore;
250 u32 reserved = get_reserved(bus);
251 u32 clock_bits;
252
253 if (state_high)
254 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
255 else
256 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
257 GPIO_CLOCK_VAL_MASK;
258
259 intel_uncore_write_notrace(uncore,
260 bus->gpio_reg,
261 reserved | clock_bits);
262 intel_uncore_posting_read(uncore, bus->gpio_reg);
263}
264
265static void set_data(void *data, int state_high)
266{
267 struct intel_gmbus *bus = data;
268 struct intel_uncore *uncore = &bus->dev_priv->uncore;
269 u32 reserved = get_reserved(bus);
270 u32 data_bits;
271
272 if (state_high)
273 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
274 else
275 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
276 GPIO_DATA_VAL_MASK;
277
278 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
279 intel_uncore_posting_read(uncore, bus->gpio_reg);
280}
281
282static int
283intel_gpio_pre_xfer(struct i2c_adapter *adapter)
284{
285 struct intel_gmbus *bus = container_of(adapter,
286 struct intel_gmbus,
287 adapter);
288 struct drm_i915_private *dev_priv = bus->dev_priv;
289
290 intel_gmbus_reset(dev_priv);
291
292 if (IS_PINEVIEW(dev_priv))
293 pnv_gmbus_clock_gating(dev_priv, false);
294
295 set_data(bus, 1);
296 set_clock(bus, 1);
297 udelay(I2C_RISEFALL_TIME);
298 return 0;
299}
300
301static void
302intel_gpio_post_xfer(struct i2c_adapter *adapter)
303{
304 struct intel_gmbus *bus = container_of(adapter,
305 struct intel_gmbus,
306 adapter);
307 struct drm_i915_private *dev_priv = bus->dev_priv;
308
309 set_data(bus, 1);
310 set_clock(bus, 1);
311
312 if (IS_PINEVIEW(dev_priv))
313 pnv_gmbus_clock_gating(dev_priv, true);
314}
315
316static void
317intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
318{
319 struct drm_i915_private *dev_priv = bus->dev_priv;
320 struct i2c_algo_bit_data *algo;
321
322 algo = &bus->bit_algo;
323
324 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
325 bus->adapter.algo_data = algo;
326 algo->setsda = set_data;
327 algo->setscl = set_clock;
328 algo->getsda = get_data;
329 algo->getscl = get_clock;
330 algo->pre_xfer = intel_gpio_pre_xfer;
331 algo->post_xfer = intel_gpio_post_xfer;
332 algo->udelay = I2C_RISEFALL_TIME;
333 algo->timeout = usecs_to_jiffies(2200);
334 algo->data = bus;
335}
336
337static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
338{
339 DEFINE_WAIT(wait);
340 u32 gmbus2;
341 int ret;
342
343 /* Important: The hw handles only the first bit, so set only one! Since
344 * we also need to check for NAKs besides the hw ready/idle signal, we
345 * need to wake up periodically and check that ourselves.
346 */
347 if (!HAS_GMBUS_IRQ(dev_priv))
348 irq_en = 0;
349
350 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
351 intel_de_write_fw(dev_priv, GMBUS4, irq_en);
352
353 status |= GMBUS_SATOER;
354 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
355 2);
356 if (ret)
357 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
358 50);
359
360 intel_de_write_fw(dev_priv, GMBUS4, 0);
361 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
362
363 if (gmbus2 & GMBUS_SATOER)
364 return -ENXIO;
365
366 return ret;
367}
368
369static int
370gmbus_wait_idle(struct drm_i915_private *dev_priv)
371{
372 DEFINE_WAIT(wait);
373 u32 irq_enable;
374 int ret;
375
376 /* Important: The hw handles only the first bit, so set only one! */
377 irq_enable = 0;
378 if (HAS_GMBUS_IRQ(dev_priv))
379 irq_enable = GMBUS_IDLE_EN;
380
381 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
382 intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
383
384 ret = intel_wait_for_register_fw(&dev_priv->uncore,
385 GMBUS2, GMBUS_ACTIVE, 0,
386 10);
387
388 intel_de_write_fw(dev_priv, GMBUS4, 0);
389 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
390
391 return ret;
392}
393
394static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
395{
396 return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
397 GMBUS_BYTE_COUNT_MAX;
398}
399
400static int
401gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
402 unsigned short addr, u8 *buf, unsigned int len,
403 u32 gmbus0_reg, u32 gmbus1_index)
404{
405 unsigned int size = len;
406 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
407 bool extra_byte_added = false;
408
409 if (burst_read) {
410 /*
411 * As per HW Spec, for 512Bytes need to read extra Byte and
412 * Ignore the extra byte read.
413 */
414 if (len == 512) {
415 extra_byte_added = true;
416 len++;
417 }
418 size = len % 256 + 256;
419 intel_de_write_fw(dev_priv, GMBUS0,
420 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
421 }
422
423 intel_de_write_fw(dev_priv, GMBUS1,
424 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
425 while (len) {
426 int ret;
427 u32 val, loop = 0;
428
429 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
430 if (ret)
431 return ret;
432
433 val = intel_de_read_fw(dev_priv, GMBUS3);
434 do {
435 if (extra_byte_added && len == 1)
436 break;
437
438 *buf++ = val & 0xff;
439 val >>= 8;
440 } while (--len && ++loop < 4);
441
442 if (burst_read && len == size - 4)
443 /* Reset the override bit */
444 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
445 }
446
447 return 0;
448}
449
450/*
451 * HW spec says that 512Bytes in Burst read need special treatment.
452 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
453 * an I2C slave, which supports such a lengthy burst read too for experiments.
454 *
455 * So until things get clarified on HW support, to avoid the burst read length
456 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
457 */
458#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
459
460static int
461gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
462 u32 gmbus0_reg, u32 gmbus1_index)
463{
464 u8 *buf = msg->buf;
465 unsigned int rx_size = msg->len;
466 unsigned int len;
467 int ret;
468
469 do {
470 if (HAS_GMBUS_BURST_READ(dev_priv))
471 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
472 else
473 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
474
475 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
476 gmbus0_reg, gmbus1_index);
477 if (ret)
478 return ret;
479
480 rx_size -= len;
481 buf += len;
482 } while (rx_size != 0);
483
484 return 0;
485}
486
487static int
488gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
489 unsigned short addr, u8 *buf, unsigned int len,
490 u32 gmbus1_index)
491{
492 unsigned int chunk_size = len;
493 u32 val, loop;
494
495 val = loop = 0;
496 while (len && loop < 4) {
497 val |= *buf++ << (8 * loop++);
498 len -= 1;
499 }
500
501 intel_de_write_fw(dev_priv, GMBUS3, val);
502 intel_de_write_fw(dev_priv, GMBUS1,
503 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
504 while (len) {
505 int ret;
506
507 val = loop = 0;
508 do {
509 val |= *buf++ << (8 * loop);
510 } while (--len && ++loop < 4);
511
512 intel_de_write_fw(dev_priv, GMBUS3, val);
513
514 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
515 if (ret)
516 return ret;
517 }
518
519 return 0;
520}
521
522static int
523gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
524 u32 gmbus1_index)
525{
526 u8 *buf = msg->buf;
527 unsigned int tx_size = msg->len;
528 unsigned int len;
529 int ret;
530
531 do {
532 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
533
534 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
535 gmbus1_index);
536 if (ret)
537 return ret;
538
539 buf += len;
540 tx_size -= len;
541 } while (tx_size != 0);
542
543 return 0;
544}
545
546/*
547 * The gmbus controller can combine a 1 or 2 byte write with another read/write
548 * that immediately follows it by using an "INDEX" cycle.
549 */
550static bool
551gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
552{
553 return (i + 1 < num &&
554 msgs[i].addr == msgs[i + 1].addr &&
555 !(msgs[i].flags & I2C_M_RD) &&
556 (msgs[i].len == 1 || msgs[i].len == 2) &&
557 msgs[i + 1].len > 0);
558}
559
560static int
561gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
562 u32 gmbus0_reg)
563{
564 u32 gmbus1_index = 0;
565 u32 gmbus5 = 0;
566 int ret;
567
568 if (msgs[0].len == 2)
569 gmbus5 = GMBUS_2BYTE_INDEX_EN |
570 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
571 if (msgs[0].len == 1)
572 gmbus1_index = GMBUS_CYCLE_INDEX |
573 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
574
575 /* GMBUS5 holds 16-bit index */
576 if (gmbus5)
577 intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
578
579 if (msgs[1].flags & I2C_M_RD)
580 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
581 gmbus1_index);
582 else
583 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
584
585 /* Clear GMBUS5 after each index transfer */
586 if (gmbus5)
587 intel_de_write_fw(dev_priv, GMBUS5, 0);
588
589 return ret;
590}
591
592static int
593do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
594 u32 gmbus0_source)
595{
596 struct intel_gmbus *bus = container_of(adapter,
597 struct intel_gmbus,
598 adapter);
599 struct drm_i915_private *dev_priv = bus->dev_priv;
600 int i = 0, inc, try = 0;
601 int ret = 0;
602
603 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
604 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
605 bxt_gmbus_clock_gating(dev_priv, false);
606 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
607 pch_gmbus_clock_gating(dev_priv, false);
608
609retry:
610 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
611
612 for (; i < num; i += inc) {
613 inc = 1;
614 if (gmbus_is_index_xfer(msgs, i, num)) {
615 ret = gmbus_index_xfer(dev_priv, &msgs[i],
616 gmbus0_source | bus->reg0);
617 inc = 2; /* an index transmission is two msgs */
618 } else if (msgs[i].flags & I2C_M_RD) {
619 ret = gmbus_xfer_read(dev_priv, &msgs[i],
620 gmbus0_source | bus->reg0, 0);
621 } else {
622 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
623 }
624
625 if (!ret)
626 ret = gmbus_wait(dev_priv,
627 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
628 if (ret == -ETIMEDOUT)
629 goto timeout;
630 else if (ret)
631 goto clear_err;
632 }
633
634 /* Generate a STOP condition on the bus. Note that gmbus can't generata
635 * a STOP on the very first cycle. To simplify the code we
636 * unconditionally generate the STOP condition with an additional gmbus
637 * cycle. */
638 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
639
640 /* Mark the GMBUS interface as disabled after waiting for idle.
641 * We will re-enable it at the start of the next xfer,
642 * till then let it sleep.
643 */
644 if (gmbus_wait_idle(dev_priv)) {
645 drm_dbg_kms(&dev_priv->drm,
646 "GMBUS [%s] timed out waiting for idle\n",
647 adapter->name);
648 ret = -ETIMEDOUT;
649 }
650 intel_de_write_fw(dev_priv, GMBUS0, 0);
651 ret = ret ?: i;
652 goto out;
653
654clear_err:
655 /*
656 * Wait for bus to IDLE before clearing NAK.
657 * If we clear the NAK while bus is still active, then it will stay
658 * active and the next transaction may fail.
659 *
660 * If no ACK is received during the address phase of a transaction, the
661 * adapter must report -ENXIO. It is not clear what to return if no ACK
662 * is received at other times. But we have to be careful to not return
663 * spurious -ENXIO because that will prevent i2c and drm edid functions
664 * from retrying. So return -ENXIO only when gmbus properly quiescents -
665 * timing out seems to happen when there _is_ a ddc chip present, but
666 * it's slow responding and only answers on the 2nd retry.
667 */
668 ret = -ENXIO;
669 if (gmbus_wait_idle(dev_priv)) {
670 drm_dbg_kms(&dev_priv->drm,
671 "GMBUS [%s] timed out after NAK\n",
672 adapter->name);
673 ret = -ETIMEDOUT;
674 }
675
676 /* Toggle the Software Clear Interrupt bit. This has the effect
677 * of resetting the GMBUS controller and so clearing the
678 * BUS_ERROR raised by the slave's NAK.
679 */
680 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
681 intel_de_write_fw(dev_priv, GMBUS1, 0);
682 intel_de_write_fw(dev_priv, GMBUS0, 0);
683
684 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
685 adapter->name, msgs[i].addr,
686 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
687
688 /*
689 * Passive adapters sometimes NAK the first probe. Retry the first
690 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
691 * has retries internally. See also the retry loop in
692 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
693 */
694 if (ret == -ENXIO && i == 0 && try++ == 0) {
695 drm_dbg_kms(&dev_priv->drm,
696 "GMBUS [%s] NAK on first message, retry\n",
697 adapter->name);
698 goto retry;
699 }
700
701 goto out;
702
703timeout:
704 drm_dbg_kms(&dev_priv->drm,
705 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
706 bus->adapter.name, bus->reg0 & 0xff);
707 intel_de_write_fw(dev_priv, GMBUS0, 0);
708
709 /*
710 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
711 * instead. Use EAGAIN to have i2c core retry.
712 */
713 ret = -EAGAIN;
714
715out:
716 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
717 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
718 bxt_gmbus_clock_gating(dev_priv, true);
719 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
720 pch_gmbus_clock_gating(dev_priv, true);
721
722 return ret;
723}
724
725static int
726gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
727{
728 struct intel_gmbus *bus =
729 container_of(adapter, struct intel_gmbus, adapter);
730 struct drm_i915_private *dev_priv = bus->dev_priv;
731 intel_wakeref_t wakeref;
732 int ret;
733
734 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
735
736 if (bus->force_bit) {
737 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
738 if (ret < 0)
739 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
740 } else {
741 ret = do_gmbus_xfer(adapter, msgs, num, 0);
742 if (ret == -EAGAIN)
743 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
744 }
745
746 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
747
748 return ret;
749}
750
751int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
752{
753 struct intel_gmbus *bus =
754 container_of(adapter, struct intel_gmbus, adapter);
755 struct drm_i915_private *dev_priv = bus->dev_priv;
756 u8 cmd = DRM_HDCP_DDC_AKSV;
757 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
758 struct i2c_msg msgs[] = {
759 {
760 .addr = DRM_HDCP_DDC_ADDR,
761 .flags = 0,
762 .len = sizeof(cmd),
763 .buf = &cmd,
764 },
765 {
766 .addr = DRM_HDCP_DDC_ADDR,
767 .flags = 0,
768 .len = sizeof(buf),
769 .buf = buf,
770 }
771 };
772 intel_wakeref_t wakeref;
773 int ret;
774
775 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
776 mutex_lock(&dev_priv->gmbus_mutex);
777
778 /*
779 * In order to output Aksv to the receiver, use an indexed write to
780 * pass the i2c command, and tell GMBUS to use the HW-provided value
781 * instead of sourcing GMBUS3 for the data.
782 */
783 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
784
785 mutex_unlock(&dev_priv->gmbus_mutex);
786 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
787
788 return ret;
789}
790
791static u32 gmbus_func(struct i2c_adapter *adapter)
792{
793 return i2c_bit_algo.functionality(adapter) &
794 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
795 /* I2C_FUNC_10BIT_ADDR | */
796 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
797 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
798}
799
800static const struct i2c_algorithm gmbus_algorithm = {
801 .master_xfer = gmbus_xfer,
802 .functionality = gmbus_func
803};
804
805static void gmbus_lock_bus(struct i2c_adapter *adapter,
806 unsigned int flags)
807{
808 struct intel_gmbus *bus = to_intel_gmbus(adapter);
809 struct drm_i915_private *dev_priv = bus->dev_priv;
810
811 mutex_lock(&dev_priv->gmbus_mutex);
812}
813
814static int gmbus_trylock_bus(struct i2c_adapter *adapter,
815 unsigned int flags)
816{
817 struct intel_gmbus *bus = to_intel_gmbus(adapter);
818 struct drm_i915_private *dev_priv = bus->dev_priv;
819
820 return mutex_trylock(&dev_priv->gmbus_mutex);
821}
822
823static void gmbus_unlock_bus(struct i2c_adapter *adapter,
824 unsigned int flags)
825{
826 struct intel_gmbus *bus = to_intel_gmbus(adapter);
827 struct drm_i915_private *dev_priv = bus->dev_priv;
828
829 mutex_unlock(&dev_priv->gmbus_mutex);
830}
831
832static const struct i2c_lock_operations gmbus_lock_ops = {
833 .lock_bus = gmbus_lock_bus,
834 .trylock_bus = gmbus_trylock_bus,
835 .unlock_bus = gmbus_unlock_bus,
836};
837
838/**
839 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
840 * @dev_priv: i915 device private
841 */
842int intel_gmbus_setup(struct drm_i915_private *dev_priv)
843{
844 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
845 struct intel_gmbus *bus;
846 unsigned int pin;
847 int ret;
848
849 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
850 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
851 else if (!HAS_GMCH(dev_priv))
852 /*
853 * Broxton uses the same PCH offsets for South Display Engine,
854 * even though it doesn't have a PCH.
855 */
856 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
857
858 mutex_init(&dev_priv->gmbus_mutex);
859 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
860
861 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
862 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
863 continue;
864
865 bus = &dev_priv->gmbus[pin];
866
867 bus->adapter.owner = THIS_MODULE;
868 bus->adapter.class = I2C_CLASS_DDC;
869 snprintf(bus->adapter.name,
870 sizeof(bus->adapter.name),
871 "i915 gmbus %s",
872 get_gmbus_pin(dev_priv, pin)->name);
873
874 bus->adapter.dev.parent = &pdev->dev;
875 bus->dev_priv = dev_priv;
876
877 bus->adapter.algo = &gmbus_algorithm;
878 bus->adapter.lock_ops = &gmbus_lock_ops;
879
880 /*
881 * We wish to retry with bit banging
882 * after a timed out GMBUS attempt.
883 */
884 bus->adapter.retries = 1;
885
886 /* By default use a conservative clock rate */
887 bus->reg0 = pin | GMBUS_RATE_100KHZ;
888
889 /* gmbus seems to be broken on i830 */
890 if (IS_I830(dev_priv))
891 bus->force_bit = 1;
892
893 intel_gpio_setup(bus, pin);
894
895 ret = i2c_add_adapter(&bus->adapter);
896 if (ret)
897 goto err;
898 }
899
900 intel_gmbus_reset(dev_priv);
901
902 return 0;
903
904err:
905 while (pin--) {
906 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
907 continue;
908
909 bus = &dev_priv->gmbus[pin];
910 i2c_del_adapter(&bus->adapter);
911 }
912 return ret;
913}
914
915struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
916 unsigned int pin)
917{
918 if (drm_WARN_ON(&dev_priv->drm,
919 !intel_gmbus_is_valid_pin(dev_priv, pin)))
920 return NULL;
921
922 return &dev_priv->gmbus[pin].adapter;
923}
924
925void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
926{
927 struct intel_gmbus *bus = to_intel_gmbus(adapter);
928
929 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
930}
931
932void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
933{
934 struct intel_gmbus *bus = to_intel_gmbus(adapter);
935 struct drm_i915_private *dev_priv = bus->dev_priv;
936
937 mutex_lock(&dev_priv->gmbus_mutex);
938
939 bus->force_bit += force_bit ? 1 : -1;
940 drm_dbg_kms(&dev_priv->drm,
941 "%sabling bit-banging on %s. force bit now %d\n",
942 force_bit ? "en" : "dis", adapter->name,
943 bus->force_bit);
944
945 mutex_unlock(&dev_priv->gmbus_mutex);
946}
947
948bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
949{
950 struct intel_gmbus *bus = to_intel_gmbus(adapter);
951
952 return bus->force_bit;
953}
954
955void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
956{
957 struct intel_gmbus *bus;
958 unsigned int pin;
959
960 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
961 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
962 continue;
963
964 bus = &dev_priv->gmbus[pin];
965 i2c_del_adapter(&bus->adapter);
966 }
967}
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30#include <linux/export.h>
31#include <linux/i2c-algo-bit.h>
32#include <linux/i2c.h>
33
34#include <drm/display/drm_hdcp_helper.h>
35
36#include "i915_drv.h"
37#include "i915_irq.h"
38#include "i915_reg.h"
39#include "intel_de.h"
40#include "intel_display_types.h"
41#include "intel_gmbus.h"
42#include "intel_gmbus_regs.h"
43
44struct intel_gmbus {
45 struct i2c_adapter adapter;
46#define GMBUS_FORCE_BIT_RETRY (1U << 31)
47 u32 force_bit;
48 u32 reg0;
49 i915_reg_t gpio_reg;
50 struct i2c_algo_bit_data bit_algo;
51 struct drm_i915_private *i915;
52};
53
54enum gmbus_gpio {
55 GPIOA,
56 GPIOB,
57 GPIOC,
58 GPIOD,
59 GPIOE,
60 GPIOF,
61 GPIOG,
62 GPIOH,
63 __GPIOI_UNUSED,
64 GPIOJ,
65 GPIOK,
66 GPIOL,
67 GPIOM,
68 GPION,
69 GPIOO,
70};
71
72struct gmbus_pin {
73 const char *name;
74 enum gmbus_gpio gpio;
75};
76
77/* Map gmbus pin pairs to names and registers. */
78static const struct gmbus_pin gmbus_pins[] = {
79 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
81 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
82 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
83 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
84 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
85};
86
87static const struct gmbus_pin gmbus_pins_bdw[] = {
88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
89 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
90 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
91 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
92};
93
94static const struct gmbus_pin gmbus_pins_skl[] = {
95 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
96 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
97 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
98};
99
100static const struct gmbus_pin gmbus_pins_bxt[] = {
101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
104};
105
106static const struct gmbus_pin gmbus_pins_cnp[] = {
107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
111};
112
113static const struct gmbus_pin gmbus_pins_icp[] = {
114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
123};
124
125static const struct gmbus_pin gmbus_pins_dg1[] = {
126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
130};
131
132static const struct gmbus_pin gmbus_pins_dg2[] = {
133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
138};
139
140static const struct gmbus_pin gmbus_pins_mtp[] = {
141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
150};
151
152static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
153 unsigned int pin)
154{
155 const struct gmbus_pin *pins;
156 size_t size;
157
158 if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
159 pins = gmbus_pins_mtp;
160 size = ARRAY_SIZE(gmbus_pins_mtp);
161 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
162 pins = gmbus_pins_dg2;
163 size = ARRAY_SIZE(gmbus_pins_dg2);
164 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
165 pins = gmbus_pins_dg1;
166 size = ARRAY_SIZE(gmbus_pins_dg1);
167 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
168 pins = gmbus_pins_mtp;
169 size = ARRAY_SIZE(gmbus_pins_mtp);
170 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
171 pins = gmbus_pins_icp;
172 size = ARRAY_SIZE(gmbus_pins_icp);
173 } else if (HAS_PCH_CNP(i915)) {
174 pins = gmbus_pins_cnp;
175 size = ARRAY_SIZE(gmbus_pins_cnp);
176 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
177 pins = gmbus_pins_bxt;
178 size = ARRAY_SIZE(gmbus_pins_bxt);
179 } else if (DISPLAY_VER(i915) == 9) {
180 pins = gmbus_pins_skl;
181 size = ARRAY_SIZE(gmbus_pins_skl);
182 } else if (IS_BROADWELL(i915)) {
183 pins = gmbus_pins_bdw;
184 size = ARRAY_SIZE(gmbus_pins_bdw);
185 } else {
186 pins = gmbus_pins;
187 size = ARRAY_SIZE(gmbus_pins);
188 }
189
190 if (pin >= size || !pins[pin].name)
191 return NULL;
192
193 return &pins[pin];
194}
195
196bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
197{
198 return get_gmbus_pin(i915, pin);
199}
200
201/* Intel GPIO access functions */
202
203#define I2C_RISEFALL_TIME 10
204
205static inline struct intel_gmbus *
206to_intel_gmbus(struct i2c_adapter *i2c)
207{
208 return container_of(i2c, struct intel_gmbus, adapter);
209}
210
211void
212intel_gmbus_reset(struct drm_i915_private *i915)
213{
214 intel_de_write(i915, GMBUS0(i915), 0);
215 intel_de_write(i915, GMBUS4(i915), 0);
216}
217
218static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
219 bool enable)
220{
221 /* When using bit bashing for I2C, this bit needs to be set to 1 */
222 intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
223 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
224}
225
226static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
227 bool enable)
228{
229 intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
230 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
231}
232
233static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
234 bool enable)
235{
236 intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
237 !enable ? BXT_GMBUS_GATING_DIS : 0);
238}
239
240static u32 get_reserved(struct intel_gmbus *bus)
241{
242 struct drm_i915_private *i915 = bus->i915;
243 u32 reserved = 0;
244
245 /* On most chips, these bits must be preserved in software. */
246 if (!IS_I830(i915) && !IS_I845G(i915))
247 reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
248 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
249
250 return reserved;
251}
252
253static int get_clock(void *data)
254{
255 struct intel_gmbus *bus = data;
256 struct drm_i915_private *i915 = bus->i915;
257 u32 reserved = get_reserved(bus);
258
259 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
260 intel_de_write_notrace(i915, bus->gpio_reg, reserved);
261
262 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
263}
264
265static int get_data(void *data)
266{
267 struct intel_gmbus *bus = data;
268 struct drm_i915_private *i915 = bus->i915;
269 u32 reserved = get_reserved(bus);
270
271 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
272 intel_de_write_notrace(i915, bus->gpio_reg, reserved);
273
274 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
275}
276
277static void set_clock(void *data, int state_high)
278{
279 struct intel_gmbus *bus = data;
280 struct drm_i915_private *i915 = bus->i915;
281 u32 reserved = get_reserved(bus);
282 u32 clock_bits;
283
284 if (state_high)
285 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
286 else
287 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
288 GPIO_CLOCK_VAL_MASK;
289
290 intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
291 intel_de_posting_read(i915, bus->gpio_reg);
292}
293
294static void set_data(void *data, int state_high)
295{
296 struct intel_gmbus *bus = data;
297 struct drm_i915_private *i915 = bus->i915;
298 u32 reserved = get_reserved(bus);
299 u32 data_bits;
300
301 if (state_high)
302 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
303 else
304 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
305 GPIO_DATA_VAL_MASK;
306
307 intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
308 intel_de_posting_read(i915, bus->gpio_reg);
309}
310
311static int
312intel_gpio_pre_xfer(struct i2c_adapter *adapter)
313{
314 struct intel_gmbus *bus = to_intel_gmbus(adapter);
315 struct drm_i915_private *i915 = bus->i915;
316
317 intel_gmbus_reset(i915);
318
319 if (IS_PINEVIEW(i915))
320 pnv_gmbus_clock_gating(i915, false);
321
322 set_data(bus, 1);
323 set_clock(bus, 1);
324 udelay(I2C_RISEFALL_TIME);
325 return 0;
326}
327
328static void
329intel_gpio_post_xfer(struct i2c_adapter *adapter)
330{
331 struct intel_gmbus *bus = to_intel_gmbus(adapter);
332 struct drm_i915_private *i915 = bus->i915;
333
334 set_data(bus, 1);
335 set_clock(bus, 1);
336
337 if (IS_PINEVIEW(i915))
338 pnv_gmbus_clock_gating(i915, true);
339}
340
341static void
342intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
343{
344 struct i2c_algo_bit_data *algo;
345
346 algo = &bus->bit_algo;
347
348 bus->gpio_reg = gpio_reg;
349 bus->adapter.algo_data = algo;
350 algo->setsda = set_data;
351 algo->setscl = set_clock;
352 algo->getsda = get_data;
353 algo->getscl = get_clock;
354 algo->pre_xfer = intel_gpio_pre_xfer;
355 algo->post_xfer = intel_gpio_post_xfer;
356 algo->udelay = I2C_RISEFALL_TIME;
357 algo->timeout = usecs_to_jiffies(2200);
358 algo->data = bus;
359}
360
361static bool has_gmbus_irq(struct drm_i915_private *i915)
362{
363 /*
364 * encoder->shutdown() may want to use GMBUS
365 * after irqs have already been disabled.
366 */
367 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
368}
369
370static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
371{
372 DEFINE_WAIT(wait);
373 u32 gmbus2;
374 int ret;
375
376 /* Important: The hw handles only the first bit, so set only one! Since
377 * we also need to check for NAKs besides the hw ready/idle signal, we
378 * need to wake up periodically and check that ourselves.
379 */
380 if (!has_gmbus_irq(i915))
381 irq_en = 0;
382
383 add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
384 intel_de_write_fw(i915, GMBUS4(i915), irq_en);
385
386 status |= GMBUS_SATOER;
387 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
388 2);
389 if (ret)
390 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
391 50);
392
393 intel_de_write_fw(i915, GMBUS4(i915), 0);
394 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
395
396 if (gmbus2 & GMBUS_SATOER)
397 return -ENXIO;
398
399 return ret;
400}
401
402static int
403gmbus_wait_idle(struct drm_i915_private *i915)
404{
405 DEFINE_WAIT(wait);
406 u32 irq_enable;
407 int ret;
408
409 /* Important: The hw handles only the first bit, so set only one! */
410 irq_enable = 0;
411 if (has_gmbus_irq(i915))
412 irq_enable = GMBUS_IDLE_EN;
413
414 add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
415 intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
416
417 ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
418
419 intel_de_write_fw(i915, GMBUS4(i915), 0);
420 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
421
422 return ret;
423}
424
425static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
426{
427 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
428 GMBUS_BYTE_COUNT_MAX;
429}
430
431static int
432gmbus_xfer_read_chunk(struct drm_i915_private *i915,
433 unsigned short addr, u8 *buf, unsigned int len,
434 u32 gmbus0_reg, u32 gmbus1_index)
435{
436 unsigned int size = len;
437 bool burst_read = len > gmbus_max_xfer_size(i915);
438 bool extra_byte_added = false;
439
440 if (burst_read) {
441 /*
442 * As per HW Spec, for 512Bytes need to read extra Byte and
443 * Ignore the extra byte read.
444 */
445 if (len == 512) {
446 extra_byte_added = true;
447 len++;
448 }
449 size = len % 256 + 256;
450 intel_de_write_fw(i915, GMBUS0(i915),
451 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
452 }
453
454 intel_de_write_fw(i915, GMBUS1(i915),
455 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
456 while (len) {
457 int ret;
458 u32 val, loop = 0;
459
460 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
461 if (ret)
462 return ret;
463
464 val = intel_de_read_fw(i915, GMBUS3(i915));
465 do {
466 if (extra_byte_added && len == 1)
467 break;
468
469 *buf++ = val & 0xff;
470 val >>= 8;
471 } while (--len && ++loop < 4);
472
473 if (burst_read && len == size - 4)
474 /* Reset the override bit */
475 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
476 }
477
478 return 0;
479}
480
481/*
482 * HW spec says that 512Bytes in Burst read need special treatment.
483 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
484 * an I2C slave, which supports such a lengthy burst read too for experiments.
485 *
486 * So until things get clarified on HW support, to avoid the burst read length
487 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
488 */
489#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
490
491static int
492gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
493 u32 gmbus0_reg, u32 gmbus1_index)
494{
495 u8 *buf = msg->buf;
496 unsigned int rx_size = msg->len;
497 unsigned int len;
498 int ret;
499
500 do {
501 if (HAS_GMBUS_BURST_READ(i915))
502 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
503 else
504 len = min(rx_size, gmbus_max_xfer_size(i915));
505
506 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
507 gmbus0_reg, gmbus1_index);
508 if (ret)
509 return ret;
510
511 rx_size -= len;
512 buf += len;
513 } while (rx_size != 0);
514
515 return 0;
516}
517
518static int
519gmbus_xfer_write_chunk(struct drm_i915_private *i915,
520 unsigned short addr, u8 *buf, unsigned int len,
521 u32 gmbus1_index)
522{
523 unsigned int chunk_size = len;
524 u32 val, loop;
525
526 val = loop = 0;
527 while (len && loop < 4) {
528 val |= *buf++ << (8 * loop++);
529 len -= 1;
530 }
531
532 intel_de_write_fw(i915, GMBUS3(i915), val);
533 intel_de_write_fw(i915, GMBUS1(i915),
534 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
535 while (len) {
536 int ret;
537
538 val = loop = 0;
539 do {
540 val |= *buf++ << (8 * loop);
541 } while (--len && ++loop < 4);
542
543 intel_de_write_fw(i915, GMBUS3(i915), val);
544
545 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
546 if (ret)
547 return ret;
548 }
549
550 return 0;
551}
552
553static int
554gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
555 u32 gmbus1_index)
556{
557 u8 *buf = msg->buf;
558 unsigned int tx_size = msg->len;
559 unsigned int len;
560 int ret;
561
562 do {
563 len = min(tx_size, gmbus_max_xfer_size(i915));
564
565 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
566 gmbus1_index);
567 if (ret)
568 return ret;
569
570 buf += len;
571 tx_size -= len;
572 } while (tx_size != 0);
573
574 return 0;
575}
576
577/*
578 * The gmbus controller can combine a 1 or 2 byte write with another read/write
579 * that immediately follows it by using an "INDEX" cycle.
580 */
581static bool
582gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
583{
584 return (i + 1 < num &&
585 msgs[i].addr == msgs[i + 1].addr &&
586 !(msgs[i].flags & I2C_M_RD) &&
587 (msgs[i].len == 1 || msgs[i].len == 2) &&
588 msgs[i + 1].len > 0);
589}
590
591static int
592gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
593 u32 gmbus0_reg)
594{
595 u32 gmbus1_index = 0;
596 u32 gmbus5 = 0;
597 int ret;
598
599 if (msgs[0].len == 2)
600 gmbus5 = GMBUS_2BYTE_INDEX_EN |
601 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
602 if (msgs[0].len == 1)
603 gmbus1_index = GMBUS_CYCLE_INDEX |
604 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
605
606 /* GMBUS5 holds 16-bit index */
607 if (gmbus5)
608 intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
609
610 if (msgs[1].flags & I2C_M_RD)
611 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
612 gmbus1_index);
613 else
614 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
615
616 /* Clear GMBUS5 after each index transfer */
617 if (gmbus5)
618 intel_de_write_fw(i915, GMBUS5(i915), 0);
619
620 return ret;
621}
622
623static int
624do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
625 u32 gmbus0_source)
626{
627 struct intel_gmbus *bus = to_intel_gmbus(adapter);
628 struct drm_i915_private *i915 = bus->i915;
629 int i = 0, inc, try = 0;
630 int ret = 0;
631
632 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
633 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
634 bxt_gmbus_clock_gating(i915, false);
635 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
636 pch_gmbus_clock_gating(i915, false);
637
638retry:
639 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
640
641 for (; i < num; i += inc) {
642 inc = 1;
643 if (gmbus_is_index_xfer(msgs, i, num)) {
644 ret = gmbus_index_xfer(i915, &msgs[i],
645 gmbus0_source | bus->reg0);
646 inc = 2; /* an index transmission is two msgs */
647 } else if (msgs[i].flags & I2C_M_RD) {
648 ret = gmbus_xfer_read(i915, &msgs[i],
649 gmbus0_source | bus->reg0, 0);
650 } else {
651 ret = gmbus_xfer_write(i915, &msgs[i], 0);
652 }
653
654 if (!ret)
655 ret = gmbus_wait(i915,
656 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
657 if (ret == -ETIMEDOUT)
658 goto timeout;
659 else if (ret)
660 goto clear_err;
661 }
662
663 /* Generate a STOP condition on the bus. Note that gmbus can't generata
664 * a STOP on the very first cycle. To simplify the code we
665 * unconditionally generate the STOP condition with an additional gmbus
666 * cycle. */
667 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
668
669 /* Mark the GMBUS interface as disabled after waiting for idle.
670 * We will re-enable it at the start of the next xfer,
671 * till then let it sleep.
672 */
673 if (gmbus_wait_idle(i915)) {
674 drm_dbg_kms(&i915->drm,
675 "GMBUS [%s] timed out waiting for idle\n",
676 adapter->name);
677 ret = -ETIMEDOUT;
678 }
679 intel_de_write_fw(i915, GMBUS0(i915), 0);
680 ret = ret ?: i;
681 goto out;
682
683clear_err:
684 /*
685 * Wait for bus to IDLE before clearing NAK.
686 * If we clear the NAK while bus is still active, then it will stay
687 * active and the next transaction may fail.
688 *
689 * If no ACK is received during the address phase of a transaction, the
690 * adapter must report -ENXIO. It is not clear what to return if no ACK
691 * is received at other times. But we have to be careful to not return
692 * spurious -ENXIO because that will prevent i2c and drm edid functions
693 * from retrying. So return -ENXIO only when gmbus properly quiescents -
694 * timing out seems to happen when there _is_ a ddc chip present, but
695 * it's slow responding and only answers on the 2nd retry.
696 */
697 ret = -ENXIO;
698 if (gmbus_wait_idle(i915)) {
699 drm_dbg_kms(&i915->drm,
700 "GMBUS [%s] timed out after NAK\n",
701 adapter->name);
702 ret = -ETIMEDOUT;
703 }
704
705 /* Toggle the Software Clear Interrupt bit. This has the effect
706 * of resetting the GMBUS controller and so clearing the
707 * BUS_ERROR raised by the slave's NAK.
708 */
709 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
710 intel_de_write_fw(i915, GMBUS1(i915), 0);
711 intel_de_write_fw(i915, GMBUS0(i915), 0);
712
713 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
714 adapter->name, msgs[i].addr,
715 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
716
717 /*
718 * Passive adapters sometimes NAK the first probe. Retry the first
719 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
720 * has retries internally. See also the retry loop in
721 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
722 */
723 if (ret == -ENXIO && i == 0 && try++ == 0) {
724 drm_dbg_kms(&i915->drm,
725 "GMBUS [%s] NAK on first message, retry\n",
726 adapter->name);
727 goto retry;
728 }
729
730 goto out;
731
732timeout:
733 drm_dbg_kms(&i915->drm,
734 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
735 bus->adapter.name, bus->reg0 & 0xff);
736 intel_de_write_fw(i915, GMBUS0(i915), 0);
737
738 /*
739 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
740 * instead. Use EAGAIN to have i2c core retry.
741 */
742 ret = -EAGAIN;
743
744out:
745 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
746 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
747 bxt_gmbus_clock_gating(i915, true);
748 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
749 pch_gmbus_clock_gating(i915, true);
750
751 return ret;
752}
753
754static int
755gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
756{
757 struct intel_gmbus *bus = to_intel_gmbus(adapter);
758 struct drm_i915_private *i915 = bus->i915;
759 intel_wakeref_t wakeref;
760 int ret;
761
762 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
763
764 if (bus->force_bit) {
765 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
766 if (ret < 0)
767 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
768 } else {
769 ret = do_gmbus_xfer(adapter, msgs, num, 0);
770 if (ret == -EAGAIN)
771 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
772 }
773
774 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
775
776 return ret;
777}
778
779int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
780{
781 struct intel_gmbus *bus = to_intel_gmbus(adapter);
782 struct drm_i915_private *i915 = bus->i915;
783 u8 cmd = DRM_HDCP_DDC_AKSV;
784 u8 buf[DRM_HDCP_KSV_LEN] = {};
785 struct i2c_msg msgs[] = {
786 {
787 .addr = DRM_HDCP_DDC_ADDR,
788 .flags = 0,
789 .len = sizeof(cmd),
790 .buf = &cmd,
791 },
792 {
793 .addr = DRM_HDCP_DDC_ADDR,
794 .flags = 0,
795 .len = sizeof(buf),
796 .buf = buf,
797 }
798 };
799 intel_wakeref_t wakeref;
800 int ret;
801
802 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
803 mutex_lock(&i915->display.gmbus.mutex);
804
805 /*
806 * In order to output Aksv to the receiver, use an indexed write to
807 * pass the i2c command, and tell GMBUS to use the HW-provided value
808 * instead of sourcing GMBUS3 for the data.
809 */
810 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
811
812 mutex_unlock(&i915->display.gmbus.mutex);
813 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
814
815 return ret;
816}
817
818static u32 gmbus_func(struct i2c_adapter *adapter)
819{
820 return i2c_bit_algo.functionality(adapter) &
821 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
822 /* I2C_FUNC_10BIT_ADDR | */
823 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
824 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
825}
826
827static const struct i2c_algorithm gmbus_algorithm = {
828 .master_xfer = gmbus_xfer,
829 .functionality = gmbus_func
830};
831
832static void gmbus_lock_bus(struct i2c_adapter *adapter,
833 unsigned int flags)
834{
835 struct intel_gmbus *bus = to_intel_gmbus(adapter);
836 struct drm_i915_private *i915 = bus->i915;
837
838 mutex_lock(&i915->display.gmbus.mutex);
839}
840
841static int gmbus_trylock_bus(struct i2c_adapter *adapter,
842 unsigned int flags)
843{
844 struct intel_gmbus *bus = to_intel_gmbus(adapter);
845 struct drm_i915_private *i915 = bus->i915;
846
847 return mutex_trylock(&i915->display.gmbus.mutex);
848}
849
850static void gmbus_unlock_bus(struct i2c_adapter *adapter,
851 unsigned int flags)
852{
853 struct intel_gmbus *bus = to_intel_gmbus(adapter);
854 struct drm_i915_private *i915 = bus->i915;
855
856 mutex_unlock(&i915->display.gmbus.mutex);
857}
858
859static const struct i2c_lock_operations gmbus_lock_ops = {
860 .lock_bus = gmbus_lock_bus,
861 .trylock_bus = gmbus_trylock_bus,
862 .unlock_bus = gmbus_unlock_bus,
863};
864
865/**
866 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
867 * @i915: i915 device private
868 */
869int intel_gmbus_setup(struct drm_i915_private *i915)
870{
871 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
872 unsigned int pin;
873 int ret;
874
875 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
876 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
877 else if (!HAS_GMCH(i915))
878 /*
879 * Broxton uses the same PCH offsets for South Display Engine,
880 * even though it doesn't have a PCH.
881 */
882 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
883
884 mutex_init(&i915->display.gmbus.mutex);
885 init_waitqueue_head(&i915->display.gmbus.wait_queue);
886
887 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
888 const struct gmbus_pin *gmbus_pin;
889 struct intel_gmbus *bus;
890
891 gmbus_pin = get_gmbus_pin(i915, pin);
892 if (!gmbus_pin)
893 continue;
894
895 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
896 if (!bus) {
897 ret = -ENOMEM;
898 goto err;
899 }
900
901 bus->adapter.owner = THIS_MODULE;
902 snprintf(bus->adapter.name,
903 sizeof(bus->adapter.name),
904 "i915 gmbus %s", gmbus_pin->name);
905
906 bus->adapter.dev.parent = &pdev->dev;
907 bus->i915 = i915;
908
909 bus->adapter.algo = &gmbus_algorithm;
910 bus->adapter.lock_ops = &gmbus_lock_ops;
911
912 /*
913 * We wish to retry with bit banging
914 * after a timed out GMBUS attempt.
915 */
916 bus->adapter.retries = 1;
917
918 /* By default use a conservative clock rate */
919 bus->reg0 = pin | GMBUS_RATE_100KHZ;
920
921 /* gmbus seems to be broken on i830 */
922 if (IS_I830(i915))
923 bus->force_bit = 1;
924
925 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
926
927 ret = i2c_add_adapter(&bus->adapter);
928 if (ret) {
929 kfree(bus);
930 goto err;
931 }
932
933 i915->display.gmbus.bus[pin] = bus;
934 }
935
936 intel_gmbus_reset(i915);
937
938 return 0;
939
940err:
941 intel_gmbus_teardown(i915);
942
943 return ret;
944}
945
946struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
947 unsigned int pin)
948{
949 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
950 !i915->display.gmbus.bus[pin]))
951 return NULL;
952
953 return &i915->display.gmbus.bus[pin]->adapter;
954}
955
956void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
957{
958 struct intel_gmbus *bus = to_intel_gmbus(adapter);
959 struct drm_i915_private *i915 = bus->i915;
960
961 mutex_lock(&i915->display.gmbus.mutex);
962
963 bus->force_bit += force_bit ? 1 : -1;
964 drm_dbg_kms(&i915->drm,
965 "%sabling bit-banging on %s. force bit now %d\n",
966 force_bit ? "en" : "dis", adapter->name,
967 bus->force_bit);
968
969 mutex_unlock(&i915->display.gmbus.mutex);
970}
971
972bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
973{
974 struct intel_gmbus *bus = to_intel_gmbus(adapter);
975
976 return bus->force_bit;
977}
978
979void intel_gmbus_teardown(struct drm_i915_private *i915)
980{
981 unsigned int pin;
982
983 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
984 struct intel_gmbus *bus;
985
986 bus = i915->display.gmbus.bus[pin];
987 if (!bus)
988 continue;
989
990 i2c_del_adapter(&bus->adapter);
991
992 kfree(bus);
993 i915->display.gmbus.bus[pin] = NULL;
994 }
995}
996
997void intel_gmbus_irq_handler(struct drm_i915_private *i915)
998{
999 wake_up_all(&i915->display.gmbus.wait_queue);
1000}