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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
30 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
34 *
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
39 */
40
41#include <drm/drm_fourcc.h>
42
43#include "i915_drv.h"
44#include "i915_trace.h"
45#include "i915_vgpu.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_fbc.h"
49#include "intel_frontbuffer.h"
50
51/*
52 * For SKL+, the plane source size used by the hardware is based on the value we
53 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
54 * we wrote to PIPESRC.
55 */
56static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
57 int *width, int *height)
58{
59 if (width)
60 *width = cache->plane.src_w;
61 if (height)
62 *height = cache->plane.src_h;
63}
64
65static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
66 const struct intel_fbc_state_cache *cache)
67{
68 int lines;
69
70 intel_fbc_get_plane_source_size(cache, NULL, &lines);
71 if (DISPLAY_VER(dev_priv) == 7)
72 lines = min(lines, 2048);
73 else if (DISPLAY_VER(dev_priv) >= 8)
74 lines = min(lines, 2560);
75
76 /* Hardware needs the full buffer stride, not just the active area. */
77 return lines * cache->fb.stride;
78}
79
80static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
81{
82 u32 fbc_ctl;
83
84 /* Disable compression */
85 fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
86 if ((fbc_ctl & FBC_CTL_EN) == 0)
87 return;
88
89 fbc_ctl &= ~FBC_CTL_EN;
90 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
91
92 /* Wait for compressing bit to clear */
93 if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
94 FBC_STAT_COMPRESSING, 10)) {
95 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
96 return;
97 }
98}
99
100static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
101{
102 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
103 int cfb_pitch;
104 int i;
105 u32 fbc_ctl;
106
107 /* Note: fbc.threshold == 1 for i8xx */
108 cfb_pitch = params->cfb_size / FBC_LL_SIZE;
109 if (params->fb.stride < cfb_pitch)
110 cfb_pitch = params->fb.stride;
111
112 /* FBC_CTL wants 32B or 64B units */
113 if (DISPLAY_VER(dev_priv) == 2)
114 cfb_pitch = (cfb_pitch / 32) - 1;
115 else
116 cfb_pitch = (cfb_pitch / 64) - 1;
117
118 /* Clear old tags */
119 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
120 intel_de_write(dev_priv, FBC_TAG(i), 0);
121
122 if (DISPLAY_VER(dev_priv) == 4) {
123 u32 fbc_ctl2;
124
125 /* Set it up... */
126 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
127 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
128 if (params->fence_id >= 0)
129 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
130 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
131 intel_de_write(dev_priv, FBC_FENCE_OFF,
132 params->fence_y_offset);
133 }
134
135 /* enable it... */
136 fbc_ctl = FBC_CTL_INTERVAL(params->interval);
137 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
138 if (IS_I945GM(dev_priv))
139 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
140 fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff);
141 if (params->fence_id >= 0)
142 fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
143 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
144}
145
146static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
147{
148 return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
149}
150
151static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
152{
153 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
154 u32 dpfc_ctl;
155
156 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
157 if (params->fb.format->cpp[0] == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161
162 if (params->fence_id >= 0) {
163 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
164 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
165 params->fence_y_offset);
166 } else {
167 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
168 }
169
170 /* enable it... */
171 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
172}
173
174static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
175{
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
183 }
184}
185
186static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
187{
188 return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
189}
190
191static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
192{
193 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
194 enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
195
196 spin_lock_irq(&dev_priv->uncore.lock);
197 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
198 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
199 spin_unlock_irq(&dev_priv->uncore.lock);
200}
201
202static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
203{
204 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
205 enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
206
207 spin_lock_irq(&dev_priv->uncore.lock);
208 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
209 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
210 spin_unlock_irq(&dev_priv->uncore.lock);
211}
212
213/* This function forces a CFB recompression through the nuke operation. */
214static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
215{
216 struct intel_fbc *fbc = &dev_priv->fbc;
217
218 trace_intel_fbc_nuke(fbc->crtc);
219
220 intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
221 intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
222}
223
224static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
225{
226 if (DISPLAY_VER(dev_priv) >= 6)
227 snb_fbc_recompress(dev_priv);
228 else if (DISPLAY_VER(dev_priv) >= 4)
229 i965_fbc_recompress(dev_priv);
230 else
231 i8xx_fbc_recompress(dev_priv);
232}
233
234static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
235{
236 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
237 u32 dpfc_ctl;
238 int threshold = dev_priv->fbc.threshold;
239
240 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
241 if (params->fb.format->cpp[0] == 2)
242 threshold++;
243
244 switch (threshold) {
245 case 4:
246 case 3:
247 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
248 break;
249 case 2:
250 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
251 break;
252 case 1:
253 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
254 break;
255 }
256
257 if (params->fence_id >= 0) {
258 dpfc_ctl |= DPFC_CTL_FENCE_EN;
259 if (IS_IRONLAKE(dev_priv))
260 dpfc_ctl |= params->fence_id;
261 if (IS_SANDYBRIDGE(dev_priv)) {
262 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
263 SNB_CPU_FENCE_ENABLE | params->fence_id);
264 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
265 params->fence_y_offset);
266 }
267 } else {
268 if (IS_SANDYBRIDGE(dev_priv)) {
269 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
270 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
271 }
272 }
273
274 intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
275 params->fence_y_offset);
276 /* enable it... */
277 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
278
279 intel_fbc_recompress(dev_priv);
280}
281
282static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
283{
284 u32 dpfc_ctl;
285
286 /* Disable compression */
287 dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
288 if (dpfc_ctl & DPFC_CTL_EN) {
289 dpfc_ctl &= ~DPFC_CTL_EN;
290 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
291 }
292}
293
294static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
295{
296 return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
297}
298
299static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
300{
301 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
302 u32 dpfc_ctl;
303 int threshold = dev_priv->fbc.threshold;
304
305 /* Display WA #0529: skl, kbl, bxt. */
306 if (DISPLAY_VER(dev_priv) == 9) {
307 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
308
309 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
310
311 if (params->gen9_wa_cfb_stride)
312 val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
313
314 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
315 }
316
317 dpfc_ctl = 0;
318 if (IS_IVYBRIDGE(dev_priv))
319 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
320
321 if (params->fb.format->cpp[0] == 2)
322 threshold++;
323
324 switch (threshold) {
325 case 4:
326 case 3:
327 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
328 break;
329 case 2:
330 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
331 break;
332 case 1:
333 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
334 break;
335 }
336
337 if (params->fence_id >= 0) {
338 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
339 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
340 SNB_CPU_FENCE_ENABLE | params->fence_id);
341 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
342 params->fence_y_offset);
343 } else if (dev_priv->ggtt.num_fences) {
344 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
345 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
346 }
347
348 if (dev_priv->fbc.false_color)
349 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
350
351 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
352
353 intel_fbc_recompress(dev_priv);
354}
355
356static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
357{
358 if (DISPLAY_VER(dev_priv) >= 5)
359 return ilk_fbc_is_active(dev_priv);
360 else if (IS_GM45(dev_priv))
361 return g4x_fbc_is_active(dev_priv);
362 else
363 return i8xx_fbc_is_active(dev_priv);
364}
365
366static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
367{
368 struct intel_fbc *fbc = &dev_priv->fbc;
369
370 trace_intel_fbc_activate(fbc->crtc);
371
372 fbc->active = true;
373 fbc->activated = true;
374
375 if (DISPLAY_VER(dev_priv) >= 7)
376 gen7_fbc_activate(dev_priv);
377 else if (DISPLAY_VER(dev_priv) >= 5)
378 ilk_fbc_activate(dev_priv);
379 else if (IS_GM45(dev_priv))
380 g4x_fbc_activate(dev_priv);
381 else
382 i8xx_fbc_activate(dev_priv);
383}
384
385static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
386{
387 struct intel_fbc *fbc = &dev_priv->fbc;
388
389 trace_intel_fbc_deactivate(fbc->crtc);
390
391 fbc->active = false;
392
393 if (DISPLAY_VER(dev_priv) >= 5)
394 ilk_fbc_deactivate(dev_priv);
395 else if (IS_GM45(dev_priv))
396 g4x_fbc_deactivate(dev_priv);
397 else
398 i8xx_fbc_deactivate(dev_priv);
399}
400
401/**
402 * intel_fbc_is_active - Is FBC active?
403 * @dev_priv: i915 device instance
404 *
405 * This function is used to verify the current state of FBC.
406 *
407 * FIXME: This should be tracked in the plane config eventually
408 * instead of queried at runtime for most callers.
409 */
410bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
411{
412 return dev_priv->fbc.active;
413}
414
415static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
416 const char *reason)
417{
418 struct intel_fbc *fbc = &dev_priv->fbc;
419
420 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
421
422 if (fbc->active)
423 intel_fbc_hw_deactivate(dev_priv);
424
425 fbc->no_fbc_reason = reason;
426}
427
428static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
429{
430 if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
431 return BIT_ULL(28);
432 else
433 return BIT_ULL(32);
434}
435
436static int find_compression_threshold(struct drm_i915_private *dev_priv,
437 struct drm_mm_node *node,
438 unsigned int size,
439 unsigned int fb_cpp)
440{
441 int compression_threshold = 1;
442 int ret;
443 u64 end;
444
445 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
446 * reserved range size, so it always assumes the maximum (8mb) is used.
447 * If we enable FBC using a CFB on that memory range we'll get FIFO
448 * underruns, even if that range is not reserved by the BIOS. */
449 if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 &&
450 !IS_BROXTON(dev_priv)))
451 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
452 else
453 end = U64_MAX;
454
455 end = min(end, intel_fbc_cfb_base_max(dev_priv));
456
457 /* HACK: This code depends on what we will do in *_enable_fbc. If that
458 * code changes, this code needs to change as well.
459 *
460 * The enable_fbc code will attempt to use one of our 2 compression
461 * thresholds, therefore, in that case, we only have 1 resort.
462 */
463
464 /* Try to over-allocate to reduce reallocations and fragmentation. */
465 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
466 4096, 0, end);
467 if (ret == 0)
468 return compression_threshold;
469
470again:
471 /* HW's ability to limit the CFB is 1:4 */
472 if (compression_threshold > 4 ||
473 (fb_cpp == 2 && compression_threshold == 2))
474 return 0;
475
476 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
477 4096, 0, end);
478 if (ret && DISPLAY_VER(dev_priv) <= 4) {
479 return 0;
480 } else if (ret) {
481 compression_threshold <<= 1;
482 goto again;
483 } else {
484 return compression_threshold;
485 }
486}
487
488static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
489 unsigned int size, unsigned int fb_cpp)
490{
491 struct intel_fbc *fbc = &dev_priv->fbc;
492 struct drm_mm_node *compressed_llb;
493 int ret;
494
495 drm_WARN_ON(&dev_priv->drm,
496 drm_mm_node_allocated(&fbc->compressed_fb));
497
498 ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
499 size, fb_cpp);
500 if (!ret)
501 goto err_llb;
502 else if (ret > 1) {
503 drm_info_once(&dev_priv->drm,
504 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
505 }
506
507 fbc->threshold = ret;
508
509 if (DISPLAY_VER(dev_priv) >= 5)
510 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
511 fbc->compressed_fb.start);
512 else if (IS_GM45(dev_priv)) {
513 intel_de_write(dev_priv, DPFC_CB_BASE,
514 fbc->compressed_fb.start);
515 } else {
516 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
517 if (!compressed_llb)
518 goto err_fb;
519
520 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
521 4096, 4096);
522 if (ret)
523 goto err_fb;
524
525 fbc->compressed_llb = compressed_llb;
526
527 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
528 fbc->compressed_fb.start,
529 U32_MAX));
530 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
531 fbc->compressed_llb->start,
532 U32_MAX));
533 intel_de_write(dev_priv, FBC_CFB_BASE,
534 dev_priv->dsm.start + fbc->compressed_fb.start);
535 intel_de_write(dev_priv, FBC_LL_BASE,
536 dev_priv->dsm.start + compressed_llb->start);
537 }
538
539 drm_dbg_kms(&dev_priv->drm,
540 "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
541 fbc->compressed_fb.size, fbc->threshold);
542
543 return 0;
544
545err_fb:
546 kfree(compressed_llb);
547 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
548err_llb:
549 if (drm_mm_initialized(&dev_priv->mm.stolen))
550 drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
551 return -ENOSPC;
552}
553
554static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
555{
556 struct intel_fbc *fbc = &dev_priv->fbc;
557
558 if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
559 return;
560
561 if (!drm_mm_node_allocated(&fbc->compressed_fb))
562 return;
563
564 if (fbc->compressed_llb) {
565 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
566 kfree(fbc->compressed_llb);
567 }
568
569 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
570}
571
572void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
573{
574 struct intel_fbc *fbc = &dev_priv->fbc;
575
576 if (!HAS_FBC(dev_priv))
577 return;
578
579 mutex_lock(&fbc->lock);
580 __intel_fbc_cleanup_cfb(dev_priv);
581 mutex_unlock(&fbc->lock);
582}
583
584static bool stride_is_valid(struct drm_i915_private *dev_priv,
585 u64 modifier, unsigned int stride)
586{
587 /* This should have been caught earlier. */
588 if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
589 return false;
590
591 /* Below are the additional FBC restrictions. */
592 if (stride < 512)
593 return false;
594
595 if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3)
596 return stride == 4096 || stride == 8192;
597
598 if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048)
599 return false;
600
601 /* Display WA #1105: skl,bxt,kbl,cfl,glk */
602 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
603 modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
604 return false;
605
606 if (stride > 16384)
607 return false;
608
609 return true;
610}
611
612static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
613 u32 pixel_format)
614{
615 switch (pixel_format) {
616 case DRM_FORMAT_XRGB8888:
617 case DRM_FORMAT_XBGR8888:
618 return true;
619 case DRM_FORMAT_XRGB1555:
620 case DRM_FORMAT_RGB565:
621 /* 16bpp not supported on gen2 */
622 if (DISPLAY_VER(dev_priv) == 2)
623 return false;
624 /* WaFbcOnly1to1Ratio:ctg */
625 if (IS_G4X(dev_priv))
626 return false;
627 return true;
628 default:
629 return false;
630 }
631}
632
633static bool rotation_is_valid(struct drm_i915_private *dev_priv,
634 u32 pixel_format, unsigned int rotation)
635{
636 if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
637 drm_rotation_90_or_270(rotation))
638 return false;
639 else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
640 rotation != DRM_MODE_ROTATE_0)
641 return false;
642
643 return true;
644}
645
646/*
647 * For some reason, the hardware tracking starts looking at whatever we
648 * programmed as the display plane base address register. It does not look at
649 * the X and Y offset registers. That's why we include the src x/y offsets
650 * instead of just looking at the plane size.
651 */
652static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
653{
654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
655 struct intel_fbc *fbc = &dev_priv->fbc;
656 unsigned int effective_w, effective_h, max_w, max_h;
657
658 if (DISPLAY_VER(dev_priv) >= 10) {
659 max_w = 5120;
660 max_h = 4096;
661 } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
662 max_w = 4096;
663 max_h = 4096;
664 } else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) {
665 max_w = 4096;
666 max_h = 2048;
667 } else {
668 max_w = 2048;
669 max_h = 1536;
670 }
671
672 intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
673 &effective_h);
674 effective_w += fbc->state_cache.plane.adjusted_x;
675 effective_h += fbc->state_cache.plane.adjusted_y;
676
677 return effective_w <= max_w && effective_h <= max_h;
678}
679
680static bool tiling_is_valid(struct drm_i915_private *dev_priv,
681 u64 modifier)
682{
683 switch (modifier) {
684 case DRM_FORMAT_MOD_LINEAR:
685 if (DISPLAY_VER(dev_priv) >= 9)
686 return true;
687 return false;
688 case I915_FORMAT_MOD_X_TILED:
689 case I915_FORMAT_MOD_Y_TILED:
690 return true;
691 default:
692 return false;
693 }
694}
695
696static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
697 const struct intel_crtc_state *crtc_state,
698 const struct intel_plane_state *plane_state)
699{
700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
701 struct intel_fbc *fbc = &dev_priv->fbc;
702 struct intel_fbc_state_cache *cache = &fbc->state_cache;
703 struct drm_framebuffer *fb = plane_state->hw.fb;
704
705 cache->plane.visible = plane_state->uapi.visible;
706 if (!cache->plane.visible)
707 return;
708
709 cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
710 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
711 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
712
713 cache->plane.rotation = plane_state->hw.rotation;
714 /*
715 * Src coordinates are already rotated by 270 degrees for
716 * the 90/270 degree plane rotation cases (to match the
717 * GTT mapping), hence no need to account for rotation here.
718 */
719 cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
720 cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
721 cache->plane.adjusted_x = plane_state->view.color_plane[0].x;
722 cache->plane.adjusted_y = plane_state->view.color_plane[0].y;
723
724 cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
725
726 cache->fb.format = fb->format;
727 cache->fb.modifier = fb->modifier;
728
729 /* FIXME is this correct? */
730 cache->fb.stride = plane_state->view.color_plane[0].stride;
731 if (drm_rotation_90_or_270(plane_state->hw.rotation))
732 cache->fb.stride *= fb->format->cpp[0];
733
734 /* FBC1 compression interval: arbitrary choice of 1 second */
735 cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
736
737 cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
738
739 drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
740 !plane_state->ggtt_vma->fence);
741
742 if (plane_state->flags & PLANE_HAS_FENCE &&
743 plane_state->ggtt_vma->fence)
744 cache->fence_id = plane_state->ggtt_vma->fence->id;
745 else
746 cache->fence_id = -1;
747
748 cache->psr2_active = crtc_state->has_psr2;
749}
750
751static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
752{
753 struct intel_fbc *fbc = &dev_priv->fbc;
754
755 return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
756 fbc->compressed_fb.size * fbc->threshold;
757}
758
759static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
760{
761 struct intel_fbc *fbc = &dev_priv->fbc;
762 struct intel_fbc_state_cache *cache = &fbc->state_cache;
763
764 if ((DISPLAY_VER(dev_priv) == 9) &&
765 cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
766 return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
767 else
768 return 0;
769}
770
771static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
772{
773 struct intel_fbc *fbc = &dev_priv->fbc;
774
775 return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
776}
777
778static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
779{
780 struct intel_fbc *fbc = &dev_priv->fbc;
781
782 if (intel_vgpu_active(dev_priv)) {
783 fbc->no_fbc_reason = "VGPU is active";
784 return false;
785 }
786
787 if (!dev_priv->params.enable_fbc) {
788 fbc->no_fbc_reason = "disabled per module param or by default";
789 return false;
790 }
791
792 if (fbc->underrun_detected) {
793 fbc->no_fbc_reason = "underrun detected";
794 return false;
795 }
796
797 return true;
798}
799
800static bool intel_fbc_can_activate(struct intel_crtc *crtc)
801{
802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
803 struct intel_fbc *fbc = &dev_priv->fbc;
804 struct intel_fbc_state_cache *cache = &fbc->state_cache;
805
806 if (!intel_fbc_can_enable(dev_priv))
807 return false;
808
809 if (!cache->plane.visible) {
810 fbc->no_fbc_reason = "primary plane not visible";
811 return false;
812 }
813
814 /* We don't need to use a state cache here since this information is
815 * global for all CRTC.
816 */
817 if (fbc->underrun_detected) {
818 fbc->no_fbc_reason = "underrun detected";
819 return false;
820 }
821
822 if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
823 fbc->no_fbc_reason = "incompatible mode";
824 return false;
825 }
826
827 if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
828 fbc->no_fbc_reason = "mode too large for compression";
829 return false;
830 }
831
832 /* The use of a CPU fence is one of two ways to detect writes by the
833 * CPU to the scanout and trigger updates to the FBC.
834 *
835 * The other method is by software tracking (see
836 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
837 * the current compressed buffer and recompress it.
838 *
839 * Note that is possible for a tiled surface to be unmappable (and
840 * so have no fence associated with it) due to aperture constraints
841 * at the time of pinning.
842 *
843 * FIXME with 90/270 degree rotation we should use the fence on
844 * the normal GTT view (the rotated view doesn't even have a
845 * fence). Would need changes to the FBC fence Y offset as well.
846 * For now this will effectively disable FBC with 90/270 degree
847 * rotation.
848 */
849 if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) {
850 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
851 return false;
852 }
853
854 if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
855 fbc->no_fbc_reason = "pixel format is invalid";
856 return false;
857 }
858
859 if (!rotation_is_valid(dev_priv, cache->fb.format->format,
860 cache->plane.rotation)) {
861 fbc->no_fbc_reason = "rotation unsupported";
862 return false;
863 }
864
865 if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
866 fbc->no_fbc_reason = "tiling unsupported";
867 return false;
868 }
869
870 if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
871 fbc->no_fbc_reason = "framebuffer stride not supported";
872 return false;
873 }
874
875 if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
876 cache->fb.format->has_alpha) {
877 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
878 return false;
879 }
880
881 /* WaFbcExceedCdClockThreshold:hsw,bdw */
882 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
883 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
884 fbc->no_fbc_reason = "pixel rate is too big";
885 return false;
886 }
887
888 /* It is possible for the required CFB size change without a
889 * crtc->disable + crtc->enable since it is possible to change the
890 * stride without triggering a full modeset. Since we try to
891 * over-allocate the CFB, there's a chance we may keep FBC enabled even
892 * if this happens, but if we exceed the current CFB size we'll have to
893 * disable FBC. Notice that it would be possible to disable FBC, wait
894 * for a frame, free the stolen node, then try to reenable FBC in case
895 * we didn't get any invalidate/deactivate calls, but this would require
896 * a lot of tracking just for a specific case. If we conclude it's an
897 * important case, we can implement it later. */
898 if (intel_fbc_cfb_size_changed(dev_priv)) {
899 fbc->no_fbc_reason = "CFB requirements changed";
900 return false;
901 }
902
903 /*
904 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
905 * having a Y offset that isn't divisible by 4 causes FIFO underrun
906 * and screen flicker.
907 */
908 if (DISPLAY_VER(dev_priv) >= 9 &&
909 (fbc->state_cache.plane.adjusted_y & 3)) {
910 fbc->no_fbc_reason = "plane Y offset is misaligned";
911 return false;
912 }
913
914 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
915 if (DISPLAY_VER(dev_priv) >= 11 &&
916 (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
917 fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
918 return false;
919 }
920
921 /*
922 * Tigerlake is not supporting FBC with PSR2.
923 * Recommendation is to keep this combination disabled
924 * Bspec: 50422 HSD: 14010260002
925 */
926 if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
927 fbc->no_fbc_reason = "not supported with PSR2";
928 return false;
929 }
930
931 return true;
932}
933
934static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
935 struct intel_fbc_reg_params *params)
936{
937 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
938 struct intel_fbc *fbc = &dev_priv->fbc;
939 struct intel_fbc_state_cache *cache = &fbc->state_cache;
940
941 /* Since all our fields are integer types, use memset here so the
942 * comparison function can rely on memcmp because the padding will be
943 * zero. */
944 memset(params, 0, sizeof(*params));
945
946 params->fence_id = cache->fence_id;
947 params->fence_y_offset = cache->fence_y_offset;
948
949 params->interval = cache->interval;
950
951 params->crtc.pipe = crtc->pipe;
952 params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
953
954 params->fb.format = cache->fb.format;
955 params->fb.modifier = cache->fb.modifier;
956 params->fb.stride = cache->fb.stride;
957
958 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
959
960 params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
961
962 params->plane_visible = cache->plane.visible;
963}
964
965static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
966{
967 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
968 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
969 const struct intel_fbc *fbc = &dev_priv->fbc;
970 const struct intel_fbc_state_cache *cache = &fbc->state_cache;
971 const struct intel_fbc_reg_params *params = &fbc->params;
972
973 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
974 return false;
975
976 if (!params->plane_visible)
977 return false;
978
979 if (!intel_fbc_can_activate(crtc))
980 return false;
981
982 if (params->fb.format != cache->fb.format)
983 return false;
984
985 if (params->fb.modifier != cache->fb.modifier)
986 return false;
987
988 if (params->fb.stride != cache->fb.stride)
989 return false;
990
991 if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
992 return false;
993
994 if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
995 return false;
996
997 return true;
998}
999
1000bool intel_fbc_pre_update(struct intel_atomic_state *state,
1001 struct intel_crtc *crtc)
1002{
1003 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1004 const struct intel_crtc_state *crtc_state =
1005 intel_atomic_get_new_crtc_state(state, crtc);
1006 const struct intel_plane_state *plane_state =
1007 intel_atomic_get_new_plane_state(state, plane);
1008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1009 struct intel_fbc *fbc = &dev_priv->fbc;
1010 const char *reason = "update pending";
1011 bool need_vblank_wait = false;
1012
1013 if (!plane->has_fbc || !plane_state)
1014 return need_vblank_wait;
1015
1016 mutex_lock(&fbc->lock);
1017
1018 if (fbc->crtc != crtc)
1019 goto unlock;
1020
1021 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1022 fbc->flip_pending = true;
1023
1024 if (!intel_fbc_can_flip_nuke(crtc_state)) {
1025 intel_fbc_deactivate(dev_priv, reason);
1026
1027 /*
1028 * Display WA #1198: glk+
1029 * Need an extra vblank wait between FBC disable and most plane
1030 * updates. Bspec says this is only needed for plane disable, but
1031 * that is not true. Touching most plane registers will cause the
1032 * corruption to appear. Also SKL/derivatives do not seem to be
1033 * affected.
1034 *
1035 * TODO: could optimize this a bit by sampling the frame
1036 * counter when we disable FBC (if it was already done earlier)
1037 * and skipping the extra vblank wait before the plane update
1038 * if at least one frame has already passed.
1039 */
1040 if (fbc->activated &&
1041 DISPLAY_VER(dev_priv) >= 10)
1042 need_vblank_wait = true;
1043 fbc->activated = false;
1044 }
1045unlock:
1046 mutex_unlock(&fbc->lock);
1047
1048 return need_vblank_wait;
1049}
1050
1051/**
1052 * __intel_fbc_disable - disable FBC
1053 * @dev_priv: i915 device instance
1054 *
1055 * This is the low level function that actually disables FBC. Callers should
1056 * grab the FBC lock.
1057 */
1058static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1059{
1060 struct intel_fbc *fbc = &dev_priv->fbc;
1061 struct intel_crtc *crtc = fbc->crtc;
1062
1063 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1064 drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
1065 drm_WARN_ON(&dev_priv->drm, fbc->active);
1066
1067 drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
1068 pipe_name(crtc->pipe));
1069
1070 __intel_fbc_cleanup_cfb(dev_priv);
1071
1072 fbc->crtc = NULL;
1073}
1074
1075static void __intel_fbc_post_update(struct intel_crtc *crtc)
1076{
1077 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1078 struct intel_fbc *fbc = &dev_priv->fbc;
1079
1080 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1081
1082 if (fbc->crtc != crtc)
1083 return;
1084
1085 fbc->flip_pending = false;
1086
1087 if (!dev_priv->params.enable_fbc) {
1088 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1089 __intel_fbc_disable(dev_priv);
1090
1091 return;
1092 }
1093
1094 intel_fbc_get_reg_params(crtc, &fbc->params);
1095
1096 if (!intel_fbc_can_activate(crtc))
1097 return;
1098
1099 if (!fbc->busy_bits)
1100 intel_fbc_hw_activate(dev_priv);
1101 else
1102 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1103}
1104
1105void intel_fbc_post_update(struct intel_atomic_state *state,
1106 struct intel_crtc *crtc)
1107{
1108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1109 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1110 const struct intel_plane_state *plane_state =
1111 intel_atomic_get_new_plane_state(state, plane);
1112 struct intel_fbc *fbc = &dev_priv->fbc;
1113
1114 if (!plane->has_fbc || !plane_state)
1115 return;
1116
1117 mutex_lock(&fbc->lock);
1118 __intel_fbc_post_update(crtc);
1119 mutex_unlock(&fbc->lock);
1120}
1121
1122static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1123{
1124 if (fbc->crtc)
1125 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1126 else
1127 return fbc->possible_framebuffer_bits;
1128}
1129
1130void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1131 unsigned int frontbuffer_bits,
1132 enum fb_op_origin origin)
1133{
1134 struct intel_fbc *fbc = &dev_priv->fbc;
1135
1136 if (!HAS_FBC(dev_priv))
1137 return;
1138
1139 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1140 return;
1141
1142 mutex_lock(&fbc->lock);
1143
1144 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1145
1146 if (fbc->crtc && fbc->busy_bits)
1147 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1148
1149 mutex_unlock(&fbc->lock);
1150}
1151
1152void intel_fbc_flush(struct drm_i915_private *dev_priv,
1153 unsigned int frontbuffer_bits, enum fb_op_origin origin)
1154{
1155 struct intel_fbc *fbc = &dev_priv->fbc;
1156
1157 if (!HAS_FBC(dev_priv))
1158 return;
1159
1160 /*
1161 * GTT tracking does not nuke the entire cfb
1162 * so don't clear busy_bits set for some other
1163 * reason.
1164 */
1165 if (origin == ORIGIN_GTT)
1166 return;
1167
1168 mutex_lock(&fbc->lock);
1169
1170 fbc->busy_bits &= ~frontbuffer_bits;
1171
1172 if (origin == ORIGIN_FLIP)
1173 goto out;
1174
1175 if (!fbc->busy_bits && fbc->crtc &&
1176 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1177 if (fbc->active)
1178 intel_fbc_recompress(dev_priv);
1179 else if (!fbc->flip_pending)
1180 __intel_fbc_post_update(fbc->crtc);
1181 }
1182
1183out:
1184 mutex_unlock(&fbc->lock);
1185}
1186
1187/**
1188 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1189 * @dev_priv: i915 device instance
1190 * @state: the atomic state structure
1191 *
1192 * This function looks at the proposed state for CRTCs and planes, then chooses
1193 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1194 * true.
1195 *
1196 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1197 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1198 */
1199void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1200 struct intel_atomic_state *state)
1201{
1202 struct intel_fbc *fbc = &dev_priv->fbc;
1203 struct intel_plane *plane;
1204 struct intel_plane_state *plane_state;
1205 bool crtc_chosen = false;
1206 int i;
1207
1208 mutex_lock(&fbc->lock);
1209
1210 /* Does this atomic commit involve the CRTC currently tied to FBC? */
1211 if (fbc->crtc &&
1212 !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1213 goto out;
1214
1215 if (!intel_fbc_can_enable(dev_priv))
1216 goto out;
1217
1218 /* Simply choose the first CRTC that is compatible and has a visible
1219 * plane. We could go for fancier schemes such as checking the plane
1220 * size, but this would just affect the few platforms that don't tie FBC
1221 * to pipe or plane A. */
1222 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1223 struct intel_crtc_state *crtc_state;
1224 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1225
1226 if (!plane->has_fbc)
1227 continue;
1228
1229 if (!plane_state->uapi.visible)
1230 continue;
1231
1232 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1233
1234 crtc_state->enable_fbc = true;
1235 crtc_chosen = true;
1236 break;
1237 }
1238
1239 if (!crtc_chosen)
1240 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1241
1242out:
1243 mutex_unlock(&fbc->lock);
1244}
1245
1246/**
1247 * intel_fbc_enable: tries to enable FBC on the CRTC
1248 * @crtc: the CRTC
1249 * @state: corresponding &drm_crtc_state for @crtc
1250 *
1251 * This function checks if the given CRTC was chosen for FBC, then enables it if
1252 * possible. Notice that it doesn't activate FBC. It is valid to call
1253 * intel_fbc_enable multiple times for the same pipe without an
1254 * intel_fbc_disable in the middle, as long as it is deactivated.
1255 */
1256void intel_fbc_enable(struct intel_atomic_state *state,
1257 struct intel_crtc *crtc)
1258{
1259 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1260 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1261 const struct intel_crtc_state *crtc_state =
1262 intel_atomic_get_new_crtc_state(state, crtc);
1263 const struct intel_plane_state *plane_state =
1264 intel_atomic_get_new_plane_state(state, plane);
1265 struct intel_fbc *fbc = &dev_priv->fbc;
1266 struct intel_fbc_state_cache *cache = &fbc->state_cache;
1267
1268 if (!plane->has_fbc || !plane_state)
1269 return;
1270
1271 mutex_lock(&fbc->lock);
1272
1273 if (fbc->crtc) {
1274 if (fbc->crtc != crtc ||
1275 (!intel_fbc_cfb_size_changed(dev_priv) &&
1276 !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
1277 goto out;
1278
1279 __intel_fbc_disable(dev_priv);
1280 }
1281
1282 drm_WARN_ON(&dev_priv->drm, fbc->active);
1283
1284 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1285
1286 /* FIXME crtc_state->enable_fbc lies :( */
1287 if (!cache->plane.visible)
1288 goto out;
1289
1290 if (intel_fbc_alloc_cfb(dev_priv,
1291 intel_fbc_calculate_cfb_size(dev_priv, cache),
1292 plane_state->hw.fb->format->cpp[0])) {
1293 cache->plane.visible = false;
1294 fbc->no_fbc_reason = "not enough stolen memory";
1295 goto out;
1296 }
1297
1298 cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
1299
1300 drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1301 pipe_name(crtc->pipe));
1302 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1303
1304 fbc->crtc = crtc;
1305out:
1306 mutex_unlock(&fbc->lock);
1307}
1308
1309/**
1310 * intel_fbc_disable - disable FBC if it's associated with crtc
1311 * @crtc: the CRTC
1312 *
1313 * This function disables FBC if it's associated with the provided CRTC.
1314 */
1315void intel_fbc_disable(struct intel_crtc *crtc)
1316{
1317 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1318 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1319 struct intel_fbc *fbc = &dev_priv->fbc;
1320
1321 if (!plane->has_fbc)
1322 return;
1323
1324 mutex_lock(&fbc->lock);
1325 if (fbc->crtc == crtc)
1326 __intel_fbc_disable(dev_priv);
1327 mutex_unlock(&fbc->lock);
1328}
1329
1330/**
1331 * intel_fbc_global_disable - globally disable FBC
1332 * @dev_priv: i915 device instance
1333 *
1334 * This function disables FBC regardless of which CRTC is associated with it.
1335 */
1336void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1337{
1338 struct intel_fbc *fbc = &dev_priv->fbc;
1339
1340 if (!HAS_FBC(dev_priv))
1341 return;
1342
1343 mutex_lock(&fbc->lock);
1344 if (fbc->crtc) {
1345 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1346 __intel_fbc_disable(dev_priv);
1347 }
1348 mutex_unlock(&fbc->lock);
1349}
1350
1351static void intel_fbc_underrun_work_fn(struct work_struct *work)
1352{
1353 struct drm_i915_private *dev_priv =
1354 container_of(work, struct drm_i915_private, fbc.underrun_work);
1355 struct intel_fbc *fbc = &dev_priv->fbc;
1356
1357 mutex_lock(&fbc->lock);
1358
1359 /* Maybe we were scheduled twice. */
1360 if (fbc->underrun_detected || !fbc->crtc)
1361 goto out;
1362
1363 drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1364 fbc->underrun_detected = true;
1365
1366 intel_fbc_deactivate(dev_priv, "FIFO underrun");
1367out:
1368 mutex_unlock(&fbc->lock);
1369}
1370
1371/*
1372 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1373 * @dev_priv: i915 device instance
1374 *
1375 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1376 * want to re-enable FBC after an underrun to increase test coverage.
1377 */
1378int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1379{
1380 int ret;
1381
1382 cancel_work_sync(&dev_priv->fbc.underrun_work);
1383
1384 ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1385 if (ret)
1386 return ret;
1387
1388 if (dev_priv->fbc.underrun_detected) {
1389 drm_dbg_kms(&dev_priv->drm,
1390 "Re-allowing FBC after fifo underrun\n");
1391 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1392 }
1393
1394 dev_priv->fbc.underrun_detected = false;
1395 mutex_unlock(&dev_priv->fbc.lock);
1396
1397 return 0;
1398}
1399
1400/**
1401 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1402 * @dev_priv: i915 device instance
1403 *
1404 * Without FBC, most underruns are harmless and don't really cause too many
1405 * problems, except for an annoying message on dmesg. With FBC, underruns can
1406 * become black screens or even worse, especially when paired with bad
1407 * watermarks. So in order for us to be on the safe side, completely disable FBC
1408 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1409 * already suggests that watermarks may be bad, so try to be as safe as
1410 * possible.
1411 *
1412 * This function is called from the IRQ handler.
1413 */
1414void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1415{
1416 struct intel_fbc *fbc = &dev_priv->fbc;
1417
1418 if (!HAS_FBC(dev_priv))
1419 return;
1420
1421 /* There's no guarantee that underrun_detected won't be set to true
1422 * right after this check and before the work is scheduled, but that's
1423 * not a problem since we'll check it again under the work function
1424 * while FBC is locked. This check here is just to prevent us from
1425 * unnecessarily scheduling the work, and it relies on the fact that we
1426 * never switch underrun_detect back to false after it's true. */
1427 if (READ_ONCE(fbc->underrun_detected))
1428 return;
1429
1430 schedule_work(&fbc->underrun_work);
1431}
1432
1433/*
1434 * The DDX driver changes its behavior depending on the value it reads from
1435 * i915.enable_fbc, so sanitize it by translating the default value into either
1436 * 0 or 1 in order to allow it to know what's going on.
1437 *
1438 * Notice that this is done at driver initialization and we still allow user
1439 * space to change the value during runtime without sanitizing it again. IGT
1440 * relies on being able to change i915.enable_fbc at runtime.
1441 */
1442static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1443{
1444 if (dev_priv->params.enable_fbc >= 0)
1445 return !!dev_priv->params.enable_fbc;
1446
1447 if (!HAS_FBC(dev_priv))
1448 return 0;
1449
1450 if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
1451 return 1;
1452
1453 return 0;
1454}
1455
1456static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1457{
1458 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1459 if (intel_vtd_active() &&
1460 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1461 drm_info(&dev_priv->drm,
1462 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1463 return true;
1464 }
1465
1466 return false;
1467}
1468
1469/**
1470 * intel_fbc_init - Initialize FBC
1471 * @dev_priv: the i915 device
1472 *
1473 * This function might be called during PM init process.
1474 */
1475void intel_fbc_init(struct drm_i915_private *dev_priv)
1476{
1477 struct intel_fbc *fbc = &dev_priv->fbc;
1478
1479 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1480 mutex_init(&fbc->lock);
1481 fbc->active = false;
1482
1483 if (!drm_mm_initialized(&dev_priv->mm.stolen))
1484 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1485
1486 if (need_fbc_vtd_wa(dev_priv))
1487 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1488
1489 dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1490 drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1491 dev_priv->params.enable_fbc);
1492
1493 if (!HAS_FBC(dev_priv)) {
1494 fbc->no_fbc_reason = "unsupported by this chipset";
1495 return;
1496 }
1497
1498 /* We still don't have any sort of hardware state readout for FBC, so
1499 * deactivate it in case the BIOS activated it to make sure software
1500 * matches the hardware state. */
1501 if (intel_fbc_hw_is_active(dev_priv))
1502 intel_fbc_hw_deactivate(dev_priv);
1503}
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
30 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
34 *
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
39 */
40
41#include <linux/string_helpers.h>
42
43#include <drm/drm_blend.h>
44#include <drm/drm_fourcc.h>
45
46#include "i915_drv.h"
47#include "i915_reg.h"
48#include "i915_utils.h"
49#include "i915_vgpu.h"
50#include "i915_vma.h"
51#include "intel_cdclk.h"
52#include "intel_de.h"
53#include "intel_display_device.h"
54#include "intel_display_trace.h"
55#include "intel_display_types.h"
56#include "intel_fbc.h"
57#include "intel_frontbuffer.h"
58
59#define for_each_fbc_id(__dev_priv, __fbc_id) \
60 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
61 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
62
63#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
64 for_each_fbc_id((__dev_priv), (__fbc_id)) \
65 for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
66
67struct intel_fbc_funcs {
68 void (*activate)(struct intel_fbc *fbc);
69 void (*deactivate)(struct intel_fbc *fbc);
70 bool (*is_active)(struct intel_fbc *fbc);
71 bool (*is_compressing)(struct intel_fbc *fbc);
72 void (*nuke)(struct intel_fbc *fbc);
73 void (*program_cfb)(struct intel_fbc *fbc);
74 void (*set_false_color)(struct intel_fbc *fbc, bool enable);
75};
76
77struct intel_fbc_state {
78 struct intel_plane *plane;
79 unsigned int cfb_stride;
80 unsigned int cfb_size;
81 unsigned int fence_y_offset;
82 u16 override_cfb_stride;
83 u16 interval;
84 s8 fence_id;
85};
86
87struct intel_fbc {
88 struct drm_i915_private *i915;
89 const struct intel_fbc_funcs *funcs;
90
91 /*
92 * This is always the inner lock when overlapping with
93 * struct_mutex and it's the outer lock when overlapping
94 * with stolen_lock.
95 */
96 struct mutex lock;
97 unsigned int busy_bits;
98
99 struct i915_stolen_fb compressed_fb, compressed_llb;
100
101 enum intel_fbc_id id;
102
103 u8 limit;
104
105 bool false_color;
106
107 bool active;
108 bool activated;
109 bool flip_pending;
110
111 bool underrun_detected;
112 struct work_struct underrun_work;
113
114 /*
115 * This structure contains everything that's relevant to program the
116 * hardware registers. When we want to figure out if we need to disable
117 * and re-enable FBC for a new configuration we just check if there's
118 * something different in the struct. The genx_fbc_activate functions
119 * are supposed to read from it in order to program the registers.
120 */
121 struct intel_fbc_state state;
122 const char *no_fbc_reason;
123};
124
125/* plane stride in pixels */
126static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
127{
128 const struct drm_framebuffer *fb = plane_state->hw.fb;
129 unsigned int stride;
130
131 stride = plane_state->view.color_plane[0].mapping_stride;
132 if (!drm_rotation_90_or_270(plane_state->hw.rotation))
133 stride /= fb->format->cpp[0];
134
135 return stride;
136}
137
138/* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
139static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
140{
141 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
142
143 return intel_fbc_plane_stride(plane_state) * cpp;
144}
145
146/* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
147static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state)
148{
149 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
150 unsigned int limit = 4; /* 1:4 compression limit is the worst case */
151 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
152 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
153 unsigned int height = 4; /* FBC segment is 4 lines */
154 unsigned int stride;
155
156 /* minimum segment stride we can use */
157 stride = width * cpp * height / limit;
158
159 /*
160 * Wa_16011863758: icl+
161 * Avoid some hardware segment address miscalculation.
162 */
163 if (DISPLAY_VER(i915) >= 11)
164 stride += 64;
165
166 /*
167 * At least some of the platforms require each 4 line segment to
168 * be 512 byte aligned. Just do it always for simplicity.
169 */
170 stride = ALIGN(stride, 512);
171
172 /* convert back to single line equivalent with 1:1 compression limit */
173 return stride * limit / height;
174}
175
176/* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
177static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
178{
179 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
180 unsigned int stride = _intel_fbc_cfb_stride(plane_state);
181
182 /*
183 * At least some of the platforms require each 4 line segment to
184 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
185 * that regardless of the compression limit we choose later.
186 */
187 if (DISPLAY_VER(i915) >= 9)
188 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state));
189 else
190 return stride;
191}
192
193static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
194{
195 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
196 int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
197
198 if (DISPLAY_VER(i915) == 7)
199 lines = min(lines, 2048);
200 else if (DISPLAY_VER(i915) >= 8)
201 lines = min(lines, 2560);
202
203 return lines * intel_fbc_cfb_stride(plane_state);
204}
205
206static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
207{
208 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
209 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
210 unsigned int stride = _intel_fbc_cfb_stride(plane_state);
211 const struct drm_framebuffer *fb = plane_state->hw.fb;
212
213 /*
214 * Override stride in 64 byte units per 4 line segment.
215 *
216 * Gen9 hw miscalculates cfb stride for linear as
217 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
218 * we always need to use the override there.
219 */
220 if (stride != stride_aligned ||
221 (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
222 return stride_aligned * 4 / 64;
223
224 return 0;
225}
226
227static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
228{
229 const struct intel_fbc_state *fbc_state = &fbc->state;
230 struct drm_i915_private *i915 = fbc->i915;
231 unsigned int cfb_stride;
232 u32 fbc_ctl;
233
234 cfb_stride = fbc_state->cfb_stride / fbc->limit;
235
236 /* FBC_CTL wants 32B or 64B units */
237 if (DISPLAY_VER(i915) == 2)
238 cfb_stride = (cfb_stride / 32) - 1;
239 else
240 cfb_stride = (cfb_stride / 64) - 1;
241
242 fbc_ctl = FBC_CTL_PERIODIC |
243 FBC_CTL_INTERVAL(fbc_state->interval) |
244 FBC_CTL_STRIDE(cfb_stride);
245
246 if (IS_I945GM(i915))
247 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
248
249 if (fbc_state->fence_id >= 0)
250 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
251
252 return fbc_ctl;
253}
254
255static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
256{
257 const struct intel_fbc_state *fbc_state = &fbc->state;
258 u32 fbc_ctl2;
259
260 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
261 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
262
263 if (fbc_state->fence_id >= 0)
264 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
265
266 return fbc_ctl2;
267}
268
269static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
270{
271 struct drm_i915_private *i915 = fbc->i915;
272 u32 fbc_ctl;
273
274 /* Disable compression */
275 fbc_ctl = intel_de_read(i915, FBC_CONTROL);
276 if ((fbc_ctl & FBC_CTL_EN) == 0)
277 return;
278
279 fbc_ctl &= ~FBC_CTL_EN;
280 intel_de_write(i915, FBC_CONTROL, fbc_ctl);
281
282 /* Wait for compressing bit to clear */
283 if (intel_de_wait_for_clear(i915, FBC_STATUS,
284 FBC_STAT_COMPRESSING, 10)) {
285 drm_dbg_kms(&i915->drm, "FBC idle timed out\n");
286 return;
287 }
288}
289
290static void i8xx_fbc_activate(struct intel_fbc *fbc)
291{
292 const struct intel_fbc_state *fbc_state = &fbc->state;
293 struct drm_i915_private *i915 = fbc->i915;
294 int i;
295
296 /* Clear old tags */
297 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
298 intel_de_write(i915, FBC_TAG(i), 0);
299
300 if (DISPLAY_VER(i915) == 4) {
301 intel_de_write(i915, FBC_CONTROL2,
302 i965_fbc_ctl2(fbc));
303 intel_de_write(i915, FBC_FENCE_OFF,
304 fbc_state->fence_y_offset);
305 }
306
307 intel_de_write(i915, FBC_CONTROL,
308 FBC_CTL_EN | i8xx_fbc_ctl(fbc));
309}
310
311static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
312{
313 return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN;
314}
315
316static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
317{
318 return intel_de_read(fbc->i915, FBC_STATUS) &
319 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
320}
321
322static void i8xx_fbc_nuke(struct intel_fbc *fbc)
323{
324 struct intel_fbc_state *fbc_state = &fbc->state;
325 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
326 struct drm_i915_private *dev_priv = fbc->i915;
327
328 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
329 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
330}
331
332static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
333{
334 struct drm_i915_private *i915 = fbc->i915;
335
336 drm_WARN_ON(&i915->drm,
337 range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
338 i915_gem_stolen_node_offset(&fbc->compressed_fb),
339 U32_MAX));
340 drm_WARN_ON(&i915->drm,
341 range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
342 i915_gem_stolen_node_offset(&fbc->compressed_llb),
343 U32_MAX));
344 intel_de_write(i915, FBC_CFB_BASE,
345 i915_gem_stolen_node_address(i915, &fbc->compressed_fb));
346 intel_de_write(i915, FBC_LL_BASE,
347 i915_gem_stolen_node_address(i915, &fbc->compressed_llb));
348}
349
350static const struct intel_fbc_funcs i8xx_fbc_funcs = {
351 .activate = i8xx_fbc_activate,
352 .deactivate = i8xx_fbc_deactivate,
353 .is_active = i8xx_fbc_is_active,
354 .is_compressing = i8xx_fbc_is_compressing,
355 .nuke = i8xx_fbc_nuke,
356 .program_cfb = i8xx_fbc_program_cfb,
357};
358
359static void i965_fbc_nuke(struct intel_fbc *fbc)
360{
361 struct intel_fbc_state *fbc_state = &fbc->state;
362 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
363 struct drm_i915_private *dev_priv = fbc->i915;
364
365 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
366 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
367}
368
369static const struct intel_fbc_funcs i965_fbc_funcs = {
370 .activate = i8xx_fbc_activate,
371 .deactivate = i8xx_fbc_deactivate,
372 .is_active = i8xx_fbc_is_active,
373 .is_compressing = i8xx_fbc_is_compressing,
374 .nuke = i965_fbc_nuke,
375 .program_cfb = i8xx_fbc_program_cfb,
376};
377
378static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
379{
380 switch (fbc->limit) {
381 default:
382 MISSING_CASE(fbc->limit);
383 fallthrough;
384 case 1:
385 return DPFC_CTL_LIMIT_1X;
386 case 2:
387 return DPFC_CTL_LIMIT_2X;
388 case 4:
389 return DPFC_CTL_LIMIT_4X;
390 }
391}
392
393static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
394{
395 const struct intel_fbc_state *fbc_state = &fbc->state;
396 struct drm_i915_private *i915 = fbc->i915;
397 u32 dpfc_ctl;
398
399 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
400 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
401
402 if (IS_G4X(i915))
403 dpfc_ctl |= DPFC_CTL_SR_EN;
404
405 if (fbc_state->fence_id >= 0) {
406 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
407
408 if (DISPLAY_VER(i915) < 6)
409 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
410 }
411
412 return dpfc_ctl;
413}
414
415static void g4x_fbc_activate(struct intel_fbc *fbc)
416{
417 const struct intel_fbc_state *fbc_state = &fbc->state;
418 struct drm_i915_private *i915 = fbc->i915;
419
420 intel_de_write(i915, DPFC_FENCE_YOFF,
421 fbc_state->fence_y_offset);
422
423 intel_de_write(i915, DPFC_CONTROL,
424 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
425}
426
427static void g4x_fbc_deactivate(struct intel_fbc *fbc)
428{
429 struct drm_i915_private *i915 = fbc->i915;
430 u32 dpfc_ctl;
431
432 /* Disable compression */
433 dpfc_ctl = intel_de_read(i915, DPFC_CONTROL);
434 if (dpfc_ctl & DPFC_CTL_EN) {
435 dpfc_ctl &= ~DPFC_CTL_EN;
436 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl);
437 }
438}
439
440static bool g4x_fbc_is_active(struct intel_fbc *fbc)
441{
442 return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN;
443}
444
445static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
446{
447 return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
448}
449
450static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
451{
452 struct drm_i915_private *i915 = fbc->i915;
453
454 intel_de_write(i915, DPFC_CB_BASE,
455 i915_gem_stolen_node_offset(&fbc->compressed_fb));
456}
457
458static const struct intel_fbc_funcs g4x_fbc_funcs = {
459 .activate = g4x_fbc_activate,
460 .deactivate = g4x_fbc_deactivate,
461 .is_active = g4x_fbc_is_active,
462 .is_compressing = g4x_fbc_is_compressing,
463 .nuke = i965_fbc_nuke,
464 .program_cfb = g4x_fbc_program_cfb,
465};
466
467static void ilk_fbc_activate(struct intel_fbc *fbc)
468{
469 struct intel_fbc_state *fbc_state = &fbc->state;
470 struct drm_i915_private *i915 = fbc->i915;
471
472 intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
473 fbc_state->fence_y_offset);
474
475 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
476 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
477}
478
479static void ilk_fbc_deactivate(struct intel_fbc *fbc)
480{
481 struct drm_i915_private *i915 = fbc->i915;
482 u32 dpfc_ctl;
483
484 /* Disable compression */
485 dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
486 if (dpfc_ctl & DPFC_CTL_EN) {
487 dpfc_ctl &= ~DPFC_CTL_EN;
488 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
489 }
490}
491
492static bool ilk_fbc_is_active(struct intel_fbc *fbc)
493{
494 return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
495}
496
497static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
498{
499 return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
500}
501
502static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
503{
504 struct drm_i915_private *i915 = fbc->i915;
505
506 intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
507 i915_gem_stolen_node_offset(&fbc->compressed_fb));
508}
509
510static const struct intel_fbc_funcs ilk_fbc_funcs = {
511 .activate = ilk_fbc_activate,
512 .deactivate = ilk_fbc_deactivate,
513 .is_active = ilk_fbc_is_active,
514 .is_compressing = ilk_fbc_is_compressing,
515 .nuke = i965_fbc_nuke,
516 .program_cfb = ilk_fbc_program_cfb,
517};
518
519static void snb_fbc_program_fence(struct intel_fbc *fbc)
520{
521 const struct intel_fbc_state *fbc_state = &fbc->state;
522 struct drm_i915_private *i915 = fbc->i915;
523 u32 ctl = 0;
524
525 if (fbc_state->fence_id >= 0)
526 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
527
528 intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
529 intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
530}
531
532static void snb_fbc_activate(struct intel_fbc *fbc)
533{
534 snb_fbc_program_fence(fbc);
535
536 ilk_fbc_activate(fbc);
537}
538
539static void snb_fbc_nuke(struct intel_fbc *fbc)
540{
541 struct drm_i915_private *i915 = fbc->i915;
542
543 intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
544 intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
545}
546
547static const struct intel_fbc_funcs snb_fbc_funcs = {
548 .activate = snb_fbc_activate,
549 .deactivate = ilk_fbc_deactivate,
550 .is_active = ilk_fbc_is_active,
551 .is_compressing = ilk_fbc_is_compressing,
552 .nuke = snb_fbc_nuke,
553 .program_cfb = ilk_fbc_program_cfb,
554};
555
556static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
557{
558 const struct intel_fbc_state *fbc_state = &fbc->state;
559 struct drm_i915_private *i915 = fbc->i915;
560 u32 val = 0;
561
562 if (fbc_state->override_cfb_stride)
563 val |= FBC_STRIDE_OVERRIDE |
564 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
565
566 intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
567}
568
569static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
570{
571 const struct intel_fbc_state *fbc_state = &fbc->state;
572 struct drm_i915_private *i915 = fbc->i915;
573 u32 val = 0;
574
575 /* Display WA #0529: skl, kbl, bxt. */
576 if (fbc_state->override_cfb_stride)
577 val |= CHICKEN_FBC_STRIDE_OVERRIDE |
578 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
579
580 intel_de_rmw(i915, CHICKEN_MISC_4,
581 CHICKEN_FBC_STRIDE_OVERRIDE |
582 CHICKEN_FBC_STRIDE_MASK, val);
583}
584
585static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
586{
587 const struct intel_fbc_state *fbc_state = &fbc->state;
588 struct drm_i915_private *i915 = fbc->i915;
589 u32 dpfc_ctl;
590
591 dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
592
593 if (IS_IVYBRIDGE(i915))
594 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
595
596 if (DISPLAY_VER(i915) >= 20)
597 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id);
598
599 if (fbc_state->fence_id >= 0)
600 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
601
602 if (fbc->false_color)
603 dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
604
605 return dpfc_ctl;
606}
607
608static void ivb_fbc_activate(struct intel_fbc *fbc)
609{
610 struct drm_i915_private *i915 = fbc->i915;
611 u32 dpfc_ctl;
612
613 if (DISPLAY_VER(i915) >= 10)
614 glk_fbc_program_cfb_stride(fbc);
615 else if (DISPLAY_VER(i915) == 9)
616 skl_fbc_program_cfb_stride(fbc);
617
618 if (intel_gt_support_legacy_fencing(to_gt(i915)))
619 snb_fbc_program_fence(fbc);
620
621 /* wa_14019417088 Alternative WA*/
622 dpfc_ctl = ivb_dpfc_ctl(fbc);
623 if (DISPLAY_VER(i915) >= 20)
624 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
625
626 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
627 DPFC_CTL_EN | dpfc_ctl);
628}
629
630static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
631{
632 return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
633}
634
635static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
636 bool enable)
637{
638 intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
639 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
640}
641
642static const struct intel_fbc_funcs ivb_fbc_funcs = {
643 .activate = ivb_fbc_activate,
644 .deactivate = ilk_fbc_deactivate,
645 .is_active = ilk_fbc_is_active,
646 .is_compressing = ivb_fbc_is_compressing,
647 .nuke = snb_fbc_nuke,
648 .program_cfb = ilk_fbc_program_cfb,
649 .set_false_color = ivb_fbc_set_false_color,
650};
651
652static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
653{
654 return fbc->funcs->is_active(fbc);
655}
656
657static void intel_fbc_hw_activate(struct intel_fbc *fbc)
658{
659 trace_intel_fbc_activate(fbc->state.plane);
660
661 fbc->active = true;
662 fbc->activated = true;
663
664 fbc->funcs->activate(fbc);
665}
666
667static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
668{
669 trace_intel_fbc_deactivate(fbc->state.plane);
670
671 fbc->active = false;
672
673 fbc->funcs->deactivate(fbc);
674}
675
676static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
677{
678 return fbc->funcs->is_compressing(fbc);
679}
680
681static void intel_fbc_nuke(struct intel_fbc *fbc)
682{
683 struct drm_i915_private *i915 = fbc->i915;
684
685 lockdep_assert_held(&fbc->lock);
686 drm_WARN_ON(&i915->drm, fbc->flip_pending);
687
688 trace_intel_fbc_nuke(fbc->state.plane);
689
690 fbc->funcs->nuke(fbc);
691}
692
693static void intel_fbc_activate(struct intel_fbc *fbc)
694{
695 lockdep_assert_held(&fbc->lock);
696
697 intel_fbc_hw_activate(fbc);
698 intel_fbc_nuke(fbc);
699
700 fbc->no_fbc_reason = NULL;
701}
702
703static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
704{
705 lockdep_assert_held(&fbc->lock);
706
707 if (fbc->active)
708 intel_fbc_hw_deactivate(fbc);
709
710 fbc->no_fbc_reason = reason;
711}
712
713static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
714{
715 if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
716 return BIT_ULL(28);
717 else
718 return BIT_ULL(32);
719}
720
721static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
722{
723 u64 end;
724
725 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
726 * reserved range size, so it always assumes the maximum (8mb) is used.
727 * If we enable FBC using a CFB on that memory range we'll get FIFO
728 * underruns, even if that range is not reserved by the BIOS. */
729 if (IS_BROADWELL(i915) ||
730 (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)))
731 end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024;
732 else
733 end = U64_MAX;
734
735 return min(end, intel_fbc_cfb_base_max(i915));
736}
737
738static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
739{
740 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
741}
742
743static int intel_fbc_max_limit(struct drm_i915_private *i915)
744{
745 /* WaFbcOnly1to1Ratio:ctg */
746 if (IS_G4X(i915))
747 return 1;
748
749 /*
750 * FBC2 can only do 1:1, 1:2, 1:4, we limit
751 * FBC1 to the same out of convenience.
752 */
753 return 4;
754}
755
756static int find_compression_limit(struct intel_fbc *fbc,
757 unsigned int size, int min_limit)
758{
759 struct drm_i915_private *i915 = fbc->i915;
760 u64 end = intel_fbc_stolen_end(i915);
761 int ret, limit = min_limit;
762
763 size /= limit;
764
765 /* Try to over-allocate to reduce reallocations and fragmentation. */
766 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
767 size <<= 1, 4096, 0, end);
768 if (ret == 0)
769 return limit;
770
771 for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) {
772 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
773 size >>= 1, 4096, 0, end);
774 if (ret == 0)
775 return limit;
776 }
777
778 return 0;
779}
780
781static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
782 unsigned int size, int min_limit)
783{
784 struct drm_i915_private *i915 = fbc->i915;
785 int ret;
786
787 drm_WARN_ON(&i915->drm,
788 i915_gem_stolen_node_allocated(&fbc->compressed_fb));
789 drm_WARN_ON(&i915->drm,
790 i915_gem_stolen_node_allocated(&fbc->compressed_llb));
791
792 if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
793 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
794 4096, 4096);
795 if (ret)
796 goto err;
797 }
798
799 ret = find_compression_limit(fbc, size, min_limit);
800 if (!ret)
801 goto err_llb;
802 else if (ret > min_limit)
803 drm_info_once(&i915->drm,
804 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
805
806 fbc->limit = ret;
807
808 drm_dbg_kms(&i915->drm,
809 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
810 i915_gem_stolen_node_size(&fbc->compressed_fb), fbc->limit);
811 return 0;
812
813err_llb:
814 if (i915_gem_stolen_node_allocated(&fbc->compressed_llb))
815 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
816err:
817 if (i915_gem_stolen_initialized(i915))
818 drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
819 return -ENOSPC;
820}
821
822static void intel_fbc_program_cfb(struct intel_fbc *fbc)
823{
824 fbc->funcs->program_cfb(fbc);
825}
826
827static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
828{
829 /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */
830 if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
831 intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
832 DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
833}
834
835static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
836{
837 struct drm_i915_private *i915 = fbc->i915;
838
839 if (WARN_ON(intel_fbc_hw_is_active(fbc)))
840 return;
841
842 if (i915_gem_stolen_node_allocated(&fbc->compressed_llb))
843 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
844 if (i915_gem_stolen_node_allocated(&fbc->compressed_fb))
845 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
846}
847
848void intel_fbc_cleanup(struct drm_i915_private *i915)
849{
850 struct intel_fbc *fbc;
851 enum intel_fbc_id fbc_id;
852
853 for_each_intel_fbc(i915, fbc, fbc_id) {
854 mutex_lock(&fbc->lock);
855 __intel_fbc_cleanup_cfb(fbc);
856 mutex_unlock(&fbc->lock);
857
858 kfree(fbc);
859 }
860}
861
862static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
863{
864 const struct drm_framebuffer *fb = plane_state->hw.fb;
865 unsigned int stride = intel_fbc_plane_stride(plane_state) *
866 fb->format->cpp[0];
867
868 return stride == 4096 || stride == 8192;
869}
870
871static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
872{
873 const struct drm_framebuffer *fb = plane_state->hw.fb;
874 unsigned int stride = intel_fbc_plane_stride(plane_state) *
875 fb->format->cpp[0];
876
877 return stride >= 2048 && stride <= 16384;
878}
879
880static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
881{
882 return true;
883}
884
885static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
886{
887 const struct drm_framebuffer *fb = plane_state->hw.fb;
888 unsigned int stride = intel_fbc_plane_stride(plane_state) *
889 fb->format->cpp[0];
890
891 /* Display WA #1105: skl,bxt,kbl,cfl,glk */
892 if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
893 return false;
894
895 return true;
896}
897
898static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
899{
900 return true;
901}
902
903static bool stride_is_valid(const struct intel_plane_state *plane_state)
904{
905 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
906
907 if (DISPLAY_VER(i915) >= 11)
908 return icl_fbc_stride_is_valid(plane_state);
909 else if (DISPLAY_VER(i915) >= 9)
910 return skl_fbc_stride_is_valid(plane_state);
911 else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
912 return g4x_fbc_stride_is_valid(plane_state);
913 else if (DISPLAY_VER(i915) == 4)
914 return i965_fbc_stride_is_valid(plane_state);
915 else
916 return i8xx_fbc_stride_is_valid(plane_state);
917}
918
919static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
920{
921 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
922 const struct drm_framebuffer *fb = plane_state->hw.fb;
923
924 switch (fb->format->format) {
925 case DRM_FORMAT_XRGB8888:
926 case DRM_FORMAT_XBGR8888:
927 return true;
928 case DRM_FORMAT_XRGB1555:
929 case DRM_FORMAT_RGB565:
930 /* 16bpp not supported on gen2 */
931 if (DISPLAY_VER(i915) == 2)
932 return false;
933 return true;
934 default:
935 return false;
936 }
937}
938
939static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
940{
941 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
942 const struct drm_framebuffer *fb = plane_state->hw.fb;
943
944 switch (fb->format->format) {
945 case DRM_FORMAT_XRGB8888:
946 case DRM_FORMAT_XBGR8888:
947 return true;
948 case DRM_FORMAT_RGB565:
949 /* WaFbcOnly1to1Ratio:ctg */
950 if (IS_G4X(i915))
951 return false;
952 return true;
953 default:
954 return false;
955 }
956}
957
958static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
959{
960 const struct drm_framebuffer *fb = plane_state->hw.fb;
961
962 switch (fb->format->format) {
963 case DRM_FORMAT_XRGB8888:
964 case DRM_FORMAT_XBGR8888:
965 case DRM_FORMAT_ARGB8888:
966 case DRM_FORMAT_ABGR8888:
967 case DRM_FORMAT_RGB565:
968 return true;
969 default:
970 return false;
971 }
972}
973
974static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
975{
976 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
977
978 if (DISPLAY_VER(i915) >= 20)
979 return lnl_fbc_pixel_format_is_valid(plane_state);
980 else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
981 return g4x_fbc_pixel_format_is_valid(plane_state);
982 else
983 return i8xx_fbc_pixel_format_is_valid(plane_state);
984}
985
986static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
987{
988 return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
989}
990
991static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
992{
993 return true;
994}
995
996static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
997{
998 const struct drm_framebuffer *fb = plane_state->hw.fb;
999 unsigned int rotation = plane_state->hw.rotation;
1000
1001 if (fb->format->format == DRM_FORMAT_RGB565 &&
1002 drm_rotation_90_or_270(rotation))
1003 return false;
1004
1005 return true;
1006}
1007
1008static bool rotation_is_valid(const struct intel_plane_state *plane_state)
1009{
1010 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1011
1012 if (DISPLAY_VER(i915) >= 9)
1013 return skl_fbc_rotation_is_valid(plane_state);
1014 else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
1015 return g4x_fbc_rotation_is_valid(plane_state);
1016 else
1017 return i8xx_fbc_rotation_is_valid(plane_state);
1018}
1019
1020/*
1021 * For some reason, the hardware tracking starts looking at whatever we
1022 * programmed as the display plane base address register. It does not look at
1023 * the X and Y offset registers. That's why we include the src x/y offsets
1024 * instead of just looking at the plane size.
1025 */
1026static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state)
1027{
1028 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1029 unsigned int effective_w, effective_h, max_w, max_h;
1030
1031 if (DISPLAY_VER(i915) >= 11) {
1032 max_w = 8192;
1033 max_h = 4096;
1034 } else if (DISPLAY_VER(i915) >= 10) {
1035 max_w = 5120;
1036 max_h = 4096;
1037 } else if (DISPLAY_VER(i915) >= 7) {
1038 max_w = 4096;
1039 max_h = 4096;
1040 } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) {
1041 max_w = 4096;
1042 max_h = 2048;
1043 } else {
1044 max_w = 2048;
1045 max_h = 1536;
1046 }
1047
1048 effective_w = plane_state->view.color_plane[0].x +
1049 (drm_rect_width(&plane_state->uapi.src) >> 16);
1050 effective_h = plane_state->view.color_plane[0].y +
1051 (drm_rect_height(&plane_state->uapi.src) >> 16);
1052
1053 return effective_w <= max_w && effective_h <= max_h;
1054}
1055
1056static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state)
1057{
1058 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1059 unsigned int w, h, max_w, max_h;
1060
1061 if (DISPLAY_VER(i915) >= 10) {
1062 max_w = 5120;
1063 max_h = 4096;
1064 } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) {
1065 max_w = 4096;
1066 max_h = 4096;
1067 } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) {
1068 max_w = 4096;
1069 max_h = 2048;
1070 } else {
1071 max_w = 2048;
1072 max_h = 1536;
1073 }
1074
1075 w = drm_rect_width(&plane_state->uapi.src) >> 16;
1076 h = drm_rect_height(&plane_state->uapi.src) >> 16;
1077
1078 return w <= max_w && h <= max_h;
1079}
1080
1081static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)
1082{
1083 const struct drm_framebuffer *fb = plane_state->hw.fb;
1084
1085 return fb->modifier == I915_FORMAT_MOD_X_TILED;
1086}
1087
1088static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)
1089{
1090 const struct drm_framebuffer *fb = plane_state->hw.fb;
1091
1092 switch (fb->modifier) {
1093 case DRM_FORMAT_MOD_LINEAR:
1094 case I915_FORMAT_MOD_Y_TILED:
1095 case I915_FORMAT_MOD_Yf_TILED:
1096 case I915_FORMAT_MOD_4_TILED:
1097 case I915_FORMAT_MOD_X_TILED:
1098 return true;
1099 default:
1100 return false;
1101 }
1102}
1103
1104static bool tiling_is_valid(const struct intel_plane_state *plane_state)
1105{
1106 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1107
1108 if (DISPLAY_VER(i915) >= 9)
1109 return skl_fbc_tiling_valid(plane_state);
1110 else
1111 return i8xx_fbc_tiling_valid(plane_state);
1112}
1113
1114static void intel_fbc_update_state(struct intel_atomic_state *state,
1115 struct intel_crtc *crtc,
1116 struct intel_plane *plane)
1117{
1118 struct drm_i915_private *i915 = to_i915(state->base.dev);
1119 const struct intel_crtc_state *crtc_state =
1120 intel_atomic_get_new_crtc_state(state, crtc);
1121 const struct intel_plane_state *plane_state =
1122 intel_atomic_get_new_plane_state(state, plane);
1123 struct intel_fbc *fbc = plane->fbc;
1124 struct intel_fbc_state *fbc_state = &fbc->state;
1125
1126 WARN_ON(plane_state->no_fbc_reason);
1127 WARN_ON(fbc_state->plane && fbc_state->plane != plane);
1128
1129 fbc_state->plane = plane;
1130
1131 /* FBC1 compression interval: arbitrary choice of 1 second */
1132 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
1133
1134 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
1135
1136 drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE &&
1137 !intel_gt_support_legacy_fencing(to_gt(i915)));
1138
1139 if (plane_state->flags & PLANE_HAS_FENCE)
1140 fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma);
1141 else
1142 fbc_state->fence_id = -1;
1143
1144 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1145 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1146 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1147}
1148
1149static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1150{
1151 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1152
1153 /*
1154 * The use of a CPU fence is one of two ways to detect writes by the
1155 * CPU to the scanout and trigger updates to the FBC.
1156 *
1157 * The other method is by software tracking (see
1158 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1159 * the current compressed buffer and recompress it.
1160 *
1161 * Note that is possible for a tiled surface to be unmappable (and
1162 * so have no fence associated with it) due to aperture constraints
1163 * at the time of pinning.
1164 */
1165 return DISPLAY_VER(i915) >= 9 ||
1166 (plane_state->flags & PLANE_HAS_FENCE &&
1167 i915_vma_fence_id(plane_state->ggtt_vma) != -1);
1168}
1169
1170static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1171{
1172 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1173 struct intel_fbc *fbc = plane->fbc;
1174
1175 return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1176 intel_fbc_cfb_size(plane_state) <= fbc->limit *
1177 i915_gem_stolen_node_size(&fbc->compressed_fb);
1178}
1179
1180static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1181{
1182 return !plane_state->no_fbc_reason &&
1183 intel_fbc_is_fence_ok(plane_state) &&
1184 intel_fbc_is_cfb_ok(plane_state);
1185}
1186
1187static int intel_fbc_check_plane(struct intel_atomic_state *state,
1188 struct intel_plane *plane)
1189{
1190 struct drm_i915_private *i915 = to_i915(state->base.dev);
1191 struct intel_plane_state *plane_state =
1192 intel_atomic_get_new_plane_state(state, plane);
1193 const struct drm_framebuffer *fb = plane_state->hw.fb;
1194 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1195 const struct intel_crtc_state *crtc_state;
1196 struct intel_fbc *fbc = plane->fbc;
1197
1198 if (!fbc)
1199 return 0;
1200
1201 if (!i915_gem_stolen_initialized(i915)) {
1202 plane_state->no_fbc_reason = "stolen memory not initialised";
1203 return 0;
1204 }
1205
1206 if (intel_vgpu_active(i915)) {
1207 plane_state->no_fbc_reason = "VGPU active";
1208 return 0;
1209 }
1210
1211 if (!i915->display.params.enable_fbc) {
1212 plane_state->no_fbc_reason = "disabled per module param or by default";
1213 return 0;
1214 }
1215
1216 if (!plane_state->uapi.visible) {
1217 plane_state->no_fbc_reason = "plane not visible";
1218 return 0;
1219 }
1220
1221 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1222
1223 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1224 plane_state->no_fbc_reason = "interlaced mode not supported";
1225 return 0;
1226 }
1227
1228 if (crtc_state->double_wide) {
1229 plane_state->no_fbc_reason = "double wide pipe not supported";
1230 return 0;
1231 }
1232
1233 /*
1234 * Display 12+ is not supporting FBC with PSR2.
1235 * Recommendation is to keep this combination disabled
1236 * Bspec: 50422 HSD: 14010260002
1237 */
1238 if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
1239 plane_state->no_fbc_reason = "PSR2 enabled";
1240 return 0;
1241 }
1242
1243 /* Wa_14016291713 */
1244 if ((IS_DISPLAY_VER(i915, 12, 13) ||
1245 IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
1246 crtc_state->has_psr) {
1247 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1248 return 0;
1249 }
1250
1251 if (!pixel_format_is_valid(plane_state)) {
1252 plane_state->no_fbc_reason = "pixel format not supported";
1253 return 0;
1254 }
1255
1256 if (!tiling_is_valid(plane_state)) {
1257 plane_state->no_fbc_reason = "tiling not supported";
1258 return 0;
1259 }
1260
1261 if (!rotation_is_valid(plane_state)) {
1262 plane_state->no_fbc_reason = "rotation not supported";
1263 return 0;
1264 }
1265
1266 if (!stride_is_valid(plane_state)) {
1267 plane_state->no_fbc_reason = "stride not supported";
1268 return 0;
1269 }
1270
1271 if (DISPLAY_VER(i915) < 20 &&
1272 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1273 fb->format->has_alpha) {
1274 plane_state->no_fbc_reason = "per-pixel alpha not supported";
1275 return 0;
1276 }
1277
1278 if (!intel_fbc_plane_size_valid(plane_state)) {
1279 plane_state->no_fbc_reason = "plane size too big";
1280 return 0;
1281 }
1282
1283 if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
1284 plane_state->no_fbc_reason = "surface size too big";
1285 return 0;
1286 }
1287
1288 /*
1289 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1290 * having a Y offset that isn't divisible by 4 causes FIFO underrun
1291 * and screen flicker.
1292 */
1293 if (DISPLAY_VER(i915) >= 9 &&
1294 plane_state->view.color_plane[0].y & 3) {
1295 plane_state->no_fbc_reason = "plane start Y offset misaligned";
1296 return 0;
1297 }
1298
1299 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1300 if (DISPLAY_VER(i915) >= 11 &&
1301 (plane_state->view.color_plane[0].y +
1302 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
1303 plane_state->no_fbc_reason = "plane end Y offset misaligned";
1304 return 0;
1305 }
1306
1307 /* WaFbcExceedCdClockThreshold:hsw,bdw */
1308 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1309 const struct intel_cdclk_state *cdclk_state;
1310
1311 cdclk_state = intel_atomic_get_cdclk_state(state);
1312 if (IS_ERR(cdclk_state))
1313 return PTR_ERR(cdclk_state);
1314
1315 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
1316 plane_state->no_fbc_reason = "pixel rate too high";
1317 return 0;
1318 }
1319 }
1320
1321 plane_state->no_fbc_reason = NULL;
1322
1323 return 0;
1324}
1325
1326
1327static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1328 struct intel_crtc *crtc,
1329 struct intel_plane *plane)
1330{
1331 const struct intel_crtc_state *new_crtc_state =
1332 intel_atomic_get_new_crtc_state(state, crtc);
1333 const struct intel_plane_state *old_plane_state =
1334 intel_atomic_get_old_plane_state(state, plane);
1335 const struct intel_plane_state *new_plane_state =
1336 intel_atomic_get_new_plane_state(state, plane);
1337 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1338 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1339
1340 if (intel_crtc_needs_modeset(new_crtc_state))
1341 return false;
1342
1343 if (!intel_fbc_is_ok(old_plane_state) ||
1344 !intel_fbc_is_ok(new_plane_state))
1345 return false;
1346
1347 if (old_fb->format->format != new_fb->format->format)
1348 return false;
1349
1350 if (old_fb->modifier != new_fb->modifier)
1351 return false;
1352
1353 if (intel_fbc_plane_stride(old_plane_state) !=
1354 intel_fbc_plane_stride(new_plane_state))
1355 return false;
1356
1357 if (intel_fbc_cfb_stride(old_plane_state) !=
1358 intel_fbc_cfb_stride(new_plane_state))
1359 return false;
1360
1361 if (intel_fbc_cfb_size(old_plane_state) !=
1362 intel_fbc_cfb_size(new_plane_state))
1363 return false;
1364
1365 if (intel_fbc_override_cfb_stride(old_plane_state) !=
1366 intel_fbc_override_cfb_stride(new_plane_state))
1367 return false;
1368
1369 return true;
1370}
1371
1372static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1373 struct intel_crtc *crtc,
1374 struct intel_plane *plane)
1375{
1376 struct drm_i915_private *i915 = to_i915(state->base.dev);
1377 struct intel_fbc *fbc = plane->fbc;
1378 bool need_vblank_wait = false;
1379
1380 lockdep_assert_held(&fbc->lock);
1381
1382 fbc->flip_pending = true;
1383
1384 if (intel_fbc_can_flip_nuke(state, crtc, plane))
1385 return need_vblank_wait;
1386
1387 intel_fbc_deactivate(fbc, "update pending");
1388
1389 /*
1390 * Display WA #1198: glk+
1391 * Need an extra vblank wait between FBC disable and most plane
1392 * updates. Bspec says this is only needed for plane disable, but
1393 * that is not true. Touching most plane registers will cause the
1394 * corruption to appear. Also SKL/derivatives do not seem to be
1395 * affected.
1396 *
1397 * TODO: could optimize this a bit by sampling the frame
1398 * counter when we disable FBC (if it was already done earlier)
1399 * and skipping the extra vblank wait before the plane update
1400 * if at least one frame has already passed.
1401 */
1402 if (fbc->activated && DISPLAY_VER(i915) >= 10)
1403 need_vblank_wait = true;
1404 fbc->activated = false;
1405
1406 return need_vblank_wait;
1407}
1408
1409bool intel_fbc_pre_update(struct intel_atomic_state *state,
1410 struct intel_crtc *crtc)
1411{
1412 const struct intel_plane_state __maybe_unused *plane_state;
1413 bool need_vblank_wait = false;
1414 struct intel_plane *plane;
1415 int i;
1416
1417 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1418 struct intel_fbc *fbc = plane->fbc;
1419
1420 if (!fbc || plane->pipe != crtc->pipe)
1421 continue;
1422
1423 mutex_lock(&fbc->lock);
1424
1425 if (fbc->state.plane == plane)
1426 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1427
1428 mutex_unlock(&fbc->lock);
1429 }
1430
1431 return need_vblank_wait;
1432}
1433
1434static void __intel_fbc_disable(struct intel_fbc *fbc)
1435{
1436 struct drm_i915_private *i915 = fbc->i915;
1437 struct intel_plane *plane = fbc->state.plane;
1438
1439 lockdep_assert_held(&fbc->lock);
1440 drm_WARN_ON(&i915->drm, fbc->active);
1441
1442 drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1443 plane->base.base.id, plane->base.name);
1444
1445 __intel_fbc_cleanup_cfb(fbc);
1446
1447 fbc->state.plane = NULL;
1448 fbc->flip_pending = false;
1449 fbc->busy_bits = 0;
1450}
1451
1452static void __intel_fbc_post_update(struct intel_fbc *fbc)
1453{
1454 lockdep_assert_held(&fbc->lock);
1455
1456 fbc->flip_pending = false;
1457 fbc->busy_bits = 0;
1458
1459 intel_fbc_activate(fbc);
1460}
1461
1462void intel_fbc_post_update(struct intel_atomic_state *state,
1463 struct intel_crtc *crtc)
1464{
1465 const struct intel_plane_state __maybe_unused *plane_state;
1466 struct intel_plane *plane;
1467 int i;
1468
1469 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1470 struct intel_fbc *fbc = plane->fbc;
1471
1472 if (!fbc || plane->pipe != crtc->pipe)
1473 continue;
1474
1475 mutex_lock(&fbc->lock);
1476
1477 if (fbc->state.plane == plane)
1478 __intel_fbc_post_update(fbc);
1479
1480 mutex_unlock(&fbc->lock);
1481 }
1482}
1483
1484static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1485{
1486 if (fbc->state.plane)
1487 return fbc->state.plane->frontbuffer_bit;
1488 else
1489 return 0;
1490}
1491
1492static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1493 unsigned int frontbuffer_bits,
1494 enum fb_op_origin origin)
1495{
1496 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1497 return;
1498
1499 mutex_lock(&fbc->lock);
1500
1501 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1502 if (!frontbuffer_bits)
1503 goto out;
1504
1505 fbc->busy_bits |= frontbuffer_bits;
1506 intel_fbc_deactivate(fbc, "frontbuffer write");
1507
1508out:
1509 mutex_unlock(&fbc->lock);
1510}
1511
1512void intel_fbc_invalidate(struct drm_i915_private *i915,
1513 unsigned int frontbuffer_bits,
1514 enum fb_op_origin origin)
1515{
1516 struct intel_fbc *fbc;
1517 enum intel_fbc_id fbc_id;
1518
1519 for_each_intel_fbc(i915, fbc, fbc_id)
1520 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1521
1522}
1523
1524static void __intel_fbc_flush(struct intel_fbc *fbc,
1525 unsigned int frontbuffer_bits,
1526 enum fb_op_origin origin)
1527{
1528 mutex_lock(&fbc->lock);
1529
1530 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1531 if (!frontbuffer_bits)
1532 goto out;
1533
1534 fbc->busy_bits &= ~frontbuffer_bits;
1535
1536 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1537 goto out;
1538
1539 if (fbc->busy_bits || fbc->flip_pending)
1540 goto out;
1541
1542 if (fbc->active)
1543 intel_fbc_nuke(fbc);
1544 else
1545 intel_fbc_activate(fbc);
1546
1547out:
1548 mutex_unlock(&fbc->lock);
1549}
1550
1551void intel_fbc_flush(struct drm_i915_private *i915,
1552 unsigned int frontbuffer_bits,
1553 enum fb_op_origin origin)
1554{
1555 struct intel_fbc *fbc;
1556 enum intel_fbc_id fbc_id;
1557
1558 for_each_intel_fbc(i915, fbc, fbc_id)
1559 __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1560}
1561
1562int intel_fbc_atomic_check(struct intel_atomic_state *state)
1563{
1564 struct intel_plane_state __maybe_unused *plane_state;
1565 struct intel_plane *plane;
1566 int i;
1567
1568 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1569 int ret;
1570
1571 ret = intel_fbc_check_plane(state, plane);
1572 if (ret)
1573 return ret;
1574 }
1575
1576 return 0;
1577}
1578
1579static void __intel_fbc_enable(struct intel_atomic_state *state,
1580 struct intel_crtc *crtc,
1581 struct intel_plane *plane)
1582{
1583 struct drm_i915_private *i915 = to_i915(state->base.dev);
1584 const struct intel_plane_state *plane_state =
1585 intel_atomic_get_new_plane_state(state, plane);
1586 struct intel_fbc *fbc = plane->fbc;
1587
1588 lockdep_assert_held(&fbc->lock);
1589
1590 if (fbc->state.plane) {
1591 if (fbc->state.plane != plane)
1592 return;
1593
1594 if (intel_fbc_is_ok(plane_state)) {
1595 intel_fbc_update_state(state, crtc, plane);
1596 return;
1597 }
1598
1599 __intel_fbc_disable(fbc);
1600 }
1601
1602 drm_WARN_ON(&i915->drm, fbc->active);
1603
1604 fbc->no_fbc_reason = plane_state->no_fbc_reason;
1605 if (fbc->no_fbc_reason)
1606 return;
1607
1608 if (!intel_fbc_is_fence_ok(plane_state)) {
1609 fbc->no_fbc_reason = "framebuffer not fenced";
1610 return;
1611 }
1612
1613 if (fbc->underrun_detected) {
1614 fbc->no_fbc_reason = "FIFO underrun";
1615 return;
1616 }
1617
1618 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
1619 intel_fbc_min_limit(plane_state))) {
1620 fbc->no_fbc_reason = "not enough stolen memory";
1621 return;
1622 }
1623
1624 drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1625 plane->base.base.id, plane->base.name);
1626 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1627
1628 intel_fbc_update_state(state, crtc, plane);
1629
1630 intel_fbc_program_workarounds(fbc);
1631 intel_fbc_program_cfb(fbc);
1632}
1633
1634/**
1635 * intel_fbc_disable - disable FBC if it's associated with crtc
1636 * @crtc: the CRTC
1637 *
1638 * This function disables FBC if it's associated with the provided CRTC.
1639 */
1640void intel_fbc_disable(struct intel_crtc *crtc)
1641{
1642 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1643 struct intel_plane *plane;
1644
1645 for_each_intel_plane(&i915->drm, plane) {
1646 struct intel_fbc *fbc = plane->fbc;
1647
1648 if (!fbc || plane->pipe != crtc->pipe)
1649 continue;
1650
1651 mutex_lock(&fbc->lock);
1652 if (fbc->state.plane == plane)
1653 __intel_fbc_disable(fbc);
1654 mutex_unlock(&fbc->lock);
1655 }
1656}
1657
1658void intel_fbc_update(struct intel_atomic_state *state,
1659 struct intel_crtc *crtc)
1660{
1661 const struct intel_crtc_state *crtc_state =
1662 intel_atomic_get_new_crtc_state(state, crtc);
1663 const struct intel_plane_state *plane_state;
1664 struct intel_plane *plane;
1665 int i;
1666
1667 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1668 struct intel_fbc *fbc = plane->fbc;
1669
1670 if (!fbc || plane->pipe != crtc->pipe)
1671 continue;
1672
1673 mutex_lock(&fbc->lock);
1674
1675 if (intel_crtc_needs_fastset(crtc_state) &&
1676 plane_state->no_fbc_reason) {
1677 if (fbc->state.plane == plane)
1678 __intel_fbc_disable(fbc);
1679 } else {
1680 __intel_fbc_enable(state, crtc, plane);
1681 }
1682
1683 mutex_unlock(&fbc->lock);
1684 }
1685}
1686
1687static void intel_fbc_underrun_work_fn(struct work_struct *work)
1688{
1689 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1690 struct drm_i915_private *i915 = fbc->i915;
1691
1692 mutex_lock(&fbc->lock);
1693
1694 /* Maybe we were scheduled twice. */
1695 if (fbc->underrun_detected || !fbc->state.plane)
1696 goto out;
1697
1698 drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
1699 fbc->underrun_detected = true;
1700
1701 intel_fbc_deactivate(fbc, "FIFO underrun");
1702 if (!fbc->flip_pending)
1703 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe));
1704 __intel_fbc_disable(fbc);
1705out:
1706 mutex_unlock(&fbc->lock);
1707}
1708
1709static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1710{
1711 struct drm_i915_private *i915 = fbc->i915;
1712
1713 cancel_work_sync(&fbc->underrun_work);
1714
1715 mutex_lock(&fbc->lock);
1716
1717 if (fbc->underrun_detected) {
1718 drm_dbg_kms(&i915->drm,
1719 "Re-allowing FBC after fifo underrun\n");
1720 fbc->no_fbc_reason = "FIFO underrun cleared";
1721 }
1722
1723 fbc->underrun_detected = false;
1724 mutex_unlock(&fbc->lock);
1725}
1726
1727/*
1728 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1729 * @i915: the i915 device
1730 *
1731 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1732 * want to re-enable FBC after an underrun to increase test coverage.
1733 */
1734void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1735{
1736 struct intel_fbc *fbc;
1737 enum intel_fbc_id fbc_id;
1738
1739 for_each_intel_fbc(i915, fbc, fbc_id)
1740 __intel_fbc_reset_underrun(fbc);
1741}
1742
1743static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1744{
1745 /*
1746 * There's no guarantee that underrun_detected won't be set to true
1747 * right after this check and before the work is scheduled, but that's
1748 * not a problem since we'll check it again under the work function
1749 * while FBC is locked. This check here is just to prevent us from
1750 * unnecessarily scheduling the work, and it relies on the fact that we
1751 * never switch underrun_detect back to false after it's true.
1752 */
1753 if (READ_ONCE(fbc->underrun_detected))
1754 return;
1755
1756 queue_work(fbc->i915->unordered_wq, &fbc->underrun_work);
1757}
1758
1759/**
1760 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1761 * @i915: i915 device
1762 *
1763 * Without FBC, most underruns are harmless and don't really cause too many
1764 * problems, except for an annoying message on dmesg. With FBC, underruns can
1765 * become black screens or even worse, especially when paired with bad
1766 * watermarks. So in order for us to be on the safe side, completely disable FBC
1767 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1768 * already suggests that watermarks may be bad, so try to be as safe as
1769 * possible.
1770 *
1771 * This function is called from the IRQ handler.
1772 */
1773void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
1774{
1775 struct intel_fbc *fbc;
1776 enum intel_fbc_id fbc_id;
1777
1778 for_each_intel_fbc(i915, fbc, fbc_id)
1779 __intel_fbc_handle_fifo_underrun_irq(fbc);
1780}
1781
1782/*
1783 * The DDX driver changes its behavior depending on the value it reads from
1784 * i915.enable_fbc, so sanitize it by translating the default value into either
1785 * 0 or 1 in order to allow it to know what's going on.
1786 *
1787 * Notice that this is done at driver initialization and we still allow user
1788 * space to change the value during runtime without sanitizing it again. IGT
1789 * relies on being able to change i915.enable_fbc at runtime.
1790 */
1791static int intel_sanitize_fbc_option(struct drm_i915_private *i915)
1792{
1793 if (i915->display.params.enable_fbc >= 0)
1794 return !!i915->display.params.enable_fbc;
1795
1796 if (!HAS_FBC(i915))
1797 return 0;
1798
1799 if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9)
1800 return 1;
1801
1802 return 0;
1803}
1804
1805static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
1806{
1807 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1808 if (i915_vtd_active(i915) &&
1809 (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
1810 drm_info(&i915->drm,
1811 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1812 return true;
1813 }
1814
1815 return false;
1816}
1817
1818void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
1819{
1820 plane->fbc = fbc;
1821}
1822
1823static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
1824 enum intel_fbc_id fbc_id)
1825{
1826 struct intel_fbc *fbc;
1827
1828 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
1829 if (!fbc)
1830 return NULL;
1831
1832 fbc->id = fbc_id;
1833 fbc->i915 = i915;
1834 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1835 mutex_init(&fbc->lock);
1836
1837 if (DISPLAY_VER(i915) >= 7)
1838 fbc->funcs = &ivb_fbc_funcs;
1839 else if (DISPLAY_VER(i915) == 6)
1840 fbc->funcs = &snb_fbc_funcs;
1841 else if (DISPLAY_VER(i915) == 5)
1842 fbc->funcs = &ilk_fbc_funcs;
1843 else if (IS_G4X(i915))
1844 fbc->funcs = &g4x_fbc_funcs;
1845 else if (DISPLAY_VER(i915) == 4)
1846 fbc->funcs = &i965_fbc_funcs;
1847 else
1848 fbc->funcs = &i8xx_fbc_funcs;
1849
1850 return fbc;
1851}
1852
1853/**
1854 * intel_fbc_init - Initialize FBC
1855 * @i915: the i915 device
1856 *
1857 * This function might be called during PM init process.
1858 */
1859void intel_fbc_init(struct drm_i915_private *i915)
1860{
1861 enum intel_fbc_id fbc_id;
1862
1863 if (need_fbc_vtd_wa(i915))
1864 DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
1865
1866 i915->display.params.enable_fbc = intel_sanitize_fbc_option(i915);
1867 drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
1868 i915->display.params.enable_fbc);
1869
1870 for_each_fbc_id(i915, fbc_id)
1871 i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
1872}
1873
1874/**
1875 * intel_fbc_sanitize - Sanitize FBC
1876 * @i915: the i915 device
1877 *
1878 * Make sure FBC is initially disabled since we have no
1879 * idea eg. into which parts of stolen it might be scribbling
1880 * into.
1881 */
1882void intel_fbc_sanitize(struct drm_i915_private *i915)
1883{
1884 struct intel_fbc *fbc;
1885 enum intel_fbc_id fbc_id;
1886
1887 for_each_intel_fbc(i915, fbc, fbc_id) {
1888 if (intel_fbc_hw_is_active(fbc))
1889 intel_fbc_hw_deactivate(fbc);
1890 }
1891}
1892
1893static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
1894{
1895 struct intel_fbc *fbc = m->private;
1896 struct drm_i915_private *i915 = fbc->i915;
1897 struct intel_plane *plane;
1898 intel_wakeref_t wakeref;
1899
1900 drm_modeset_lock_all(&i915->drm);
1901
1902 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1903 mutex_lock(&fbc->lock);
1904
1905 if (fbc->active) {
1906 seq_puts(m, "FBC enabled\n");
1907 seq_printf(m, "Compressing: %s\n",
1908 str_yes_no(intel_fbc_is_compressing(fbc)));
1909 } else {
1910 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1911 }
1912
1913 for_each_intel_plane(&i915->drm, plane) {
1914 const struct intel_plane_state *plane_state =
1915 to_intel_plane_state(plane->base.state);
1916
1917 if (plane->fbc != fbc)
1918 continue;
1919
1920 seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
1921 fbc->state.plane == plane ? '*' : ' ',
1922 plane->base.base.id, plane->base.name,
1923 plane_state->no_fbc_reason ?: "FBC possible");
1924 }
1925
1926 mutex_unlock(&fbc->lock);
1927 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1928
1929 drm_modeset_unlock_all(&i915->drm);
1930
1931 return 0;
1932}
1933
1934DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
1935
1936static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
1937{
1938 struct intel_fbc *fbc = data;
1939
1940 *val = fbc->false_color;
1941
1942 return 0;
1943}
1944
1945static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
1946{
1947 struct intel_fbc *fbc = data;
1948
1949 mutex_lock(&fbc->lock);
1950
1951 fbc->false_color = val;
1952
1953 if (fbc->active)
1954 fbc->funcs->set_false_color(fbc, fbc->false_color);
1955
1956 mutex_unlock(&fbc->lock);
1957
1958 return 0;
1959}
1960
1961DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
1962 intel_fbc_debugfs_false_color_get,
1963 intel_fbc_debugfs_false_color_set,
1964 "%llu\n");
1965
1966static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
1967 struct dentry *parent)
1968{
1969 debugfs_create_file("i915_fbc_status", 0444, parent,
1970 fbc, &intel_fbc_debugfs_status_fops);
1971
1972 if (fbc->funcs->set_false_color)
1973 debugfs_create_file_unsafe("i915_fbc_false_color", 0644, parent,
1974 fbc, &intel_fbc_debugfs_false_color_fops);
1975}
1976
1977void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
1978{
1979 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1980
1981 if (plane->fbc)
1982 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
1983}
1984
1985/* FIXME: remove this once igt is on board with per-crtc stuff */
1986void intel_fbc_debugfs_register(struct drm_i915_private *i915)
1987{
1988 struct drm_minor *minor = i915->drm.primary;
1989 struct intel_fbc *fbc;
1990
1991 fbc = i915->display.fbc[INTEL_FBC_A];
1992 if (fbc)
1993 intel_fbc_debugfs_add(fbc, minor->debugfs_root);
1994}