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1/* SPDX-License-Identifier: MIT
2 *
3 * Copyright © 2023 Intel Corporation
4 */
5
6#ifndef __INTEL_CX0_PHY_REGS_H__
7#define __INTEL_CX0_PHY_REGS_H__
8
9#include "i915_reg_defs.h"
10
11#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
12#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
13#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
14#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
15#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
16 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
17 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
18 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
20#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
21#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
22#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
23#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
24#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
25#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
26#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
27#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
28#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
29#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
30#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
31 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
32 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
33 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
35#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
36#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
37#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
38#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
39#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
40#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
41#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
42
43#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
44#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
45#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
46#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
47#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
48#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
49#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
50#define XELPDP_PORT_RESET_END_TIMEOUT 15
51#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
52
53#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
54#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
55#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
56#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
57#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
58 _XELPDP_PORT_BUF_CTL1_LN0_A, \
59 _XELPDP_PORT_BUF_CTL1_LN0_B, \
60 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
61 _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
62#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
63#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
64#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
65#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
66#define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
67#define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
68#define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
69#define XELPDP_PORT_REVERSAL REG_BIT(16)
70#define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11)
71#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
72#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
73#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
74#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
75#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
76#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
77
78#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
79 _XELPDP_PORT_BUF_CTL1_LN0_A, \
80 _XELPDP_PORT_BUF_CTL1_LN0_B, \
81 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
82 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
83
84#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
85#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
86#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
87#define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
88#define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
89#define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
90#define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
91#define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \
92 _XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \
93 _XELPDP_LANE1_POWERDOWN_NEW_STATE(val))
94#define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0)
95#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
96#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
97
98#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
99 _XELPDP_PORT_BUF_CTL1_LN0_A, \
100 _XELPDP_PORT_BUF_CTL1_LN0_B, \
101 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
102 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
103#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
104#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
105#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
106#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
107#define CX0_P0_STATE_ACTIVE 0x0
108#define CX0_P2_STATE_READY 0x2
109#define CX0_P2PG_STATE_DISABLE 0x9
110#define CX0_P4PG_STATE_DISABLE 0xC
111#define CX0_P2_STATE_RESET 0x2
112
113#define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8
114#define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8
115#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258
116#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458
117#define XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
118 _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \
119 _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \
120 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \
121 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
122#define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31)
123#define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0)
124#define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000)
125
126#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
127#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
128#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
129#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
130#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
131 _XELPDP_PORT_CLOCK_CTL_A, \
132 _XELPDP_PORT_CLOCK_CTL_B, \
133 _XELPDP_PORT_CLOCK_CTL_USBC1, \
134 _XELPDP_PORT_CLOCK_CTL_USBC2))
135#define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
136#define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
137#define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
138#define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4))
139
140#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
141#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
142#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
143#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
144#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
145#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
146#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
147#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
148#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
149#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
150#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
151#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
152#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
153#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
154#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
155
156/* C10 Vendor Registers */
157#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
158#define C10_PLL0_FRACEN REG_BIT8(4)
159#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
160#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
161#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
162
163#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
164#define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1)
165#define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1)
166#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
167#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
168#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
169#define C10_TX0_TX_MPLLB_SEL REG_BIT(4)
170#define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5)
171#define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val)
172#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
173#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
174#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
175#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
176#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
177#define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
178#define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0)
179#define PHY_C10_VDR_OVRD 0xD71
180#define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0)
181#define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2)
182#define PHY_C10_VDR_PRE_OVRD_TX1 0xD80
183#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
184#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
185#define PHY_CX0_VDROVRD_CTL(lane, tx, control) \
186 (PHY_C10_VDR_PRE_OVRD_TX1 + \
187 ((lane) ^ (tx)) * 0x10 + (control))
188
189/* PIPE SPEC Defined Registers */
190#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
191#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
192
193/* C20 Registers */
194#define PHY_C20_WR_ADDRESS_L 0xC02
195#define PHY_C20_WR_ADDRESS_H 0xC03
196#define PHY_C20_WR_DATA_L 0xC04
197#define PHY_C20_WR_DATA_H 0xC05
198#define PHY_C20_RD_ADDRESS_L 0xC06
199#define PHY_C20_RD_ADDRESS_H 0xC07
200#define PHY_C20_RD_DATA_L 0xC08
201#define PHY_C20_RD_DATA_H 0xC09
202#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
203#define PHY_C20_VDR_HDMI_RATE 0xD01
204#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
205#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
206#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
207#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
208#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
209#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
210#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
211#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
212#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
213#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
214#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
215#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
216#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
217#define C20_MPLLA_FRACEN REG_BIT(14)
218#define C20_FB_CLK_DIV4_EN REG_BIT(13)
219#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
220#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
221#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
222#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
223#define C20_MPLLB_FRACEN REG_BIT(13)
224#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
225#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
226#define C20_PHY_USE_MPLLB REG_BIT(7)
227
228/* C20 Phy VSwing Masks */
229#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
230#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
231
232#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
233
234/* C20 HDMI computed pll definitions */
235#define REFCLK_38_4_MHZ 38400000
236#define CLOCK_4999MHZ 4999999999
237#define CLOCK_9999MHZ 9999999999
238#define DATARATE_3000000000 3000000000
239#define DATARATE_3500000000 3500000000
240#define DATARATE_4000000000 4000000000
241#define MPLL_FRACN_DEN 0xFFFF
242
243#define SSC_UP_SPREAD REG_BIT16(9)
244#define WORD_CLK_DIV REG_BIT16(8)
245
246#define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
247#define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)
248
249#define MPLLB_ANA_FREQ_VCO_0 0
250#define MPLLB_ANA_FREQ_VCO_1 1
251#define MPLLB_ANA_FREQ_VCO_2 2
252#define MPLLB_ANA_FREQ_VCO_3 3
253#define MPLLB_ANA_FREQ_VCO_MASK REG_GENMASK16(15, 14)
254#define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)
255
256#define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0)
257#define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)
258
259#define CAL_DAC_CODE_31 31
260#define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10)
261#define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)
262
263#define CP_INT_GS_28 28
264#define CP_INT_GS_MASK REG_GENMASK16(6, 0)
265#define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val)
266
267#define CP_PROP_GS_30 30
268#define CP_PROP_GS_MASK REG_GENMASK16(13, 7)
269#define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val)
270
271#define CP_INT_6 6
272#define CP_INT_MASK REG_GENMASK16(6, 0)
273#define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val)
274
275#define CP_PROP_20 20
276#define CP_PROP_MASK REG_GENMASK16(13, 7)
277#define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val)
278
279#define V2I_2 2
280#define V2I_MASK REG_GENMASK16(15, 14)
281#define V2I(val) REG_FIELD_PREP16(V2I_MASK, val)
282
283#define HDMI_DIV_1 1
284#define HDMI_DIV_MASK REG_GENMASK16(2, 0)
285#define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val)
286
287#endif /* __INTEL_CX0_REG_DEFS_H__ */