Loading...
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/pci.h>
25#include "amdgpu.h"
26#include "amdgpu_atomfirmware.h"
27#include "gmc_v10_0.h"
28#include "umc_v8_7.h"
29
30#include "athub/athub_2_0_0_sh_mask.h"
31#include "athub/athub_2_0_0_offset.h"
32#include "dcn/dcn_2_0_0_offset.h"
33#include "dcn/dcn_2_0_0_sh_mask.h"
34#include "oss/osssys_5_0_0_offset.h"
35#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
36#include "navi10_enum.h"
37
38#include "soc15.h"
39#include "soc15d.h"
40#include "soc15_common.h"
41
42#include "nbio_v2_3.h"
43
44#include "gfxhub_v2_0.h"
45#include "gfxhub_v2_1.h"
46#include "mmhub_v2_0.h"
47#include "mmhub_v2_3.h"
48#include "athub_v2_0.h"
49#include "athub_v2_1.h"
50
51#if 0
52static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
53{
54 /* TODO add golden setting for hdp */
55};
56#endif
57
58static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
59 struct amdgpu_irq_src *src,
60 unsigned type,
61 enum amdgpu_interrupt_state state)
62{
63 return 0;
64}
65
66static int
67gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
68 struct amdgpu_irq_src *src, unsigned type,
69 enum amdgpu_interrupt_state state)
70{
71 switch (state) {
72 case AMDGPU_IRQ_STATE_DISABLE:
73 /* MM HUB */
74 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
75 /* GFX HUB */
76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
77 break;
78 case AMDGPU_IRQ_STATE_ENABLE:
79 /* MM HUB */
80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
81 /* GFX HUB */
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
83 break;
84 default:
85 break;
86 }
87
88 return 0;
89}
90
91static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
92 struct amdgpu_irq_src *source,
93 struct amdgpu_iv_entry *entry)
94{
95 bool retry_fault = !!(entry->src_data[1] & 0x80);
96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
97 struct amdgpu_task_info task_info;
98 uint32_t status = 0;
99 u64 addr;
100
101 addr = (u64)entry->src_data[0] << 12;
102 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
103
104 if (retry_fault) {
105 /* Returning 1 here also prevents sending the IV to the KFD */
106
107 /* Process it onyl if it's the first fault for this address */
108 if (entry->ih != &adev->irq.ih_soft &&
109 amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
110 entry->timestamp))
111 return 1;
112
113 /* Delegate it to a different ring if the hardware hasn't
114 * already done it.
115 */
116 if (entry->ih == &adev->irq.ih) {
117 amdgpu_irq_delegate(adev, entry, 8);
118 return 1;
119 }
120
121 /* Try to handle the recoverable page faults by filling page
122 * tables
123 */
124 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
125 return 1;
126 }
127
128 if (!amdgpu_sriov_vf(adev)) {
129 /*
130 * Issue a dummy read to wait for the status register to
131 * be updated to avoid reading an incorrect value due to
132 * the new fast GRBM interface.
133 */
134 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
135 (adev->asic_type < CHIP_SIENNA_CICHLID))
136 RREG32(hub->vm_l2_pro_fault_status);
137
138 status = RREG32(hub->vm_l2_pro_fault_status);
139 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
140 }
141
142 if (!printk_ratelimit())
143 return 0;
144
145 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
146 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
147
148 dev_err(adev->dev,
149 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
150 "for process %s pid %d thread %s pid %d)\n",
151 entry->vmid_src ? "mmhub" : "gfxhub",
152 entry->src_id, entry->ring_id, entry->vmid,
153 entry->pasid, task_info.process_name, task_info.tgid,
154 task_info.task_name, task_info.pid);
155 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n",
156 addr, entry->client_id,
157 soc15_ih_clientid_name[entry->client_id]);
158
159 if (!amdgpu_sriov_vf(adev))
160 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
161 status);
162
163 return 0;
164}
165
166static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
167 .set = gmc_v10_0_vm_fault_interrupt_state,
168 .process = gmc_v10_0_process_interrupt,
169};
170
171static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
172 .set = gmc_v10_0_ecc_interrupt_state,
173 .process = amdgpu_umc_process_ecc_irq,
174};
175
176static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
177{
178 adev->gmc.vm_fault.num_types = 1;
179 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
180
181 if (!amdgpu_sriov_vf(adev)) {
182 adev->gmc.ecc_irq.num_types = 1;
183 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
184 }
185}
186
187/**
188 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
189 *
190 * @adev: amdgpu_device pointer
191 * @vmhub: vmhub type
192 *
193 */
194static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
195 uint32_t vmhub)
196{
197 return ((vmhub == AMDGPU_MMHUB_0 ||
198 vmhub == AMDGPU_MMHUB_1) &&
199 (!amdgpu_sriov_vf(adev)));
200}
201
202static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
203 struct amdgpu_device *adev,
204 uint8_t vmid, uint16_t *p_pasid)
205{
206 uint32_t value;
207
208 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
209 + vmid);
210 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
211
212 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
213}
214
215/*
216 * GART
217 * VMID 0 is the physical GPU addresses as used by the kernel.
218 * VMIDs 1-15 are used for userspace clients and are handled
219 * by the amdgpu vm/hsa code.
220 */
221
222static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
223 unsigned int vmhub, uint32_t flush_type)
224{
225 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
226 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
227 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
228 u32 tmp;
229 /* Use register 17 for GART */
230 const unsigned eng = 17;
231 unsigned int i;
232 unsigned char hub_ip = 0;
233
234 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
235 GC_HWIP : MMHUB_HWIP;
236
237 spin_lock(&adev->gmc.invalidate_lock);
238 /*
239 * It may lose gpuvm invalidate acknowldege state across power-gating
240 * off cycle, add semaphore acquire before invalidation and semaphore
241 * release after invalidation to avoid entering power gated state
242 * to WA the Issue
243 */
244
245 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
246 if (use_semaphore) {
247 for (i = 0; i < adev->usec_timeout; i++) {
248 /* a read return value of 1 means semaphore acuqire */
249 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
250 hub->eng_distance * eng, hub_ip);
251
252 if (tmp & 0x1)
253 break;
254 udelay(1);
255 }
256
257 if (i >= adev->usec_timeout)
258 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
259 }
260
261 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
262 hub->eng_distance * eng,
263 inv_req, hub_ip);
264
265 /*
266 * Issue a dummy read to wait for the ACK register to be cleared
267 * to avoid a false ACK due to the new fast GRBM interface.
268 */
269 if ((vmhub == AMDGPU_GFXHUB_0) &&
270 (adev->asic_type < CHIP_SIENNA_CICHLID))
271 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
272 hub->eng_distance * eng, hub_ip);
273
274 /* Wait for ACK with a delay.*/
275 for (i = 0; i < adev->usec_timeout; i++) {
276 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
277 hub->eng_distance * eng, hub_ip);
278
279 tmp &= 1 << vmid;
280 if (tmp)
281 break;
282
283 udelay(1);
284 }
285
286 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
287 if (use_semaphore)
288 /*
289 * add semaphore release after invalidation,
290 * write with 0 means semaphore release
291 */
292 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
293 hub->eng_distance * eng, 0, hub_ip);
294
295 spin_unlock(&adev->gmc.invalidate_lock);
296
297 if (i < adev->usec_timeout)
298 return;
299
300 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
301}
302
303/**
304 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
305 *
306 * @adev: amdgpu_device pointer
307 * @vmid: vm instance to flush
308 * @vmhub: vmhub type
309 * @flush_type: the flush type
310 *
311 * Flush the TLB for the requested page table.
312 */
313static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
314 uint32_t vmhub, uint32_t flush_type)
315{
316 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
317 struct dma_fence *fence;
318 struct amdgpu_job *job;
319
320 int r;
321
322 /* flush hdp cache */
323 adev->hdp.funcs->flush_hdp(adev, NULL);
324
325 /* For SRIOV run time, driver shouldn't access the register through MMIO
326 * Directly use kiq to do the vm invalidation instead
327 */
328 if (adev->gfx.kiq.ring.sched.ready &&
329 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
330 down_read_trylock(&adev->reset_sem)) {
331 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
332 const unsigned eng = 17;
333 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
334 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
335 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
336
337 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
338 1 << vmid);
339
340 up_read(&adev->reset_sem);
341 return;
342 }
343
344 mutex_lock(&adev->mman.gtt_window_lock);
345
346 if (vmhub == AMDGPU_MMHUB_0) {
347 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
348 mutex_unlock(&adev->mman.gtt_window_lock);
349 return;
350 }
351
352 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
353
354 if (!adev->mman.buffer_funcs_enabled ||
355 !adev->ib_pool_ready ||
356 amdgpu_in_reset(adev) ||
357 ring->sched.ready == false) {
358 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
359 mutex_unlock(&adev->mman.gtt_window_lock);
360 return;
361 }
362
363 /* The SDMA on Navi has a bug which can theoretically result in memory
364 * corruption if an invalidation happens at the same time as an VA
365 * translation. Avoid this by doing the invalidation from the SDMA
366 * itself.
367 */
368 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
369 &job);
370 if (r)
371 goto error_alloc;
372
373 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
374 job->vm_needs_flush = true;
375 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
376 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
377 r = amdgpu_job_submit(job, &adev->mman.entity,
378 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
379 if (r)
380 goto error_submit;
381
382 mutex_unlock(&adev->mman.gtt_window_lock);
383
384 dma_fence_wait(fence, false);
385 dma_fence_put(fence);
386
387 return;
388
389error_submit:
390 amdgpu_job_free(job);
391
392error_alloc:
393 mutex_unlock(&adev->mman.gtt_window_lock);
394 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
395}
396
397/**
398 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
399 *
400 * @adev: amdgpu_device pointer
401 * @pasid: pasid to be flush
402 * @flush_type: the flush type
403 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
404 *
405 * Flush the TLB for the requested pasid.
406 */
407static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
408 uint16_t pasid, uint32_t flush_type,
409 bool all_hub)
410{
411 int vmid, i;
412 signed long r;
413 uint32_t seq;
414 uint16_t queried_pasid;
415 bool ret;
416 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
417 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
418
419 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
420 spin_lock(&adev->gfx.kiq.ring_lock);
421 /* 2 dwords flush + 8 dwords fence */
422 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
423 kiq->pmf->kiq_invalidate_tlbs(ring,
424 pasid, flush_type, all_hub);
425 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
426 if (r) {
427 amdgpu_ring_undo(ring);
428 spin_unlock(&adev->gfx.kiq.ring_lock);
429 return -ETIME;
430 }
431
432 amdgpu_ring_commit(ring);
433 spin_unlock(&adev->gfx.kiq.ring_lock);
434 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
435 if (r < 1) {
436 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
437 return -ETIME;
438 }
439
440 return 0;
441 }
442
443 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
444
445 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
446 &queried_pasid);
447 if (ret && queried_pasid == pasid) {
448 if (all_hub) {
449 for (i = 0; i < adev->num_vmhubs; i++)
450 gmc_v10_0_flush_gpu_tlb(adev, vmid,
451 i, flush_type);
452 } else {
453 gmc_v10_0_flush_gpu_tlb(adev, vmid,
454 AMDGPU_GFXHUB_0, flush_type);
455 }
456 break;
457 }
458 }
459
460 return 0;
461}
462
463static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
464 unsigned vmid, uint64_t pd_addr)
465{
466 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
467 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
468 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
469 unsigned eng = ring->vm_inv_eng;
470
471 /*
472 * It may lose gpuvm invalidate acknowldege state across power-gating
473 * off cycle, add semaphore acquire before invalidation and semaphore
474 * release after invalidation to avoid entering power gated state
475 * to WA the Issue
476 */
477
478 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
479 if (use_semaphore)
480 /* a read return value of 1 means semaphore acuqire */
481 amdgpu_ring_emit_reg_wait(ring,
482 hub->vm_inv_eng0_sem +
483 hub->eng_distance * eng, 0x1, 0x1);
484
485 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
486 (hub->ctx_addr_distance * vmid),
487 lower_32_bits(pd_addr));
488
489 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
490 (hub->ctx_addr_distance * vmid),
491 upper_32_bits(pd_addr));
492
493 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
494 hub->eng_distance * eng,
495 hub->vm_inv_eng0_ack +
496 hub->eng_distance * eng,
497 req, 1 << vmid);
498
499 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
500 if (use_semaphore)
501 /*
502 * add semaphore release after invalidation,
503 * write with 0 means semaphore release
504 */
505 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
506 hub->eng_distance * eng, 0);
507
508 return pd_addr;
509}
510
511static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
512 unsigned pasid)
513{
514 struct amdgpu_device *adev = ring->adev;
515 uint32_t reg;
516
517 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
518 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
519 else
520 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
521
522 amdgpu_ring_emit_wreg(ring, reg, pasid);
523}
524
525/*
526 * PTE format on NAVI 10:
527 * 63:59 reserved
528 * 58 reserved and for sienna_cichlid is used for MALL noalloc
529 * 57 reserved
530 * 56 F
531 * 55 L
532 * 54 reserved
533 * 53:52 SW
534 * 51 T
535 * 50:48 mtype
536 * 47:12 4k physical page base address
537 * 11:7 fragment
538 * 6 write
539 * 5 read
540 * 4 exe
541 * 3 Z
542 * 2 snooped
543 * 1 system
544 * 0 valid
545 *
546 * PDE format on NAVI 10:
547 * 63:59 block fragment size
548 * 58:55 reserved
549 * 54 P
550 * 53:48 reserved
551 * 47:6 physical base address of PD or PTE
552 * 5:3 reserved
553 * 2 C
554 * 1 system
555 * 0 valid
556 */
557
558static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
559{
560 switch (flags) {
561 case AMDGPU_VM_MTYPE_DEFAULT:
562 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
563 case AMDGPU_VM_MTYPE_NC:
564 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
565 case AMDGPU_VM_MTYPE_WC:
566 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
567 case AMDGPU_VM_MTYPE_CC:
568 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
569 case AMDGPU_VM_MTYPE_UC:
570 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
571 default:
572 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
573 }
574}
575
576static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
577 uint64_t *addr, uint64_t *flags)
578{
579 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
580 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
581 BUG_ON(*addr & 0xFFFF00000000003FULL);
582
583 if (!adev->gmc.translate_further)
584 return;
585
586 if (level == AMDGPU_VM_PDB1) {
587 /* Set the block fragment size */
588 if (!(*flags & AMDGPU_PDE_PTE))
589 *flags |= AMDGPU_PDE_BFS(0x9);
590
591 } else if (level == AMDGPU_VM_PDB0) {
592 if (*flags & AMDGPU_PDE_PTE)
593 *flags &= ~AMDGPU_PDE_PTE;
594 else
595 *flags |= AMDGPU_PTE_TF;
596 }
597}
598
599static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
600 struct amdgpu_bo_va_mapping *mapping,
601 uint64_t *flags)
602{
603 *flags &= ~AMDGPU_PTE_EXECUTABLE;
604 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
605
606 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
607 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
608
609 if (mapping->flags & AMDGPU_PTE_PRT) {
610 *flags |= AMDGPU_PTE_PRT;
611 *flags |= AMDGPU_PTE_SNOOPED;
612 *flags |= AMDGPU_PTE_LOG;
613 *flags |= AMDGPU_PTE_SYSTEM;
614 *flags &= ~AMDGPU_PTE_VALID;
615 }
616}
617
618static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
619{
620 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
621 unsigned size;
622
623 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
624 size = AMDGPU_VBIOS_VGA_ALLOCATION;
625 } else {
626 u32 viewport;
627 u32 pitch;
628
629 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
630 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
631 size = (REG_GET_FIELD(viewport,
632 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
633 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
634 4);
635 }
636
637 return size;
638}
639
640static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
641 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
642 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
643 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
644 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
645 .map_mtype = gmc_v10_0_map_mtype,
646 .get_vm_pde = gmc_v10_0_get_vm_pde,
647 .get_vm_pte = gmc_v10_0_get_vm_pte,
648 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
649};
650
651static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
652{
653 if (adev->gmc.gmc_funcs == NULL)
654 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
655}
656
657static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
658{
659 switch (adev->asic_type) {
660 case CHIP_SIENNA_CICHLID:
661 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
662 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
663 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
664 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
665 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
666 adev->umc.ras_funcs = &umc_v8_7_ras_funcs;
667 break;
668 default:
669 break;
670 }
671}
672
673
674static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
675{
676 switch (adev->asic_type) {
677 case CHIP_VANGOGH:
678 case CHIP_YELLOW_CARP:
679 adev->mmhub.funcs = &mmhub_v2_3_funcs;
680 break;
681 default:
682 adev->mmhub.funcs = &mmhub_v2_0_funcs;
683 break;
684 }
685}
686
687static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
688{
689 switch (adev->asic_type) {
690 case CHIP_SIENNA_CICHLID:
691 case CHIP_NAVY_FLOUNDER:
692 case CHIP_VANGOGH:
693 case CHIP_DIMGREY_CAVEFISH:
694 case CHIP_BEIGE_GOBY:
695 case CHIP_YELLOW_CARP:
696 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
697 break;
698 default:
699 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
700 break;
701 }
702}
703
704
705static int gmc_v10_0_early_init(void *handle)
706{
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
708
709 gmc_v10_0_set_mmhub_funcs(adev);
710 gmc_v10_0_set_gfxhub_funcs(adev);
711 gmc_v10_0_set_gmc_funcs(adev);
712 gmc_v10_0_set_irq_funcs(adev);
713 gmc_v10_0_set_umc_funcs(adev);
714
715 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
716 adev->gmc.shared_aperture_end =
717 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
718 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
719 adev->gmc.private_aperture_end =
720 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
721
722 return 0;
723}
724
725static int gmc_v10_0_late_init(void *handle)
726{
727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
728 int r;
729
730 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
731 if (r)
732 return r;
733
734 r = amdgpu_gmc_ras_late_init(adev);
735 if (r)
736 return r;
737
738 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
739}
740
741static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
742 struct amdgpu_gmc *mc)
743{
744 u64 base = 0;
745
746 base = adev->gfxhub.funcs->get_fb_location(adev);
747
748 /* add the xgmi offset of the physical node */
749 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
750
751 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
752 amdgpu_gmc_gart_location(adev, mc);
753 amdgpu_gmc_agp_location(adev, mc);
754
755 /* base offset of vram pages */
756 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
757
758 /* add the xgmi offset of the physical node */
759 adev->vm_manager.vram_base_offset +=
760 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
761}
762
763/**
764 * gmc_v10_0_mc_init - initialize the memory controller driver params
765 *
766 * @adev: amdgpu_device pointer
767 *
768 * Look up the amount of vram, vram width, and decide how to place
769 * vram and gart within the GPU's physical address space.
770 * Returns 0 for success.
771 */
772static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
773{
774 int r;
775
776 /* size in MB on si */
777 adev->gmc.mc_vram_size =
778 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
779 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
780
781 if (!(adev->flags & AMD_IS_APU)) {
782 r = amdgpu_device_resize_fb_bar(adev);
783 if (r)
784 return r;
785 }
786 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
787 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
788
789#ifdef CONFIG_X86_64
790 if (adev->flags & AMD_IS_APU) {
791 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
792 adev->gmc.aper_size = adev->gmc.real_vram_size;
793 }
794#endif
795
796 /* In case the PCI BAR is larger than the actual amount of vram */
797 adev->gmc.visible_vram_size = adev->gmc.aper_size;
798 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
799 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
800
801 /* set the gart size */
802 if (amdgpu_gart_size == -1) {
803 switch (adev->asic_type) {
804 case CHIP_NAVI10:
805 case CHIP_NAVI14:
806 case CHIP_NAVI12:
807 case CHIP_SIENNA_CICHLID:
808 case CHIP_NAVY_FLOUNDER:
809 case CHIP_VANGOGH:
810 case CHIP_DIMGREY_CAVEFISH:
811 case CHIP_BEIGE_GOBY:
812 case CHIP_YELLOW_CARP:
813 default:
814 adev->gmc.gart_size = 512ULL << 20;
815 break;
816 }
817 } else
818 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
819
820 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
821
822 return 0;
823}
824
825static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
826{
827 int r;
828
829 if (adev->gart.bo) {
830 WARN(1, "NAVI10 PCIE GART already initialized\n");
831 return 0;
832 }
833
834 /* Initialize common gart structure */
835 r = amdgpu_gart_init(adev);
836 if (r)
837 return r;
838
839 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
840 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
841 AMDGPU_PTE_EXECUTABLE;
842
843 return amdgpu_gart_table_vram_alloc(adev);
844}
845
846static int gmc_v10_0_sw_init(void *handle)
847{
848 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
850
851 adev->gfxhub.funcs->init(adev);
852
853 adev->mmhub.funcs->init(adev);
854
855 spin_lock_init(&adev->gmc.invalidate_lock);
856
857 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
858 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
859 adev->gmc.vram_width = 64;
860 } else if (amdgpu_emu_mode == 1) {
861 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
862 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
863 } else {
864 r = amdgpu_atomfirmware_get_vram_info(adev,
865 &vram_width, &vram_type, &vram_vendor);
866 adev->gmc.vram_width = vram_width;
867
868 adev->gmc.vram_type = vram_type;
869 adev->gmc.vram_vendor = vram_vendor;
870 }
871
872 switch (adev->asic_type) {
873 case CHIP_NAVI10:
874 case CHIP_NAVI14:
875 case CHIP_NAVI12:
876 case CHIP_SIENNA_CICHLID:
877 case CHIP_NAVY_FLOUNDER:
878 case CHIP_VANGOGH:
879 case CHIP_DIMGREY_CAVEFISH:
880 case CHIP_BEIGE_GOBY:
881 case CHIP_YELLOW_CARP:
882 adev->num_vmhubs = 2;
883 /*
884 * To fulfill 4-level page support,
885 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
886 * block size 512 (9bit)
887 */
888 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
889 break;
890 default:
891 break;
892 }
893
894 /* This interrupt is VMC page fault.*/
895 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
896 VMC_1_0__SRCID__VM_FAULT,
897 &adev->gmc.vm_fault);
898
899 if (r)
900 return r;
901
902 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
903 UTCL2_1_0__SRCID__FAULT,
904 &adev->gmc.vm_fault);
905 if (r)
906 return r;
907
908 if (!amdgpu_sriov_vf(adev)) {
909 /* interrupt sent to DF. */
910 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
911 &adev->gmc.ecc_irq);
912 if (r)
913 return r;
914 }
915
916 /*
917 * Set the internal MC address mask This is the max address of the GPU's
918 * internal address space.
919 */
920 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
921
922 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
923 if (r) {
924 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
925 return r;
926 }
927
928 if (adev->gmc.xgmi.supported) {
929 r = adev->gfxhub.funcs->get_xgmi_info(adev);
930 if (r)
931 return r;
932 }
933
934 r = gmc_v10_0_mc_init(adev);
935 if (r)
936 return r;
937
938 amdgpu_gmc_get_vbios_allocations(adev);
939 amdgpu_gmc_get_reserved_allocation(adev);
940
941 /* Memory manager */
942 r = amdgpu_bo_init(adev);
943 if (r)
944 return r;
945
946 r = gmc_v10_0_gart_init(adev);
947 if (r)
948 return r;
949
950 /*
951 * number of VMs
952 * VMID 0 is reserved for System
953 * amdgpu graphics/compute will use VMIDs 1-7
954 * amdkfd will use VMIDs 8-15
955 */
956 adev->vm_manager.first_kfd_vmid = 8;
957
958 amdgpu_vm_manager_init(adev);
959
960 return 0;
961}
962
963/**
964 * gmc_v10_0_gart_fini - vm fini callback
965 *
966 * @adev: amdgpu_device pointer
967 *
968 * Tears down the driver GART/VM setup (CIK).
969 */
970static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
971{
972 amdgpu_gart_table_vram_free(adev);
973}
974
975static int gmc_v10_0_sw_fini(void *handle)
976{
977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
978
979 amdgpu_vm_manager_fini(adev);
980 gmc_v10_0_gart_fini(adev);
981 amdgpu_gem_force_release(adev);
982 amdgpu_bo_fini(adev);
983
984 return 0;
985}
986
987static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
988{
989 switch (adev->asic_type) {
990 case CHIP_NAVI10:
991 case CHIP_NAVI14:
992 case CHIP_NAVI12:
993 case CHIP_SIENNA_CICHLID:
994 case CHIP_NAVY_FLOUNDER:
995 case CHIP_VANGOGH:
996 case CHIP_DIMGREY_CAVEFISH:
997 case CHIP_BEIGE_GOBY:
998 case CHIP_YELLOW_CARP:
999 break;
1000 default:
1001 break;
1002 }
1003}
1004
1005/**
1006 * gmc_v10_0_gart_enable - gart enable
1007 *
1008 * @adev: amdgpu_device pointer
1009 */
1010static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1011{
1012 int r;
1013 bool value;
1014
1015 if (adev->gart.bo == NULL) {
1016 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1017 return -EINVAL;
1018 }
1019
1020 r = amdgpu_gart_table_vram_pin(adev);
1021 if (r)
1022 return r;
1023
1024 r = adev->gfxhub.funcs->gart_enable(adev);
1025 if (r)
1026 return r;
1027
1028 r = adev->mmhub.funcs->gart_enable(adev);
1029 if (r)
1030 return r;
1031
1032 adev->hdp.funcs->init_registers(adev);
1033
1034 /* Flush HDP after it is initialized */
1035 adev->hdp.funcs->flush_hdp(adev, NULL);
1036
1037 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1038 false : true;
1039
1040 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1041 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1042 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1043 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1044
1045 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1046 (unsigned)(adev->gmc.gart_size >> 20),
1047 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1048
1049 adev->gart.ready = true;
1050
1051 return 0;
1052}
1053
1054static int gmc_v10_0_hw_init(void *handle)
1055{
1056 int r;
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1058
1059 /* The sequence of these two function calls matters.*/
1060 gmc_v10_0_init_golden_registers(adev);
1061
1062 /*
1063 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1064 * register setup within GMC, or else system hang when harvesting SA.
1065 */
1066 if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1067 adev->gfxhub.funcs->utcl2_harvest(adev);
1068
1069 r = gmc_v10_0_gart_enable(adev);
1070 if (r)
1071 return r;
1072
1073 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1074 adev->umc.funcs->init_registers(adev);
1075
1076 return 0;
1077}
1078
1079/**
1080 * gmc_v10_0_gart_disable - gart disable
1081 *
1082 * @adev: amdgpu_device pointer
1083 *
1084 * This disables all VM page table.
1085 */
1086static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1087{
1088 adev->gfxhub.funcs->gart_disable(adev);
1089 adev->mmhub.funcs->gart_disable(adev);
1090 amdgpu_gart_table_vram_unpin(adev);
1091}
1092
1093static int gmc_v10_0_hw_fini(void *handle)
1094{
1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097 gmc_v10_0_gart_disable(adev);
1098
1099 if (amdgpu_sriov_vf(adev)) {
1100 /* full access mode, so don't touch any GMC register */
1101 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1102 return 0;
1103 }
1104
1105 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1106 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1107
1108 return 0;
1109}
1110
1111static int gmc_v10_0_suspend(void *handle)
1112{
1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115 gmc_v10_0_hw_fini(adev);
1116
1117 return 0;
1118}
1119
1120static int gmc_v10_0_resume(void *handle)
1121{
1122 int r;
1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124
1125 r = gmc_v10_0_hw_init(adev);
1126 if (r)
1127 return r;
1128
1129 amdgpu_vmid_reset_all(adev);
1130
1131 return 0;
1132}
1133
1134static bool gmc_v10_0_is_idle(void *handle)
1135{
1136 /* MC is always ready in GMC v10.*/
1137 return true;
1138}
1139
1140static int gmc_v10_0_wait_for_idle(void *handle)
1141{
1142 /* There is no need to wait for MC idle in GMC v10.*/
1143 return 0;
1144}
1145
1146static int gmc_v10_0_soft_reset(void *handle)
1147{
1148 return 0;
1149}
1150
1151static int gmc_v10_0_set_clockgating_state(void *handle,
1152 enum amd_clockgating_state state)
1153{
1154 int r;
1155 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
1157 r = adev->mmhub.funcs->set_clockgating(adev, state);
1158 if (r)
1159 return r;
1160
1161 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1162 adev->asic_type <= CHIP_YELLOW_CARP)
1163 return athub_v2_1_set_clockgating(adev, state);
1164 else
1165 return athub_v2_0_set_clockgating(adev, state);
1166}
1167
1168static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1169{
1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171
1172 adev->mmhub.funcs->get_clockgating(adev, flags);
1173
1174 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1175 adev->asic_type <= CHIP_YELLOW_CARP)
1176 athub_v2_1_get_clockgating(adev, flags);
1177 else
1178 athub_v2_0_get_clockgating(adev, flags);
1179}
1180
1181static int gmc_v10_0_set_powergating_state(void *handle,
1182 enum amd_powergating_state state)
1183{
1184 return 0;
1185}
1186
1187const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1188 .name = "gmc_v10_0",
1189 .early_init = gmc_v10_0_early_init,
1190 .late_init = gmc_v10_0_late_init,
1191 .sw_init = gmc_v10_0_sw_init,
1192 .sw_fini = gmc_v10_0_sw_fini,
1193 .hw_init = gmc_v10_0_hw_init,
1194 .hw_fini = gmc_v10_0_hw_fini,
1195 .suspend = gmc_v10_0_suspend,
1196 .resume = gmc_v10_0_resume,
1197 .is_idle = gmc_v10_0_is_idle,
1198 .wait_for_idle = gmc_v10_0_wait_for_idle,
1199 .soft_reset = gmc_v10_0_soft_reset,
1200 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1201 .set_powergating_state = gmc_v10_0_set_powergating_state,
1202 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1203};
1204
1205const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1206{
1207 .type = AMD_IP_BLOCK_TYPE_GMC,
1208 .major = 10,
1209 .minor = 0,
1210 .rev = 0,
1211 .funcs = &gmc_v10_0_ip_funcs,
1212};
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/pci.h>
25
26#include <drm/drm_cache.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atomfirmware.h"
30#include "gmc_v10_0.h"
31#include "umc_v8_7.h"
32
33#include "athub/athub_2_0_0_sh_mask.h"
34#include "athub/athub_2_0_0_offset.h"
35#include "dcn/dcn_2_0_0_offset.h"
36#include "dcn/dcn_2_0_0_sh_mask.h"
37#include "oss/osssys_5_0_0_offset.h"
38#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
39#include "navi10_enum.h"
40
41#include "soc15.h"
42#include "soc15d.h"
43#include "soc15_common.h"
44
45#include "nbio_v2_3.h"
46
47#include "gfxhub_v2_0.h"
48#include "gfxhub_v2_1.h"
49#include "mmhub_v2_0.h"
50#include "mmhub_v2_3.h"
51#include "athub_v2_0.h"
52#include "athub_v2_1.h"
53
54static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
55 struct amdgpu_irq_src *src,
56 unsigned int type,
57 enum amdgpu_interrupt_state state)
58{
59 return 0;
60}
61
62static int
63gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
64 struct amdgpu_irq_src *src, unsigned int type,
65 enum amdgpu_interrupt_state state)
66{
67 switch (state) {
68 case AMDGPU_IRQ_STATE_DISABLE:
69 /* MM HUB */
70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
71 /* GFX HUB */
72 /* This works because this interrupt is only
73 * enabled at init/resume and disabled in
74 * fini/suspend, so the overall state doesn't
75 * change over the course of suspend/resume.
76 */
77 if (!adev->in_s0ix)
78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
79 break;
80 case AMDGPU_IRQ_STATE_ENABLE:
81 /* MM HUB */
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
83 /* GFX HUB */
84 /* This works because this interrupt is only
85 * enabled at init/resume and disabled in
86 * fini/suspend, so the overall state doesn't
87 * change over the course of suspend/resume.
88 */
89 if (!adev->in_s0ix)
90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
91 break;
92 default:
93 break;
94 }
95
96 return 0;
97}
98
99static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
100 struct amdgpu_irq_src *source,
101 struct amdgpu_iv_entry *entry)
102{
103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ?
104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);
105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index];
106 bool retry_fault = !!(entry->src_data[1] & 0x80);
107 bool write_fault = !!(entry->src_data[1] & 0x20);
108 struct amdgpu_task_info task_info;
109 uint32_t status = 0;
110 u64 addr;
111
112 addr = (u64)entry->src_data[0] << 12;
113 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
114
115 if (retry_fault) {
116 /* Returning 1 here also prevents sending the IV to the KFD */
117
118 /* Process it onyl if it's the first fault for this address */
119 if (entry->ih != &adev->irq.ih_soft &&
120 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
121 entry->timestamp))
122 return 1;
123
124 /* Delegate it to a different ring if the hardware hasn't
125 * already done it.
126 */
127 if (entry->ih == &adev->irq.ih) {
128 amdgpu_irq_delegate(adev, entry, 8);
129 return 1;
130 }
131
132 /* Try to handle the recoverable page faults by filling page
133 * tables
134 */
135 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault))
136 return 1;
137 }
138
139 if (!amdgpu_sriov_vf(adev)) {
140 /*
141 * Issue a dummy read to wait for the status register to
142 * be updated to avoid reading an incorrect value due to
143 * the new fast GRBM interface.
144 */
145 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
146 (amdgpu_ip_version(adev, GC_HWIP, 0) <
147 IP_VERSION(10, 3, 0)))
148 RREG32(hub->vm_l2_pro_fault_status);
149
150 status = RREG32(hub->vm_l2_pro_fault_status);
151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
152
153 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status,
154 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0));
155 }
156
157 if (!printk_ratelimit())
158 return 0;
159
160 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
161 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
162
163 dev_err(adev->dev,
164 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
165 entry->vmid_src ? "mmhub" : "gfxhub",
166 entry->src_id, entry->ring_id, entry->vmid,
167 entry->pasid, task_info.process_name, task_info.tgid,
168 task_info.task_name, task_info.pid);
169 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n",
170 addr, entry->client_id,
171 soc15_ih_clientid_name[entry->client_id]);
172
173 if (!amdgpu_sriov_vf(adev))
174 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
175 status);
176
177 return 0;
178}
179
180static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
181 .set = gmc_v10_0_vm_fault_interrupt_state,
182 .process = gmc_v10_0_process_interrupt,
183};
184
185static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
186 .set = gmc_v10_0_ecc_interrupt_state,
187 .process = amdgpu_umc_process_ecc_irq,
188};
189
190static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
191{
192 adev->gmc.vm_fault.num_types = 1;
193 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
194
195 if (!amdgpu_sriov_vf(adev)) {
196 adev->gmc.ecc_irq.num_types = 1;
197 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
198 }
199}
200
201/**
202 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
203 *
204 * @adev: amdgpu_device pointer
205 * @vmhub: vmhub type
206 *
207 */
208static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
209 uint32_t vmhub)
210{
211 return ((vmhub == AMDGPU_MMHUB0(0)) &&
212 (!amdgpu_sriov_vf(adev)));
213}
214
215static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
216 struct amdgpu_device *adev,
217 uint8_t vmid, uint16_t *p_pasid)
218{
219 uint32_t value;
220
221 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
222 + vmid);
223 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
224
225 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
226}
227
228/*
229 * GART
230 * VMID 0 is the physical GPU addresses as used by the kernel.
231 * VMIDs 1-15 are used for userspace clients and are handled
232 * by the amdgpu vm/hsa code.
233 */
234
235/**
236 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
237 *
238 * @adev: amdgpu_device pointer
239 * @vmid: vm instance to flush
240 * @vmhub: vmhub type
241 * @flush_type: the flush type
242 *
243 * Flush the TLB for the requested page table.
244 */
245static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
246 uint32_t vmhub, uint32_t flush_type)
247{
248 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
249 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
250 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
251 /* Use register 17 for GART */
252 const unsigned int eng = 17;
253 unsigned char hub_ip = 0;
254 u32 sem, req, ack;
255 unsigned int i;
256 u32 tmp;
257
258 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
259 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
260 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
261
262 /* flush hdp cache */
263 adev->hdp.funcs->flush_hdp(adev, NULL);
264
265 /* For SRIOV run time, driver shouldn't access the register through MMIO
266 * Directly use kiq to do the vm invalidation instead
267 */
268 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&
269 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
270 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
271 1 << vmid, GET_INST(GC, 0));
272 return;
273 }
274
275 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP;
276
277 spin_lock(&adev->gmc.invalidate_lock);
278 /*
279 * It may lose gpuvm invalidate acknowldege state across power-gating
280 * off cycle, add semaphore acquire before invalidation and semaphore
281 * release after invalidation to avoid entering power gated state
282 * to WA the Issue
283 */
284
285 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
286 if (use_semaphore) {
287 for (i = 0; i < adev->usec_timeout; i++) {
288 /* a read return value of 1 means semaphore acuqire */
289 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip);
290 if (tmp & 0x1)
291 break;
292 udelay(1);
293 }
294
295 if (i >= adev->usec_timeout)
296 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
297 }
298
299 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip);
300
301 /*
302 * Issue a dummy read to wait for the ACK register to be cleared
303 * to avoid a false ACK due to the new fast GRBM interface.
304 */
305 if ((vmhub == AMDGPU_GFXHUB(0)) &&
306 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0)))
307 RREG32_RLC_NO_KIQ(req, hub_ip);
308
309 /* Wait for ACK with a delay.*/
310 for (i = 0; i < adev->usec_timeout; i++) {
311 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip);
312 tmp &= 1 << vmid;
313 if (tmp)
314 break;
315
316 udelay(1);
317 }
318
319 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
320 if (use_semaphore)
321 WREG32_RLC_NO_KIQ(sem, 0, hub_ip);
322
323 spin_unlock(&adev->gmc.invalidate_lock);
324
325 if (i >= adev->usec_timeout)
326 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n",
327 vmhub);
328}
329
330/**
331 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
332 *
333 * @adev: amdgpu_device pointer
334 * @pasid: pasid to be flush
335 * @flush_type: the flush type
336 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
337 * @inst: is used to select which instance of KIQ to use for the invalidation
338 *
339 * Flush the TLB for the requested pasid.
340 */
341static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
342 uint16_t pasid, uint32_t flush_type,
343 bool all_hub, uint32_t inst)
344{
345 uint16_t queried;
346 int vmid, i;
347
348 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
349 bool valid;
350
351 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
352 &queried);
353 if (!valid || queried != pasid)
354 continue;
355
356 if (all_hub) {
357 for_each_set_bit(i, adev->vmhubs_mask,
358 AMDGPU_MAX_VMHUBS)
359 gmc_v10_0_flush_gpu_tlb(adev, vmid, i,
360 flush_type);
361 } else {
362 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),
363 flush_type);
364 }
365 }
366}
367
368static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
369 unsigned int vmid, uint64_t pd_addr)
370{
371 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
372 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
373 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
374 unsigned int eng = ring->vm_inv_eng;
375
376 /*
377 * It may lose gpuvm invalidate acknowldege state across power-gating
378 * off cycle, add semaphore acquire before invalidation and semaphore
379 * release after invalidation to avoid entering power gated state
380 * to WA the Issue
381 */
382
383 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
384 if (use_semaphore)
385 /* a read return value of 1 means semaphore acuqire */
386 amdgpu_ring_emit_reg_wait(ring,
387 hub->vm_inv_eng0_sem +
388 hub->eng_distance * eng, 0x1, 0x1);
389
390 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
391 (hub->ctx_addr_distance * vmid),
392 lower_32_bits(pd_addr));
393
394 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
395 (hub->ctx_addr_distance * vmid),
396 upper_32_bits(pd_addr));
397
398 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
399 hub->eng_distance * eng,
400 hub->vm_inv_eng0_ack +
401 hub->eng_distance * eng,
402 req, 1 << vmid);
403
404 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
405 if (use_semaphore)
406 /*
407 * add semaphore release after invalidation,
408 * write with 0 means semaphore release
409 */
410 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
411 hub->eng_distance * eng, 0);
412
413 return pd_addr;
414}
415
416static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
417 unsigned int pasid)
418{
419 struct amdgpu_device *adev = ring->adev;
420 uint32_t reg;
421
422 /* MES fw manages IH_VMID_x_LUT updating */
423 if (ring->is_mes_queue)
424 return;
425
426 if (ring->vm_hub == AMDGPU_GFXHUB(0))
427 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
428 else
429 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
430
431 amdgpu_ring_emit_wreg(ring, reg, pasid);
432}
433
434/*
435 * PTE format on NAVI 10:
436 * 63:59 reserved
437 * 58 reserved and for sienna_cichlid is used for MALL noalloc
438 * 57 reserved
439 * 56 F
440 * 55 L
441 * 54 reserved
442 * 53:52 SW
443 * 51 T
444 * 50:48 mtype
445 * 47:12 4k physical page base address
446 * 11:7 fragment
447 * 6 write
448 * 5 read
449 * 4 exe
450 * 3 Z
451 * 2 snooped
452 * 1 system
453 * 0 valid
454 *
455 * PDE format on NAVI 10:
456 * 63:59 block fragment size
457 * 58:55 reserved
458 * 54 P
459 * 53:48 reserved
460 * 47:6 physical base address of PD or PTE
461 * 5:3 reserved
462 * 2 C
463 * 1 system
464 * 0 valid
465 */
466
467static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
468{
469 switch (flags) {
470 case AMDGPU_VM_MTYPE_DEFAULT:
471 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
472 case AMDGPU_VM_MTYPE_NC:
473 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
474 case AMDGPU_VM_MTYPE_WC:
475 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
476 case AMDGPU_VM_MTYPE_CC:
477 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
478 case AMDGPU_VM_MTYPE_UC:
479 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
480 default:
481 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
482 }
483}
484
485static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
486 uint64_t *addr, uint64_t *flags)
487{
488 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
489 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
490 BUG_ON(*addr & 0xFFFF00000000003FULL);
491
492 if (!adev->gmc.translate_further)
493 return;
494
495 if (level == AMDGPU_VM_PDB1) {
496 /* Set the block fragment size */
497 if (!(*flags & AMDGPU_PDE_PTE))
498 *flags |= AMDGPU_PDE_BFS(0x9);
499
500 } else if (level == AMDGPU_VM_PDB0) {
501 if (*flags & AMDGPU_PDE_PTE)
502 *flags &= ~AMDGPU_PDE_PTE;
503 else
504 *flags |= AMDGPU_PTE_TF;
505 }
506}
507
508static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
509 struct amdgpu_bo_va_mapping *mapping,
510 uint64_t *flags)
511{
512 struct amdgpu_bo *bo = mapping->bo_va->base.bo;
513
514 *flags &= ~AMDGPU_PTE_EXECUTABLE;
515 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
516
517 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
518 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
519
520 *flags &= ~AMDGPU_PTE_NOALLOC;
521 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
522
523 if (mapping->flags & AMDGPU_PTE_PRT) {
524 *flags |= AMDGPU_PTE_PRT;
525 *flags |= AMDGPU_PTE_SNOOPED;
526 *flags |= AMDGPU_PTE_LOG;
527 *flags |= AMDGPU_PTE_SYSTEM;
528 *flags &= ~AMDGPU_PTE_VALID;
529 }
530
531 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
532 AMDGPU_GEM_CREATE_EXT_COHERENT |
533 AMDGPU_GEM_CREATE_UNCACHED))
534 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
535 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
536}
537
538static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
539{
540 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
541 unsigned int size;
542
543 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
544 size = AMDGPU_VBIOS_VGA_ALLOCATION;
545 } else {
546 u32 viewport;
547 u32 pitch;
548
549 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
550 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
551 size = (REG_GET_FIELD(viewport,
552 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
553 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
554 4);
555 }
556
557 return size;
558}
559
560static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
561 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
562 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
563 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
564 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
565 .map_mtype = gmc_v10_0_map_mtype,
566 .get_vm_pde = gmc_v10_0_get_vm_pde,
567 .get_vm_pte = gmc_v10_0_get_vm_pte,
568 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
569};
570
571static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
572{
573 if (adev->gmc.gmc_funcs == NULL)
574 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
575}
576
577static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
578{
579 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
580 case IP_VERSION(8, 7, 0):
581 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
582 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
583 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
584 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
585 adev->umc.retire_unit = 1;
586 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
587 adev->umc.ras = &umc_v8_7_ras;
588 break;
589 default:
590 break;
591 }
592}
593
594static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
595{
596 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
597 case IP_VERSION(2, 3, 0):
598 case IP_VERSION(2, 4, 0):
599 case IP_VERSION(2, 4, 1):
600 adev->mmhub.funcs = &mmhub_v2_3_funcs;
601 break;
602 default:
603 adev->mmhub.funcs = &mmhub_v2_0_funcs;
604 break;
605 }
606}
607
608static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
609{
610 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
611 case IP_VERSION(10, 3, 0):
612 case IP_VERSION(10, 3, 2):
613 case IP_VERSION(10, 3, 1):
614 case IP_VERSION(10, 3, 4):
615 case IP_VERSION(10, 3, 5):
616 case IP_VERSION(10, 3, 6):
617 case IP_VERSION(10, 3, 3):
618 case IP_VERSION(10, 3, 7):
619 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
620 break;
621 default:
622 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
623 break;
624 }
625}
626
627
628static int gmc_v10_0_early_init(void *handle)
629{
630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
631
632 gmc_v10_0_set_mmhub_funcs(adev);
633 gmc_v10_0_set_gfxhub_funcs(adev);
634 gmc_v10_0_set_gmc_funcs(adev);
635 gmc_v10_0_set_irq_funcs(adev);
636 gmc_v10_0_set_umc_funcs(adev);
637
638 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
639 adev->gmc.shared_aperture_end =
640 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
641 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
642 adev->gmc.private_aperture_end =
643 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
644 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
645
646 return 0;
647}
648
649static int gmc_v10_0_late_init(void *handle)
650{
651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
652 int r;
653
654 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
655 if (r)
656 return r;
657
658 r = amdgpu_gmc_ras_late_init(adev);
659 if (r)
660 return r;
661
662 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
663}
664
665static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
666 struct amdgpu_gmc *mc)
667{
668 u64 base = 0;
669
670 base = adev->gfxhub.funcs->get_fb_location(adev);
671
672 /* add the xgmi offset of the physical node */
673 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
674
675 amdgpu_gmc_set_agp_default(adev, mc);
676 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
677 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
678 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
679 amdgpu_gmc_agp_location(adev, mc);
680
681 /* base offset of vram pages */
682 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
683
684 /* add the xgmi offset of the physical node */
685 adev->vm_manager.vram_base_offset +=
686 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
687}
688
689/**
690 * gmc_v10_0_mc_init - initialize the memory controller driver params
691 *
692 * @adev: amdgpu_device pointer
693 *
694 * Look up the amount of vram, vram width, and decide how to place
695 * vram and gart within the GPU's physical address space.
696 * Returns 0 for success.
697 */
698static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
699{
700 int r;
701
702 /* size in MB on si */
703 adev->gmc.mc_vram_size =
704 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
705 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
706
707 if (!(adev->flags & AMD_IS_APU)) {
708 r = amdgpu_device_resize_fb_bar(adev);
709 if (r)
710 return r;
711 }
712 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
713 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
714
715#ifdef CONFIG_X86_64
716 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
717 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
718 adev->gmc.aper_size = adev->gmc.real_vram_size;
719 }
720#endif
721
722 adev->gmc.visible_vram_size = adev->gmc.aper_size;
723
724 /* set the gart size */
725 if (amdgpu_gart_size == -1) {
726 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
727 default:
728 adev->gmc.gart_size = 512ULL << 20;
729 break;
730 case IP_VERSION(10, 3, 1): /* DCE SG support */
731 case IP_VERSION(10, 3, 3): /* DCE SG support */
732 case IP_VERSION(10, 3, 6): /* DCE SG support */
733 case IP_VERSION(10, 3, 7): /* DCE SG support */
734 adev->gmc.gart_size = 1024ULL << 20;
735 break;
736 }
737 } else {
738 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
739 }
740
741 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
742
743 return 0;
744}
745
746static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
747{
748 int r;
749
750 if (adev->gart.bo) {
751 WARN(1, "NAVI10 PCIE GART already initialized\n");
752 return 0;
753 }
754
755 /* Initialize common gart structure */
756 r = amdgpu_gart_init(adev);
757 if (r)
758 return r;
759
760 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
761 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
762 AMDGPU_PTE_EXECUTABLE;
763
764 return amdgpu_gart_table_vram_alloc(adev);
765}
766
767static int gmc_v10_0_sw_init(void *handle)
768{
769 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 adev->gfxhub.funcs->init(adev);
773
774 adev->mmhub.funcs->init(adev);
775
776 spin_lock_init(&adev->gmc.invalidate_lock);
777
778 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
779 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
780 adev->gmc.vram_width = 64;
781 } else if (amdgpu_emu_mode == 1) {
782 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
783 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
784 } else {
785 r = amdgpu_atomfirmware_get_vram_info(adev,
786 &vram_width, &vram_type, &vram_vendor);
787 adev->gmc.vram_width = vram_width;
788
789 adev->gmc.vram_type = vram_type;
790 adev->gmc.vram_vendor = vram_vendor;
791 }
792
793 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
794 case IP_VERSION(10, 3, 0):
795 adev->gmc.mall_size = 128 * 1024 * 1024;
796 break;
797 case IP_VERSION(10, 3, 2):
798 adev->gmc.mall_size = 96 * 1024 * 1024;
799 break;
800 case IP_VERSION(10, 3, 4):
801 adev->gmc.mall_size = 32 * 1024 * 1024;
802 break;
803 case IP_VERSION(10, 3, 5):
804 adev->gmc.mall_size = 16 * 1024 * 1024;
805 break;
806 default:
807 adev->gmc.mall_size = 0;
808 break;
809 }
810
811 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
812 case IP_VERSION(10, 1, 10):
813 case IP_VERSION(10, 1, 1):
814 case IP_VERSION(10, 1, 2):
815 case IP_VERSION(10, 1, 3):
816 case IP_VERSION(10, 1, 4):
817 case IP_VERSION(10, 3, 0):
818 case IP_VERSION(10, 3, 2):
819 case IP_VERSION(10, 3, 1):
820 case IP_VERSION(10, 3, 4):
821 case IP_VERSION(10, 3, 5):
822 case IP_VERSION(10, 3, 6):
823 case IP_VERSION(10, 3, 3):
824 case IP_VERSION(10, 3, 7):
825 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
826 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
827 /*
828 * To fulfill 4-level page support,
829 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
830 * block size 512 (9bit)
831 */
832 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
833 break;
834 default:
835 break;
836 }
837
838 /* This interrupt is VMC page fault.*/
839 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
840 VMC_1_0__SRCID__VM_FAULT,
841 &adev->gmc.vm_fault);
842
843 if (r)
844 return r;
845
846 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
847 UTCL2_1_0__SRCID__FAULT,
848 &adev->gmc.vm_fault);
849 if (r)
850 return r;
851
852 if (!amdgpu_sriov_vf(adev)) {
853 /* interrupt sent to DF. */
854 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
855 &adev->gmc.ecc_irq);
856 if (r)
857 return r;
858 }
859
860 /*
861 * Set the internal MC address mask This is the max address of the GPU's
862 * internal address space.
863 */
864 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
865
866 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
867 if (r) {
868 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
869 return r;
870 }
871
872 adev->need_swiotlb = drm_need_swiotlb(44);
873
874 r = gmc_v10_0_mc_init(adev);
875 if (r)
876 return r;
877
878 amdgpu_gmc_get_vbios_allocations(adev);
879
880 /* Memory manager */
881 r = amdgpu_bo_init(adev);
882 if (r)
883 return r;
884
885 r = gmc_v10_0_gart_init(adev);
886 if (r)
887 return r;
888
889 /*
890 * number of VMs
891 * VMID 0 is reserved for System
892 * amdgpu graphics/compute will use VMIDs 1-7
893 * amdkfd will use VMIDs 8-15
894 */
895 adev->vm_manager.first_kfd_vmid = 8;
896
897 amdgpu_vm_manager_init(adev);
898
899 r = amdgpu_gmc_ras_sw_init(adev);
900 if (r)
901 return r;
902
903 return 0;
904}
905
906/**
907 * gmc_v10_0_gart_fini - vm fini callback
908 *
909 * @adev: amdgpu_device pointer
910 *
911 * Tears down the driver GART/VM setup (CIK).
912 */
913static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
914{
915 amdgpu_gart_table_vram_free(adev);
916}
917
918static int gmc_v10_0_sw_fini(void *handle)
919{
920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
921
922 amdgpu_vm_manager_fini(adev);
923 gmc_v10_0_gart_fini(adev);
924 amdgpu_gem_force_release(adev);
925 amdgpu_bo_fini(adev);
926
927 return 0;
928}
929
930static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
931{
932}
933
934/**
935 * gmc_v10_0_gart_enable - gart enable
936 *
937 * @adev: amdgpu_device pointer
938 */
939static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
940{
941 int r;
942 bool value;
943
944 if (adev->gart.bo == NULL) {
945 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
946 return -EINVAL;
947 }
948
949 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
950
951 if (!adev->in_s0ix) {
952 r = adev->gfxhub.funcs->gart_enable(adev);
953 if (r)
954 return r;
955 }
956
957 r = adev->mmhub.funcs->gart_enable(adev);
958 if (r)
959 return r;
960
961 adev->hdp.funcs->init_registers(adev);
962
963 /* Flush HDP after it is initialized */
964 adev->hdp.funcs->flush_hdp(adev, NULL);
965
966 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
967 false : true;
968
969 if (!adev->in_s0ix)
970 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
971 adev->mmhub.funcs->set_fault_enable_default(adev, value);
972 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
973 if (!adev->in_s0ix)
974 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
975
976 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
977 (unsigned int)(adev->gmc.gart_size >> 20),
978 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
979
980 return 0;
981}
982
983static int gmc_v10_0_hw_init(void *handle)
984{
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
986 int r;
987
988 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;
989
990 /* The sequence of these two function calls matters.*/
991 gmc_v10_0_init_golden_registers(adev);
992
993 /*
994 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
995 * register setup within GMC, or else system hang when harvesting SA.
996 */
997 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
998 adev->gfxhub.funcs->utcl2_harvest(adev);
999
1000 r = gmc_v10_0_gart_enable(adev);
1001 if (r)
1002 return r;
1003
1004 if (amdgpu_emu_mode == 1) {
1005 r = amdgpu_gmc_vram_checking(adev);
1006 if (r)
1007 return r;
1008 }
1009
1010 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1011 adev->umc.funcs->init_registers(adev);
1012
1013 return 0;
1014}
1015
1016/**
1017 * gmc_v10_0_gart_disable - gart disable
1018 *
1019 * @adev: amdgpu_device pointer
1020 *
1021 * This disables all VM page table.
1022 */
1023static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1024{
1025 if (!adev->in_s0ix)
1026 adev->gfxhub.funcs->gart_disable(adev);
1027 adev->mmhub.funcs->gart_disable(adev);
1028}
1029
1030static int gmc_v10_0_hw_fini(void *handle)
1031{
1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033
1034 gmc_v10_0_gart_disable(adev);
1035
1036 if (amdgpu_sriov_vf(adev)) {
1037 /* full access mode, so don't touch any GMC register */
1038 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1039 return 0;
1040 }
1041
1042 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1043
1044 if (adev->gmc.ecc_irq.funcs &&
1045 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
1046 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1047
1048 return 0;
1049}
1050
1051static int gmc_v10_0_suspend(void *handle)
1052{
1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055 gmc_v10_0_hw_fini(adev);
1056
1057 return 0;
1058}
1059
1060static int gmc_v10_0_resume(void *handle)
1061{
1062 int r;
1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064
1065 r = gmc_v10_0_hw_init(adev);
1066 if (r)
1067 return r;
1068
1069 amdgpu_vmid_reset_all(adev);
1070
1071 return 0;
1072}
1073
1074static bool gmc_v10_0_is_idle(void *handle)
1075{
1076 /* MC is always ready in GMC v10.*/
1077 return true;
1078}
1079
1080static int gmc_v10_0_wait_for_idle(void *handle)
1081{
1082 /* There is no need to wait for MC idle in GMC v10.*/
1083 return 0;
1084}
1085
1086static int gmc_v10_0_soft_reset(void *handle)
1087{
1088 return 0;
1089}
1090
1091static int gmc_v10_0_set_clockgating_state(void *handle,
1092 enum amd_clockgating_state state)
1093{
1094 int r;
1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097 /*
1098 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
1099 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not
1100 * seen any issue on the DF 3.0.2 series platform.
1101 */
1102 if (adev->in_s0ix &&
1103 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) {
1104 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");
1105 return 0;
1106 }
1107
1108 r = adev->mmhub.funcs->set_clockgating(adev, state);
1109 if (r)
1110 return r;
1111
1112 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0))
1113 return athub_v2_1_set_clockgating(adev, state);
1114 else
1115 return athub_v2_0_set_clockgating(adev, state);
1116}
1117
1118static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
1119{
1120 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) ||
1123 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4))
1124 return;
1125
1126 adev->mmhub.funcs->get_clockgating(adev, flags);
1127
1128 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0))
1129 athub_v2_1_get_clockgating(adev, flags);
1130 else
1131 athub_v2_0_get_clockgating(adev, flags);
1132}
1133
1134static int gmc_v10_0_set_powergating_state(void *handle,
1135 enum amd_powergating_state state)
1136{
1137 return 0;
1138}
1139
1140const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1141 .name = "gmc_v10_0",
1142 .early_init = gmc_v10_0_early_init,
1143 .late_init = gmc_v10_0_late_init,
1144 .sw_init = gmc_v10_0_sw_init,
1145 .sw_fini = gmc_v10_0_sw_fini,
1146 .hw_init = gmc_v10_0_hw_init,
1147 .hw_fini = gmc_v10_0_hw_fini,
1148 .suspend = gmc_v10_0_suspend,
1149 .resume = gmc_v10_0_resume,
1150 .is_idle = gmc_v10_0_is_idle,
1151 .wait_for_idle = gmc_v10_0_wait_for_idle,
1152 .soft_reset = gmc_v10_0_soft_reset,
1153 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1154 .set_powergating_state = gmc_v10_0_set_powergating_state,
1155 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1156};
1157
1158const struct amdgpu_ip_block_version gmc_v10_0_ip_block = {
1159 .type = AMD_IP_BLOCK_TYPE_GMC,
1160 .major = 10,
1161 .minor = 0,
1162 .rev = 0,
1163 .funcs = &gmc_v10_0_ip_funcs,
1164};