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1#ifndef _VC4_HDMI_REGS_H_
2#define _VC4_HDMI_REGS_H_
3
4#include "vc4_hdmi.h"
5
6#define VC4_HDMI_PACKET_STRIDE 0x24
7
8enum vc4_hdmi_regs {
9 VC4_INVALID = 0,
10 VC4_HDMI,
11 VC4_HD,
12 VC5_CEC,
13 VC5_CSC,
14 VC5_DVP,
15 VC5_PHY,
16 VC5_RAM,
17 VC5_RM,
18};
19
20enum vc4_hdmi_field {
21 HDMI_AUDIO_PACKET_CONFIG,
22 HDMI_CEC_CNTRL_1,
23 HDMI_CEC_CNTRL_2,
24 HDMI_CEC_CNTRL_3,
25 HDMI_CEC_CNTRL_4,
26 HDMI_CEC_CNTRL_5,
27 HDMI_CEC_CPU_CLEAR,
28 HDMI_CEC_CPU_MASK_CLEAR,
29 HDMI_CEC_CPU_MASK_SET,
30 HDMI_CEC_CPU_MASK_STATUS,
31 HDMI_CEC_CPU_STATUS,
32 HDMI_CEC_CPU_SET,
33
34 /*
35 * Transmit data, first byte is low byte of the 32-bit reg.
36 * MSB of each byte transmitted first.
37 */
38 HDMI_CEC_RX_DATA_1,
39 HDMI_CEC_RX_DATA_2,
40 HDMI_CEC_RX_DATA_3,
41 HDMI_CEC_RX_DATA_4,
42 HDMI_CEC_TX_DATA_1,
43 HDMI_CEC_TX_DATA_2,
44 HDMI_CEC_TX_DATA_3,
45 HDMI_CEC_TX_DATA_4,
46 HDMI_CLOCK_STOP,
47 HDMI_CORE_REV,
48 HDMI_CRP_CFG,
49 HDMI_CSC_12_11,
50 HDMI_CSC_14_13,
51 HDMI_CSC_22_21,
52 HDMI_CSC_24_23,
53 HDMI_CSC_32_31,
54 HDMI_CSC_34_33,
55 HDMI_CSC_CTL,
56
57 /*
58 * 20-bit fields containing CTS values to be transmitted if
59 * !EXTERNAL_CTS_EN
60 */
61 HDMI_CTS_0,
62 HDMI_CTS_1,
63 HDMI_DEEP_COLOR_CONFIG_1,
64 HDMI_DVP_CTL,
65 HDMI_FIFO_CTL,
66 HDMI_FRAME_COUNT,
67 HDMI_GCP_CONFIG,
68 HDMI_GCP_WORD_1,
69 HDMI_HORZA,
70 HDMI_HORZB,
71 HDMI_HOTPLUG,
72 HDMI_HOTPLUG_INT,
73
74 /*
75 * 3 bits per field, where each field maps from that
76 * corresponding MAI bus channel to the given HDMI channel.
77 */
78 HDMI_MAI_CHANNEL_MAP,
79 HDMI_MAI_CONFIG,
80 HDMI_MAI_CTL,
81
82 /*
83 * Register for DMAing in audio data to be transported over
84 * the MAI bus to the Falcon core.
85 */
86 HDMI_MAI_DATA,
87
88 /* Format header to be placed on the MAI data. Unused. */
89 HDMI_MAI_FMT,
90
91 /* Last received format word on the MAI bus. */
92 HDMI_MAI_FORMAT,
93 HDMI_MAI_SMP,
94 HDMI_MAI_THR,
95 HDMI_M_CTL,
96 HDMI_RAM_PACKET_CONFIG,
97 HDMI_RAM_PACKET_START,
98 HDMI_RAM_PACKET_STATUS,
99 HDMI_RM_CONTROL,
100 HDMI_RM_FORMAT,
101 HDMI_RM_OFFSET,
102 HDMI_SCHEDULER_CONTROL,
103 HDMI_SCRAMBLER_CTL,
104 HDMI_SW_RESET_CONTROL,
105 HDMI_TX_PHY_CHANNEL_SWAP,
106 HDMI_TX_PHY_CLK_DIV,
107 HDMI_TX_PHY_CTL_0,
108 HDMI_TX_PHY_CTL_1,
109 HDMI_TX_PHY_CTL_2,
110 HDMI_TX_PHY_CTL_3,
111 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
112 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
113 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
114 HDMI_TX_PHY_PLL_CFG,
115 HDMI_TX_PHY_PLL_CTL_0,
116 HDMI_TX_PHY_PLL_CTL_1,
117 HDMI_TX_PHY_POWERDOWN_CTL,
118 HDMI_TX_PHY_RESET_CTL,
119 HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
120 HDMI_VEC_INTERFACE_XBAR,
121 HDMI_VERTA0,
122 HDMI_VERTA1,
123 HDMI_VERTB0,
124 HDMI_VERTB1,
125 HDMI_VID_CTL,
126};
127
128struct vc4_hdmi_register {
129 char *name;
130 enum vc4_hdmi_regs reg;
131 unsigned int offset;
132};
133
134#define _VC4_REG(_base, _reg, _offset) \
135 [_reg] = { \
136 .name = #_reg, \
137 .reg = _base, \
138 .offset = _offset, \
139 }
140
141#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset)
142#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset)
143#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
144#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
145#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
146#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
147#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
148#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
149
150static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
151 VC4_HD_REG(HDMI_M_CTL, 0x000c),
152 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
153 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
154 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
155 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
156 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
157 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
158 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
159 VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
160 VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
161 VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
162 VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
163 VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
164 VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
165 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
166
167 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
168 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
169 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
170 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
171 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
172 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
173 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
174 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
175 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
176 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
177 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
178 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
179 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
180 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
181 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
182 VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
183 VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
184 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
185 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
186 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
187 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
188 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
189 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
190 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
191 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
192 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
193 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
194 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
195 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
196 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
197 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
198 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
199 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
200 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
201 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
202 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
203 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
204 VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
205 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
206 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
207 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
208 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
209 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
210};
211
212static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
213 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
214 VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
215 VC4_HD_REG(HDMI_MAI_THR, 0x0014),
216 VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
217 VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
218 VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
219 VC4_HD_REG(HDMI_VID_CTL, 0x0044),
220 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
221
222 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
223 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
224 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
225 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
226 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
227 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
228 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
229 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
230 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
231 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
232 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
233 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
234 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
235 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
236 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
237 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
238 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
239 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
240 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
241 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
242 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
243
244 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
245 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
246
247 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
248 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
249 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
250 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
251 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
252 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
253 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
254 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
255 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
256 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
257 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
258 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
259 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
260 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
261 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
262
263 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
264 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
265 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
266
267 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
268
269 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
270 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
271 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
272 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
273 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
274 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
275 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
276 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
277 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
278 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
279 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
280 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
281 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
282
283 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
284 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
285 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
286 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
287 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
288 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
289 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
290};
291
292static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
293 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
294 VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
295 VC4_HD_REG(HDMI_MAI_THR, 0x0034),
296 VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
297 VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
298 VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
299 VC4_HD_REG(HDMI_VID_CTL, 0x0048),
300 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
301
302 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
303 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
304 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
305 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
306 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
307 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
308 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
309 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
310 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
311 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
312 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
313 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
314 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
315 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
316 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
317 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
318 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
319 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
320 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
321 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
322 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
323
324 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
325 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
326
327 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
328 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
329 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
330 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
331 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
332 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
333 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
334 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
335 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
336 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
337 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
338 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
339 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
340 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
341 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
342
343 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
344 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
345 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
346
347 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
348
349 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
350 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
351 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
352 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
353 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
354 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
355 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
356 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
357 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
358 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
359 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
360 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
361 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
362
363 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
364 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
365 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
366 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
367 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
368 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
369 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
370};
371
372static inline
373void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
374 enum vc4_hdmi_regs reg)
375{
376 switch (reg) {
377 case VC4_HD:
378 return hdmi->hd_regs;
379
380 case VC4_HDMI:
381 return hdmi->hdmicore_regs;
382
383 case VC5_CSC:
384 return hdmi->csc_regs;
385
386 case VC5_CEC:
387 return hdmi->cec_regs;
388
389 case VC5_DVP:
390 return hdmi->dvp_regs;
391
392 case VC5_PHY:
393 return hdmi->phy_regs;
394
395 case VC5_RAM:
396 return hdmi->ram_regs;
397
398 case VC5_RM:
399 return hdmi->rm_regs;
400
401 default:
402 return NULL;
403 }
404
405 return NULL;
406}
407
408static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
409 enum vc4_hdmi_field reg)
410{
411 const struct vc4_hdmi_register *field;
412 const struct vc4_hdmi_variant *variant = hdmi->variant;
413 void __iomem *base;
414
415 if (reg >= variant->num_registers) {
416 dev_warn(&hdmi->pdev->dev,
417 "Invalid register ID %u\n", reg);
418 return 0;
419 }
420
421 field = &variant->registers[reg];
422 base = __vc4_hdmi_get_field_base(hdmi, field->reg);
423 if (!base) {
424 dev_warn(&hdmi->pdev->dev,
425 "Unknown register ID %u\n", reg);
426 return 0;
427 }
428
429 return readl(base + field->offset);
430}
431#define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg)
432
433static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
434 enum vc4_hdmi_field reg,
435 u32 value)
436{
437 const struct vc4_hdmi_register *field;
438 const struct vc4_hdmi_variant *variant = hdmi->variant;
439 void __iomem *base;
440
441 if (reg >= variant->num_registers) {
442 dev_warn(&hdmi->pdev->dev,
443 "Invalid register ID %u\n", reg);
444 return;
445 }
446
447 field = &variant->registers[reg];
448 base = __vc4_hdmi_get_field_base(hdmi, field->reg);
449 if (!base)
450 return;
451
452 writel(value, base + field->offset);
453}
454#define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val)
455
456#endif /* _VC4_HDMI_REGS_H_ */
1#ifndef _VC4_HDMI_REGS_H_
2#define _VC4_HDMI_REGS_H_
3
4#include <linux/pm_runtime.h>
5
6#include "vc4_hdmi.h"
7
8#define VC4_HDMI_PACKET_STRIDE 0x24
9
10enum vc4_hdmi_regs {
11 VC4_INVALID = 0,
12 VC4_HDMI,
13 VC4_HD,
14 VC5_CEC,
15 VC5_CSC,
16 VC5_DVP,
17 VC5_PHY,
18 VC5_RAM,
19 VC5_RM,
20};
21
22enum vc4_hdmi_field {
23 HDMI_AUDIO_PACKET_CONFIG,
24 HDMI_CEC_CNTRL_1,
25 HDMI_CEC_CNTRL_2,
26 HDMI_CEC_CNTRL_3,
27 HDMI_CEC_CNTRL_4,
28 HDMI_CEC_CNTRL_5,
29 HDMI_CEC_CPU_CLEAR,
30 HDMI_CEC_CPU_MASK_CLEAR,
31 HDMI_CEC_CPU_MASK_SET,
32 HDMI_CEC_CPU_MASK_STATUS,
33 HDMI_CEC_CPU_STATUS,
34 HDMI_CEC_CPU_SET,
35
36 /*
37 * Transmit data, first byte is low byte of the 32-bit reg.
38 * MSB of each byte transmitted first.
39 */
40 HDMI_CEC_RX_DATA_1,
41 HDMI_CEC_RX_DATA_2,
42 HDMI_CEC_RX_DATA_3,
43 HDMI_CEC_RX_DATA_4,
44 HDMI_CEC_TX_DATA_1,
45 HDMI_CEC_TX_DATA_2,
46 HDMI_CEC_TX_DATA_3,
47 HDMI_CEC_TX_DATA_4,
48 HDMI_CLOCK_STOP,
49 HDMI_CORE_REV,
50 HDMI_CRP_CFG,
51 HDMI_CSC_12_11,
52 HDMI_CSC_14_13,
53 HDMI_CSC_22_21,
54 HDMI_CSC_24_23,
55 HDMI_CSC_32_31,
56 HDMI_CSC_34_33,
57 HDMI_CSC_CHANNEL_CTL,
58 HDMI_CSC_CTL,
59
60 /*
61 * 20-bit fields containing CTS values to be transmitted if
62 * !EXTERNAL_CTS_EN
63 */
64 HDMI_CTS_0,
65 HDMI_CTS_1,
66 HDMI_DEEP_COLOR_CONFIG_1,
67 HDMI_DVP_CTL,
68 HDMI_FIFO_CTL,
69 HDMI_FRAME_COUNT,
70 HDMI_GCP_CONFIG,
71 HDMI_GCP_WORD_1,
72 HDMI_HORZA,
73 HDMI_HORZB,
74 HDMI_HOTPLUG,
75 HDMI_HOTPLUG_INT,
76
77 /*
78 * 3 bits per field, where each field maps from that
79 * corresponding MAI bus channel to the given HDMI channel.
80 */
81 HDMI_MAI_CHANNEL_MAP,
82 HDMI_MAI_CONFIG,
83 HDMI_MAI_CTL,
84
85 /*
86 * Register for DMAing in audio data to be transported over
87 * the MAI bus to the Falcon core.
88 */
89 HDMI_MAI_DATA,
90
91 /* Format header to be placed on the MAI data. Unused. */
92 HDMI_MAI_FMT,
93
94 /* Last received format word on the MAI bus. */
95 HDMI_MAI_FORMAT,
96 HDMI_MAI_SMP,
97 HDMI_MAI_THR,
98 HDMI_M_CTL,
99 HDMI_RAM_PACKET_CONFIG,
100 HDMI_RAM_PACKET_START,
101 HDMI_RAM_PACKET_STATUS,
102 HDMI_RM_CONTROL,
103 HDMI_RM_FORMAT,
104 HDMI_RM_OFFSET,
105 HDMI_SCHEDULER_CONTROL,
106 HDMI_SCRAMBLER_CTL,
107 HDMI_SW_RESET_CONTROL,
108 HDMI_TX_PHY_CHANNEL_SWAP,
109 HDMI_TX_PHY_CLK_DIV,
110 HDMI_TX_PHY_CTL_0,
111 HDMI_TX_PHY_CTL_1,
112 HDMI_TX_PHY_CTL_2,
113 HDMI_TX_PHY_CTL_3,
114 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
115 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
116 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
117 HDMI_TX_PHY_PLL_CFG,
118 HDMI_TX_PHY_PLL_CTL_0,
119 HDMI_TX_PHY_PLL_CTL_1,
120 HDMI_TX_PHY_POWERDOWN_CTL,
121 HDMI_TX_PHY_RESET_CTL,
122 HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
123 HDMI_VEC_INTERFACE_CFG,
124 HDMI_VEC_INTERFACE_XBAR,
125 HDMI_VERTA0,
126 HDMI_VERTA1,
127 HDMI_VERTB0,
128 HDMI_VERTB1,
129 HDMI_VID_CTL,
130 HDMI_MISC_CONTROL,
131 HDMI_FORMAT_DET_1,
132 HDMI_FORMAT_DET_2,
133 HDMI_FORMAT_DET_3,
134 HDMI_FORMAT_DET_4,
135 HDMI_FORMAT_DET_5,
136 HDMI_FORMAT_DET_6,
137 HDMI_FORMAT_DET_7,
138 HDMI_FORMAT_DET_8,
139 HDMI_FORMAT_DET_9,
140 HDMI_FORMAT_DET_10,
141};
142
143struct vc4_hdmi_register {
144 char *name;
145 enum vc4_hdmi_regs reg;
146 unsigned int offset;
147};
148
149#define _VC4_REG(_base, _reg, _offset) \
150 [_reg] = { \
151 .name = #_reg, \
152 .reg = _base, \
153 .offset = _offset, \
154 }
155
156#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset)
157#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset)
158#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
159#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
160#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
161#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
162#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
163#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
164
165static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
166 VC4_HD_REG(HDMI_M_CTL, 0x000c),
167 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
168 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
169 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
170 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
171 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
172 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
173 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
174 VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
175 VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
176 VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
177 VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
178 VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
179 VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
180 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
181
182 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
183 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
184 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
185 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
186 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
187 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
188 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
189 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
190 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
191 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
192 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
193 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
194 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
195 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
196 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
197 VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
198 VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
199 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
200 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
201 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
202 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
203 VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x00e4),
204 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
205 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
206 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
207 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
208 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
209 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
210 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
211 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
212 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
213 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
214 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
215 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
216 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
217 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
218 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
219 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
220 VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
221 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
222 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
223 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
224 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
225 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
226};
227
228static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
229 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
230 VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
231 VC4_HD_REG(HDMI_MAI_THR, 0x0014),
232 VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
233 VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
234 VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
235 VC4_HD_REG(HDMI_VID_CTL, 0x0044),
236 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
237
238 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
239 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
240 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
241 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
242 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
243 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
244 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
245 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
246 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
247 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
248 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
249 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
250 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
251 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
252 VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
253 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
254 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
255 VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
256 VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
257 VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
258 VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
259 VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
260 VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
261 VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
262 VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
263 VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
264 VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
265 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
266 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
267 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
268 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
269 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
270
271 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
272 VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
273 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
274
275 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
276 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
277 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
278 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
279 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
280 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
281 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
282 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
283 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
284 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
285 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
286 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
287 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
288 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
289 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
290
291 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
292 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
293 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
294
295 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
296
297 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
298 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
299 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
300 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
301 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
302 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
303 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
304 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
305 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
306 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
307 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
308 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
309 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
310
311 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
312 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
313 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
314 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
315 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
316 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
317 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
318 VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
319};
320
321static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
322 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
323 VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
324 VC4_HD_REG(HDMI_MAI_THR, 0x0034),
325 VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
326 VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
327 VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
328 VC4_HD_REG(HDMI_VID_CTL, 0x0048),
329 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
330
331 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
332 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
333 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
334 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
335 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
336 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
337 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
338 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
339 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
340 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
341 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
342 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
343 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
344 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
345 VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
346 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
347 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
348 VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
349 VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
350 VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
351 VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
352 VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
353 VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
354 VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
355 VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
356 VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
357 VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
358 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
359 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
360 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
361 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
362 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
363
364 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
365 VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
366 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
367
368 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
369 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
370 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
371 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
372 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
373 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
374 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
375 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
376 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
377 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
378 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
379 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
380 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
381 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
382 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
383
384 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
385 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
386 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
387
388 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
389
390 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
391 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
392 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
393 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
394 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
395 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
396 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
397 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
398 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
399 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
400 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
401 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
402 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
403
404 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
405 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
406 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
407 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
408 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
409 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
410 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
411 VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
412};
413
414static inline
415void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
416 enum vc4_hdmi_regs reg)
417{
418 switch (reg) {
419 case VC4_HD:
420 return hdmi->hd_regs;
421
422 case VC4_HDMI:
423 return hdmi->hdmicore_regs;
424
425 case VC5_CSC:
426 return hdmi->csc_regs;
427
428 case VC5_CEC:
429 return hdmi->cec_regs;
430
431 case VC5_DVP:
432 return hdmi->dvp_regs;
433
434 case VC5_PHY:
435 return hdmi->phy_regs;
436
437 case VC5_RAM:
438 return hdmi->ram_regs;
439
440 case VC5_RM:
441 return hdmi->rm_regs;
442
443 default:
444 return NULL;
445 }
446
447 return NULL;
448}
449
450static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
451 enum vc4_hdmi_field reg)
452{
453 const struct vc4_hdmi_register *field;
454 const struct vc4_hdmi_variant *variant = hdmi->variant;
455 void __iomem *base;
456
457 WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
458
459 kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
460
461 if (reg >= variant->num_registers) {
462 dev_warn(&hdmi->pdev->dev,
463 "Invalid register ID %u\n", reg);
464 return 0;
465 }
466
467 field = &variant->registers[reg];
468 base = __vc4_hdmi_get_field_base(hdmi, field->reg);
469 if (!base) {
470 dev_warn(&hdmi->pdev->dev,
471 "Unknown register ID %u\n", reg);
472 return 0;
473 }
474
475 return readl(base + field->offset);
476}
477#define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg)
478
479static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
480 enum vc4_hdmi_field reg,
481 u32 value)
482{
483 const struct vc4_hdmi_register *field;
484 const struct vc4_hdmi_variant *variant = hdmi->variant;
485 void __iomem *base;
486
487 lockdep_assert_held(&hdmi->hw_lock);
488
489 WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
490
491 kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
492
493 if (reg >= variant->num_registers) {
494 dev_warn(&hdmi->pdev->dev,
495 "Invalid register ID %u\n", reg);
496 return;
497 }
498
499 field = &variant->registers[reg];
500 base = __vc4_hdmi_get_field_base(hdmi, field->reg);
501 if (!base)
502 return;
503
504 writel(value, base + field->offset);
505}
506#define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val)
507
508#endif /* _VC4_HDMI_REGS_H_ */