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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2008-2018 Intel Corporation
4 */
5
6#include <linux/sched/mm.h>
7#include <linux/stop_machine.h>
8
9#include "display/intel_display_types.h"
10#include "display/intel_overlay.h"
11
12#include "gem/i915_gem_context.h"
13
14#include "i915_drv.h"
15#include "i915_gpu_error.h"
16#include "i915_irq.h"
17#include "intel_breadcrumbs.h"
18#include "intel_engine_pm.h"
19#include "intel_gt.h"
20#include "intel_gt_pm.h"
21#include "intel_gt_requests.h"
22#include "intel_reset.h"
23
24#include "uc/intel_guc.h"
25#include "uc/intel_guc_submission.h"
26
27#define RESET_MAX_RETRIES 3
28
29/* XXX How to handle concurrent GGTT updates using tiling registers? */
30#define RESET_UNDER_STOP_MACHINE 0
31
32static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
33{
34 intel_uncore_rmw_fw(uncore, reg, 0, set);
35}
36
37static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
38{
39 intel_uncore_rmw_fw(uncore, reg, clr, 0);
40}
41
42static void skip_context(struct i915_request *rq)
43{
44 struct intel_context *hung_ctx = rq->context;
45
46 list_for_each_entry_from_rcu(rq, &hung_ctx->timeline->requests, link) {
47 if (!i915_request_is_active(rq))
48 return;
49
50 if (rq->context == hung_ctx) {
51 i915_request_set_error_once(rq, -EIO);
52 __i915_request_skip(rq);
53 }
54 }
55}
56
57static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
58{
59 struct drm_i915_file_private *file_priv = ctx->file_priv;
60 unsigned long prev_hang;
61 unsigned int score;
62
63 if (IS_ERR_OR_NULL(file_priv))
64 return;
65
66 score = 0;
67 if (banned)
68 score = I915_CLIENT_SCORE_CONTEXT_BAN;
69
70 prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
71 if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
72 score += I915_CLIENT_SCORE_HANG_FAST;
73
74 if (score) {
75 atomic_add(score, &file_priv->ban_score);
76
77 drm_dbg(&ctx->i915->drm,
78 "client %s: gained %u ban score, now %u\n",
79 ctx->name, score,
80 atomic_read(&file_priv->ban_score));
81 }
82}
83
84static bool mark_guilty(struct i915_request *rq)
85{
86 struct i915_gem_context *ctx;
87 unsigned long prev_hang;
88 bool banned;
89 int i;
90
91 if (intel_context_is_closed(rq->context)) {
92 intel_context_set_banned(rq->context);
93 return true;
94 }
95
96 rcu_read_lock();
97 ctx = rcu_dereference(rq->context->gem_context);
98 if (ctx && !kref_get_unless_zero(&ctx->ref))
99 ctx = NULL;
100 rcu_read_unlock();
101 if (!ctx)
102 return intel_context_is_banned(rq->context);
103
104 atomic_inc(&ctx->guilty_count);
105
106 /* Cool contexts are too cool to be banned! (Used for reset testing.) */
107 if (!i915_gem_context_is_bannable(ctx)) {
108 banned = false;
109 goto out;
110 }
111
112 drm_notice(&ctx->i915->drm,
113 "%s context reset due to GPU hang\n",
114 ctx->name);
115
116 /* Record the timestamp for the last N hangs */
117 prev_hang = ctx->hang_timestamp[0];
118 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
119 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
120 ctx->hang_timestamp[i] = jiffies;
121
122 /* If we have hung N+1 times in rapid succession, we ban the context! */
123 banned = !i915_gem_context_is_recoverable(ctx);
124 if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
125 banned = true;
126 if (banned) {
127 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
128 ctx->name, atomic_read(&ctx->guilty_count));
129 intel_context_set_banned(rq->context);
130 }
131
132 client_mark_guilty(ctx, banned);
133
134out:
135 i915_gem_context_put(ctx);
136 return banned;
137}
138
139static void mark_innocent(struct i915_request *rq)
140{
141 struct i915_gem_context *ctx;
142
143 rcu_read_lock();
144 ctx = rcu_dereference(rq->context->gem_context);
145 if (ctx)
146 atomic_inc(&ctx->active_count);
147 rcu_read_unlock();
148}
149
150void __i915_request_reset(struct i915_request *rq, bool guilty)
151{
152 RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
153 GEM_BUG_ON(__i915_request_is_complete(rq));
154
155 rcu_read_lock(); /* protect the GEM context */
156 if (guilty) {
157 i915_request_set_error_once(rq, -EIO);
158 __i915_request_skip(rq);
159 if (mark_guilty(rq))
160 skip_context(rq);
161 } else {
162 i915_request_set_error_once(rq, -EAGAIN);
163 mark_innocent(rq);
164 }
165 rcu_read_unlock();
166}
167
168static bool i915_in_reset(struct pci_dev *pdev)
169{
170 u8 gdrst;
171
172 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
173 return gdrst & GRDOM_RESET_STATUS;
174}
175
176static int i915_do_reset(struct intel_gt *gt,
177 intel_engine_mask_t engine_mask,
178 unsigned int retry)
179{
180 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
181 int err;
182
183 /* Assert reset for at least 20 usec, and wait for acknowledgement. */
184 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
185 udelay(50);
186 err = wait_for_atomic(i915_in_reset(pdev), 50);
187
188 /* Clear the reset request. */
189 pci_write_config_byte(pdev, I915_GDRST, 0);
190 udelay(50);
191 if (!err)
192 err = wait_for_atomic(!i915_in_reset(pdev), 50);
193
194 return err;
195}
196
197static bool g4x_reset_complete(struct pci_dev *pdev)
198{
199 u8 gdrst;
200
201 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
202 return (gdrst & GRDOM_RESET_ENABLE) == 0;
203}
204
205static int g33_do_reset(struct intel_gt *gt,
206 intel_engine_mask_t engine_mask,
207 unsigned int retry)
208{
209 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
210
211 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
212 return wait_for_atomic(g4x_reset_complete(pdev), 50);
213}
214
215static int g4x_do_reset(struct intel_gt *gt,
216 intel_engine_mask_t engine_mask,
217 unsigned int retry)
218{
219 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
220 struct intel_uncore *uncore = gt->uncore;
221 int ret;
222
223 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
224 rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
225 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
226
227 pci_write_config_byte(pdev, I915_GDRST,
228 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
229 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
230 if (ret) {
231 GT_TRACE(gt, "Wait for media reset failed\n");
232 goto out;
233 }
234
235 pci_write_config_byte(pdev, I915_GDRST,
236 GRDOM_RENDER | GRDOM_RESET_ENABLE);
237 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
238 if (ret) {
239 GT_TRACE(gt, "Wait for render reset failed\n");
240 goto out;
241 }
242
243out:
244 pci_write_config_byte(pdev, I915_GDRST, 0);
245
246 rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
247 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
248
249 return ret;
250}
251
252static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
253 unsigned int retry)
254{
255 struct intel_uncore *uncore = gt->uncore;
256 int ret;
257
258 intel_uncore_write_fw(uncore, ILK_GDSR,
259 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
260 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
261 ILK_GRDOM_RESET_ENABLE, 0,
262 5000, 0,
263 NULL);
264 if (ret) {
265 GT_TRACE(gt, "Wait for render reset failed\n");
266 goto out;
267 }
268
269 intel_uncore_write_fw(uncore, ILK_GDSR,
270 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
271 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
272 ILK_GRDOM_RESET_ENABLE, 0,
273 5000, 0,
274 NULL);
275 if (ret) {
276 GT_TRACE(gt, "Wait for media reset failed\n");
277 goto out;
278 }
279
280out:
281 intel_uncore_write_fw(uncore, ILK_GDSR, 0);
282 intel_uncore_posting_read_fw(uncore, ILK_GDSR);
283 return ret;
284}
285
286/* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
287static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
288{
289 struct intel_uncore *uncore = gt->uncore;
290 int err;
291
292 /*
293 * GEN6_GDRST is not in the gt power well, no need to check
294 * for fifo space for the write or forcewake the chip for
295 * the read
296 */
297 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
298
299 /* Wait for the device to ack the reset requests */
300 err = __intel_wait_for_register_fw(uncore,
301 GEN6_GDRST, hw_domain_mask, 0,
302 500, 0,
303 NULL);
304 if (err)
305 GT_TRACE(gt,
306 "Wait for 0x%08x engines reset failed\n",
307 hw_domain_mask);
308
309 return err;
310}
311
312static int gen6_reset_engines(struct intel_gt *gt,
313 intel_engine_mask_t engine_mask,
314 unsigned int retry)
315{
316 static const u32 hw_engine_mask[] = {
317 [RCS0] = GEN6_GRDOM_RENDER,
318 [BCS0] = GEN6_GRDOM_BLT,
319 [VCS0] = GEN6_GRDOM_MEDIA,
320 [VCS1] = GEN8_GRDOM_MEDIA2,
321 [VECS0] = GEN6_GRDOM_VECS,
322 };
323 struct intel_engine_cs *engine;
324 u32 hw_mask;
325
326 if (engine_mask == ALL_ENGINES) {
327 hw_mask = GEN6_GRDOM_FULL;
328 } else {
329 intel_engine_mask_t tmp;
330
331 hw_mask = 0;
332 for_each_engine_masked(engine, gt, engine_mask, tmp) {
333 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
334 hw_mask |= hw_engine_mask[engine->id];
335 }
336 }
337
338 return gen6_hw_domain_reset(gt, hw_mask);
339}
340
341static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
342{
343 int vecs_id;
344
345 GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
346
347 vecs_id = _VECS((engine->instance) / 2);
348
349 return engine->gt->engine[vecs_id];
350}
351
352struct sfc_lock_data {
353 i915_reg_t lock_reg;
354 i915_reg_t ack_reg;
355 i915_reg_t usage_reg;
356 u32 lock_bit;
357 u32 ack_bit;
358 u32 usage_bit;
359 u32 reset_bit;
360};
361
362static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
363 struct sfc_lock_data *sfc_lock)
364{
365 switch (engine->class) {
366 default:
367 MISSING_CASE(engine->class);
368 fallthrough;
369 case VIDEO_DECODE_CLASS:
370 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine);
371 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
372
373 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
374 sfc_lock->ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
375
376 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
377 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
378 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
379
380 break;
381 case VIDEO_ENHANCEMENT_CLASS:
382 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine);
383 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
384
385 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine);
386 sfc_lock->ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
387
388 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine);
389 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
390 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
391
392 break;
393 }
394}
395
396static int gen11_lock_sfc(struct intel_engine_cs *engine,
397 u32 *reset_mask,
398 u32 *unlock_mask)
399{
400 struct intel_uncore *uncore = engine->uncore;
401 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
402 struct sfc_lock_data sfc_lock;
403 bool lock_obtained, lock_to_other = false;
404 int ret;
405
406 switch (engine->class) {
407 case VIDEO_DECODE_CLASS:
408 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
409 return 0;
410
411 fallthrough;
412 case VIDEO_ENHANCEMENT_CLASS:
413 get_sfc_forced_lock_data(engine, &sfc_lock);
414
415 break;
416 default:
417 return 0;
418 }
419
420 if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
421 struct intel_engine_cs *paired_vecs;
422
423 if (engine->class != VIDEO_DECODE_CLASS ||
424 GRAPHICS_VER(engine->i915) != 12)
425 return 0;
426
427 /*
428 * Wa_14010733141
429 *
430 * If the VCS-MFX isn't using the SFC, we also need to check
431 * whether VCS-HCP is using it. If so, we need to issue a *VE*
432 * forced lock on the VE engine that shares the same SFC.
433 */
434 if (!(intel_uncore_read_fw(uncore,
435 GEN12_HCP_SFC_LOCK_STATUS(engine)) &
436 GEN12_HCP_SFC_USAGE_BIT))
437 return 0;
438
439 paired_vecs = find_sfc_paired_vecs_engine(engine);
440 get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
441 lock_to_other = true;
442 *unlock_mask |= paired_vecs->mask;
443 } else {
444 *unlock_mask |= engine->mask;
445 }
446
447 /*
448 * If the engine is using an SFC, tell the engine that a software reset
449 * is going to happen. The engine will then try to force lock the SFC.
450 * If SFC ends up being locked to the engine we want to reset, we have
451 * to reset it as well (we will unlock it once the reset sequence is
452 * completed).
453 */
454 rmw_set_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
455
456 ret = __intel_wait_for_register_fw(uncore,
457 sfc_lock.ack_reg,
458 sfc_lock.ack_bit,
459 sfc_lock.ack_bit,
460 1000, 0, NULL);
461
462 /*
463 * Was the SFC released while we were trying to lock it?
464 *
465 * We should reset both the engine and the SFC if:
466 * - We were locking the SFC to this engine and the lock succeeded
467 * OR
468 * - We were locking the SFC to a different engine (Wa_14010733141)
469 * but the SFC was released before the lock was obtained.
470 *
471 * Otherwise we need only reset the engine by itself and we can
472 * leave the SFC alone.
473 */
474 lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
475 sfc_lock.usage_bit) != 0;
476 if (lock_obtained == lock_to_other)
477 return 0;
478
479 if (ret) {
480 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
481 return ret;
482 }
483
484 *reset_mask |= sfc_lock.reset_bit;
485 return 0;
486}
487
488static void gen11_unlock_sfc(struct intel_engine_cs *engine)
489{
490 struct intel_uncore *uncore = engine->uncore;
491 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
492 struct sfc_lock_data sfc_lock = {};
493
494 if (engine->class != VIDEO_DECODE_CLASS &&
495 engine->class != VIDEO_ENHANCEMENT_CLASS)
496 return;
497
498 if (engine->class == VIDEO_DECODE_CLASS &&
499 (BIT(engine->instance) & vdbox_sfc_access) == 0)
500 return;
501
502 get_sfc_forced_lock_data(engine, &sfc_lock);
503
504 rmw_clear_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
505}
506
507static int gen11_reset_engines(struct intel_gt *gt,
508 intel_engine_mask_t engine_mask,
509 unsigned int retry)
510{
511 static const u32 hw_engine_mask[] = {
512 [RCS0] = GEN11_GRDOM_RENDER,
513 [BCS0] = GEN11_GRDOM_BLT,
514 [VCS0] = GEN11_GRDOM_MEDIA,
515 [VCS1] = GEN11_GRDOM_MEDIA2,
516 [VCS2] = GEN11_GRDOM_MEDIA3,
517 [VCS3] = GEN11_GRDOM_MEDIA4,
518 [VECS0] = GEN11_GRDOM_VECS,
519 [VECS1] = GEN11_GRDOM_VECS2,
520 };
521 struct intel_engine_cs *engine;
522 intel_engine_mask_t tmp;
523 u32 reset_mask, unlock_mask = 0;
524 int ret;
525
526 if (engine_mask == ALL_ENGINES) {
527 reset_mask = GEN11_GRDOM_FULL;
528 } else {
529 reset_mask = 0;
530 for_each_engine_masked(engine, gt, engine_mask, tmp) {
531 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
532 reset_mask |= hw_engine_mask[engine->id];
533 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
534 if (ret)
535 goto sfc_unlock;
536 }
537 }
538
539 ret = gen6_hw_domain_reset(gt, reset_mask);
540
541sfc_unlock:
542 /*
543 * We unlock the SFC based on the lock status and not the result of
544 * gen11_lock_sfc to make sure that we clean properly if something
545 * wrong happened during the lock (e.g. lock acquired after timeout
546 * expiration).
547 *
548 * Due to Wa_14010733141, we may have locked an SFC to an engine that
549 * wasn't being reset. So instead of calling gen11_unlock_sfc()
550 * on engine_mask, we instead call it on the mask of engines that our
551 * gen11_lock_sfc() calls told us actually had locks attempted.
552 */
553 for_each_engine_masked(engine, gt, unlock_mask, tmp)
554 gen11_unlock_sfc(engine);
555
556 return ret;
557}
558
559static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
560{
561 struct intel_uncore *uncore = engine->uncore;
562 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
563 u32 request, mask, ack;
564 int ret;
565
566 if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
567 return -ETIMEDOUT;
568
569 ack = intel_uncore_read_fw(uncore, reg);
570 if (ack & RESET_CTL_CAT_ERROR) {
571 /*
572 * For catastrophic errors, ready-for-reset sequence
573 * needs to be bypassed: HAS#396813
574 */
575 request = RESET_CTL_CAT_ERROR;
576 mask = RESET_CTL_CAT_ERROR;
577
578 /* Catastrophic errors need to be cleared by HW */
579 ack = 0;
580 } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
581 request = RESET_CTL_REQUEST_RESET;
582 mask = RESET_CTL_READY_TO_RESET;
583 ack = RESET_CTL_READY_TO_RESET;
584 } else {
585 return 0;
586 }
587
588 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
589 ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
590 700, 0, NULL);
591 if (ret)
592 drm_err(&engine->i915->drm,
593 "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
594 engine->name, request,
595 intel_uncore_read_fw(uncore, reg));
596
597 return ret;
598}
599
600static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
601{
602 intel_uncore_write_fw(engine->uncore,
603 RING_RESET_CTL(engine->mmio_base),
604 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
605}
606
607static int gen8_reset_engines(struct intel_gt *gt,
608 intel_engine_mask_t engine_mask,
609 unsigned int retry)
610{
611 struct intel_engine_cs *engine;
612 const bool reset_non_ready = retry >= 1;
613 intel_engine_mask_t tmp;
614 int ret;
615
616 for_each_engine_masked(engine, gt, engine_mask, tmp) {
617 ret = gen8_engine_reset_prepare(engine);
618 if (ret && !reset_non_ready)
619 goto skip_reset;
620
621 /*
622 * If this is not the first failed attempt to prepare,
623 * we decide to proceed anyway.
624 *
625 * By doing so we risk context corruption and with
626 * some gens (kbl), possible system hang if reset
627 * happens during active bb execution.
628 *
629 * We rather take context corruption instead of
630 * failed reset with a wedged driver/gpu. And
631 * active bb execution case should be covered by
632 * stop_engines() we have before the reset.
633 */
634 }
635
636 if (GRAPHICS_VER(gt->i915) >= 11)
637 ret = gen11_reset_engines(gt, engine_mask, retry);
638 else
639 ret = gen6_reset_engines(gt, engine_mask, retry);
640
641skip_reset:
642 for_each_engine_masked(engine, gt, engine_mask, tmp)
643 gen8_engine_reset_cancel(engine);
644
645 return ret;
646}
647
648static int mock_reset(struct intel_gt *gt,
649 intel_engine_mask_t mask,
650 unsigned int retry)
651{
652 return 0;
653}
654
655typedef int (*reset_func)(struct intel_gt *,
656 intel_engine_mask_t engine_mask,
657 unsigned int retry);
658
659static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
660{
661 struct drm_i915_private *i915 = gt->i915;
662
663 if (is_mock_gt(gt))
664 return mock_reset;
665 else if (GRAPHICS_VER(i915) >= 8)
666 return gen8_reset_engines;
667 else if (GRAPHICS_VER(i915) >= 6)
668 return gen6_reset_engines;
669 else if (GRAPHICS_VER(i915) >= 5)
670 return ilk_do_reset;
671 else if (IS_G4X(i915))
672 return g4x_do_reset;
673 else if (IS_G33(i915) || IS_PINEVIEW(i915))
674 return g33_do_reset;
675 else if (GRAPHICS_VER(i915) >= 3)
676 return i915_do_reset;
677 else
678 return NULL;
679}
680
681int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
682{
683 const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
684 reset_func reset;
685 int ret = -ETIMEDOUT;
686 int retry;
687
688 reset = intel_get_gpu_reset(gt);
689 if (!reset)
690 return -ENODEV;
691
692 /*
693 * If the power well sleeps during the reset, the reset
694 * request may be dropped and never completes (causing -EIO).
695 */
696 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
697 for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
698 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
699 preempt_disable();
700 ret = reset(gt, engine_mask, retry);
701 preempt_enable();
702 }
703 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
704
705 return ret;
706}
707
708bool intel_has_gpu_reset(const struct intel_gt *gt)
709{
710 if (!gt->i915->params.reset)
711 return NULL;
712
713 return intel_get_gpu_reset(gt);
714}
715
716bool intel_has_reset_engine(const struct intel_gt *gt)
717{
718 if (gt->i915->params.reset < 2)
719 return false;
720
721 return INTEL_INFO(gt->i915)->has_reset_engine;
722}
723
724int intel_reset_guc(struct intel_gt *gt)
725{
726 u32 guc_domain =
727 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
728 int ret;
729
730 GEM_BUG_ON(!HAS_GT_UC(gt->i915));
731
732 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
733 ret = gen6_hw_domain_reset(gt, guc_domain);
734 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
735
736 return ret;
737}
738
739/*
740 * Ensure irq handler finishes, and not run again.
741 * Also return the active request so that we only search for it once.
742 */
743static void reset_prepare_engine(struct intel_engine_cs *engine)
744{
745 /*
746 * During the reset sequence, we must prevent the engine from
747 * entering RC6. As the context state is undefined until we restart
748 * the engine, if it does enter RC6 during the reset, the state
749 * written to the powercontext is undefined and so we may lose
750 * GPU state upon resume, i.e. fail to restart after a reset.
751 */
752 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
753 if (engine->reset.prepare)
754 engine->reset.prepare(engine);
755}
756
757static void revoke_mmaps(struct intel_gt *gt)
758{
759 int i;
760
761 for (i = 0; i < gt->ggtt->num_fences; i++) {
762 struct drm_vma_offset_node *node;
763 struct i915_vma *vma;
764 u64 vma_offset;
765
766 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
767 if (!vma)
768 continue;
769
770 if (!i915_vma_has_userfault(vma))
771 continue;
772
773 GEM_BUG_ON(vma->fence != >->ggtt->fence_regs[i]);
774
775 if (!vma->mmo)
776 continue;
777
778 node = &vma->mmo->vma_node;
779 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
780
781 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
782 drm_vma_node_offset_addr(node) + vma_offset,
783 vma->size,
784 1);
785 }
786}
787
788static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
789{
790 struct intel_engine_cs *engine;
791 intel_engine_mask_t awake = 0;
792 enum intel_engine_id id;
793
794 for_each_engine(engine, gt, id) {
795 if (intel_engine_pm_get_if_awake(engine))
796 awake |= engine->mask;
797 reset_prepare_engine(engine);
798 }
799
800 intel_uc_reset_prepare(>->uc);
801
802 return awake;
803}
804
805static void gt_revoke(struct intel_gt *gt)
806{
807 revoke_mmaps(gt);
808}
809
810static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
811{
812 struct intel_engine_cs *engine;
813 enum intel_engine_id id;
814 int err;
815
816 /*
817 * Everything depends on having the GTT running, so we need to start
818 * there.
819 */
820 err = i915_ggtt_enable_hw(gt->i915);
821 if (err)
822 return err;
823
824 local_bh_disable();
825 for_each_engine(engine, gt, id)
826 __intel_engine_reset(engine, stalled_mask & engine->mask);
827 local_bh_enable();
828
829 intel_ggtt_restore_fences(gt->ggtt);
830
831 return err;
832}
833
834static void reset_finish_engine(struct intel_engine_cs *engine)
835{
836 if (engine->reset.finish)
837 engine->reset.finish(engine);
838 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
839
840 intel_engine_signal_breadcrumbs(engine);
841}
842
843static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
844{
845 struct intel_engine_cs *engine;
846 enum intel_engine_id id;
847
848 for_each_engine(engine, gt, id) {
849 reset_finish_engine(engine);
850 if (awake & engine->mask)
851 intel_engine_pm_put(engine);
852 }
853}
854
855static void nop_submit_request(struct i915_request *request)
856{
857 RQ_TRACE(request, "-EIO\n");
858
859 request = i915_request_mark_eio(request);
860 if (request) {
861 i915_request_submit(request);
862 intel_engine_signal_breadcrumbs(request->engine);
863
864 i915_request_put(request);
865 }
866}
867
868static void __intel_gt_set_wedged(struct intel_gt *gt)
869{
870 struct intel_engine_cs *engine;
871 intel_engine_mask_t awake;
872 enum intel_engine_id id;
873
874 if (test_bit(I915_WEDGED, >->reset.flags))
875 return;
876
877 GT_TRACE(gt, "start\n");
878
879 /*
880 * First, stop submission to hw, but do not yet complete requests by
881 * rolling the global seqno forward (since this would complete requests
882 * for which we haven't set the fence error to EIO yet).
883 */
884 awake = reset_prepare(gt);
885
886 /* Even if the GPU reset fails, it should still stop the engines */
887 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
888 __intel_gt_reset(gt, ALL_ENGINES);
889
890 for_each_engine(engine, gt, id)
891 engine->submit_request = nop_submit_request;
892
893 /*
894 * Make sure no request can slip through without getting completed by
895 * either this call here to intel_engine_write_global_seqno, or the one
896 * in nop_submit_request.
897 */
898 synchronize_rcu_expedited();
899 set_bit(I915_WEDGED, >->reset.flags);
900
901 /* Mark all executing requests as skipped */
902 local_bh_disable();
903 for_each_engine(engine, gt, id)
904 if (engine->reset.cancel)
905 engine->reset.cancel(engine);
906 local_bh_enable();
907
908 reset_finish(gt, awake);
909
910 GT_TRACE(gt, "end\n");
911}
912
913void intel_gt_set_wedged(struct intel_gt *gt)
914{
915 intel_wakeref_t wakeref;
916
917 if (test_bit(I915_WEDGED, >->reset.flags))
918 return;
919
920 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
921 mutex_lock(>->reset.mutex);
922
923 if (GEM_SHOW_DEBUG()) {
924 struct drm_printer p = drm_debug_printer(__func__);
925 struct intel_engine_cs *engine;
926 enum intel_engine_id id;
927
928 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
929 for_each_engine(engine, gt, id) {
930 if (intel_engine_is_idle(engine))
931 continue;
932
933 intel_engine_dump(engine, &p, "%s\n", engine->name);
934 }
935 }
936
937 __intel_gt_set_wedged(gt);
938
939 mutex_unlock(>->reset.mutex);
940 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
941}
942
943static bool __intel_gt_unset_wedged(struct intel_gt *gt)
944{
945 struct intel_gt_timelines *timelines = >->timelines;
946 struct intel_timeline *tl;
947 bool ok;
948
949 if (!test_bit(I915_WEDGED, >->reset.flags))
950 return true;
951
952 /* Never fully initialised, recovery impossible */
953 if (intel_gt_has_unrecoverable_error(gt))
954 return false;
955
956 GT_TRACE(gt, "start\n");
957
958 /*
959 * Before unwedging, make sure that all pending operations
960 * are flushed and errored out - we may have requests waiting upon
961 * third party fences. We marked all inflight requests as EIO, and
962 * every execbuf since returned EIO, for consistency we want all
963 * the currently pending requests to also be marked as EIO, which
964 * is done inside our nop_submit_request - and so we must wait.
965 *
966 * No more can be submitted until we reset the wedged bit.
967 */
968 spin_lock(&timelines->lock);
969 list_for_each_entry(tl, &timelines->active_list, link) {
970 struct dma_fence *fence;
971
972 fence = i915_active_fence_get(&tl->last_request);
973 if (!fence)
974 continue;
975
976 spin_unlock(&timelines->lock);
977
978 /*
979 * All internal dependencies (i915_requests) will have
980 * been flushed by the set-wedge, but we may be stuck waiting
981 * for external fences. These should all be capped to 10s
982 * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
983 * in the worst case.
984 */
985 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
986 dma_fence_put(fence);
987
988 /* Restart iteration after droping lock */
989 spin_lock(&timelines->lock);
990 tl = list_entry(&timelines->active_list, typeof(*tl), link);
991 }
992 spin_unlock(&timelines->lock);
993
994 /* We must reset pending GPU events before restoring our submission */
995 ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
996 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
997 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
998 if (!ok) {
999 /*
1000 * Warn CI about the unrecoverable wedged condition.
1001 * Time for a reboot.
1002 */
1003 add_taint_for_CI(gt->i915, TAINT_WARN);
1004 return false;
1005 }
1006
1007 /*
1008 * Undo nop_submit_request. We prevent all new i915 requests from
1009 * being queued (by disallowing execbuf whilst wedged) so having
1010 * waited for all active requests above, we know the system is idle
1011 * and do not have to worry about a thread being inside
1012 * engine->submit_request() as we swap over. So unlike installing
1013 * the nop_submit_request on reset, we can do this from normal
1014 * context and do not require stop_machine().
1015 */
1016 intel_engines_reset_default_submission(gt);
1017
1018 GT_TRACE(gt, "end\n");
1019
1020 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
1021 clear_bit(I915_WEDGED, >->reset.flags);
1022
1023 return true;
1024}
1025
1026bool intel_gt_unset_wedged(struct intel_gt *gt)
1027{
1028 bool result;
1029
1030 mutex_lock(>->reset.mutex);
1031 result = __intel_gt_unset_wedged(gt);
1032 mutex_unlock(>->reset.mutex);
1033
1034 return result;
1035}
1036
1037static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
1038{
1039 int err, i;
1040
1041 err = __intel_gt_reset(gt, ALL_ENGINES);
1042 for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
1043 msleep(10 * (i + 1));
1044 err = __intel_gt_reset(gt, ALL_ENGINES);
1045 }
1046 if (err)
1047 return err;
1048
1049 return gt_reset(gt, stalled_mask);
1050}
1051
1052static int resume(struct intel_gt *gt)
1053{
1054 struct intel_engine_cs *engine;
1055 enum intel_engine_id id;
1056 int ret;
1057
1058 for_each_engine(engine, gt, id) {
1059 ret = intel_engine_resume(engine);
1060 if (ret)
1061 return ret;
1062 }
1063
1064 return 0;
1065}
1066
1067/**
1068 * intel_gt_reset - reset chip after a hang
1069 * @gt: #intel_gt to reset
1070 * @stalled_mask: mask of the stalled engines with the guilty requests
1071 * @reason: user error message for why we are resetting
1072 *
1073 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1074 * on failure.
1075 *
1076 * Procedure is fairly simple:
1077 * - reset the chip using the reset reg
1078 * - re-init context state
1079 * - re-init hardware status page
1080 * - re-init ring buffer
1081 * - re-init interrupt state
1082 * - re-init display
1083 */
1084void intel_gt_reset(struct intel_gt *gt,
1085 intel_engine_mask_t stalled_mask,
1086 const char *reason)
1087{
1088 intel_engine_mask_t awake;
1089 int ret;
1090
1091 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1092
1093 might_sleep();
1094 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags));
1095
1096 /*
1097 * FIXME: Revoking cpu mmap ptes cannot be done from a dma_fence
1098 * critical section like gpu reset.
1099 */
1100 gt_revoke(gt);
1101
1102 mutex_lock(>->reset.mutex);
1103
1104 /* Clear any previous failed attempts at recovery. Time to try again. */
1105 if (!__intel_gt_unset_wedged(gt))
1106 goto unlock;
1107
1108 if (reason)
1109 drm_notice(>->i915->drm,
1110 "Resetting chip for %s\n", reason);
1111 atomic_inc(>->i915->gpu_error.reset_count);
1112
1113 awake = reset_prepare(gt);
1114
1115 if (!intel_has_gpu_reset(gt)) {
1116 if (gt->i915->params.reset)
1117 drm_err(>->i915->drm, "GPU reset not supported\n");
1118 else
1119 drm_dbg(>->i915->drm, "GPU reset disabled\n");
1120 goto error;
1121 }
1122
1123 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1124 intel_runtime_pm_disable_interrupts(gt->i915);
1125
1126 if (do_reset(gt, stalled_mask)) {
1127 drm_err(>->i915->drm, "Failed to reset chip\n");
1128 goto taint;
1129 }
1130
1131 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1132 intel_runtime_pm_enable_interrupts(gt->i915);
1133
1134 intel_overlay_reset(gt->i915);
1135
1136 /*
1137 * Next we need to restore the context, but we don't use those
1138 * yet either...
1139 *
1140 * Ring buffer needs to be re-initialized in the KMS case, or if X
1141 * was running at the time of the reset (i.e. we weren't VT
1142 * switched away).
1143 */
1144 ret = intel_gt_init_hw(gt);
1145 if (ret) {
1146 drm_err(>->i915->drm,
1147 "Failed to initialise HW following reset (%d)\n",
1148 ret);
1149 goto taint;
1150 }
1151
1152 ret = resume(gt);
1153 if (ret)
1154 goto taint;
1155
1156finish:
1157 reset_finish(gt, awake);
1158unlock:
1159 mutex_unlock(>->reset.mutex);
1160 return;
1161
1162taint:
1163 /*
1164 * History tells us that if we cannot reset the GPU now, we
1165 * never will. This then impacts everything that is run
1166 * subsequently. On failing the reset, we mark the driver
1167 * as wedged, preventing further execution on the GPU.
1168 * We also want to go one step further and add a taint to the
1169 * kernel so that any subsequent faults can be traced back to
1170 * this failure. This is important for CI, where if the
1171 * GPU/driver fails we would like to reboot and restart testing
1172 * rather than continue on into oblivion. For everyone else,
1173 * the system should still plod along, but they have been warned!
1174 */
1175 add_taint_for_CI(gt->i915, TAINT_WARN);
1176error:
1177 __intel_gt_set_wedged(gt);
1178 goto finish;
1179}
1180
1181static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1182{
1183 return __intel_gt_reset(engine->gt, engine->mask);
1184}
1185
1186int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1187{
1188 struct intel_gt *gt = engine->gt;
1189 int ret;
1190
1191 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1192 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags));
1193
1194 if (!intel_engine_pm_get_if_awake(engine))
1195 return 0;
1196
1197 reset_prepare_engine(engine);
1198
1199 if (msg)
1200 drm_notice(&engine->i915->drm,
1201 "Resetting %s for %s\n", engine->name, msg);
1202 atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1203
1204 if (intel_engine_uses_guc(engine))
1205 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1206 else
1207 ret = intel_gt_reset_engine(engine);
1208 if (ret) {
1209 /* If we fail here, we expect to fallback to a global reset */
1210 ENGINE_TRACE(engine, "Failed to reset, err: %d\n", ret);
1211 goto out;
1212 }
1213
1214 /*
1215 * The request that caused the hang is stuck on elsp, we know the
1216 * active request and can drop it, adjust head to skip the offending
1217 * request to resume executing remaining requests in the queue.
1218 */
1219 __intel_engine_reset(engine, true);
1220
1221 /*
1222 * The engine and its registers (and workarounds in case of render)
1223 * have been reset to their default values. Follow the init_ring
1224 * process to program RING_MODE, HWSP and re-enable submission.
1225 */
1226 ret = intel_engine_resume(engine);
1227
1228out:
1229 intel_engine_cancel_stop_cs(engine);
1230 reset_finish_engine(engine);
1231 intel_engine_pm_put_async(engine);
1232 return ret;
1233}
1234
1235/**
1236 * intel_engine_reset - reset GPU engine to recover from a hang
1237 * @engine: engine to reset
1238 * @msg: reason for GPU reset; or NULL for no drm_notice()
1239 *
1240 * Reset a specific GPU engine. Useful if a hang is detected.
1241 * Returns zero on successful reset or otherwise an error code.
1242 *
1243 * Procedure is:
1244 * - identifies the request that caused the hang and it is dropped
1245 * - reset engine (which will force the engine to idle)
1246 * - re-init/configure engine
1247 */
1248int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1249{
1250 int err;
1251
1252 local_bh_disable();
1253 err = __intel_engine_reset_bh(engine, msg);
1254 local_bh_enable();
1255
1256 return err;
1257}
1258
1259static void intel_gt_reset_global(struct intel_gt *gt,
1260 u32 engine_mask,
1261 const char *reason)
1262{
1263 struct kobject *kobj = >->i915->drm.primary->kdev->kobj;
1264 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1265 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1266 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1267 struct intel_wedge_me w;
1268
1269 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1270
1271 GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1272 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1273
1274 /* Use a watchdog to ensure that our reset completes */
1275 intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1276 intel_display_prepare_reset(gt->i915);
1277
1278 /* Flush everyone using a resource about to be clobbered */
1279 synchronize_srcu_expedited(>->reset.backoff_srcu);
1280
1281 intel_gt_reset(gt, engine_mask, reason);
1282
1283 intel_display_finish_reset(gt->i915);
1284 }
1285
1286 if (!test_bit(I915_WEDGED, >->reset.flags))
1287 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1288}
1289
1290/**
1291 * intel_gt_handle_error - handle a gpu error
1292 * @gt: the intel_gt
1293 * @engine_mask: mask representing engines that are hung
1294 * @flags: control flags
1295 * @fmt: Error message format string
1296 *
1297 * Do some basic checking of register state at error time and
1298 * dump it to the syslog. Also call i915_capture_error_state() to make
1299 * sure we get a record and make it available in debugfs. Fire a uevent
1300 * so userspace knows something bad happened (should trigger collection
1301 * of a ring dump etc.).
1302 */
1303void intel_gt_handle_error(struct intel_gt *gt,
1304 intel_engine_mask_t engine_mask,
1305 unsigned long flags,
1306 const char *fmt, ...)
1307{
1308 struct intel_engine_cs *engine;
1309 intel_wakeref_t wakeref;
1310 intel_engine_mask_t tmp;
1311 char error_msg[80];
1312 char *msg = NULL;
1313
1314 if (fmt) {
1315 va_list args;
1316
1317 va_start(args, fmt);
1318 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1319 va_end(args);
1320
1321 msg = error_msg;
1322 }
1323
1324 /*
1325 * In most cases it's guaranteed that we get here with an RPM
1326 * reference held, for example because there is a pending GPU
1327 * request that won't finish until the reset is done. This
1328 * isn't the case at least when we get here by doing a
1329 * simulated reset via debugfs, so get an RPM reference.
1330 */
1331 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1332
1333 engine_mask &= gt->info.engine_mask;
1334
1335 if (flags & I915_ERROR_CAPTURE) {
1336 i915_capture_error_state(gt, engine_mask);
1337 intel_gt_clear_error_registers(gt, engine_mask);
1338 }
1339
1340 /*
1341 * Try engine reset when available. We fall back to full reset if
1342 * single reset fails.
1343 */
1344 if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1345 local_bh_disable();
1346 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1347 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1348 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1349 >->reset.flags))
1350 continue;
1351
1352 if (__intel_engine_reset_bh(engine, msg) == 0)
1353 engine_mask &= ~engine->mask;
1354
1355 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1356 >->reset.flags);
1357 }
1358 local_bh_enable();
1359 }
1360
1361 if (!engine_mask)
1362 goto out;
1363
1364 /* Full reset needs the mutex, stop any other user trying to do so. */
1365 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1366 wait_event(gt->reset.queue,
1367 !test_bit(I915_RESET_BACKOFF, >->reset.flags));
1368 goto out; /* piggy-back on the other reset */
1369 }
1370
1371 /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1372 synchronize_rcu_expedited();
1373
1374 /* Prevent any other reset-engine attempt. */
1375 for_each_engine(engine, gt, tmp) {
1376 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1377 >->reset.flags))
1378 wait_on_bit(>->reset.flags,
1379 I915_RESET_ENGINE + engine->id,
1380 TASK_UNINTERRUPTIBLE);
1381 }
1382
1383 intel_gt_reset_global(gt, engine_mask, msg);
1384
1385 for_each_engine(engine, gt, tmp)
1386 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1387 >->reset.flags);
1388 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags);
1389 smp_mb__after_atomic();
1390 wake_up_all(>->reset.queue);
1391
1392out:
1393 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1394}
1395
1396int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1397{
1398 might_lock(>->reset.backoff_srcu);
1399 might_sleep();
1400
1401 rcu_read_lock();
1402 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1403 rcu_read_unlock();
1404
1405 if (wait_event_interruptible(gt->reset.queue,
1406 !test_bit(I915_RESET_BACKOFF,
1407 >->reset.flags)))
1408 return -EINTR;
1409
1410 rcu_read_lock();
1411 }
1412 *srcu = srcu_read_lock(>->reset.backoff_srcu);
1413 rcu_read_unlock();
1414
1415 return 0;
1416}
1417
1418void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1419__releases(>->reset.backoff_srcu)
1420{
1421 srcu_read_unlock(>->reset.backoff_srcu, tag);
1422}
1423
1424int intel_gt_terminally_wedged(struct intel_gt *gt)
1425{
1426 might_sleep();
1427
1428 if (!intel_gt_is_wedged(gt))
1429 return 0;
1430
1431 if (intel_gt_has_unrecoverable_error(gt))
1432 return -EIO;
1433
1434 /* Reset still in progress? Maybe we will recover? */
1435 if (wait_event_interruptible(gt->reset.queue,
1436 !test_bit(I915_RESET_BACKOFF,
1437 >->reset.flags)))
1438 return -EINTR;
1439
1440 return intel_gt_is_wedged(gt) ? -EIO : 0;
1441}
1442
1443void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1444{
1445 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1446 I915_WEDGED_ON_INIT);
1447 intel_gt_set_wedged(gt);
1448 set_bit(I915_WEDGED_ON_INIT, >->reset.flags);
1449
1450 /* Wedged on init is non-recoverable */
1451 add_taint_for_CI(gt->i915, TAINT_WARN);
1452}
1453
1454void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1455{
1456 intel_gt_set_wedged(gt);
1457 set_bit(I915_WEDGED_ON_FINI, >->reset.flags);
1458 intel_gt_retire_requests(gt); /* cleanup any wedged requests */
1459}
1460
1461void intel_gt_init_reset(struct intel_gt *gt)
1462{
1463 init_waitqueue_head(>->reset.queue);
1464 mutex_init(>->reset.mutex);
1465 init_srcu_struct(>->reset.backoff_srcu);
1466
1467 /*
1468 * While undesirable to wait inside the shrinker, complain anyway.
1469 *
1470 * If we have to wait during shrinking, we guarantee forward progress
1471 * by forcing the reset. Therefore during the reset we must not
1472 * re-enter the shrinker. By declaring that we take the reset mutex
1473 * within the shrinker, we forbid ourselves from performing any
1474 * fs-reclaim or taking related locks during reset.
1475 */
1476 i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex);
1477
1478 /* no GPU until we are ready! */
1479 __set_bit(I915_WEDGED, >->reset.flags);
1480}
1481
1482void intel_gt_fini_reset(struct intel_gt *gt)
1483{
1484 cleanup_srcu_struct(>->reset.backoff_srcu);
1485}
1486
1487static void intel_wedge_me(struct work_struct *work)
1488{
1489 struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1490
1491 drm_err(&w->gt->i915->drm,
1492 "%s timed out, cancelling all in-flight rendering.\n",
1493 w->name);
1494 intel_gt_set_wedged(w->gt);
1495}
1496
1497void __intel_init_wedge(struct intel_wedge_me *w,
1498 struct intel_gt *gt,
1499 long timeout,
1500 const char *name)
1501{
1502 w->gt = gt;
1503 w->name = name;
1504
1505 INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1506 schedule_delayed_work(&w->work, timeout);
1507}
1508
1509void __intel_fini_wedge(struct intel_wedge_me *w)
1510{
1511 cancel_delayed_work_sync(&w->work);
1512 destroy_delayed_work_on_stack(&w->work);
1513 w->gt = NULL;
1514}
1515
1516#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1517#include "selftest_reset.c"
1518#include "selftest_hangcheck.c"
1519#endif
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2008-2018 Intel Corporation
4 */
5
6#include <linux/sched/mm.h>
7#include <linux/stop_machine.h>
8#include <linux/string_helpers.h>
9
10#include "display/intel_display_reset.h"
11#include "display/intel_overlay.h"
12
13#include "gem/i915_gem_context.h"
14
15#include "gt/intel_gt_regs.h"
16
17#include "gt/uc/intel_gsc_fw.h"
18
19#include "i915_drv.h"
20#include "i915_file_private.h"
21#include "i915_gpu_error.h"
22#include "i915_irq.h"
23#include "i915_reg.h"
24#include "intel_breadcrumbs.h"
25#include "intel_engine_pm.h"
26#include "intel_engine_regs.h"
27#include "intel_gt.h"
28#include "intel_gt_pm.h"
29#include "intel_gt_print.h"
30#include "intel_gt_requests.h"
31#include "intel_mchbar_regs.h"
32#include "intel_pci_config.h"
33#include "intel_reset.h"
34
35#include "uc/intel_guc.h"
36
37#define RESET_MAX_RETRIES 3
38
39static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
40{
41 struct drm_i915_file_private *file_priv = ctx->file_priv;
42 unsigned long prev_hang;
43 unsigned int score;
44
45 if (IS_ERR_OR_NULL(file_priv))
46 return;
47
48 score = 0;
49 if (banned)
50 score = I915_CLIENT_SCORE_CONTEXT_BAN;
51
52 prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
53 if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
54 score += I915_CLIENT_SCORE_HANG_FAST;
55
56 if (score) {
57 atomic_add(score, &file_priv->ban_score);
58
59 drm_dbg(&ctx->i915->drm,
60 "client %s: gained %u ban score, now %u\n",
61 ctx->name, score,
62 atomic_read(&file_priv->ban_score));
63 }
64}
65
66static bool mark_guilty(struct i915_request *rq)
67{
68 struct i915_gem_context *ctx;
69 unsigned long prev_hang;
70 bool banned;
71 int i;
72
73 if (intel_context_is_closed(rq->context))
74 return true;
75
76 rcu_read_lock();
77 ctx = rcu_dereference(rq->context->gem_context);
78 if (ctx && !kref_get_unless_zero(&ctx->ref))
79 ctx = NULL;
80 rcu_read_unlock();
81 if (!ctx)
82 return intel_context_is_banned(rq->context);
83
84 atomic_inc(&ctx->guilty_count);
85
86 /* Cool contexts are too cool to be banned! (Used for reset testing.) */
87 if (!i915_gem_context_is_bannable(ctx)) {
88 banned = false;
89 goto out;
90 }
91
92 drm_notice(&ctx->i915->drm,
93 "%s context reset due to GPU hang\n",
94 ctx->name);
95
96 /* Record the timestamp for the last N hangs */
97 prev_hang = ctx->hang_timestamp[0];
98 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
99 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
100 ctx->hang_timestamp[i] = jiffies;
101
102 /* If we have hung N+1 times in rapid succession, we ban the context! */
103 banned = !i915_gem_context_is_recoverable(ctx);
104 if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
105 banned = true;
106 if (banned)
107 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
108 ctx->name, atomic_read(&ctx->guilty_count));
109
110 client_mark_guilty(ctx, banned);
111
112out:
113 i915_gem_context_put(ctx);
114 return banned;
115}
116
117static void mark_innocent(struct i915_request *rq)
118{
119 struct i915_gem_context *ctx;
120
121 rcu_read_lock();
122 ctx = rcu_dereference(rq->context->gem_context);
123 if (ctx)
124 atomic_inc(&ctx->active_count);
125 rcu_read_unlock();
126}
127
128void __i915_request_reset(struct i915_request *rq, bool guilty)
129{
130 bool banned = false;
131
132 RQ_TRACE(rq, "guilty? %s\n", str_yes_no(guilty));
133 GEM_BUG_ON(__i915_request_is_complete(rq));
134
135 rcu_read_lock(); /* protect the GEM context */
136 if (guilty) {
137 i915_request_set_error_once(rq, -EIO);
138 __i915_request_skip(rq);
139 banned = mark_guilty(rq);
140 } else {
141 i915_request_set_error_once(rq, -EAGAIN);
142 mark_innocent(rq);
143 }
144 rcu_read_unlock();
145
146 if (banned)
147 intel_context_ban(rq->context, rq);
148}
149
150static bool i915_in_reset(struct pci_dev *pdev)
151{
152 u8 gdrst;
153
154 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
155 return gdrst & GRDOM_RESET_STATUS;
156}
157
158static int i915_do_reset(struct intel_gt *gt,
159 intel_engine_mask_t engine_mask,
160 unsigned int retry)
161{
162 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
163 int err;
164
165 /* Assert reset for at least 50 usec, and wait for acknowledgement. */
166 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
167 udelay(50);
168 err = _wait_for_atomic(i915_in_reset(pdev), 50000, 0);
169
170 /* Clear the reset request. */
171 pci_write_config_byte(pdev, I915_GDRST, 0);
172 udelay(50);
173 if (!err)
174 err = _wait_for_atomic(!i915_in_reset(pdev), 50000, 0);
175
176 return err;
177}
178
179static bool g4x_reset_complete(struct pci_dev *pdev)
180{
181 u8 gdrst;
182
183 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
184 return (gdrst & GRDOM_RESET_ENABLE) == 0;
185}
186
187static int g33_do_reset(struct intel_gt *gt,
188 intel_engine_mask_t engine_mask,
189 unsigned int retry)
190{
191 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
192
193 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
194 return _wait_for_atomic(g4x_reset_complete(pdev), 50000, 0);
195}
196
197static int g4x_do_reset(struct intel_gt *gt,
198 intel_engine_mask_t engine_mask,
199 unsigned int retry)
200{
201 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
202 struct intel_uncore *uncore = gt->uncore;
203 int ret;
204
205 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
206 intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, 0, VCP_UNIT_CLOCK_GATE_DISABLE);
207 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
208
209 pci_write_config_byte(pdev, I915_GDRST,
210 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
211 ret = _wait_for_atomic(g4x_reset_complete(pdev), 50000, 0);
212 if (ret) {
213 GT_TRACE(gt, "Wait for media reset failed\n");
214 goto out;
215 }
216
217 pci_write_config_byte(pdev, I915_GDRST,
218 GRDOM_RENDER | GRDOM_RESET_ENABLE);
219 ret = _wait_for_atomic(g4x_reset_complete(pdev), 50000, 0);
220 if (ret) {
221 GT_TRACE(gt, "Wait for render reset failed\n");
222 goto out;
223 }
224
225out:
226 pci_write_config_byte(pdev, I915_GDRST, 0);
227
228 intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE, 0);
229 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
230
231 return ret;
232}
233
234static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
235 unsigned int retry)
236{
237 struct intel_uncore *uncore = gt->uncore;
238 int ret;
239
240 intel_uncore_write_fw(uncore, ILK_GDSR,
241 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
242 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
243 ILK_GRDOM_RESET_ENABLE, 0,
244 5000, 0,
245 NULL);
246 if (ret) {
247 GT_TRACE(gt, "Wait for render reset failed\n");
248 goto out;
249 }
250
251 intel_uncore_write_fw(uncore, ILK_GDSR,
252 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
253 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
254 ILK_GRDOM_RESET_ENABLE, 0,
255 5000, 0,
256 NULL);
257 if (ret) {
258 GT_TRACE(gt, "Wait for media reset failed\n");
259 goto out;
260 }
261
262out:
263 intel_uncore_write_fw(uncore, ILK_GDSR, 0);
264 intel_uncore_posting_read_fw(uncore, ILK_GDSR);
265 return ret;
266}
267
268/* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
269static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
270{
271 struct intel_uncore *uncore = gt->uncore;
272 int loops;
273 int err;
274
275 /*
276 * On some platforms, e.g. Jasperlake, we see that the engine register
277 * state is not cleared until shortly after GDRST reports completion,
278 * causing a failure as we try to immediately resume while the internal
279 * state is still in flux. If we immediately repeat the reset, the
280 * second reset appears to serialise with the first, and since it is a
281 * no-op, the registers should retain their reset value. However, there
282 * is still a concern that upon leaving the second reset, the internal
283 * engine state is still in flux and not ready for resuming.
284 *
285 * Starting on MTL, there are some prep steps that we need to do when
286 * resetting some engines that need to be applied every time we write to
287 * GEN6_GDRST. As those are time consuming (tens of ms), we don't want
288 * to perform that twice, so, since the Jasperlake issue hasn't been
289 * observed on MTL, we avoid repeating the reset on newer platforms.
290 */
291 loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1;
292
293 /*
294 * GEN6_GDRST is not in the gt power well, no need to check
295 * for fifo space for the write or forcewake the chip for
296 * the read
297 */
298 do {
299 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
300
301 /* Wait for the device to ack the reset requests. */
302 err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
303 hw_domain_mask, 0,
304 2000, 0,
305 NULL);
306 } while (err == 0 && --loops);
307 if (err)
308 GT_TRACE(gt,
309 "Wait for 0x%08x engines reset failed\n",
310 hw_domain_mask);
311
312 /*
313 * As we have observed that the engine state is still volatile
314 * after GDRST is acked, impose a small delay to let everything settle.
315 */
316 udelay(50);
317
318 return err;
319}
320
321static int __gen6_reset_engines(struct intel_gt *gt,
322 intel_engine_mask_t engine_mask,
323 unsigned int retry)
324{
325 struct intel_engine_cs *engine;
326 u32 hw_mask;
327
328 if (engine_mask == ALL_ENGINES) {
329 hw_mask = GEN6_GRDOM_FULL;
330 } else {
331 intel_engine_mask_t tmp;
332
333 hw_mask = 0;
334 for_each_engine_masked(engine, gt, engine_mask, tmp) {
335 hw_mask |= engine->reset_domain;
336 }
337 }
338
339 return gen6_hw_domain_reset(gt, hw_mask);
340}
341
342static int gen6_reset_engines(struct intel_gt *gt,
343 intel_engine_mask_t engine_mask,
344 unsigned int retry)
345{
346 unsigned long flags;
347 int ret;
348
349 spin_lock_irqsave(>->uncore->lock, flags);
350 ret = __gen6_reset_engines(gt, engine_mask, retry);
351 spin_unlock_irqrestore(>->uncore->lock, flags);
352
353 return ret;
354}
355
356static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
357{
358 int vecs_id;
359
360 GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
361
362 vecs_id = _VECS((engine->instance) / 2);
363
364 return engine->gt->engine[vecs_id];
365}
366
367struct sfc_lock_data {
368 i915_reg_t lock_reg;
369 i915_reg_t ack_reg;
370 i915_reg_t usage_reg;
371 u32 lock_bit;
372 u32 ack_bit;
373 u32 usage_bit;
374 u32 reset_bit;
375};
376
377static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
378 struct sfc_lock_data *sfc_lock)
379{
380 switch (engine->class) {
381 default:
382 MISSING_CASE(engine->class);
383 fallthrough;
384 case VIDEO_DECODE_CLASS:
385 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base);
386 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
387
388 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);
389 sfc_lock->ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
390
391 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);
392 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
393 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
394
395 break;
396 case VIDEO_ENHANCEMENT_CLASS:
397 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base);
398 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
399
400 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base);
401 sfc_lock->ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
402
403 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base);
404 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
405 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
406
407 break;
408 }
409}
410
411static int gen11_lock_sfc(struct intel_engine_cs *engine,
412 u32 *reset_mask,
413 u32 *unlock_mask)
414{
415 struct intel_uncore *uncore = engine->uncore;
416 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
417 struct sfc_lock_data sfc_lock;
418 bool lock_obtained, lock_to_other = false;
419 int ret;
420
421 switch (engine->class) {
422 case VIDEO_DECODE_CLASS:
423 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
424 return 0;
425
426 fallthrough;
427 case VIDEO_ENHANCEMENT_CLASS:
428 get_sfc_forced_lock_data(engine, &sfc_lock);
429
430 break;
431 default:
432 return 0;
433 }
434
435 if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
436 struct intel_engine_cs *paired_vecs;
437
438 if (engine->class != VIDEO_DECODE_CLASS ||
439 GRAPHICS_VER(engine->i915) != 12)
440 return 0;
441
442 /*
443 * Wa_14010733141
444 *
445 * If the VCS-MFX isn't using the SFC, we also need to check
446 * whether VCS-HCP is using it. If so, we need to issue a *VE*
447 * forced lock on the VE engine that shares the same SFC.
448 */
449 if (!(intel_uncore_read_fw(uncore,
450 GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) &
451 GEN12_HCP_SFC_USAGE_BIT))
452 return 0;
453
454 paired_vecs = find_sfc_paired_vecs_engine(engine);
455 get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
456 lock_to_other = true;
457 *unlock_mask |= paired_vecs->mask;
458 } else {
459 *unlock_mask |= engine->mask;
460 }
461
462 /*
463 * If the engine is using an SFC, tell the engine that a software reset
464 * is going to happen. The engine will then try to force lock the SFC.
465 * If SFC ends up being locked to the engine we want to reset, we have
466 * to reset it as well (we will unlock it once the reset sequence is
467 * completed).
468 */
469 intel_uncore_rmw_fw(uncore, sfc_lock.lock_reg, 0, sfc_lock.lock_bit);
470
471 ret = __intel_wait_for_register_fw(uncore,
472 sfc_lock.ack_reg,
473 sfc_lock.ack_bit,
474 sfc_lock.ack_bit,
475 1000, 0, NULL);
476
477 /*
478 * Was the SFC released while we were trying to lock it?
479 *
480 * We should reset both the engine and the SFC if:
481 * - We were locking the SFC to this engine and the lock succeeded
482 * OR
483 * - We were locking the SFC to a different engine (Wa_14010733141)
484 * but the SFC was released before the lock was obtained.
485 *
486 * Otherwise we need only reset the engine by itself and we can
487 * leave the SFC alone.
488 */
489 lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
490 sfc_lock.usage_bit) != 0;
491 if (lock_obtained == lock_to_other)
492 return 0;
493
494 if (ret) {
495 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
496 return ret;
497 }
498
499 *reset_mask |= sfc_lock.reset_bit;
500 return 0;
501}
502
503static void gen11_unlock_sfc(struct intel_engine_cs *engine)
504{
505 struct intel_uncore *uncore = engine->uncore;
506 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
507 struct sfc_lock_data sfc_lock = {};
508
509 if (engine->class != VIDEO_DECODE_CLASS &&
510 engine->class != VIDEO_ENHANCEMENT_CLASS)
511 return;
512
513 if (engine->class == VIDEO_DECODE_CLASS &&
514 (BIT(engine->instance) & vdbox_sfc_access) == 0)
515 return;
516
517 get_sfc_forced_lock_data(engine, &sfc_lock);
518
519 intel_uncore_rmw_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit, 0);
520}
521
522static int __gen11_reset_engines(struct intel_gt *gt,
523 intel_engine_mask_t engine_mask,
524 unsigned int retry)
525{
526 struct intel_engine_cs *engine;
527 intel_engine_mask_t tmp;
528 u32 reset_mask, unlock_mask = 0;
529 int ret;
530
531 if (engine_mask == ALL_ENGINES) {
532 reset_mask = GEN11_GRDOM_FULL;
533 } else {
534 reset_mask = 0;
535 for_each_engine_masked(engine, gt, engine_mask, tmp) {
536 reset_mask |= engine->reset_domain;
537 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
538 if (ret)
539 goto sfc_unlock;
540 }
541 }
542
543 ret = gen6_hw_domain_reset(gt, reset_mask);
544
545sfc_unlock:
546 /*
547 * We unlock the SFC based on the lock status and not the result of
548 * gen11_lock_sfc to make sure that we clean properly if something
549 * wrong happened during the lock (e.g. lock acquired after timeout
550 * expiration).
551 *
552 * Due to Wa_14010733141, we may have locked an SFC to an engine that
553 * wasn't being reset. So instead of calling gen11_unlock_sfc()
554 * on engine_mask, we instead call it on the mask of engines that our
555 * gen11_lock_sfc() calls told us actually had locks attempted.
556 */
557 for_each_engine_masked(engine, gt, unlock_mask, tmp)
558 gen11_unlock_sfc(engine);
559
560 return ret;
561}
562
563static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
564{
565 struct intel_uncore *uncore = engine->uncore;
566 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
567 u32 request, mask, ack;
568 int ret;
569
570 if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
571 return -ETIMEDOUT;
572
573 ack = intel_uncore_read_fw(uncore, reg);
574 if (ack & RESET_CTL_CAT_ERROR) {
575 /*
576 * For catastrophic errors, ready-for-reset sequence
577 * needs to be bypassed: HAS#396813
578 */
579 request = RESET_CTL_CAT_ERROR;
580 mask = RESET_CTL_CAT_ERROR;
581
582 /* Catastrophic errors need to be cleared by HW */
583 ack = 0;
584 } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
585 request = RESET_CTL_REQUEST_RESET;
586 mask = RESET_CTL_READY_TO_RESET;
587 ack = RESET_CTL_READY_TO_RESET;
588 } else {
589 return 0;
590 }
591
592 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
593 ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
594 700, 0, NULL);
595 if (ret)
596 gt_err(engine->gt,
597 "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
598 engine->name, request,
599 intel_uncore_read_fw(uncore, reg));
600
601 return ret;
602}
603
604static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
605{
606 intel_uncore_write_fw(engine->uncore,
607 RING_RESET_CTL(engine->mmio_base),
608 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
609}
610
611static int gen8_reset_engines(struct intel_gt *gt,
612 intel_engine_mask_t engine_mask,
613 unsigned int retry)
614{
615 struct intel_engine_cs *engine;
616 const bool reset_non_ready = retry >= 1;
617 intel_engine_mask_t tmp;
618 unsigned long flags;
619 int ret;
620
621 spin_lock_irqsave(>->uncore->lock, flags);
622
623 for_each_engine_masked(engine, gt, engine_mask, tmp) {
624 ret = gen8_engine_reset_prepare(engine);
625 if (ret && !reset_non_ready)
626 goto skip_reset;
627
628 /*
629 * If this is not the first failed attempt to prepare,
630 * we decide to proceed anyway.
631 *
632 * By doing so we risk context corruption and with
633 * some gens (kbl), possible system hang if reset
634 * happens during active bb execution.
635 *
636 * We rather take context corruption instead of
637 * failed reset with a wedged driver/gpu. And
638 * active bb execution case should be covered by
639 * stop_engines() we have before the reset.
640 */
641 }
642
643 /*
644 * Wa_22011100796:dg2, whenever Full soft reset is required,
645 * reset all individual engines firstly, and then do a full soft reset.
646 *
647 * This is best effort, so ignore any error from the initial reset.
648 */
649 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES)
650 __gen11_reset_engines(gt, gt->info.engine_mask, 0);
651
652 if (GRAPHICS_VER(gt->i915) >= 11)
653 ret = __gen11_reset_engines(gt, engine_mask, retry);
654 else
655 ret = __gen6_reset_engines(gt, engine_mask, retry);
656
657skip_reset:
658 for_each_engine_masked(engine, gt, engine_mask, tmp)
659 gen8_engine_reset_cancel(engine);
660
661 spin_unlock_irqrestore(>->uncore->lock, flags);
662
663 return ret;
664}
665
666static int mock_reset(struct intel_gt *gt,
667 intel_engine_mask_t mask,
668 unsigned int retry)
669{
670 return 0;
671}
672
673typedef int (*reset_func)(struct intel_gt *,
674 intel_engine_mask_t engine_mask,
675 unsigned int retry);
676
677static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
678{
679 struct drm_i915_private *i915 = gt->i915;
680
681 if (is_mock_gt(gt))
682 return mock_reset;
683 else if (GRAPHICS_VER(i915) >= 8)
684 return gen8_reset_engines;
685 else if (GRAPHICS_VER(i915) >= 6)
686 return gen6_reset_engines;
687 else if (GRAPHICS_VER(i915) >= 5)
688 return ilk_do_reset;
689 else if (IS_G4X(i915))
690 return g4x_do_reset;
691 else if (IS_G33(i915) || IS_PINEVIEW(i915))
692 return g33_do_reset;
693 else if (GRAPHICS_VER(i915) >= 3)
694 return i915_do_reset;
695 else
696 return NULL;
697}
698
699static int __reset_guc(struct intel_gt *gt)
700{
701 u32 guc_domain =
702 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
703
704 return gen6_hw_domain_reset(gt, guc_domain);
705}
706
707static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
708{
709 if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
710 return false;
711
712 if (!__HAS_ENGINE(engine_mask, GSC0))
713 return false;
714
715 return intel_gsc_uc_fw_init_done(>->uc.gsc);
716}
717
718static intel_engine_mask_t
719wa_14015076503_start(struct intel_gt *gt, intel_engine_mask_t engine_mask, bool first)
720{
721 if (!needs_wa_14015076503(gt, engine_mask))
722 return engine_mask;
723
724 /*
725 * wa_14015076503: if the GSC FW is loaded, we need to alert it that
726 * we're going to do a GSC engine reset and then wait for 200ms for the
727 * FW to get ready for it. However, if this is the first ALL_ENGINES
728 * reset attempt and the GSC is not busy, we can try to instead reset
729 * the GuC and all the other engines individually to avoid the 200ms
730 * wait.
731 * Skipping the GSC engine is safe because, differently from other
732 * engines, the GSCCS only role is to forward the commands to the GSC
733 * FW, so it doesn't have any HW outside of the CS itself and therefore
734 * it has no state that we don't explicitly re-init on resume or on
735 * context switch LRC or power context). The HW for the GSC uC is
736 * managed by the GSC FW so we don't need to care about that.
737 */
738 if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) {
739 __reset_guc(gt);
740 engine_mask = gt->info.engine_mask & ~BIT(GSC0);
741 } else {
742 intel_uncore_rmw(gt->uncore,
743 HECI_H_GS1(MTL_GSC_HECI2_BASE),
744 0, HECI_H_GS1_ER_PREP);
745
746 /* make sure the reset bit is clear when writing the CSR reg */
747 intel_uncore_rmw(gt->uncore,
748 HECI_H_CSR(MTL_GSC_HECI2_BASE),
749 HECI_H_CSR_RST, HECI_H_CSR_IG);
750 msleep(200);
751 }
752
753 return engine_mask;
754}
755
756static void
757wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t engine_mask)
758{
759 if (!needs_wa_14015076503(gt, engine_mask))
760 return;
761
762 intel_uncore_rmw(gt->uncore,
763 HECI_H_GS1(MTL_GSC_HECI2_BASE),
764 HECI_H_GS1_ER_PREP, 0);
765}
766
767int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
768{
769 const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
770 reset_func reset;
771 int ret = -ETIMEDOUT;
772 int retry;
773
774 reset = intel_get_gpu_reset(gt);
775 if (!reset)
776 return -ENODEV;
777
778 /*
779 * If the power well sleeps during the reset, the reset
780 * request may be dropped and never completes (causing -EIO).
781 */
782 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
783 for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
784 intel_engine_mask_t reset_mask;
785
786 reset_mask = wa_14015076503_start(gt, engine_mask, !retry);
787
788 GT_TRACE(gt, "engine_mask=%x\n", reset_mask);
789 ret = reset(gt, reset_mask, retry);
790
791 wa_14015076503_end(gt, reset_mask);
792 }
793 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
794
795 return ret;
796}
797
798bool intel_has_gpu_reset(const struct intel_gt *gt)
799{
800 if (!gt->i915->params.reset)
801 return NULL;
802
803 return intel_get_gpu_reset(gt);
804}
805
806bool intel_has_reset_engine(const struct intel_gt *gt)
807{
808 if (gt->i915->params.reset < 2)
809 return false;
810
811 return INTEL_INFO(gt->i915)->has_reset_engine;
812}
813
814int intel_reset_guc(struct intel_gt *gt)
815{
816 int ret;
817
818 GEM_BUG_ON(!HAS_GT_UC(gt->i915));
819
820 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
821 ret = __reset_guc(gt);
822 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
823
824 return ret;
825}
826
827/*
828 * Ensure irq handler finishes, and not run again.
829 * Also return the active request so that we only search for it once.
830 */
831static void reset_prepare_engine(struct intel_engine_cs *engine)
832{
833 /*
834 * During the reset sequence, we must prevent the engine from
835 * entering RC6. As the context state is undefined until we restart
836 * the engine, if it does enter RC6 during the reset, the state
837 * written to the powercontext is undefined and so we may lose
838 * GPU state upon resume, i.e. fail to restart after a reset.
839 */
840 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
841 if (engine->reset.prepare)
842 engine->reset.prepare(engine);
843}
844
845static void revoke_mmaps(struct intel_gt *gt)
846{
847 int i;
848
849 for (i = 0; i < gt->ggtt->num_fences; i++) {
850 struct drm_vma_offset_node *node;
851 struct i915_vma *vma;
852 u64 vma_offset;
853
854 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
855 if (!vma)
856 continue;
857
858 if (!i915_vma_has_userfault(vma))
859 continue;
860
861 GEM_BUG_ON(vma->fence != >->ggtt->fence_regs[i]);
862
863 if (!vma->mmo)
864 continue;
865
866 node = &vma->mmo->vma_node;
867 vma_offset = vma->gtt_view.partial.offset << PAGE_SHIFT;
868
869 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
870 drm_vma_node_offset_addr(node) + vma_offset,
871 vma->size,
872 1);
873 }
874}
875
876static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
877{
878 struct intel_engine_cs *engine;
879 intel_engine_mask_t awake = 0;
880 enum intel_engine_id id;
881
882 /* For GuC mode, ensure submission is disabled before stopping ring */
883 intel_uc_reset_prepare(>->uc);
884
885 for_each_engine(engine, gt, id) {
886 if (intel_engine_pm_get_if_awake(engine))
887 awake |= engine->mask;
888 reset_prepare_engine(engine);
889 }
890
891 return awake;
892}
893
894static void gt_revoke(struct intel_gt *gt)
895{
896 revoke_mmaps(gt);
897}
898
899static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
900{
901 struct intel_engine_cs *engine;
902 enum intel_engine_id id;
903 int err;
904
905 /*
906 * Everything depends on having the GTT running, so we need to start
907 * there.
908 */
909 err = i915_ggtt_enable_hw(gt->i915);
910 if (err)
911 return err;
912
913 local_bh_disable();
914 for_each_engine(engine, gt, id)
915 __intel_engine_reset(engine, stalled_mask & engine->mask);
916 local_bh_enable();
917
918 intel_uc_reset(>->uc, ALL_ENGINES);
919
920 intel_ggtt_restore_fences(gt->ggtt);
921
922 return err;
923}
924
925static void reset_finish_engine(struct intel_engine_cs *engine)
926{
927 if (engine->reset.finish)
928 engine->reset.finish(engine);
929 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
930
931 intel_engine_signal_breadcrumbs(engine);
932}
933
934static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
935{
936 struct intel_engine_cs *engine;
937 enum intel_engine_id id;
938
939 for_each_engine(engine, gt, id) {
940 reset_finish_engine(engine);
941 if (awake & engine->mask)
942 intel_engine_pm_put(engine);
943 }
944
945 intel_uc_reset_finish(>->uc);
946}
947
948static void nop_submit_request(struct i915_request *request)
949{
950 RQ_TRACE(request, "-EIO\n");
951
952 request = i915_request_mark_eio(request);
953 if (request) {
954 i915_request_submit(request);
955 intel_engine_signal_breadcrumbs(request->engine);
956
957 i915_request_put(request);
958 }
959}
960
961static void __intel_gt_set_wedged(struct intel_gt *gt)
962{
963 struct intel_engine_cs *engine;
964 intel_engine_mask_t awake;
965 enum intel_engine_id id;
966
967 if (test_bit(I915_WEDGED, >->reset.flags))
968 return;
969
970 GT_TRACE(gt, "start\n");
971
972 /*
973 * First, stop submission to hw, but do not yet complete requests by
974 * rolling the global seqno forward (since this would complete requests
975 * for which we haven't set the fence error to EIO yet).
976 */
977 awake = reset_prepare(gt);
978
979 /* Even if the GPU reset fails, it should still stop the engines */
980 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
981 __intel_gt_reset(gt, ALL_ENGINES);
982
983 for_each_engine(engine, gt, id)
984 engine->submit_request = nop_submit_request;
985
986 /*
987 * Make sure no request can slip through without getting completed by
988 * either this call here to intel_engine_write_global_seqno, or the one
989 * in nop_submit_request.
990 */
991 synchronize_rcu_expedited();
992 set_bit(I915_WEDGED, >->reset.flags);
993
994 /* Mark all executing requests as skipped */
995 local_bh_disable();
996 for_each_engine(engine, gt, id)
997 if (engine->reset.cancel)
998 engine->reset.cancel(engine);
999 intel_uc_cancel_requests(>->uc);
1000 local_bh_enable();
1001
1002 reset_finish(gt, awake);
1003
1004 GT_TRACE(gt, "end\n");
1005}
1006
1007void intel_gt_set_wedged(struct intel_gt *gt)
1008{
1009 intel_wakeref_t wakeref;
1010
1011 if (test_bit(I915_WEDGED, >->reset.flags))
1012 return;
1013
1014 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1015 mutex_lock(>->reset.mutex);
1016
1017 if (GEM_SHOW_DEBUG()) {
1018 struct drm_printer p = drm_debug_printer(__func__);
1019 struct intel_engine_cs *engine;
1020 enum intel_engine_id id;
1021
1022 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
1023 for_each_engine(engine, gt, id) {
1024 if (intel_engine_is_idle(engine))
1025 continue;
1026
1027 intel_engine_dump(engine, &p, "%s\n", engine->name);
1028 }
1029 }
1030
1031 __intel_gt_set_wedged(gt);
1032
1033 mutex_unlock(>->reset.mutex);
1034 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1035}
1036
1037static bool __intel_gt_unset_wedged(struct intel_gt *gt)
1038{
1039 struct intel_gt_timelines *timelines = >->timelines;
1040 struct intel_timeline *tl;
1041 bool ok;
1042
1043 if (!test_bit(I915_WEDGED, >->reset.flags))
1044 return true;
1045
1046 /* Never fully initialised, recovery impossible */
1047 if (intel_gt_has_unrecoverable_error(gt))
1048 return false;
1049
1050 GT_TRACE(gt, "start\n");
1051
1052 /*
1053 * Before unwedging, make sure that all pending operations
1054 * are flushed and errored out - we may have requests waiting upon
1055 * third party fences. We marked all inflight requests as EIO, and
1056 * every execbuf since returned EIO, for consistency we want all
1057 * the currently pending requests to also be marked as EIO, which
1058 * is done inside our nop_submit_request - and so we must wait.
1059 *
1060 * No more can be submitted until we reset the wedged bit.
1061 */
1062 spin_lock(&timelines->lock);
1063 list_for_each_entry(tl, &timelines->active_list, link) {
1064 struct dma_fence *fence;
1065
1066 fence = i915_active_fence_get(&tl->last_request);
1067 if (!fence)
1068 continue;
1069
1070 spin_unlock(&timelines->lock);
1071
1072 /*
1073 * All internal dependencies (i915_requests) will have
1074 * been flushed by the set-wedge, but we may be stuck waiting
1075 * for external fences. These should all be capped to 10s
1076 * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
1077 * in the worst case.
1078 */
1079 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
1080 dma_fence_put(fence);
1081
1082 /* Restart iteration after droping lock */
1083 spin_lock(&timelines->lock);
1084 tl = list_entry(&timelines->active_list, typeof(*tl), link);
1085 }
1086 spin_unlock(&timelines->lock);
1087
1088 /* We must reset pending GPU events before restoring our submission */
1089 ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
1090 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1091 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
1092 if (!ok) {
1093 /*
1094 * Warn CI about the unrecoverable wedged condition.
1095 * Time for a reboot.
1096 */
1097 add_taint_for_CI(gt->i915, TAINT_WARN);
1098 return false;
1099 }
1100
1101 /*
1102 * Undo nop_submit_request. We prevent all new i915 requests from
1103 * being queued (by disallowing execbuf whilst wedged) so having
1104 * waited for all active requests above, we know the system is idle
1105 * and do not have to worry about a thread being inside
1106 * engine->submit_request() as we swap over. So unlike installing
1107 * the nop_submit_request on reset, we can do this from normal
1108 * context and do not require stop_machine().
1109 */
1110 intel_engines_reset_default_submission(gt);
1111
1112 GT_TRACE(gt, "end\n");
1113
1114 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
1115 clear_bit(I915_WEDGED, >->reset.flags);
1116
1117 return true;
1118}
1119
1120bool intel_gt_unset_wedged(struct intel_gt *gt)
1121{
1122 bool result;
1123
1124 mutex_lock(>->reset.mutex);
1125 result = __intel_gt_unset_wedged(gt);
1126 mutex_unlock(>->reset.mutex);
1127
1128 return result;
1129}
1130
1131static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
1132{
1133 int err, i;
1134
1135 err = __intel_gt_reset(gt, ALL_ENGINES);
1136 for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
1137 msleep(10 * (i + 1));
1138 err = __intel_gt_reset(gt, ALL_ENGINES);
1139 }
1140 if (err)
1141 return err;
1142
1143 return gt_reset(gt, stalled_mask);
1144}
1145
1146static int resume(struct intel_gt *gt)
1147{
1148 struct intel_engine_cs *engine;
1149 enum intel_engine_id id;
1150 int ret;
1151
1152 for_each_engine(engine, gt, id) {
1153 ret = intel_engine_resume(engine);
1154 if (ret)
1155 return ret;
1156 }
1157
1158 return 0;
1159}
1160
1161/**
1162 * intel_gt_reset - reset chip after a hang
1163 * @gt: #intel_gt to reset
1164 * @stalled_mask: mask of the stalled engines with the guilty requests
1165 * @reason: user error message for why we are resetting
1166 *
1167 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1168 * on failure.
1169 *
1170 * Procedure is fairly simple:
1171 * - reset the chip using the reset reg
1172 * - re-init context state
1173 * - re-init hardware status page
1174 * - re-init ring buffer
1175 * - re-init interrupt state
1176 * - re-init display
1177 */
1178void intel_gt_reset(struct intel_gt *gt,
1179 intel_engine_mask_t stalled_mask,
1180 const char *reason)
1181{
1182 intel_engine_mask_t awake;
1183 int ret;
1184
1185 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1186
1187 might_sleep();
1188 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags));
1189
1190 /*
1191 * FIXME: Revoking cpu mmap ptes cannot be done from a dma_fence
1192 * critical section like gpu reset.
1193 */
1194 gt_revoke(gt);
1195
1196 mutex_lock(>->reset.mutex);
1197
1198 /* Clear any previous failed attempts at recovery. Time to try again. */
1199 if (!__intel_gt_unset_wedged(gt))
1200 goto unlock;
1201
1202 if (reason)
1203 gt_notice(gt, "Resetting chip for %s\n", reason);
1204 atomic_inc(>->i915->gpu_error.reset_count);
1205
1206 awake = reset_prepare(gt);
1207
1208 if (!intel_has_gpu_reset(gt)) {
1209 if (gt->i915->params.reset)
1210 gt_err(gt, "GPU reset not supported\n");
1211 else
1212 gt_dbg(gt, "GPU reset disabled\n");
1213 goto error;
1214 }
1215
1216 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1217 intel_runtime_pm_disable_interrupts(gt->i915);
1218
1219 if (do_reset(gt, stalled_mask)) {
1220 gt_err(gt, "Failed to reset chip\n");
1221 goto taint;
1222 }
1223
1224 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1225 intel_runtime_pm_enable_interrupts(gt->i915);
1226
1227 intel_overlay_reset(gt->i915);
1228
1229 /*
1230 * Next we need to restore the context, but we don't use those
1231 * yet either...
1232 *
1233 * Ring buffer needs to be re-initialized in the KMS case, or if X
1234 * was running at the time of the reset (i.e. we weren't VT
1235 * switched away).
1236 */
1237 ret = intel_gt_init_hw(gt);
1238 if (ret) {
1239 gt_err(gt, "Failed to initialise HW following reset (%d)\n", ret);
1240 goto taint;
1241 }
1242
1243 ret = resume(gt);
1244 if (ret)
1245 goto taint;
1246
1247finish:
1248 reset_finish(gt, awake);
1249unlock:
1250 mutex_unlock(>->reset.mutex);
1251 return;
1252
1253taint:
1254 /*
1255 * History tells us that if we cannot reset the GPU now, we
1256 * never will. This then impacts everything that is run
1257 * subsequently. On failing the reset, we mark the driver
1258 * as wedged, preventing further execution on the GPU.
1259 * We also want to go one step further and add a taint to the
1260 * kernel so that any subsequent faults can be traced back to
1261 * this failure. This is important for CI, where if the
1262 * GPU/driver fails we would like to reboot and restart testing
1263 * rather than continue on into oblivion. For everyone else,
1264 * the system should still plod along, but they have been warned!
1265 */
1266 add_taint_for_CI(gt->i915, TAINT_WARN);
1267error:
1268 __intel_gt_set_wedged(gt);
1269 goto finish;
1270}
1271
1272static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1273{
1274 return __intel_gt_reset(engine->gt, engine->mask);
1275}
1276
1277int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1278{
1279 struct intel_gt *gt = engine->gt;
1280 int ret;
1281
1282 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1283 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags));
1284
1285 if (intel_engine_uses_guc(engine))
1286 return -ENODEV;
1287
1288 if (!intel_engine_pm_get_if_awake(engine))
1289 return 0;
1290
1291 reset_prepare_engine(engine);
1292
1293 if (msg)
1294 drm_notice(&engine->i915->drm,
1295 "Resetting %s for %s\n", engine->name, msg);
1296 i915_increase_reset_engine_count(&engine->i915->gpu_error, engine);
1297
1298 ret = intel_gt_reset_engine(engine);
1299 if (ret) {
1300 /* If we fail here, we expect to fallback to a global reset */
1301 ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);
1302 goto out;
1303 }
1304
1305 /*
1306 * The request that caused the hang is stuck on elsp, we know the
1307 * active request and can drop it, adjust head to skip the offending
1308 * request to resume executing remaining requests in the queue.
1309 */
1310 __intel_engine_reset(engine, true);
1311
1312 /*
1313 * The engine and its registers (and workarounds in case of render)
1314 * have been reset to their default values. Follow the init_ring
1315 * process to program RING_MODE, HWSP and re-enable submission.
1316 */
1317 ret = intel_engine_resume(engine);
1318
1319out:
1320 intel_engine_cancel_stop_cs(engine);
1321 reset_finish_engine(engine);
1322 intel_engine_pm_put_async(engine);
1323 return ret;
1324}
1325
1326/**
1327 * intel_engine_reset - reset GPU engine to recover from a hang
1328 * @engine: engine to reset
1329 * @msg: reason for GPU reset; or NULL for no drm_notice()
1330 *
1331 * Reset a specific GPU engine. Useful if a hang is detected.
1332 * Returns zero on successful reset or otherwise an error code.
1333 *
1334 * Procedure is:
1335 * - identifies the request that caused the hang and it is dropped
1336 * - reset engine (which will force the engine to idle)
1337 * - re-init/configure engine
1338 */
1339int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1340{
1341 int err;
1342
1343 local_bh_disable();
1344 err = __intel_engine_reset_bh(engine, msg);
1345 local_bh_enable();
1346
1347 return err;
1348}
1349
1350static void intel_gt_reset_global(struct intel_gt *gt,
1351 u32 engine_mask,
1352 const char *reason)
1353{
1354 struct kobject *kobj = >->i915->drm.primary->kdev->kobj;
1355 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1356 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1357 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1358 struct intel_wedge_me w;
1359
1360 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1361
1362 GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1363 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1364
1365 /* Use a watchdog to ensure that our reset completes */
1366 intel_wedge_on_timeout(&w, gt, 60 * HZ) {
1367 intel_display_reset_prepare(gt->i915);
1368
1369 intel_gt_reset(gt, engine_mask, reason);
1370
1371 intel_display_reset_finish(gt->i915);
1372 }
1373
1374 if (!test_bit(I915_WEDGED, >->reset.flags))
1375 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1376}
1377
1378/**
1379 * intel_gt_handle_error - handle a gpu error
1380 * @gt: the intel_gt
1381 * @engine_mask: mask representing engines that are hung
1382 * @flags: control flags
1383 * @fmt: Error message format string
1384 *
1385 * Do some basic checking of register state at error time and
1386 * dump it to the syslog. Also call i915_capture_error_state() to make
1387 * sure we get a record and make it available in debugfs. Fire a uevent
1388 * so userspace knows something bad happened (should trigger collection
1389 * of a ring dump etc.).
1390 */
1391void intel_gt_handle_error(struct intel_gt *gt,
1392 intel_engine_mask_t engine_mask,
1393 unsigned long flags,
1394 const char *fmt, ...)
1395{
1396 struct intel_engine_cs *engine;
1397 intel_wakeref_t wakeref;
1398 intel_engine_mask_t tmp;
1399 char error_msg[80];
1400 char *msg = NULL;
1401
1402 if (fmt) {
1403 va_list args;
1404
1405 va_start(args, fmt);
1406 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1407 va_end(args);
1408
1409 msg = error_msg;
1410 }
1411
1412 /*
1413 * In most cases it's guaranteed that we get here with an RPM
1414 * reference held, for example because there is a pending GPU
1415 * request that won't finish until the reset is done. This
1416 * isn't the case at least when we get here by doing a
1417 * simulated reset via debugfs, so get an RPM reference.
1418 */
1419 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1420
1421 engine_mask &= gt->info.engine_mask;
1422
1423 if (flags & I915_ERROR_CAPTURE) {
1424 i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_NONE);
1425 intel_gt_clear_error_registers(gt, engine_mask);
1426 }
1427
1428 /*
1429 * Try engine reset when available. We fall back to full reset if
1430 * single reset fails.
1431 */
1432 if (!intel_uc_uses_guc_submission(>->uc) &&
1433 intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1434 local_bh_disable();
1435 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1436 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1437 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1438 >->reset.flags))
1439 continue;
1440
1441 if (__intel_engine_reset_bh(engine, msg) == 0)
1442 engine_mask &= ~engine->mask;
1443
1444 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1445 >->reset.flags);
1446 }
1447 local_bh_enable();
1448 }
1449
1450 if (!engine_mask)
1451 goto out;
1452
1453 /* Full reset needs the mutex, stop any other user trying to do so. */
1454 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1455 wait_event(gt->reset.queue,
1456 !test_bit(I915_RESET_BACKOFF, >->reset.flags));
1457 goto out; /* piggy-back on the other reset */
1458 }
1459
1460 /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1461 synchronize_rcu_expedited();
1462
1463 /*
1464 * Prevent any other reset-engine attempt. We don't do this for GuC
1465 * submission the GuC owns the per-engine reset, not the i915.
1466 */
1467 if (!intel_uc_uses_guc_submission(>->uc)) {
1468 for_each_engine(engine, gt, tmp) {
1469 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1470 >->reset.flags))
1471 wait_on_bit(>->reset.flags,
1472 I915_RESET_ENGINE + engine->id,
1473 TASK_UNINTERRUPTIBLE);
1474 }
1475 }
1476
1477 /* Flush everyone using a resource about to be clobbered */
1478 synchronize_srcu_expedited(>->reset.backoff_srcu);
1479
1480 intel_gt_reset_global(gt, engine_mask, msg);
1481
1482 if (!intel_uc_uses_guc_submission(>->uc)) {
1483 for_each_engine(engine, gt, tmp)
1484 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1485 >->reset.flags);
1486 }
1487 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags);
1488 smp_mb__after_atomic();
1489 wake_up_all(>->reset.queue);
1490
1491out:
1492 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1493}
1494
1495static int _intel_gt_reset_lock(struct intel_gt *gt, int *srcu, bool retry)
1496{
1497 might_lock(>->reset.backoff_srcu);
1498 if (retry)
1499 might_sleep();
1500
1501 rcu_read_lock();
1502 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1503 rcu_read_unlock();
1504
1505 if (!retry)
1506 return -EBUSY;
1507
1508 if (wait_event_interruptible(gt->reset.queue,
1509 !test_bit(I915_RESET_BACKOFF,
1510 >->reset.flags)))
1511 return -EINTR;
1512
1513 rcu_read_lock();
1514 }
1515 *srcu = srcu_read_lock(>->reset.backoff_srcu);
1516 rcu_read_unlock();
1517
1518 return 0;
1519}
1520
1521int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1522{
1523 return _intel_gt_reset_lock(gt, srcu, false);
1524}
1525
1526int intel_gt_reset_lock_interruptible(struct intel_gt *gt, int *srcu)
1527{
1528 return _intel_gt_reset_lock(gt, srcu, true);
1529}
1530
1531void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1532__releases(>->reset.backoff_srcu)
1533{
1534 srcu_read_unlock(>->reset.backoff_srcu, tag);
1535}
1536
1537int intel_gt_terminally_wedged(struct intel_gt *gt)
1538{
1539 might_sleep();
1540
1541 if (!intel_gt_is_wedged(gt))
1542 return 0;
1543
1544 if (intel_gt_has_unrecoverable_error(gt))
1545 return -EIO;
1546
1547 /* Reset still in progress? Maybe we will recover? */
1548 if (wait_event_interruptible(gt->reset.queue,
1549 !test_bit(I915_RESET_BACKOFF,
1550 >->reset.flags)))
1551 return -EINTR;
1552
1553 return intel_gt_is_wedged(gt) ? -EIO : 0;
1554}
1555
1556void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1557{
1558 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1559 I915_WEDGED_ON_INIT);
1560 intel_gt_set_wedged(gt);
1561 i915_disable_error_state(gt->i915, -ENODEV);
1562 set_bit(I915_WEDGED_ON_INIT, >->reset.flags);
1563
1564 /* Wedged on init is non-recoverable */
1565 add_taint_for_CI(gt->i915, TAINT_WARN);
1566}
1567
1568void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1569{
1570 intel_gt_set_wedged(gt);
1571 i915_disable_error_state(gt->i915, -ENODEV);
1572 set_bit(I915_WEDGED_ON_FINI, >->reset.flags);
1573 intel_gt_retire_requests(gt); /* cleanup any wedged requests */
1574}
1575
1576void intel_gt_init_reset(struct intel_gt *gt)
1577{
1578 init_waitqueue_head(>->reset.queue);
1579 mutex_init(>->reset.mutex);
1580 init_srcu_struct(>->reset.backoff_srcu);
1581
1582 /*
1583 * While undesirable to wait inside the shrinker, complain anyway.
1584 *
1585 * If we have to wait during shrinking, we guarantee forward progress
1586 * by forcing the reset. Therefore during the reset we must not
1587 * re-enter the shrinker. By declaring that we take the reset mutex
1588 * within the shrinker, we forbid ourselves from performing any
1589 * fs-reclaim or taking related locks during reset.
1590 */
1591 i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex);
1592
1593 /* no GPU until we are ready! */
1594 __set_bit(I915_WEDGED, >->reset.flags);
1595}
1596
1597void intel_gt_fini_reset(struct intel_gt *gt)
1598{
1599 cleanup_srcu_struct(>->reset.backoff_srcu);
1600}
1601
1602static void intel_wedge_me(struct work_struct *work)
1603{
1604 struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1605
1606 gt_err(w->gt, "%s timed out, cancelling all in-flight rendering.\n", w->name);
1607 intel_gt_set_wedged(w->gt);
1608}
1609
1610void __intel_init_wedge(struct intel_wedge_me *w,
1611 struct intel_gt *gt,
1612 long timeout,
1613 const char *name)
1614{
1615 w->gt = gt;
1616 w->name = name;
1617
1618 INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1619 queue_delayed_work(gt->i915->unordered_wq, &w->work, timeout);
1620}
1621
1622void __intel_fini_wedge(struct intel_wedge_me *w)
1623{
1624 cancel_delayed_work_sync(&w->work);
1625 destroy_delayed_work_on_stack(&w->work);
1626 w->gt = NULL;
1627}
1628
1629/*
1630 * Wa_22011802037 requires that we (or the GuC) ensure that no command
1631 * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
1632 */
1633bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
1634{
1635 if (GRAPHICS_VER(gt->i915) < 11)
1636 return false;
1637
1638 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
1639 return true;
1640
1641 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
1642 return false;
1643
1644 return true;
1645}
1646
1647#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1648#include "selftest_reset.c"
1649#include "selftest_hangcheck.c"
1650#endif