1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/delay.h>
  25#include <linux/firmware.h>
  26#include <linux/module.h>
  27#include <linux/pci.h>
  28
  29#include "amdgpu.h"
  30#include "amdgpu_ucode.h"
  31#include "amdgpu_trace.h"
  32
  33#include "gc/gc_10_3_0_offset.h"
  34#include "gc/gc_10_3_0_sh_mask.h"
  35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37#include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38#include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40#include "soc15_common.h"
  41#include "soc15.h"
  42#include "navi10_sdma_pkt_open.h"
  43#include "nbio_v2_3.h"
  44#include "sdma_common.h"
  45#include "sdma_v5_2.h"
  46
  47MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
  51
  52MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  53MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
 
 
  54
  55#define SDMA1_REG_OFFSET 0x600
  56#define SDMA3_REG_OFFSET 0x400
  57#define SDMA0_HYP_DEC_REG_START 0x5880
  58#define SDMA0_HYP_DEC_REG_END 0x5893
  59#define SDMA1_HYP_DEC_REG_OFFSET 0x20
  60
  61static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  62static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  63static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  64static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  65
  66static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  67{
  68	u32 base;
  69
  70	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  71	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
  72		base = adev->reg_offset[GC_HWIP][0][1];
  73		if (instance != 0)
  74			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  75	} else {
  76		if (instance < 2) {
  77			base = adev->reg_offset[GC_HWIP][0][0];
  78			if (instance == 1)
  79				internal_offset += SDMA1_REG_OFFSET;
  80		} else {
  81			base = adev->reg_offset[GC_HWIP][0][2];
  82			if (instance == 3)
  83				internal_offset += SDMA3_REG_OFFSET;
  84		}
  85	}
  86
  87	return base + internal_offset;
  88}
  89
  90static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  91{
  92	switch (adev->asic_type) {
  93	case CHIP_SIENNA_CICHLID:
  94	case CHIP_NAVY_FLOUNDER:
  95	case CHIP_VANGOGH:
  96	case CHIP_DIMGREY_CAVEFISH:
  97	case CHIP_BEIGE_GOBY:
  98	case CHIP_YELLOW_CARP:
  99		break;
 100	default:
 101		break;
 102	}
 103}
 104
 105static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 106{
 107	int err = 0;
 108	const struct sdma_firmware_header_v1_0 *hdr;
 109
 110	err = amdgpu_ucode_validate(sdma_inst->fw);
 111	if (err)
 112		return err;
 113
 114	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 115	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 116	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 117
 118	if (sdma_inst->feature_version >= 20)
 119		sdma_inst->burst_nop = true;
 120
 121	return 0;
 122}
 123
 124static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 125{
 126	release_firmware(adev->sdma.instance[0].fw);
 127
 128	memset((void *)adev->sdma.instance, 0,
 129	       sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 130}
 131
 132/**
 133 * sdma_v5_2_init_microcode - load ucode images from disk
 134 *
 135 * @adev: amdgpu_device pointer
 136 *
 137 * Use the firmware interface to load the ucode images into
 138 * the driver (not loaded into hw).
 139 * Returns 0 on success, error on failure.
 140 */
 141
 142// emulation only, won't work on real chip
 143// navi10 real chip need to use PSP to load firmware
 144static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 145{
 146	const char *chip_name;
 147	char fw_name[40];
 148	int err = 0, i;
 149	struct amdgpu_firmware_info *info = NULL;
 150	const struct common_firmware_header *header = NULL;
 151
 152	DRM_DEBUG("\n");
 153
 154	switch (adev->asic_type) {
 155	case CHIP_SIENNA_CICHLID:
 156		chip_name = "sienna_cichlid";
 157		break;
 158	case CHIP_NAVY_FLOUNDER:
 159		chip_name = "navy_flounder";
 160		break;
 161	case CHIP_VANGOGH:
 162		chip_name = "vangogh";
 163		break;
 164	case CHIP_DIMGREY_CAVEFISH:
 165		chip_name = "dimgrey_cavefish";
 166		break;
 167	case CHIP_BEIGE_GOBY:
 168		chip_name = "beige_goby";
 169		break;
 170	case CHIP_YELLOW_CARP:
 171		chip_name = "yellow_carp";
 172		break;
 173	default:
 174		BUG();
 175	}
 176
 177	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 178
 179	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 180	if (err)
 181		goto out;
 182
 183	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 184	if (err)
 185		goto out;
 186
 187	for (i = 1; i < adev->sdma.num_instances; i++)
 188		memcpy((void *)&adev->sdma.instance[i],
 189		       (void *)&adev->sdma.instance[0],
 190		       sizeof(struct amdgpu_sdma_instance));
 191
 192	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
 193		return 0;
 194
 195	DRM_DEBUG("psp_load == '%s'\n",
 196		  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 197
 198	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 199		for (i = 0; i < adev->sdma.num_instances; i++) {
 200			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 201			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 202			info->fw = adev->sdma.instance[i].fw;
 203			header = (const struct common_firmware_header *)info->fw->data;
 204			adev->firmware.fw_size +=
 205				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 206		}
 207	}
 208
 209out:
 210	if (err) {
 211		DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 212		sdma_v5_2_destroy_inst_ctx(adev);
 213	}
 214	return err;
 215}
 216
 217static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 218{
 219	unsigned ret;
 220
 221	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 222	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 223	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 224	amdgpu_ring_write(ring, 1);
 225	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 226	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 227
 228	return ret;
 229}
 230
 231static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 232					   unsigned offset)
 233{
 234	unsigned cur;
 235
 236	BUG_ON(offset > ring->buf_mask);
 237	BUG_ON(ring->ring[offset] != 0x55aa55aa);
 238
 239	cur = (ring->wptr - 1) & ring->buf_mask;
 240	if (cur > offset)
 241		ring->ring[offset] = cur - offset;
 242	else
 243		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 244}
 245
 246/**
 247 * sdma_v5_2_ring_get_rptr - get the current read pointer
 248 *
 249 * @ring: amdgpu ring pointer
 250 *
 251 * Get the current rptr from the hardware (NAVI10+).
 252 */
 253static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 254{
 255	u64 *rptr;
 256
 257	/* XXX check if swapping is necessary on BE */
 258	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 259
 260	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 261	return ((*rptr) >> 2);
 262}
 263
 264/**
 265 * sdma_v5_2_ring_get_wptr - get the current write pointer
 266 *
 267 * @ring: amdgpu ring pointer
 268 *
 269 * Get the current wptr from the hardware (NAVI10+).
 270 */
 271static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 272{
 273	struct amdgpu_device *adev = ring->adev;
 274	u64 wptr;
 275
 276	if (ring->use_doorbell) {
 277		/* XXX check if swapping is necessary on BE */
 278		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 279		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 280	} else {
 281		wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 282		wptr = wptr << 32;
 283		wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 284		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 285	}
 286
 287	return wptr >> 2;
 288}
 289
 290/**
 291 * sdma_v5_2_ring_set_wptr - commit the write pointer
 292 *
 293 * @ring: amdgpu ring pointer
 294 *
 295 * Write the wptr back to the hardware (NAVI10+).
 296 */
 297static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 298{
 299	struct amdgpu_device *adev = ring->adev;
 300
 301	DRM_DEBUG("Setting write pointer\n");
 302	if (ring->use_doorbell) {
 303		DRM_DEBUG("Using doorbell -- "
 304				"wptr_offs == 0x%08x "
 305				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
 306				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 307				ring->wptr_offs,
 308				lower_32_bits(ring->wptr << 2),
 309				upper_32_bits(ring->wptr << 2));
 310		/* XXX check if swapping is necessary on BE */
 311		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 312		adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 313		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 314				ring->doorbell_index, ring->wptr << 2);
 315		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 316	} else {
 317		DRM_DEBUG("Not using doorbell -- "
 318				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 319				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 320				ring->me,
 321				lower_32_bits(ring->wptr << 2),
 322				ring->me,
 323				upper_32_bits(ring->wptr << 2));
 324		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 325			lower_32_bits(ring->wptr << 2));
 326		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 327			upper_32_bits(ring->wptr << 2));
 328	}
 329}
 330
 331static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 332{
 333	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 334	int i;
 335
 336	for (i = 0; i < count; i++)
 337		if (sdma && sdma->burst_nop && (i == 0))
 338			amdgpu_ring_write(ring, ring->funcs->nop |
 339				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 340		else
 341			amdgpu_ring_write(ring, ring->funcs->nop);
 342}
 343
 344/**
 345 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 346 *
 347 * @ring: amdgpu ring pointer
 348 * @job: job to retrieve vmid from
 349 * @ib: IB object to schedule
 350 * @flags: unused
 351 *
 352 * Schedule an IB in the DMA ring.
 353 */
 354static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 355				   struct amdgpu_job *job,
 356				   struct amdgpu_ib *ib,
 357				   uint32_t flags)
 358{
 359	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 360	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 361
 362	/* An IB packet must end on a 8 DW boundary--the next dword
 363	 * must be on a 8-dword boundary. Our IB packet below is 6
 364	 * dwords long, thus add x number of NOPs, such that, in
 365	 * modular arithmetic,
 366	 * wptr + 6 + x = 8k, k >= 0, which in C is,
 367	 * (wptr + 6 + x) % 8 = 0.
 368	 * The expression below, is a solution of x.
 369	 */
 370	sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 371
 372	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 373			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 374	/* base must be 32 byte aligned */
 375	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 376	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 377	amdgpu_ring_write(ring, ib->length_dw);
 378	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 379	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 380}
 381
 382/**
 383 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
 384 *
 385 * @ring: amdgpu ring pointer
 386 * @job: job to retrieve vmid from
 387 * @ib: IB object to schedule
 388 *
 389 * flush the IB by graphics cache rinse.
 390 */
 391static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
 392{
 393    uint32_t gcr_cntl =
 394		    SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 395			SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 396			SDMA_GCR_GLI_INV(1);
 397
 398	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 399	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 400	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 401	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 402			SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 403	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 404			SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 405	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 406			SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 407}
 408
 409/**
 410 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 411 *
 412 * @ring: amdgpu ring pointer
 413 *
 414 * Emit an hdp flush packet on the requested DMA ring.
 415 */
 416static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 417{
 418	struct amdgpu_device *adev = ring->adev;
 419	u32 ref_and_mask = 0;
 420	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 421
 422	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 423
 424	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 425			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 426			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 427	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 428	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 429	amdgpu_ring_write(ring, ref_and_mask); /* reference */
 430	amdgpu_ring_write(ring, ref_and_mask); /* mask */
 431	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 432			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 433}
 434
 435/**
 436 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 437 *
 438 * @ring: amdgpu ring pointer
 439 * @addr: address
 440 * @seq: sequence number
 441 * @flags: fence related flags
 442 *
 443 * Add a DMA fence packet to the ring to write
 444 * the fence seq number and DMA trap packet to generate
 445 * an interrupt if needed.
 446 */
 447static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 448				      unsigned flags)
 449{
 450	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 451	/* write the fence */
 452	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 453			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 454	/* zero in first two bits */
 455	BUG_ON(addr & 0x3);
 456	amdgpu_ring_write(ring, lower_32_bits(addr));
 457	amdgpu_ring_write(ring, upper_32_bits(addr));
 458	amdgpu_ring_write(ring, lower_32_bits(seq));
 459
 460	/* optionally write high bits as well */
 461	if (write64bit) {
 462		addr += 4;
 463		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 464				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 465		/* zero in first two bits */
 466		BUG_ON(addr & 0x3);
 467		amdgpu_ring_write(ring, lower_32_bits(addr));
 468		amdgpu_ring_write(ring, upper_32_bits(addr));
 469		amdgpu_ring_write(ring, upper_32_bits(seq));
 470	}
 471
 472	if (flags & AMDGPU_FENCE_FLAG_INT) {
 
 
 473		/* generate an interrupt */
 474		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 475		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 476	}
 477}
 478
 479
 480/**
 481 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 482 *
 483 * @adev: amdgpu_device pointer
 484 *
 485 * Stop the gfx async dma ring buffers.
 486 */
 487static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 488{
 489	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 490	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 491	struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 492	struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 493	u32 rb_cntl, ib_cntl;
 494	int i;
 495
 496	if ((adev->mman.buffer_funcs_ring == sdma0) ||
 497	    (adev->mman.buffer_funcs_ring == sdma1) ||
 498	    (adev->mman.buffer_funcs_ring == sdma2) ||
 499	    (adev->mman.buffer_funcs_ring == sdma3))
 500		amdgpu_ttm_set_buffer_funcs_status(adev, false);
 501
 502	for (i = 0; i < adev->sdma.num_instances; i++) {
 503		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 504		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 505		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 506		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 507		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 508		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 509	}
 510}
 511
 512/**
 513 * sdma_v5_2_rlc_stop - stop the compute async dma engines
 514 *
 515 * @adev: amdgpu_device pointer
 516 *
 517 * Stop the compute async dma queues.
 518 */
 519static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 520{
 521	/* XXX todo */
 522}
 523
 524/**
 525 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
 526 *
 527 * @adev: amdgpu_device pointer
 528 * @enable: enable/disable the DMA MEs context switch.
 529 *
 530 * Halt or unhalt the async dma engines context switch.
 531 */
 532static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 533{
 534	u32 f32_cntl, phase_quantum = 0;
 535	int i;
 536
 537	if (amdgpu_sdma_phase_quantum) {
 538		unsigned value = amdgpu_sdma_phase_quantum;
 539		unsigned unit = 0;
 540
 541		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 542				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 543			value = (value + 1) >> 1;
 544			unit++;
 545		}
 546		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 547			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 548			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 549				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 550			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 551				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 552			WARN_ONCE(1,
 553			"clamping sdma_phase_quantum to %uK clock cycles\n",
 554				  value << unit);
 555		}
 556		phase_quantum =
 557			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 558			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 559	}
 560
 561	for (i = 0; i < adev->sdma.num_instances; i++) {
 562		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 563		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 564				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 565		if (enable && amdgpu_sdma_phase_quantum) {
 566			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 567			       phase_quantum);
 568			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 569			       phase_quantum);
 570			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 571			       phase_quantum);
 572		}
 573		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 
 
 
 
 
 
 574	}
 575
 576}
 577
 578/**
 579 * sdma_v5_2_enable - stop the async dma engines
 580 *
 581 * @adev: amdgpu_device pointer
 582 * @enable: enable/disable the DMA MEs.
 583 *
 584 * Halt or unhalt the async dma engines.
 585 */
 586static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 587{
 588	u32 f32_cntl;
 589	int i;
 590
 591	if (!enable) {
 592		sdma_v5_2_gfx_stop(adev);
 593		sdma_v5_2_rlc_stop(adev);
 594	}
 595
 596	for (i = 0; i < adev->sdma.num_instances; i++) {
 597		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 598		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 599		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 
 
 600	}
 601}
 602
 603/**
 604 * sdma_v5_2_gfx_resume - setup and start the async dma engines
 605 *
 606 * @adev: amdgpu_device pointer
 607 *
 608 * Set up the gfx DMA ring buffers and enable them.
 609 * Returns 0 for success, error for failure.
 610 */
 611static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 612{
 613	struct amdgpu_ring *ring;
 614	u32 rb_cntl, ib_cntl;
 615	u32 rb_bufsz;
 616	u32 wb_offset;
 617	u32 doorbell;
 618	u32 doorbell_offset;
 619	u32 temp;
 620	u32 wptr_poll_cntl;
 621	u64 wptr_gpu_addr;
 622	int i, r;
 623
 624	for (i = 0; i < adev->sdma.num_instances; i++) {
 625		ring = &adev->sdma.instance[i].ring;
 626		wb_offset = (ring->rptr_offs * 4);
 627
 628		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 
 629
 630		/* Set ring buffer size in dwords */
 631		rb_bufsz = order_base_2(ring->ring_size / 4);
 632		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 633		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 634#ifdef __BIG_ENDIAN
 635		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 636		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 637					RPTR_WRITEBACK_SWAP_ENABLE, 1);
 638#endif
 639		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 640
 641		/* Initialize the ring buffer's read and write pointers */
 642		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 643		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 644		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 645		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 646
 647		/* setup the wptr shadow polling */
 648		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 649		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 650		       lower_32_bits(wptr_gpu_addr));
 651		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 652		       upper_32_bits(wptr_gpu_addr));
 653		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
 654							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 655		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 656					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 657					       F32_POLL_ENABLE, 1);
 658		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 659		       wptr_poll_cntl);
 660
 661		/* set the wb address whether it's enabled or not */
 662		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 663		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 664		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 665		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 666
 667		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 668
 669		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 670		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 671
 672		ring->wptr = 0;
 673
 674		/* before programing wptr to a less value, need set minor_ptr_update first */
 675		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 676
 677		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 678			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 679			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 680		}
 681
 682		doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 683		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 684
 685		if (ring->use_doorbell) {
 686			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 687			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 688					OFFSET, ring->doorbell_index);
 689		} else {
 690			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 691		}
 692		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 693		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 694
 695		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 696						      ring->doorbell_index,
 697						      adev->doorbell_index.sdma_doorbell_range);
 698
 699		if (amdgpu_sriov_vf(adev))
 700			sdma_v5_2_ring_set_wptr(ring);
 701
 702		/* set minor_ptr_update to 0 after wptr programed */
 703		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 704
 705		/* set utc l1 enable flag always to 1 */
 706		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 707		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 708
 709		/* enable MCBP */
 710		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 711		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 712
 713		/* Set up RESP_MODE to non-copy addresses */
 714		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 715		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 716		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 717		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 718
 719		/* program default cache read and write policy */
 720		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 721		/* clean read policy and write policy bits */
 722		temp &= 0xFF0FFF;
 723		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 724			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 725			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 726		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 727
 
 728		if (!amdgpu_sriov_vf(adev)) {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 729			/* unhalt engine */
 730			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 731			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 732			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 733		}
 734
 735		/* enable DMA RB */
 736		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 737		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 738
 739		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 740		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 741#ifdef __BIG_ENDIAN
 742		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 743#endif
 744		/* enable DMA IBs */
 745		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 746
 747		ring->sched.ready = true;
 748
 749		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 750			sdma_v5_2_ctx_switch_enable(adev, true);
 751			sdma_v5_2_enable(adev, true);
 752		}
 753
 754		r = amdgpu_ring_test_ring(ring);
 755		if (r) {
 756			ring->sched.ready = false;
 757			return r;
 758		}
 759
 760		if (adev->mman.buffer_funcs_ring == ring)
 761			amdgpu_ttm_set_buffer_funcs_status(adev, true);
 762	}
 763
 764	return 0;
 765}
 766
 767/**
 768 * sdma_v5_2_rlc_resume - setup and start the async dma engines
 769 *
 770 * @adev: amdgpu_device pointer
 771 *
 772 * Set up the compute DMA queues and enable them.
 773 * Returns 0 for success, error for failure.
 774 */
 775static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 776{
 777	return 0;
 778}
 779
 780/**
 781 * sdma_v5_2_load_microcode - load the sDMA ME ucode
 782 *
 783 * @adev: amdgpu_device pointer
 784 *
 785 * Loads the sDMA0/1/2/3 ucode.
 786 * Returns 0 for success, -EINVAL if the ucode is not available.
 787 */
 788static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 789{
 790	const struct sdma_firmware_header_v1_0 *hdr;
 791	const __le32 *fw_data;
 792	u32 fw_size;
 793	int i, j;
 794
 795	/* halt the MEs */
 796	sdma_v5_2_enable(adev, false);
 797
 798	for (i = 0; i < adev->sdma.num_instances; i++) {
 799		if (!adev->sdma.instance[i].fw)
 800			return -EINVAL;
 801
 802		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 803		amdgpu_ucode_print_sdma_hdr(&hdr->header);
 804		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 805
 806		fw_data = (const __le32 *)
 807			(adev->sdma.instance[i].fw->data +
 808				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 809
 810		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 811
 812		for (j = 0; j < fw_size; j++) {
 813			if (amdgpu_emu_mode == 1 && j % 500 == 0)
 814				msleep(1);
 815			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 816		}
 817
 818		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 819	}
 820
 821	return 0;
 822}
 823
 824static int sdma_v5_2_soft_reset(void *handle)
 825{
 826	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 827	u32 grbm_soft_reset;
 828	u32 tmp;
 829	int i;
 830
 831	for (i = 0; i < adev->sdma.num_instances; i++) {
 832		grbm_soft_reset = REG_SET_FIELD(0,
 833						GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 834						1);
 835		grbm_soft_reset <<= i;
 836
 837		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 838		tmp |= grbm_soft_reset;
 839		DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 840		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 841		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 842
 843		udelay(50);
 844
 845		tmp &= ~grbm_soft_reset;
 846		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 847		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 848
 849		udelay(50);
 850	}
 851
 852	return 0;
 853}
 854
 855/**
 856 * sdma_v5_2_start - setup and start the async dma engines
 857 *
 858 * @adev: amdgpu_device pointer
 859 *
 860 * Set up the DMA engines and enable them.
 861 * Returns 0 for success, error for failure.
 862 */
 863static int sdma_v5_2_start(struct amdgpu_device *adev)
 864{
 865	int r = 0;
 866
 867	if (amdgpu_sriov_vf(adev)) {
 868		sdma_v5_2_ctx_switch_enable(adev, false);
 869		sdma_v5_2_enable(adev, false);
 870
 871		/* set RB registers */
 872		r = sdma_v5_2_gfx_resume(adev);
 873		return r;
 874	}
 875
 876	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 877		r = sdma_v5_2_load_microcode(adev);
 878		if (r)
 879			return r;
 880
 881		/* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 882		if (amdgpu_emu_mode == 1)
 883			msleep(1000);
 884	}
 885
 886	/* TODO: check whether can submit a doorbell request to raise
 887	 * a doorbell fence to exit gfxoff.
 888	 */
 889	if (adev->in_s0ix)
 890		amdgpu_gfx_off_ctrl(adev, false);
 891
 892	sdma_v5_2_soft_reset(adev);
 893	/* unhalt the MEs */
 894	sdma_v5_2_enable(adev, true);
 895	/* enable sdma ring preemption */
 896	sdma_v5_2_ctx_switch_enable(adev, true);
 897
 898	/* start the gfx rings and rlc compute queues */
 899	r = sdma_v5_2_gfx_resume(adev);
 900	if (adev->in_s0ix)
 901		amdgpu_gfx_off_ctrl(adev, true);
 902	if (r)
 903		return r;
 904	r = sdma_v5_2_rlc_resume(adev);
 905
 906	return r;
 907}
 908
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 909/**
 910 * sdma_v5_2_ring_test_ring - simple async dma engine test
 911 *
 912 * @ring: amdgpu_ring structure holding ring information
 913 *
 914 * Test the DMA engine by writing using it to write an
 915 * value to memory.
 916 * Returns 0 for success, error for failure.
 917 */
 918static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 919{
 920	struct amdgpu_device *adev = ring->adev;
 921	unsigned i;
 922	unsigned index;
 923	int r;
 924	u32 tmp;
 925	u64 gpu_addr;
 
 926
 927	r = amdgpu_device_wb_get(adev, &index);
 928	if (r) {
 929		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 930		return r;
 931	}
 932
 933	gpu_addr = adev->wb.gpu_addr + (index * 4);
 934	tmp = 0xCAFEDEAD;
 935	adev->wb.wb[index] = cpu_to_le32(tmp);
 936
 937	r = amdgpu_ring_alloc(ring, 5);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 938	if (r) {
 939		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 940		amdgpu_device_wb_free(adev, index);
 941		return r;
 942	}
 943
 944	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 945			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 946	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 947	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 948	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 949	amdgpu_ring_write(ring, 0xDEADBEEF);
 950	amdgpu_ring_commit(ring);
 951
 952	for (i = 0; i < adev->usec_timeout; i++) {
 953		tmp = le32_to_cpu(adev->wb.wb[index]);
 
 
 
 954		if (tmp == 0xDEADBEEF)
 955			break;
 956		if (amdgpu_emu_mode == 1)
 957			msleep(1);
 958		else
 959			udelay(1);
 960	}
 961
 962	if (i >= adev->usec_timeout)
 963		r = -ETIMEDOUT;
 964
 965	amdgpu_device_wb_free(adev, index);
 
 966
 967	return r;
 968}
 969
 970/**
 971 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 972 *
 973 * @ring: amdgpu_ring structure holding ring information
 974 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 975 *
 976 * Test a simple IB in the DMA ring.
 977 * Returns 0 on success, error on failure.
 978 */
 979static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 980{
 981	struct amdgpu_device *adev = ring->adev;
 982	struct amdgpu_ib ib;
 983	struct dma_fence *f = NULL;
 984	unsigned index;
 985	long r;
 986	u32 tmp = 0;
 987	u64 gpu_addr;
 
 988
 989	r = amdgpu_device_wb_get(adev, &index);
 990	if (r) {
 991		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 992		return r;
 993	}
 994
 995	gpu_addr = adev->wb.gpu_addr + (index * 4);
 996	tmp = 0xCAFEDEAD;
 997	adev->wb.wb[index] = cpu_to_le32(tmp);
 998	memset(&ib, 0, sizeof(ib));
 999	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1000	if (r) {
1001		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1002		goto err0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1003	}
1004
1005	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1006		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1007	ib.ptr[1] = lower_32_bits(gpu_addr);
1008	ib.ptr[2] = upper_32_bits(gpu_addr);
1009	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1010	ib.ptr[4] = 0xDEADBEEF;
1011	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1012	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1013	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1014	ib.length_dw = 8;
1015
1016	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1017	if (r)
1018		goto err1;
1019
1020	r = dma_fence_wait_timeout(f, false, timeout);
1021	if (r == 0) {
1022		DRM_ERROR("amdgpu: IB test timed out\n");
1023		r = -ETIMEDOUT;
1024		goto err1;
1025	} else if (r < 0) {
1026		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1027		goto err1;
1028	}
1029	tmp = le32_to_cpu(adev->wb.wb[index]);
 
 
 
 
 
1030	if (tmp == 0xDEADBEEF)
1031		r = 0;
1032	else
1033		r = -EINVAL;
1034
1035err1:
1036	amdgpu_ib_free(adev, &ib, NULL);
1037	dma_fence_put(f);
1038err0:
1039	amdgpu_device_wb_free(adev, index);
 
1040	return r;
1041}
1042
1043
1044/**
1045 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1046 *
1047 * @ib: indirect buffer to fill with commands
1048 * @pe: addr of the page entry
1049 * @src: src addr to copy from
1050 * @count: number of page entries to update
1051 *
1052 * Update PTEs by copying them from the GART using sDMA.
1053 */
1054static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1055				  uint64_t pe, uint64_t src,
1056				  unsigned count)
1057{
1058	unsigned bytes = count * 8;
1059
1060	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1061		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1062	ib->ptr[ib->length_dw++] = bytes - 1;
1063	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1064	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1065	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1066	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1067	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1068
1069}
1070
1071/**
1072 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1073 *
1074 * @ib: indirect buffer to fill with commands
1075 * @pe: addr of the page entry
1076 * @value: dst addr to write into pe
1077 * @count: number of page entries to update
1078 * @incr: increase next addr by incr bytes
1079 *
1080 * Update PTEs by writing them manually using sDMA.
1081 */
1082static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1083				   uint64_t value, unsigned count,
1084				   uint32_t incr)
1085{
1086	unsigned ndw = count * 2;
1087
1088	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1089		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1090	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1091	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1092	ib->ptr[ib->length_dw++] = ndw - 1;
1093	for (; ndw > 0; ndw -= 2) {
1094		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1095		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1096		value += incr;
1097	}
1098}
1099
1100/**
1101 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1102 *
1103 * @ib: indirect buffer to fill with commands
1104 * @pe: addr of the page entry
1105 * @addr: dst addr to write into pe
1106 * @count: number of page entries to update
1107 * @incr: increase next addr by incr bytes
1108 * @flags: access flags
1109 *
1110 * Update the page tables using sDMA.
1111 */
1112static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1113				     uint64_t pe,
1114				     uint64_t addr, unsigned count,
1115				     uint32_t incr, uint64_t flags)
1116{
1117	/* for physically contiguous pages (vram) */
1118	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1119	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1120	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1121	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1122	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1123	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1124	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1125	ib->ptr[ib->length_dw++] = incr; /* increment size */
1126	ib->ptr[ib->length_dw++] = 0;
1127	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1128}
1129
1130/**
1131 * sdma_v5_2_ring_pad_ib - pad the IB
1132 *
1133 * @ib: indirect buffer to fill with padding
1134 * @ring: amdgpu_ring structure holding ring information
1135 *
1136 * Pad the IB with NOPs to a boundary multiple of 8.
1137 */
1138static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1139{
1140	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1141	u32 pad_count;
1142	int i;
1143
1144	pad_count = (-ib->length_dw) & 0x7;
1145	for (i = 0; i < pad_count; i++)
1146		if (sdma && sdma->burst_nop && (i == 0))
1147			ib->ptr[ib->length_dw++] =
1148				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1149				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1150		else
1151			ib->ptr[ib->length_dw++] =
1152				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1153}
1154
1155
1156/**
1157 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1158 *
1159 * @ring: amdgpu_ring pointer
1160 *
1161 * Make sure all previous operations are completed (CIK).
1162 */
1163static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1164{
1165	uint32_t seq = ring->fence_drv.sync_seq;
1166	uint64_t addr = ring->fence_drv.gpu_addr;
1167
1168	/* wait for idle */
1169	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1170			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1171			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1172			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1173	amdgpu_ring_write(ring, addr & 0xfffffffc);
1174	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1175	amdgpu_ring_write(ring, seq); /* reference */
1176	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1177	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1178			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1179}
1180
1181
1182/**
1183 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1184 *
1185 * @ring: amdgpu_ring pointer
1186 * @vmid: vmid number to use
1187 * @pd_addr: address
1188 *
1189 * Update the page table base and flush the VM TLB
1190 * using sDMA.
1191 */
1192static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1193					 unsigned vmid, uint64_t pd_addr)
1194{
1195	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1196}
1197
1198static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1199				     uint32_t reg, uint32_t val)
1200{
1201	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1202			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1203	amdgpu_ring_write(ring, reg);
1204	amdgpu_ring_write(ring, val);
1205}
1206
1207static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1208					 uint32_t val, uint32_t mask)
1209{
1210	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1211			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1212			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1213	amdgpu_ring_write(ring, reg << 2);
1214	amdgpu_ring_write(ring, 0);
1215	amdgpu_ring_write(ring, val); /* reference */
1216	amdgpu_ring_write(ring, mask); /* mask */
1217	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1218			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1219}
1220
1221static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1222						   uint32_t reg0, uint32_t reg1,
1223						   uint32_t ref, uint32_t mask)
1224{
1225	amdgpu_ring_emit_wreg(ring, reg0, ref);
1226	/* wait for a cycle to reset vm_inv_eng*_ack */
1227	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1228	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1229}
1230
1231static int sdma_v5_2_early_init(void *handle)
1232{
1233	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
1234
1235	switch (adev->asic_type) {
1236	case CHIP_SIENNA_CICHLID:
1237		adev->sdma.num_instances = 4;
1238		break;
1239	case CHIP_NAVY_FLOUNDER:
1240	case CHIP_DIMGREY_CAVEFISH:
1241		adev->sdma.num_instances = 2;
1242		break;
1243	case CHIP_VANGOGH:
1244	case CHIP_BEIGE_GOBY:
1245	case CHIP_YELLOW_CARP:
1246		adev->sdma.num_instances = 1;
1247		break;
1248	default:
1249		break;
1250	}
1251
1252	sdma_v5_2_set_ring_funcs(adev);
1253	sdma_v5_2_set_buffer_funcs(adev);
1254	sdma_v5_2_set_vm_pte_funcs(adev);
1255	sdma_v5_2_set_irq_funcs(adev);
 
1256
1257	return 0;
1258}
1259
1260static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1261{
1262	switch (seq_num) {
1263	case 0:
1264		return SOC15_IH_CLIENTID_SDMA0;
1265	case 1:
1266		return SOC15_IH_CLIENTID_SDMA1;
1267	case 2:
1268		return SOC15_IH_CLIENTID_SDMA2;
1269	case 3:
1270		return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1271	default:
1272		break;
1273	}
1274	return -EINVAL;
1275}
1276
1277static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1278{
1279	switch (seq_num) {
1280	case 0:
1281		return SDMA0_5_0__SRCID__SDMA_TRAP;
1282	case 1:
1283		return SDMA1_5_0__SRCID__SDMA_TRAP;
1284	case 2:
1285		return SDMA2_5_0__SRCID__SDMA_TRAP;
1286	case 3:
1287		return SDMA3_5_0__SRCID__SDMA_TRAP;
1288	default:
1289		break;
1290	}
1291	return -EINVAL;
1292}
1293
1294static int sdma_v5_2_sw_init(void *handle)
1295{
1296	struct amdgpu_ring *ring;
1297	int r, i;
1298	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299
1300	/* SDMA trap event */
1301	for (i = 0; i < adev->sdma.num_instances; i++) {
1302		r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1303				      sdma_v5_2_seq_to_trap_id(i),
1304				      &adev->sdma.trap_irq);
1305		if (r)
1306			return r;
1307	}
1308
1309	r = sdma_v5_2_init_microcode(adev);
1310	if (r) {
1311		DRM_ERROR("Failed to load sdma firmware!\n");
1312		return r;
1313	}
1314
1315	for (i = 0; i < adev->sdma.num_instances; i++) {
1316		ring = &adev->sdma.instance[i].ring;
1317		ring->ring_obj = NULL;
1318		ring->use_doorbell = true;
1319		ring->me = i;
1320
1321		DRM_INFO("use_doorbell being set to: [%s]\n",
1322				ring->use_doorbell?"true":"false");
1323
1324		ring->doorbell_index =
1325			(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1326
 
1327		sprintf(ring->name, "sdma%d", i);
1328		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1329				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1330				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1331		if (r)
1332			return r;
1333	}
1334
1335	return r;
1336}
1337
1338static int sdma_v5_2_sw_fini(void *handle)
1339{
1340	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341	int i;
1342
1343	for (i = 0; i < adev->sdma.num_instances; i++)
1344		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1345
1346	sdma_v5_2_destroy_inst_ctx(adev);
1347
1348	return 0;
1349}
1350
1351static int sdma_v5_2_hw_init(void *handle)
1352{
1353	int r;
1354	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355
1356	sdma_v5_2_init_golden_registers(adev);
1357
1358	r = sdma_v5_2_start(adev);
1359
1360	return r;
1361}
1362
1363static int sdma_v5_2_hw_fini(void *handle)
1364{
1365	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366
1367	if (amdgpu_sriov_vf(adev))
1368		return 0;
1369
1370	sdma_v5_2_ctx_switch_enable(adev, false);
1371	sdma_v5_2_enable(adev, false);
1372
1373	return 0;
1374}
1375
1376static int sdma_v5_2_suspend(void *handle)
1377{
1378	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379
1380	return sdma_v5_2_hw_fini(adev);
1381}
1382
1383static int sdma_v5_2_resume(void *handle)
1384{
1385	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1386
1387	return sdma_v5_2_hw_init(adev);
1388}
1389
1390static bool sdma_v5_2_is_idle(void *handle)
1391{
1392	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1393	u32 i;
1394
1395	for (i = 0; i < adev->sdma.num_instances; i++) {
1396		u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1397
1398		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1399			return false;
1400	}
1401
1402	return true;
1403}
1404
1405static int sdma_v5_2_wait_for_idle(void *handle)
1406{
1407	unsigned i;
1408	u32 sdma0, sdma1, sdma2, sdma3;
1409	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410
1411	for (i = 0; i < adev->usec_timeout; i++) {
1412		sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1413		sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1414		sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1415		sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1416
1417		if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1418			return 0;
1419		udelay(1);
1420	}
1421	return -ETIMEDOUT;
1422}
1423
1424static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1425{
1426	int i, r = 0;
1427	struct amdgpu_device *adev = ring->adev;
1428	u32 index = 0;
1429	u64 sdma_gfx_preempt;
1430
1431	amdgpu_sdma_get_index_from_ring(ring, &index);
1432	sdma_gfx_preempt =
1433		sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1434
1435	/* assert preemption condition */
1436	amdgpu_ring_set_preempt_cond_exec(ring, false);
1437
1438	/* emit the trailing fence */
1439	ring->trail_seq += 1;
1440	amdgpu_ring_alloc(ring, 10);
1441	sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1442				  ring->trail_seq, 0);
1443	amdgpu_ring_commit(ring);
1444
1445	/* assert IB preemption */
1446	WREG32(sdma_gfx_preempt, 1);
1447
1448	/* poll the trailing fence */
1449	for (i = 0; i < adev->usec_timeout; i++) {
1450		if (ring->trail_seq ==
1451		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1452			break;
1453		udelay(1);
1454	}
1455
1456	if (i >= adev->usec_timeout) {
1457		r = -EINVAL;
1458		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1459	}
1460
1461	/* deassert IB preemption */
1462	WREG32(sdma_gfx_preempt, 0);
1463
1464	/* deassert the preemption condition */
1465	amdgpu_ring_set_preempt_cond_exec(ring, true);
1466	return r;
1467}
1468
1469static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1470					struct amdgpu_irq_src *source,
1471					unsigned type,
1472					enum amdgpu_interrupt_state state)
1473{
1474	u32 sdma_cntl;
1475
1476	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1477
1478	sdma_cntl = RREG32(reg_offset);
1479	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1480		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1481	WREG32(reg_offset, sdma_cntl);
 
 
1482
1483	return 0;
1484}
1485
1486static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1487				      struct amdgpu_irq_src *source,
1488				      struct amdgpu_iv_entry *entry)
1489{
 
 
1490	DRM_DEBUG("IH: SDMA trap\n");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1491	switch (entry->client_id) {
1492	case SOC15_IH_CLIENTID_SDMA0:
1493		switch (entry->ring_id) {
1494		case 0:
1495			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1496			break;
1497		case 1:
1498			/* XXX compute */
1499			break;
1500		case 2:
1501			/* XXX compute */
1502			break;
1503		case 3:
1504			/* XXX page queue*/
1505			break;
1506		}
1507		break;
1508	case SOC15_IH_CLIENTID_SDMA1:
1509		switch (entry->ring_id) {
1510		case 0:
1511			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1512			break;
1513		case 1:
1514			/* XXX compute */
1515			break;
1516		case 2:
1517			/* XXX compute */
1518			break;
1519		case 3:
1520			/* XXX page queue*/
1521			break;
1522		}
1523		break;
1524	case SOC15_IH_CLIENTID_SDMA2:
1525		switch (entry->ring_id) {
1526		case 0:
1527			amdgpu_fence_process(&adev->sdma.instance[2].ring);
1528			break;
1529		case 1:
1530			/* XXX compute */
1531			break;
1532		case 2:
1533			/* XXX compute */
1534			break;
1535		case 3:
1536			/* XXX page queue*/
1537			break;
1538		}
1539		break;
1540	case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1541		switch (entry->ring_id) {
1542		case 0:
1543			amdgpu_fence_process(&adev->sdma.instance[3].ring);
1544			break;
1545		case 1:
1546			/* XXX compute */
1547			break;
1548		case 2:
1549			/* XXX compute */
1550			break;
1551		case 3:
1552			/* XXX page queue*/
1553			break;
1554		}
1555		break;
1556	}
1557	return 0;
1558}
1559
1560static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1561					      struct amdgpu_irq_src *source,
1562					      struct amdgpu_iv_entry *entry)
1563{
1564	return 0;
1565}
1566
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1567static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1568						       bool enable)
1569{
1570	uint32_t data, def;
1571	int i;
1572
1573	for (i = 0; i < adev->sdma.num_instances; i++) {
1574
1575		if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
1576			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1577
1578		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1579			/* Enable sdma clock gating */
1580			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1581			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1582				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1583				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1584				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1585				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1586				  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1587			if (def != data)
1588				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1589		} else {
1590			/* Disable sdma clock gating */
1591			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1592			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1593				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1594				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1595				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1596				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1597				 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1598			if (def != data)
1599				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1600		}
1601	}
1602}
1603
1604static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1605						      bool enable)
1606{
1607	uint32_t data, def;
1608	int i;
1609
1610	for (i = 0; i < adev->sdma.num_instances; i++) {
1611
1612		if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
 
1613			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1614
1615		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1616			/* Enable sdma mem light sleep */
1617			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1618			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1619			if (def != data)
1620				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1621
1622		} else {
1623			/* Disable sdma mem light sleep */
1624			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1625			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1626			if (def != data)
1627				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1628
1629		}
1630	}
1631}
1632
1633static int sdma_v5_2_set_clockgating_state(void *handle,
1634					   enum amd_clockgating_state state)
1635{
1636	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1637
1638	if (amdgpu_sriov_vf(adev))
1639		return 0;
1640
1641	switch (adev->asic_type) {
1642	case CHIP_SIENNA_CICHLID:
1643	case CHIP_NAVY_FLOUNDER:
1644	case CHIP_VANGOGH:
1645	case CHIP_DIMGREY_CAVEFISH:
1646	case CHIP_BEIGE_GOBY:
1647	case CHIP_YELLOW_CARP:
 
 
1648		sdma_v5_2_update_medium_grain_clock_gating(adev,
1649				state == AMD_CG_STATE_GATE);
1650		sdma_v5_2_update_medium_grain_light_sleep(adev,
1651				state == AMD_CG_STATE_GATE);
1652		break;
1653	default:
1654		break;
1655	}
1656
1657	return 0;
1658}
1659
1660static int sdma_v5_2_set_powergating_state(void *handle,
1661					  enum amd_powergating_state state)
1662{
1663	return 0;
1664}
1665
1666static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1667{
1668	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1669	int data;
1670
1671	if (amdgpu_sriov_vf(adev))
1672		*flags = 0;
1673
 
 
 
 
 
1674	/* AMD_CG_SUPPORT_SDMA_LS */
1675	data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1676	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1677		*flags |= AMD_CG_SUPPORT_SDMA_LS;
1678}
1679
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1680const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1681	.name = "sdma_v5_2",
1682	.early_init = sdma_v5_2_early_init,
1683	.late_init = NULL,
1684	.sw_init = sdma_v5_2_sw_init,
1685	.sw_fini = sdma_v5_2_sw_fini,
1686	.hw_init = sdma_v5_2_hw_init,
1687	.hw_fini = sdma_v5_2_hw_fini,
1688	.suspend = sdma_v5_2_suspend,
1689	.resume = sdma_v5_2_resume,
1690	.is_idle = sdma_v5_2_is_idle,
1691	.wait_for_idle = sdma_v5_2_wait_for_idle,
1692	.soft_reset = sdma_v5_2_soft_reset,
1693	.set_clockgating_state = sdma_v5_2_set_clockgating_state,
1694	.set_powergating_state = sdma_v5_2_set_powergating_state,
1695	.get_clockgating_state = sdma_v5_2_get_clockgating_state,
1696};
1697
1698static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1699	.type = AMDGPU_RING_TYPE_SDMA,
1700	.align_mask = 0xf,
1701	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1702	.support_64bit_ptrs = true,
1703	.vmhub = AMDGPU_GFXHUB_0,
1704	.get_rptr = sdma_v5_2_ring_get_rptr,
1705	.get_wptr = sdma_v5_2_ring_get_wptr,
1706	.set_wptr = sdma_v5_2_ring_set_wptr,
1707	.emit_frame_size =
1708		5 + /* sdma_v5_2_ring_init_cond_exec */
1709		6 + /* sdma_v5_2_ring_emit_hdp_flush */
1710		3 + /* hdp_invalidate */
1711		6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1712		/* sdma_v5_2_ring_emit_vm_flush */
1713		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1714		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1715		10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1716	.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1717	.emit_ib = sdma_v5_2_ring_emit_ib,
1718	.emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1719	.emit_fence = sdma_v5_2_ring_emit_fence,
1720	.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1721	.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1722	.emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1723	.test_ring = sdma_v5_2_ring_test_ring,
1724	.test_ib = sdma_v5_2_ring_test_ib,
1725	.insert_nop = sdma_v5_2_ring_insert_nop,
1726	.pad_ib = sdma_v5_2_ring_pad_ib,
 
 
1727	.emit_wreg = sdma_v5_2_ring_emit_wreg,
1728	.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1729	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1730	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1731	.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1732	.preempt_ib = sdma_v5_2_ring_preempt_ib,
1733};
1734
1735static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1736{
1737	int i;
1738
1739	for (i = 0; i < adev->sdma.num_instances; i++) {
1740		adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1741		adev->sdma.instance[i].ring.me = i;
1742	}
1743}
1744
1745static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1746	.set = sdma_v5_2_set_trap_irq_state,
1747	.process = sdma_v5_2_process_trap_irq,
1748};
1749
1750static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1751	.process = sdma_v5_2_process_illegal_inst_irq,
1752};
1753
1754static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1755{
1756	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1757					adev->sdma.num_instances;
1758	adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1759	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1760}
1761
1762/**
1763 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1764 *
1765 * @ib: indirect buffer to copy to
1766 * @src_offset: src GPU address
1767 * @dst_offset: dst GPU address
1768 * @byte_count: number of bytes to xfer
1769 * @tmz: if a secure copy should be used
1770 *
1771 * Copy GPU buffers using the DMA engine.
1772 * Used by the amdgpu ttm implementation to move pages if
1773 * registered as the asic copy callback.
1774 */
1775static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1776				       uint64_t src_offset,
1777				       uint64_t dst_offset,
1778				       uint32_t byte_count,
1779				       bool tmz)
1780{
1781	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1782		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1783		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1784	ib->ptr[ib->length_dw++] = byte_count - 1;
1785	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1786	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1787	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1788	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1789	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1790}
1791
1792/**
1793 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1794 *
1795 * @ib: indirect buffer to fill
1796 * @src_data: value to write to buffer
1797 * @dst_offset: dst GPU address
1798 * @byte_count: number of bytes to xfer
1799 *
1800 * Fill GPU buffers using the DMA engine.
1801 */
1802static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1803				       uint32_t src_data,
1804				       uint64_t dst_offset,
1805				       uint32_t byte_count)
1806{
1807	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1808	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1809	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1810	ib->ptr[ib->length_dw++] = src_data;
1811	ib->ptr[ib->length_dw++] = byte_count - 1;
1812}
1813
1814static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1815	.copy_max_bytes = 0x400000,
1816	.copy_num_dw = 7,
1817	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1818
1819	.fill_max_bytes = 0x400000,
1820	.fill_num_dw = 5,
1821	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1822};
1823
1824static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1825{
1826	if (adev->mman.buffer_funcs == NULL) {
1827		adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1828		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1829	}
1830}
1831
1832static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1833	.copy_pte_num_dw = 7,
1834	.copy_pte = sdma_v5_2_vm_copy_pte,
1835	.write_pte = sdma_v5_2_vm_write_pte,
1836	.set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1837};
1838
1839static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1840{
1841	unsigned i;
1842
1843	if (adev->vm_manager.vm_pte_funcs == NULL) {
1844		adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1845		for (i = 0; i < adev->sdma.num_instances; i++) {
1846			adev->vm_manager.vm_pte_scheds[i] =
1847				&adev->sdma.instance[i].ring.sched;
1848		}
1849		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1850	}
1851}
1852
1853const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1854	.type = AMD_IP_BLOCK_TYPE_SDMA,
1855	.major = 5,
1856	.minor = 2,
1857	.rev = 0,
1858	.funcs = &sdma_v5_2_ip_funcs,
1859};