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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2021 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10#ifndef MPI3MR_H_INCLUDED
11#define MPI3MR_H_INCLUDED
12
13#include <linux/blkdev.h>
14#include <linux/blk-mq.h>
15#include <linux/blk-mq-pci.h>
16#include <linux/delay.h>
17#include <linux/dmapool.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/miscdevice.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/poll.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/types.h>
30#include <linux/uaccess.h>
31#include <linux/utsname.h>
32#include <linux/version.h>
33#include <linux/workqueue.h>
34#include <asm/unaligned.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37#include <scsi/scsi_dbg.h>
38#include <scsi/scsi_device.h>
39#include <scsi/scsi_host.h>
40#include <scsi/scsi_tcq.h>
41
42#include "mpi/mpi30_transport.h"
43#include "mpi/mpi30_cnfg.h"
44#include "mpi/mpi30_image.h"
45#include "mpi/mpi30_init.h"
46#include "mpi/mpi30_ioc.h"
47#include "mpi/mpi30_sas.h"
48#include "mpi3mr_debug.h"
49
50/* Global list and lock for storing multiple adapters managed by the driver */
51extern spinlock_t mrioc_list_lock;
52extern struct list_head mrioc_list;
53extern int prot_mask;
54
55#define MPI3MR_DRIVER_VERSION "00.255.45.01"
56#define MPI3MR_DRIVER_RELDATE "12-December-2020"
57
58#define MPI3MR_DRIVER_NAME "mpi3mr"
59#define MPI3MR_DRIVER_LICENSE "GPL"
60#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
61#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
62
63#define MPI3MR_NAME_LENGTH 32
64#define IOCNAME "%s: "
65
66/* Definitions for internal SGL and Chain SGL buffers */
67#define MPI3MR_PAGE_SIZE_4K 4096
68#define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
69
70/* Definitions for MAX values for shost */
71#define MPI3MR_MAX_CMDS_LUN 7
72#define MPI3MR_MAX_CDB_LENGTH 32
73
74/* Admin queue management definitions */
75#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
76#define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)
77#define MPI3MR_ADMIN_REQ_FRAME_SZ 128
78#define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
79
80/* Operational queue management definitions */
81#define MPI3MR_OP_REQ_Q_QD 512
82#define MPI3MR_OP_REP_Q_QD 4096
83#define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
84#define MPI3MR_OP_REP_Q_SEG_SIZE 4096
85#define MPI3MR_MAX_SEG_LIST_SIZE 4096
86
87/* Reserved Host Tag definitions */
88#define MPI3MR_HOSTTAG_INVALID 0xFFFF
89#define MPI3MR_HOSTTAG_INITCMDS 1
90#define MPI3MR_HOSTTAG_IOCTLCMDS 2
91#define MPI3MR_HOSTTAG_BLK_TMS 5
92
93#define MPI3MR_NUM_DEVRMCMD 1
94#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1)
95#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
96 MPI3MR_NUM_DEVRMCMD - 1)
97
98#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
99
100/* Reduced resource count definition for crash kernel */
101#define MPI3MR_HOST_IOS_KDUMP 128
102
103/* command/controller interaction timeout definitions in seconds */
104#define MPI3MR_INTADMCMD_TIMEOUT 10
105#define MPI3MR_PORTENABLE_TIMEOUT 300
106#define MPI3MR_ABORTTM_TIMEOUT 30
107#define MPI3MR_RESETTM_TIMEOUT 30
108#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
109#define MPI3MR_TSUPDATE_INTERVAL 900
110#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
111#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
112
113#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
114
115/* Internal admin command state definitions*/
116#define MPI3MR_CMD_NOTUSED 0x8000
117#define MPI3MR_CMD_COMPLETE 0x0001
118#define MPI3MR_CMD_PENDING 0x0002
119#define MPI3MR_CMD_REPLY_VALID 0x0004
120#define MPI3MR_CMD_RESET 0x0008
121
122/* Definitions for Event replies and sense buffer allocated per controller */
123#define MPI3MR_NUM_EVT_REPLIES 64
124#define MPI3MR_SENSEBUF_SZ 256
125#define MPI3MR_SENSEBUF_FACTOR 3
126#define MPI3MR_CHAINBUF_FACTOR 3
127#define MPI3MR_CHAINBUFDIX_FACTOR 2
128
129/* Invalid target device handle */
130#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
131
132/* Controller Reset related definitions */
133#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
134#define MPI3MR_MAX_RESET_RETRY_COUNT 3
135
136/* ResponseCode definitions */
137#define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
138#define MPI3MR_RSP_TM_COMPLETE 0x00
139#define MPI3MR_RSP_INVALID_FRAME 0x02
140#define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04
141#define MPI3MR_RSP_TM_FAILED 0x05
142#define MPI3MR_RSP_TM_SUCCEEDED 0x08
143#define MPI3MR_RSP_TM_INVALID_LUN 0x09
144#define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A
145#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
146 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
147
148#define MPI3MR_DEFAULT_MDTS (128 * 1024)
149/* Command retry count definitions */
150#define MPI3MR_DEV_RMHS_RETRY_COUNT 3
151
152/* Default target device queue depth */
153#define MPI3MR_DEFAULT_SDEV_QD 32
154
155/* Definitions for Threaded IRQ poll*/
156#define MPI3MR_IRQ_POLL_SLEEP 2
157#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
158
159/* Definitions for the controller security status*/
160#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
161#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
162
163#define MPI3MR_INVALID_DEVICE 0x00
164#define MPI3MR_CONFIG_SECURE_DEVICE 0x04
165#define MPI3MR_HARD_SECURE_DEVICE 0x08
166#define MPI3MR_TAMPERED_DEVICE 0x0C
167
168/* SGE Flag definition */
169#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
170 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
171 MPI3_SGE_FLAGS_END_OF_LIST)
172
173/* MSI Index from Reply Queue Index */
174#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
175
176/* IOC State definitions */
177enum mpi3mr_iocstate {
178 MRIOC_STATE_READY = 1,
179 MRIOC_STATE_RESET,
180 MRIOC_STATE_FAULT,
181 MRIOC_STATE_BECOMING_READY,
182 MRIOC_STATE_RESET_REQUESTED,
183 MRIOC_STATE_UNRECOVERABLE,
184};
185
186/* Reset reason code definitions*/
187enum mpi3mr_reset_reason {
188 MPI3MR_RESET_FROM_BRINGUP = 1,
189 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
190 MPI3MR_RESET_FROM_IOCTL = 3,
191 MPI3MR_RESET_FROM_EH_HOS = 4,
192 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
193 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
194 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
195 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
196 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
197 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
198 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
199 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
200 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
201 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
202 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
203 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
204 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
205 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
206 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
207 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
208 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
209 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
210 MPI3MR_RESET_FROM_SYSFS = 23,
211 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24
212};
213
214/**
215 * struct mpi3mr_compimg_ver - replica of component image
216 * version defined in mpi30_image.h in host endianness
217 *
218 */
219struct mpi3mr_compimg_ver {
220 u16 build_num;
221 u16 cust_id;
222 u8 ph_minor;
223 u8 ph_major;
224 u8 gen_minor;
225 u8 gen_major;
226};
227
228/**
229 * struct mpi3mr_ioc_facs - replica of component image version
230 * defined in mpi30_ioc.h in host endianness
231 *
232 */
233struct mpi3mr_ioc_facts {
234 u32 ioc_capabilities;
235 struct mpi3mr_compimg_ver fw_ver;
236 u32 mpi_version;
237 u16 max_reqs;
238 u16 product_id;
239 u16 op_req_sz;
240 u16 reply_sz;
241 u16 exceptions;
242 u16 max_perids;
243 u16 max_pds;
244 u16 max_sasexpanders;
245 u16 max_sasinitiators;
246 u16 max_enclosures;
247 u16 max_pcie_switches;
248 u16 max_nvme;
249 u16 max_vds;
250 u16 max_hpds;
251 u16 max_advhpds;
252 u16 max_raidpds;
253 u16 min_devhandle;
254 u16 max_devhandle;
255 u16 max_op_req_q;
256 u16 max_op_reply_q;
257 u16 shutdown_timeout;
258 u8 ioc_num;
259 u8 who_init;
260 u16 max_msix_vectors;
261 u8 personality;
262 u8 dma_mask;
263 u8 protocol_flags;
264 u8 sge_mod_mask;
265 u8 sge_mod_value;
266 u8 sge_mod_shift;
267};
268
269/**
270 * struct segments - memory descriptor structure to store
271 * virtual and dma addresses for operational queue segments.
272 *
273 * @segment: virtual address
274 * @segment_dma: dma address
275 */
276struct segments {
277 void *segment;
278 dma_addr_t segment_dma;
279};
280
281/**
282 * struct op_req_qinfo - Operational Request Queue Information
283 *
284 * @ci: consumer index
285 * @pi: producer index
286 * @num_request: Maximum number of entries in the queue
287 * @qid: Queue Id starting from 1
288 * @reply_qid: Associated reply queue Id
289 * @num_segments: Number of discontiguous memory segments
290 * @segment_qd: Depth of each segments
291 * @q_lock: Concurrent queue access lock
292 * @q_segments: Segment descriptor pointer
293 * @q_segment_list: Segment list base virtual address
294 * @q_segment_list_dma: Segment list base DMA address
295 */
296struct op_req_qinfo {
297 u16 ci;
298 u16 pi;
299 u16 num_requests;
300 u16 qid;
301 u16 reply_qid;
302 u16 num_segments;
303 u16 segment_qd;
304 spinlock_t q_lock;
305 struct segments *q_segments;
306 void *q_segment_list;
307 dma_addr_t q_segment_list_dma;
308};
309
310/**
311 * struct op_reply_qinfo - Operational Reply Queue Information
312 *
313 * @ci: consumer index
314 * @qid: Queue Id starting from 1
315 * @num_replies: Maximum number of entries in the queue
316 * @num_segments: Number of discontiguous memory segments
317 * @segment_qd: Depth of each segments
318 * @q_segments: Segment descriptor pointer
319 * @q_segment_list: Segment list base virtual address
320 * @q_segment_list_dma: Segment list base DMA address
321 * @ephase: Expected phased identifier for the reply queue
322 * @pend_ios: Number of IOs pending in HW for this queue
323 * @enable_irq_poll: Flag to indicate polling is enabled
324 * @in_use: Queue is handled by poll/ISR
325 */
326struct op_reply_qinfo {
327 u16 ci;
328 u16 qid;
329 u16 num_replies;
330 u16 num_segments;
331 u16 segment_qd;
332 struct segments *q_segments;
333 void *q_segment_list;
334 dma_addr_t q_segment_list_dma;
335 u8 ephase;
336 atomic_t pend_ios;
337 bool enable_irq_poll;
338 atomic_t in_use;
339};
340
341/**
342 * struct mpi3mr_intr_info - Interrupt cookie information
343 *
344 * @mrioc: Adapter instance reference
345 * @msix_index: MSIx index
346 * @op_reply_q: Associated operational reply queue
347 * @name: Dev name for the irq claiming device
348 */
349struct mpi3mr_intr_info {
350 struct mpi3mr_ioc *mrioc;
351 u16 msix_index;
352 struct op_reply_qinfo *op_reply_q;
353 char name[MPI3MR_NAME_LENGTH];
354};
355
356/**
357 * struct tgt_dev_sas_sata - SAS/SATA device specific
358 * information cached from firmware given data
359 *
360 * @sas_address: World wide unique SAS address
361 * @dev_info: Device information bits
362 */
363struct tgt_dev_sas_sata {
364 u64 sas_address;
365 u16 dev_info;
366};
367
368/**
369 * struct tgt_dev_pcie - PCIe device specific information cached
370 * from firmware given data
371 *
372 * @mdts: Maximum data transfer size
373 * @capb: Device capabilities
374 * @pgsz: Device page size
375 * @abort_to: Timeout for abort TM
376 * @reset_to: Timeout for Target/LUN reset TM
377 */
378struct tgt_dev_pcie {
379 u32 mdts;
380 u16 capb;
381 u8 pgsz;
382 u8 abort_to;
383 u8 reset_to;
384};
385
386/**
387 * struct tgt_dev_volume - virtual device specific information
388 * cached from firmware given data
389 *
390 * @state: State of the VD
391 */
392struct tgt_dev_volume {
393 u8 state;
394};
395
396/**
397 * union _form_spec_inf - union of device specific information
398 */
399union _form_spec_inf {
400 struct tgt_dev_sas_sata sas_sata_inf;
401 struct tgt_dev_pcie pcie_inf;
402 struct tgt_dev_volume vol_inf;
403};
404
405
406
407/**
408 * struct mpi3mr_tgt_dev - target device data structure
409 *
410 * @list: List pointer
411 * @starget: Scsi_target pointer
412 * @dev_handle: FW device handle
413 * @parent_handle: FW parent device handle
414 * @slot: Slot number
415 * @encl_handle: FW enclosure handle
416 * @perst_id: FW assigned Persistent ID
417 * @dev_type: SAS/SATA/PCIE device type
418 * @is_hidden: Should be exposed to upper layers or not
419 * @host_exposed: Already exposed to host or not
420 * @q_depth: Device specific Queue Depth
421 * @wwid: World wide ID
422 * @dev_spec: Device type specific information
423 * @ref_count: Reference count
424 */
425struct mpi3mr_tgt_dev {
426 struct list_head list;
427 struct scsi_target *starget;
428 u16 dev_handle;
429 u16 parent_handle;
430 u16 slot;
431 u16 encl_handle;
432 u16 perst_id;
433 u8 dev_type;
434 u8 is_hidden;
435 u8 host_exposed;
436 u16 q_depth;
437 u64 wwid;
438 union _form_spec_inf dev_spec;
439 struct kref ref_count;
440};
441
442/**
443 * mpi3mr_tgtdev_get - k reference incrementor
444 * @s: Target device reference
445 *
446 * Increment target device reference count.
447 */
448static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
449{
450 kref_get(&s->ref_count);
451}
452
453/**
454 * mpi3mr_free_tgtdev - target device memory dealloctor
455 * @r: k reference pointer of the target device
456 *
457 * Free target device memory when no reference.
458 */
459static inline void mpi3mr_free_tgtdev(struct kref *r)
460{
461 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
462}
463
464/**
465 * mpi3mr_tgtdev_put - k reference decrementor
466 * @s: Target device reference
467 *
468 * Decrement target device reference count.
469 */
470static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
471{
472 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
473}
474
475
476/**
477 * struct mpi3mr_stgt_priv_data - SCSI target private structure
478 *
479 * @starget: Scsi_target pointer
480 * @dev_handle: FW device handle
481 * @perst_id: FW assigned Persistent ID
482 * @num_luns: Number of Logical Units
483 * @block_io: I/O blocked to the device or not
484 * @dev_removed: Device removed in the Firmware
485 * @dev_removedelay: Device is waiting to be removed in FW
486 * @dev_type: Device type
487 * @tgt_dev: Internal target device pointer
488 */
489struct mpi3mr_stgt_priv_data {
490 struct scsi_target *starget;
491 u16 dev_handle;
492 u16 perst_id;
493 u32 num_luns;
494 atomic_t block_io;
495 u8 dev_removed;
496 u8 dev_removedelay;
497 u8 dev_type;
498 struct mpi3mr_tgt_dev *tgt_dev;
499};
500
501/**
502 * struct mpi3mr_stgt_priv_data - SCSI device private structure
503 *
504 * @tgt_priv_data: Scsi_target private data pointer
505 * @lun_id: LUN ID of the device
506 * @ncq_prio_enable: NCQ priority enable for SATA device
507 */
508struct mpi3mr_sdev_priv_data {
509 struct mpi3mr_stgt_priv_data *tgt_priv_data;
510 u32 lun_id;
511 u8 ncq_prio_enable;
512};
513
514/**
515 * struct mpi3mr_drv_cmd - Internal command tracker
516 *
517 * @mutex: Command mutex
518 * @done: Completeor for wakeup
519 * @reply: Firmware reply for internal commands
520 * @sensebuf: Sensebuf for SCSI IO commands
521 * @iou_rc: IO Unit control reason code
522 * @state: Command State
523 * @dev_handle: Firmware handle for device specific commands
524 * @ioc_status: IOC status from the firmware
525 * @ioc_loginfo:IOC log info from the firmware
526 * @is_waiting: Is the command issued in block mode
527 * @retry_count: Retry count for retriable commands
528 * @host_tag: Host tag used by the command
529 * @callback: Callback for non blocking commands
530 */
531struct mpi3mr_drv_cmd {
532 struct mutex mutex;
533 struct completion done;
534 void *reply;
535 u8 *sensebuf;
536 u8 iou_rc;
537 u16 state;
538 u16 dev_handle;
539 u16 ioc_status;
540 u32 ioc_loginfo;
541 u8 is_waiting;
542 u8 retry_count;
543 u16 host_tag;
544
545 void (*callback)(struct mpi3mr_ioc *mrioc,
546 struct mpi3mr_drv_cmd *drv_cmd);
547};
548
549
550/**
551 * struct chain_element - memory descriptor structure to store
552 * virtual and dma addresses for chain elements.
553 *
554 * @addr: virtual address
555 * @dma_addr: dma address
556 */
557struct chain_element {
558 void *addr;
559 dma_addr_t dma_addr;
560};
561
562/**
563 * struct scmd_priv - SCSI command private data
564 *
565 * @host_tag: Host tag specific to operational queue
566 * @in_lld_scope: Command in LLD scope or not
567 * @meta_sg_valid: DIX command with meta data SGL or not
568 * @scmd: SCSI Command pointer
569 * @req_q_idx: Operational request queue index
570 * @chain_idx: Chain frame index
571 * @meta_chain_idx: Chain frame index of meta data SGL
572 * @mpi3mr_scsiio_req: MPI SCSI IO request
573 */
574struct scmd_priv {
575 u16 host_tag;
576 u8 in_lld_scope;
577 u8 meta_sg_valid;
578 struct scsi_cmnd *scmd;
579 u16 req_q_idx;
580 int chain_idx;
581 int meta_chain_idx;
582 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
583};
584
585/**
586 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
587 * private data
588 *
589 * @list: List pointer
590 * @pdev: PCI device pointer
591 * @shost: Scsi_Host pointer
592 * @id: Controller ID
593 * @cpu_count: Number of online CPUs
594 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
595 * @name: Controller ASCII name
596 * @driver_name: Driver ASCII name
597 * @sysif_regs: System interface registers virtual address
598 * @sysif_regs_phys: System interface registers physical address
599 * @bars: PCI BARS
600 * @dma_mask: DMA mask
601 * @msix_count: Number of MSIX vectors used
602 * @intr_enabled: Is interrupts enabled
603 * @num_admin_req: Number of admin requests
604 * @admin_req_q_sz: Admin request queue size
605 * @admin_req_pi: Admin request queue producer index
606 * @admin_req_ci: Admin request queue consumer index
607 * @admin_req_base: Admin request queue base virtual address
608 * @admin_req_dma: Admin request queue base dma address
609 * @admin_req_lock: Admin queue access lock
610 * @num_admin_replies: Number of admin replies
611 * @admin_reply_q_sz: Admin reply queue size
612 * @admin_reply_ci: Admin reply queue consumer index
613 * @admin_reply_ephase:Admin reply queue expected phase
614 * @admin_reply_base: Admin reply queue base virtual address
615 * @admin_reply_dma: Admin reply queue base dma address
616 * @ready_timeout: Controller ready timeout
617 * @intr_info: Interrupt cookie pointer
618 * @intr_info_count: Number of interrupt cookies
619 * @num_queues: Number of operational queues
620 * @num_op_req_q: Number of operational request queues
621 * @req_qinfo: Operational request queue info pointer
622 * @num_op_reply_q: Number of operational reply queues
623 * @op_reply_qinfo: Operational reply queue info pointer
624 * @init_cmds: Command tracker for initialization commands
625 * @facts: Cached IOC facts data
626 * @op_reply_desc_sz: Operational reply descriptor size
627 * @num_reply_bufs: Number of reply buffers allocated
628 * @reply_buf_pool: Reply buffer pool
629 * @reply_buf: Reply buffer base virtual address
630 * @reply_buf_dma: Reply buffer DMA address
631 * @reply_buf_dma_max_address: Reply DMA address max limit
632 * @reply_free_qsz: Reply free queue size
633 * @reply_free_q_pool: Reply free queue pool
634 * @reply_free_q: Reply free queue base virtual address
635 * @reply_free_q_dma: Reply free queue base DMA address
636 * @reply_free_queue_lock: Reply free queue lock
637 * @reply_free_queue_host_index: Reply free queue host index
638 * @num_sense_bufs: Number of sense buffers
639 * @sense_buf_pool: Sense buffer pool
640 * @sense_buf: Sense buffer base virtual address
641 * @sense_buf_dma: Sense buffer base DMA address
642 * @sense_buf_q_sz: Sense buffer queue size
643 * @sense_buf_q_pool: Sense buffer queue pool
644 * @sense_buf_q: Sense buffer queue virtual address
645 * @sense_buf_q_dma: Sense buffer queue DMA address
646 * @sbq_lock: Sense buffer queue lock
647 * @sbq_host_index: Sense buffer queuehost index
648 * @event_masks: Event mask bitmap
649 * @fwevt_worker_name: Firmware event worker thread name
650 * @fwevt_worker_thread: Firmware event worker thread
651 * @fwevt_lock: Firmware event lock
652 * @fwevt_list: Firmware event list
653 * @watchdog_work_q_name: Fault watchdog worker thread name
654 * @watchdog_work_q: Fault watchdog worker thread
655 * @watchdog_work: Fault watchdog work
656 * @watchdog_lock: Fault watchdog lock
657 * @is_driver_loading: Is driver still loading
658 * @scan_started: Async scan started
659 * @scan_failed: Asycn scan failed
660 * @stop_drv_processing: Stop all command processing
661 * @max_host_ios: Maximum host I/O count
662 * @chain_buf_count: Chain buffer count
663 * @chain_buf_pool: Chain buffer pool
664 * @chain_sgl_list: Chain SGL list
665 * @chain_bitmap_sz: Chain buffer allocator bitmap size
666 * @chain_bitmap: Chain buffer allocator bitmap
667 * @chain_buf_lock: Chain buffer list lock
668 * @host_tm_cmds: Command tracker for task management commands
669 * @dev_rmhs_cmds: Command tracker for device removal commands
670 * @devrem_bitmap_sz: Device removal bitmap size
671 * @devrem_bitmap: Device removal bitmap
672 * @dev_handle_bitmap_sz: Device handle bitmap size
673 * @removepend_bitmap: Remove pending bitmap
674 * @delayed_rmhs_list: Delayed device removal list
675 * @ts_update_counter: Timestamp update counter
676 * @fault_dbg: Fault debug flag
677 * @reset_in_progress: Reset in progress flag
678 * @unrecoverable: Controller unrecoverable flag
679 * @reset_mutex: Controller reset mutex
680 * @reset_waitq: Controller reset wait queue
681 * @diagsave_timeout: Diagnostic information save timeout
682 * @logging_level: Controller debug logging level
683 * @flush_io_count: I/O count to flush after reset
684 * @current_event: Firmware event currently in process
685 * @driver_info: Driver, Kernel, OS information to firmware
686 * @change_count: Topology change count
687 * @op_reply_q_offset: Operational reply queue offset with MSIx
688 */
689struct mpi3mr_ioc {
690 struct list_head list;
691 struct pci_dev *pdev;
692 struct Scsi_Host *shost;
693 u8 id;
694 int cpu_count;
695 bool enable_segqueue;
696 u32 irqpoll_sleep;
697
698 char name[MPI3MR_NAME_LENGTH];
699 char driver_name[MPI3MR_NAME_LENGTH];
700
701 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
702 resource_size_t sysif_regs_phys;
703 int bars;
704 u64 dma_mask;
705
706 u16 msix_count;
707 u8 intr_enabled;
708
709 u16 num_admin_req;
710 u32 admin_req_q_sz;
711 u16 admin_req_pi;
712 u16 admin_req_ci;
713 void *admin_req_base;
714 dma_addr_t admin_req_dma;
715 spinlock_t admin_req_lock;
716
717 u16 num_admin_replies;
718 u32 admin_reply_q_sz;
719 u16 admin_reply_ci;
720 u8 admin_reply_ephase;
721 void *admin_reply_base;
722 dma_addr_t admin_reply_dma;
723
724 u32 ready_timeout;
725
726 struct mpi3mr_intr_info *intr_info;
727 u16 intr_info_count;
728
729 u16 num_queues;
730 u16 num_op_req_q;
731 struct op_req_qinfo *req_qinfo;
732
733 u16 num_op_reply_q;
734 struct op_reply_qinfo *op_reply_qinfo;
735
736 struct mpi3mr_drv_cmd init_cmds;
737 struct mpi3mr_ioc_facts facts;
738 u16 op_reply_desc_sz;
739
740 u32 num_reply_bufs;
741 struct dma_pool *reply_buf_pool;
742 u8 *reply_buf;
743 dma_addr_t reply_buf_dma;
744 dma_addr_t reply_buf_dma_max_address;
745
746 u16 reply_free_qsz;
747 struct dma_pool *reply_free_q_pool;
748 __le64 *reply_free_q;
749 dma_addr_t reply_free_q_dma;
750 spinlock_t reply_free_queue_lock;
751 u32 reply_free_queue_host_index;
752
753 u32 num_sense_bufs;
754 struct dma_pool *sense_buf_pool;
755 u8 *sense_buf;
756 dma_addr_t sense_buf_dma;
757
758 u16 sense_buf_q_sz;
759 struct dma_pool *sense_buf_q_pool;
760 __le64 *sense_buf_q;
761 dma_addr_t sense_buf_q_dma;
762 spinlock_t sbq_lock;
763 u32 sbq_host_index;
764 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
765
766 char fwevt_worker_name[MPI3MR_NAME_LENGTH];
767 struct workqueue_struct *fwevt_worker_thread;
768 spinlock_t fwevt_lock;
769 struct list_head fwevt_list;
770
771 char watchdog_work_q_name[20];
772 struct workqueue_struct *watchdog_work_q;
773 struct delayed_work watchdog_work;
774 spinlock_t watchdog_lock;
775
776 u8 is_driver_loading;
777 u8 scan_started;
778 u16 scan_failed;
779 u8 stop_drv_processing;
780
781 u16 max_host_ios;
782 spinlock_t tgtdev_lock;
783 struct list_head tgtdev_list;
784
785 u32 chain_buf_count;
786 struct dma_pool *chain_buf_pool;
787 struct chain_element *chain_sgl_list;
788 u16 chain_bitmap_sz;
789 void *chain_bitmap;
790 spinlock_t chain_buf_lock;
791
792 struct mpi3mr_drv_cmd host_tm_cmds;
793 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
794 u16 devrem_bitmap_sz;
795 void *devrem_bitmap;
796 u16 dev_handle_bitmap_sz;
797 void *removepend_bitmap;
798 struct list_head delayed_rmhs_list;
799
800 u32 ts_update_counter;
801 u8 fault_dbg;
802 u8 reset_in_progress;
803 u8 unrecoverable;
804 struct mutex reset_mutex;
805 wait_queue_head_t reset_waitq;
806
807 u16 diagsave_timeout;
808 int logging_level;
809 u16 flush_io_count;
810
811 struct mpi3mr_fwevt *current_event;
812 struct mpi3_driver_info_layout driver_info;
813 u16 change_count;
814 u16 op_reply_q_offset;
815};
816
817/**
818 * struct mpi3mr_fwevt - Firmware event structure.
819 *
820 * @list: list head
821 * @work: Work structure
822 * @mrioc: Adapter instance reference
823 * @event_id: MPI3 firmware event ID
824 * @send_ack: Event acknowledgment required or not
825 * @process_evt: Bottomhalf processing required or not
826 * @evt_ctx: Event context to send in Ack
827 * @ref_count: kref count
828 * @event_data: Actual MPI3 event data
829 */
830struct mpi3mr_fwevt {
831 struct list_head list;
832 struct work_struct work;
833 struct mpi3mr_ioc *mrioc;
834 u16 event_id;
835 bool send_ack;
836 bool process_evt;
837 u32 evt_ctx;
838 struct kref ref_count;
839 char event_data[0] __aligned(4);
840};
841
842
843/**
844 * struct delayed_dev_rmhs_node - Delayed device removal node
845 *
846 * @list: list head
847 * @handle: Device handle
848 * @iou_rc: IO Unit Control Reason Code
849 */
850struct delayed_dev_rmhs_node {
851 struct list_head list;
852 u16 handle;
853 u8 iou_rc;
854};
855
856int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
857void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
858int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 re_init);
859void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 re_init);
860int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
861int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
862u16 admin_req_sz, u8 ignore_reset);
863int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
864 struct op_req_qinfo *opreqq, u8 *req);
865void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
866 dma_addr_t dma_addr);
867void mpi3mr_build_zero_len_sge(void *paddr);
868void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
869 dma_addr_t phys_addr);
870void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
871 dma_addr_t phys_addr);
872void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
873 u64 sense_buf_dma);
874
875void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
876 struct mpi3_event_notification_reply *event_reply);
877void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
878 struct mpi3_default_reply_descriptor *reply_desc,
879 u64 *reply_dma, u16 qidx);
880void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
881void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
882
883int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
884 u32 reset_reason, u8 snapdump);
885int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc,
886 u32 reset_reason);
887void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
888void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
889
890enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
891int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
892 u32 event_ctx);
893
894void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
895void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
896void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
897void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
898void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
899void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc);
900
901#endif /*MPI3MR_H_INCLUDED*/
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2022 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10#ifndef MPI3MR_H_INCLUDED
11#define MPI3MR_H_INCLUDED
12
13#include <linux/blkdev.h>
14#include <linux/blk-mq.h>
15#include <linux/blk-mq-pci.h>
16#include <linux/delay.h>
17#include <linux/dmapool.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/miscdevice.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/poll.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/types.h>
30#include <linux/uaccess.h>
31#include <linux/utsname.h>
32#include <linux/version.h>
33#include <linux/workqueue.h>
34#include <asm/unaligned.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37#include <scsi/scsi_dbg.h>
38#include <scsi/scsi_device.h>
39#include <scsi/scsi_host.h>
40#include <scsi/scsi_tcq.h>
41#include <uapi/scsi/scsi_bsg_mpi3mr.h>
42#include <scsi/scsi_transport_sas.h>
43
44#include "mpi/mpi30_transport.h"
45#include "mpi/mpi30_cnfg.h"
46#include "mpi/mpi30_image.h"
47#include "mpi/mpi30_init.h"
48#include "mpi/mpi30_ioc.h"
49#include "mpi/mpi30_sas.h"
50#include "mpi/mpi30_pci.h"
51#include "mpi3mr_debug.h"
52
53/* Global list and lock for storing multiple adapters managed by the driver */
54extern spinlock_t mrioc_list_lock;
55extern struct list_head mrioc_list;
56extern int prot_mask;
57extern atomic64_t event_counter;
58
59#define MPI3MR_DRIVER_VERSION "8.2.0.3.0"
60#define MPI3MR_DRIVER_RELDATE "08-September-2022"
61
62#define MPI3MR_DRIVER_NAME "mpi3mr"
63#define MPI3MR_DRIVER_LICENSE "GPL"
64#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
65#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
66
67#define MPI3MR_NAME_LENGTH 32
68#define IOCNAME "%s: "
69
70#define MPI3MR_MAX_SECTORS 2048
71
72/* Definitions for internal SGL and Chain SGL buffers */
73#define MPI3MR_PAGE_SIZE_4K 4096
74#define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
75
76/* Definitions for MAX values for shost */
77#define MPI3MR_MAX_CMDS_LUN 128
78#define MPI3MR_MAX_CDB_LENGTH 32
79
80/* Admin queue management definitions */
81#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
82#define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)
83#define MPI3MR_ADMIN_REQ_FRAME_SZ 128
84#define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
85
86/* Operational queue management definitions */
87#define MPI3MR_OP_REQ_Q_QD 512
88#define MPI3MR_OP_REP_Q_QD 1024
89#define MPI3MR_OP_REP_Q_QD4K 4096
90#define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
91#define MPI3MR_OP_REP_Q_SEG_SIZE 4096
92#define MPI3MR_MAX_SEG_LIST_SIZE 4096
93
94/* Reserved Host Tag definitions */
95#define MPI3MR_HOSTTAG_INVALID 0xFFFF
96#define MPI3MR_HOSTTAG_INITCMDS 1
97#define MPI3MR_HOSTTAG_BSG_CMDS 2
98#define MPI3MR_HOSTTAG_PEL_ABORT 3
99#define MPI3MR_HOSTTAG_PEL_WAIT 4
100#define MPI3MR_HOSTTAG_BLK_TMS 5
101#define MPI3MR_HOSTTAG_CFG_CMDS 6
102#define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7
103
104#define MPI3MR_NUM_DEVRMCMD 16
105#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1)
106#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
107 MPI3MR_NUM_DEVRMCMD - 1)
108
109#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
110#define MPI3MR_NUM_EVTACKCMD 4
111#define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
112#define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
113 MPI3MR_NUM_EVTACKCMD - 1)
114
115/* Reduced resource count definition for crash kernel */
116#define MPI3MR_HOST_IOS_KDUMP 128
117
118/* command/controller interaction timeout definitions in seconds */
119#define MPI3MR_INTADMCMD_TIMEOUT 60
120#define MPI3MR_PORTENABLE_TIMEOUT 300
121#define MPI3MR_PORTENABLE_POLL_INTERVAL 5
122#define MPI3MR_ABORTTM_TIMEOUT 60
123#define MPI3MR_RESETTM_TIMEOUT 60
124#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
125#define MPI3MR_TSUPDATE_INTERVAL 900
126#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
127#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
128#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
129#define MPI3MR_RESET_ACK_TIMEOUT 30
130
131#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
132
133#define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */
134
135#define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10
136
137#define MPI3MR_SCMD_TIMEOUT (60 * HZ)
138#define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
139
140/* Internal admin command state definitions*/
141#define MPI3MR_CMD_NOTUSED 0x8000
142#define MPI3MR_CMD_COMPLETE 0x0001
143#define MPI3MR_CMD_PENDING 0x0002
144#define MPI3MR_CMD_REPLY_VALID 0x0004
145#define MPI3MR_CMD_RESET 0x0008
146
147/* Definitions for Event replies and sense buffer allocated per controller */
148#define MPI3MR_NUM_EVT_REPLIES 64
149#define MPI3MR_SENSE_BUF_SZ 256
150#define MPI3MR_SENSEBUF_FACTOR 3
151#define MPI3MR_CHAINBUF_FACTOR 3
152#define MPI3MR_CHAINBUFDIX_FACTOR 2
153
154/* Invalid target device handle */
155#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
156
157/* Controller Reset related definitions */
158#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
159#define MPI3MR_MAX_RESET_RETRY_COUNT 3
160
161/* ResponseCode definitions */
162#define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
163#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
164 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
165
166#define MPI3MR_DEFAULT_MDTS (128 * 1024)
167#define MPI3MR_DEFAULT_PGSZEXP (12)
168
169/* Command retry count definitions */
170#define MPI3MR_DEV_RMHS_RETRY_COUNT 3
171#define MPI3MR_PEL_RETRY_COUNT 3
172
173/* Default target device queue depth */
174#define MPI3MR_DEFAULT_SDEV_QD 32
175
176/* Definitions for Threaded IRQ poll*/
177#define MPI3MR_IRQ_POLL_SLEEP 2
178#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
179
180/* Definitions for the controller security status*/
181#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
182#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
183
184#define MPI3MR_INVALID_DEVICE 0x00
185#define MPI3MR_CONFIG_SECURE_DEVICE 0x04
186#define MPI3MR_HARD_SECURE_DEVICE 0x08
187#define MPI3MR_TAMPERED_DEVICE 0x0C
188
189/* SGE Flag definition */
190#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
191 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
192 MPI3_SGE_FLAGS_END_OF_LIST)
193
194/* MSI Index from Reply Queue Index */
195#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
196
197/*
198 * Maximum data transfer size definitions for management
199 * application commands
200 */
201#define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)
202#define MPI3MR_MAX_APP_XFER_SEGMENTS 512
203/*
204 * 2048 sectors are for data buffers and additional 512 sectors for
205 * other buffers
206 */
207#define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
208
209/**
210 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe
211 * Encapsulated commands.
212 *
213 * @base_addr: Physical address
214 * @length: SGE length
215 * @rsvd: Reserved
216 * @rsvd1: Reserved
217 * @sgl_type: sgl type
218 */
219struct mpi3mr_nvme_pt_sge {
220 u64 base_addr;
221 u32 length;
222 u16 rsvd;
223 u8 rsvd1;
224 u8 sgl_type;
225};
226
227/**
228 * struct mpi3mr_buf_map - local structure to
229 * track kernel and user buffers associated with an BSG
230 * structure.
231 *
232 * @bsg_buf: BSG buffer virtual address
233 * @bsg_buf_len: BSG buffer length
234 * @kern_buf: Kernel buffer virtual address
235 * @kern_buf_len: Kernel buffer length
236 * @kern_buf_dma: Kernel buffer DMA address
237 * @data_dir: Data direction.
238 */
239struct mpi3mr_buf_map {
240 void *bsg_buf;
241 u32 bsg_buf_len;
242 void *kern_buf;
243 u32 kern_buf_len;
244 dma_addr_t kern_buf_dma;
245 u8 data_dir;
246};
247
248/* IOC State definitions */
249enum mpi3mr_iocstate {
250 MRIOC_STATE_READY = 1,
251 MRIOC_STATE_RESET,
252 MRIOC_STATE_FAULT,
253 MRIOC_STATE_BECOMING_READY,
254 MRIOC_STATE_RESET_REQUESTED,
255 MRIOC_STATE_UNRECOVERABLE,
256};
257
258/* Reset reason code definitions*/
259enum mpi3mr_reset_reason {
260 MPI3MR_RESET_FROM_BRINGUP = 1,
261 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
262 MPI3MR_RESET_FROM_APP = 3,
263 MPI3MR_RESET_FROM_EH_HOS = 4,
264 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
265 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
266 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
267 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
268 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
269 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
270 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
271 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
272 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
273 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
274 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
275 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
276 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
277 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
278 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
279 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
280 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
281 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
282 MPI3MR_RESET_FROM_SYSFS = 23,
283 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
284 MPI3MR_RESET_FROM_FIRMWARE = 27,
285 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,
286 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
287};
288
289/* Queue type definitions */
290enum queue_type {
291 MPI3MR_DEFAULT_QUEUE = 0,
292 MPI3MR_POLL_QUEUE,
293};
294
295/**
296 * struct mpi3mr_compimg_ver - replica of component image
297 * version defined in mpi30_image.h in host endianness
298 *
299 */
300struct mpi3mr_compimg_ver {
301 u16 build_num;
302 u16 cust_id;
303 u8 ph_minor;
304 u8 ph_major;
305 u8 gen_minor;
306 u8 gen_major;
307};
308
309/**
310 * struct mpi3mr_ioc_facs - replica of component image version
311 * defined in mpi30_ioc.h in host endianness
312 *
313 */
314struct mpi3mr_ioc_facts {
315 u32 ioc_capabilities;
316 struct mpi3mr_compimg_ver fw_ver;
317 u32 mpi_version;
318 u16 max_reqs;
319 u16 product_id;
320 u16 op_req_sz;
321 u16 reply_sz;
322 u16 exceptions;
323 u16 max_perids;
324 u16 max_pds;
325 u16 max_sasexpanders;
326 u16 max_sasinitiators;
327 u16 max_enclosures;
328 u16 max_pcie_switches;
329 u16 max_nvme;
330 u16 max_vds;
331 u16 max_hpds;
332 u16 max_advhpds;
333 u16 max_raid_pds;
334 u16 min_devhandle;
335 u16 max_devhandle;
336 u16 max_op_req_q;
337 u16 max_op_reply_q;
338 u16 shutdown_timeout;
339 u8 ioc_num;
340 u8 who_init;
341 u16 max_msix_vectors;
342 u8 personality;
343 u8 dma_mask;
344 u8 protocol_flags;
345 u8 sge_mod_mask;
346 u8 sge_mod_value;
347 u8 sge_mod_shift;
348 u8 max_dev_per_tg;
349 u16 max_io_throttle_group;
350 u16 io_throttle_data_length;
351 u16 io_throttle_low;
352 u16 io_throttle_high;
353
354};
355
356/**
357 * struct segments - memory descriptor structure to store
358 * virtual and dma addresses for operational queue segments.
359 *
360 * @segment: virtual address
361 * @segment_dma: dma address
362 */
363struct segments {
364 void *segment;
365 dma_addr_t segment_dma;
366};
367
368/**
369 * struct op_req_qinfo - Operational Request Queue Information
370 *
371 * @ci: consumer index
372 * @pi: producer index
373 * @num_request: Maximum number of entries in the queue
374 * @qid: Queue Id starting from 1
375 * @reply_qid: Associated reply queue Id
376 * @num_segments: Number of discontiguous memory segments
377 * @segment_qd: Depth of each segments
378 * @q_lock: Concurrent queue access lock
379 * @q_segments: Segment descriptor pointer
380 * @q_segment_list: Segment list base virtual address
381 * @q_segment_list_dma: Segment list base DMA address
382 */
383struct op_req_qinfo {
384 u16 ci;
385 u16 pi;
386 u16 num_requests;
387 u16 qid;
388 u16 reply_qid;
389 u16 num_segments;
390 u16 segment_qd;
391 spinlock_t q_lock;
392 struct segments *q_segments;
393 void *q_segment_list;
394 dma_addr_t q_segment_list_dma;
395};
396
397/**
398 * struct op_reply_qinfo - Operational Reply Queue Information
399 *
400 * @ci: consumer index
401 * @qid: Queue Id starting from 1
402 * @num_replies: Maximum number of entries in the queue
403 * @num_segments: Number of discontiguous memory segments
404 * @segment_qd: Depth of each segments
405 * @q_segments: Segment descriptor pointer
406 * @q_segment_list: Segment list base virtual address
407 * @q_segment_list_dma: Segment list base DMA address
408 * @ephase: Expected phased identifier for the reply queue
409 * @pend_ios: Number of IOs pending in HW for this queue
410 * @enable_irq_poll: Flag to indicate polling is enabled
411 * @in_use: Queue is handled by poll/ISR
412 * @qtype: Type of queue (types defined in enum queue_type)
413 */
414struct op_reply_qinfo {
415 u16 ci;
416 u16 qid;
417 u16 num_replies;
418 u16 num_segments;
419 u16 segment_qd;
420 struct segments *q_segments;
421 void *q_segment_list;
422 dma_addr_t q_segment_list_dma;
423 u8 ephase;
424 atomic_t pend_ios;
425 bool enable_irq_poll;
426 atomic_t in_use;
427 enum queue_type qtype;
428};
429
430/**
431 * struct mpi3mr_intr_info - Interrupt cookie information
432 *
433 * @mrioc: Adapter instance reference
434 * @os_irq: irq number
435 * @msix_index: MSIx index
436 * @op_reply_q: Associated operational reply queue
437 * @name: Dev name for the irq claiming device
438 */
439struct mpi3mr_intr_info {
440 struct mpi3mr_ioc *mrioc;
441 int os_irq;
442 u16 msix_index;
443 struct op_reply_qinfo *op_reply_q;
444 char name[MPI3MR_NAME_LENGTH];
445};
446
447/**
448 * struct mpi3mr_throttle_group_info - Throttle group info
449 *
450 * @io_divert: Flag indicates io divert is on or off for the TG
451 * @need_qd_reduction: Flag to indicate QD reduction is needed
452 * @qd_reduction: Queue Depth reduction in units of 10%
453 * @fw_qd: QueueDepth value reported by the firmware
454 * @modified_qd: Modified QueueDepth value due to throttling
455 * @id: Throttle Group ID.
456 * @high: High limit to turn on throttling in 512 byte blocks
457 * @low: Low limit to turn off throttling in 512 byte blocks
458 * @pend_large_data_sz: Counter to track pending large data
459 */
460struct mpi3mr_throttle_group_info {
461 u8 io_divert;
462 u8 need_qd_reduction;
463 u8 qd_reduction;
464 u16 fw_qd;
465 u16 modified_qd;
466 u16 id;
467 u32 high;
468 u32 low;
469 atomic_t pend_large_data_sz;
470};
471
472/* HBA port flags */
473#define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01
474
475/**
476 * struct mpi3mr_hba_port - HBA's port information
477 * @port_id: Port number
478 * @flags: HBA port flags
479 */
480struct mpi3mr_hba_port {
481 struct list_head list;
482 u8 port_id;
483 u8 flags;
484};
485
486/**
487 * struct mpi3mr_sas_port - Internal SAS port information
488 * @port_list: List of ports belonging to a SAS node
489 * @num_phys: Number of phys associated with port
490 * @marked_responding: used while refresing the sas ports
491 * @lowest_phy: lowest phy ID of current sas port
492 * @phy_mask: phy_mask of current sas port
493 * @hba_port: HBA port entry
494 * @remote_identify: Attached device identification
495 * @rphy: SAS transport layer rphy object
496 * @port: SAS transport layer port object
497 * @phy_list: mpi3mr_sas_phy objects belonging to this port
498 */
499struct mpi3mr_sas_port {
500 struct list_head port_list;
501 u8 num_phys;
502 u8 marked_responding;
503 int lowest_phy;
504 u32 phy_mask;
505 struct mpi3mr_hba_port *hba_port;
506 struct sas_identify remote_identify;
507 struct sas_rphy *rphy;
508 struct sas_port *port;
509 struct list_head phy_list;
510};
511
512/**
513 * struct mpi3mr_sas_phy - Internal SAS Phy information
514 * @port_siblings: List of phys belonging to a port
515 * @identify: Phy identification
516 * @remote_identify: Attached device identification
517 * @phy: SAS transport layer Phy object
518 * @phy_id: Unique phy id within a port
519 * @handle: Firmware device handle for this phy
520 * @attached_handle: Firmware device handle for attached device
521 * @phy_belongs_to_port: Flag to indicate phy belongs to port
522 @hba_port: HBA port entry
523 */
524struct mpi3mr_sas_phy {
525 struct list_head port_siblings;
526 struct sas_identify identify;
527 struct sas_identify remote_identify;
528 struct sas_phy *phy;
529 u8 phy_id;
530 u16 handle;
531 u16 attached_handle;
532 u8 phy_belongs_to_port;
533 struct mpi3mr_hba_port *hba_port;
534};
535
536/**
537 * struct mpi3mr_sas_node - SAS host/expander information
538 * @list: List of sas nodes in a controller
539 * @parent_dev: Parent device class
540 * @num_phys: Number phys belonging to sas_node
541 * @sas_address: SAS address of sas_node
542 * @handle: Firmware device handle for this sas_host/expander
543 * @sas_address_parent: SAS address of parent expander or host
544 * @enclosure_handle: Firmware handle of enclosure of this node
545 * @device_info: Capabilities of this sas_host/expander
546 * @non_responding: used to refresh the expander devices during reset
547 * @host_node: Flag to indicate this is a host_node
548 * @hba_port: HBA port entry
549 * @phy: A list of phys that make up this sas_host/expander
550 * @sas_port_list: List of internal ports of this node
551 * @rphy: sas_rphy object of this expander node
552 */
553struct mpi3mr_sas_node {
554 struct list_head list;
555 struct device *parent_dev;
556 u8 num_phys;
557 u64 sas_address;
558 u16 handle;
559 u64 sas_address_parent;
560 u16 enclosure_handle;
561 u64 enclosure_logical_id;
562 u8 non_responding;
563 u8 host_node;
564 struct mpi3mr_hba_port *hba_port;
565 struct mpi3mr_sas_phy *phy;
566 struct list_head sas_port_list;
567 struct sas_rphy *rphy;
568};
569
570/**
571 * struct mpi3mr_enclosure_node - enclosure information
572 * @list: List of enclosures
573 * @pg0: Enclosure page 0;
574 */
575struct mpi3mr_enclosure_node {
576 struct list_head list;
577 struct mpi3_enclosure_page0 pg0;
578};
579
580/**
581 * struct tgt_dev_sas_sata - SAS/SATA device specific
582 * information cached from firmware given data
583 *
584 * @sas_address: World wide unique SAS address
585 * @sas_address_parent: Sas address of parent expander or host
586 * @dev_info: Device information bits
587 * @phy_id: Phy identifier provided in device page 0
588 * @attached_phy_id: Attached phy identifier provided in device page 0
589 * @sas_transport_attached: Is this device exposed to transport
590 * @pend_sas_rphy_add: Flag to check device is in process of add
591 * @hba_port: HBA port entry
592 * @rphy: SAS transport layer rphy object
593 */
594struct tgt_dev_sas_sata {
595 u64 sas_address;
596 u64 sas_address_parent;
597 u16 dev_info;
598 u8 phy_id;
599 u8 attached_phy_id;
600 u8 sas_transport_attached;
601 u8 pend_sas_rphy_add;
602 struct mpi3mr_hba_port *hba_port;
603 struct sas_rphy *rphy;
604};
605
606/**
607 * struct tgt_dev_pcie - PCIe device specific information cached
608 * from firmware given data
609 *
610 * @mdts: Maximum data transfer size
611 * @capb: Device capabilities
612 * @pgsz: Device page size
613 * @abort_to: Timeout for abort TM
614 * @reset_to: Timeout for Target/LUN reset TM
615 * @dev_info: Device information bits
616 */
617struct tgt_dev_pcie {
618 u32 mdts;
619 u16 capb;
620 u8 pgsz;
621 u8 abort_to;
622 u8 reset_to;
623 u16 dev_info;
624};
625
626/**
627 * struct tgt_dev_vd - virtual device specific information
628 * cached from firmware given data
629 *
630 * @state: State of the VD
631 * @tg_qd_reduction: Queue Depth reduction in units of 10%
632 * @tg_id: VDs throttle group ID
633 * @high: High limit to turn on throttling in 512 byte blocks
634 * @low: Low limit to turn off throttling in 512 byte blocks
635 * @tg: Pointer to throttle group info
636 */
637struct tgt_dev_vd {
638 u8 state;
639 u8 tg_qd_reduction;
640 u16 tg_id;
641 u32 tg_high;
642 u32 tg_low;
643 struct mpi3mr_throttle_group_info *tg;
644};
645
646
647/**
648 * union _form_spec_inf - union of device specific information
649 */
650union _form_spec_inf {
651 struct tgt_dev_sas_sata sas_sata_inf;
652 struct tgt_dev_pcie pcie_inf;
653 struct tgt_dev_vd vd_inf;
654};
655
656
657
658/**
659 * struct mpi3mr_tgt_dev - target device data structure
660 *
661 * @list: List pointer
662 * @starget: Scsi_target pointer
663 * @dev_handle: FW device handle
664 * @parent_handle: FW parent device handle
665 * @slot: Slot number
666 * @encl_handle: FW enclosure handle
667 * @perst_id: FW assigned Persistent ID
668 * @devpg0_flag: Device Page0 flag
669 * @dev_type: SAS/SATA/PCIE device type
670 * @is_hidden: Should be exposed to upper layers or not
671 * @host_exposed: Already exposed to host or not
672 * @io_unit_port: IO Unit port ID
673 * @non_stl: Is this device not to be attached with SAS TL
674 * @io_throttle_enabled: I/O throttling needed or not
675 * @q_depth: Device specific Queue Depth
676 * @wwid: World wide ID
677 * @enclosure_logical_id: Enclosure logical identifier
678 * @dev_spec: Device type specific information
679 * @ref_count: Reference count
680 */
681struct mpi3mr_tgt_dev {
682 struct list_head list;
683 struct scsi_target *starget;
684 u16 dev_handle;
685 u16 parent_handle;
686 u16 slot;
687 u16 encl_handle;
688 u16 perst_id;
689 u16 devpg0_flag;
690 u8 dev_type;
691 u8 is_hidden;
692 u8 host_exposed;
693 u8 io_unit_port;
694 u8 non_stl;
695 u8 io_throttle_enabled;
696 u16 q_depth;
697 u64 wwid;
698 u64 enclosure_logical_id;
699 union _form_spec_inf dev_spec;
700 struct kref ref_count;
701};
702
703/**
704 * mpi3mr_tgtdev_get - k reference incrementor
705 * @s: Target device reference
706 *
707 * Increment target device reference count.
708 */
709static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
710{
711 kref_get(&s->ref_count);
712}
713
714/**
715 * mpi3mr_free_tgtdev - target device memory dealloctor
716 * @r: k reference pointer of the target device
717 *
718 * Free target device memory when no reference.
719 */
720static inline void mpi3mr_free_tgtdev(struct kref *r)
721{
722 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
723}
724
725/**
726 * mpi3mr_tgtdev_put - k reference decrementor
727 * @s: Target device reference
728 *
729 * Decrement target device reference count.
730 */
731static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
732{
733 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
734}
735
736
737/**
738 * struct mpi3mr_stgt_priv_data - SCSI target private structure
739 *
740 * @starget: Scsi_target pointer
741 * @dev_handle: FW device handle
742 * @perst_id: FW assigned Persistent ID
743 * @num_luns: Number of Logical Units
744 * @block_io: I/O blocked to the device or not
745 * @dev_removed: Device removed in the Firmware
746 * @dev_removedelay: Device is waiting to be removed in FW
747 * @dev_type: Device type
748 * @io_throttle_enabled: I/O throttling needed or not
749 * @io_divert: Flag indicates io divert is on or off for the dev
750 * @throttle_group: Pointer to throttle group info
751 * @tgt_dev: Internal target device pointer
752 * @pend_count: Counter to track pending I/Os during error
753 * handling
754 */
755struct mpi3mr_stgt_priv_data {
756 struct scsi_target *starget;
757 u16 dev_handle;
758 u16 perst_id;
759 u32 num_luns;
760 atomic_t block_io;
761 u8 dev_removed;
762 u8 dev_removedelay;
763 u8 dev_type;
764 u8 io_throttle_enabled;
765 u8 io_divert;
766 struct mpi3mr_throttle_group_info *throttle_group;
767 struct mpi3mr_tgt_dev *tgt_dev;
768 u32 pend_count;
769};
770
771/**
772 * struct mpi3mr_stgt_priv_data - SCSI device private structure
773 *
774 * @tgt_priv_data: Scsi_target private data pointer
775 * @lun_id: LUN ID of the device
776 * @ncq_prio_enable: NCQ priority enable for SATA device
777 * @pend_count: Counter to track pending I/Os during error
778 * handling
779 */
780struct mpi3mr_sdev_priv_data {
781 struct mpi3mr_stgt_priv_data *tgt_priv_data;
782 u32 lun_id;
783 u8 ncq_prio_enable;
784 u32 pend_count;
785};
786
787/**
788 * struct mpi3mr_drv_cmd - Internal command tracker
789 *
790 * @mutex: Command mutex
791 * @done: Completeor for wakeup
792 * @reply: Firmware reply for internal commands
793 * @sensebuf: Sensebuf for SCSI IO commands
794 * @iou_rc: IO Unit control reason code
795 * @state: Command State
796 * @dev_handle: Firmware handle for device specific commands
797 * @ioc_status: IOC status from the firmware
798 * @ioc_loginfo:IOC log info from the firmware
799 * @is_waiting: Is the command issued in block mode
800 * @is_sense: Is Sense data present
801 * @retry_count: Retry count for retriable commands
802 * @host_tag: Host tag used by the command
803 * @callback: Callback for non blocking commands
804 */
805struct mpi3mr_drv_cmd {
806 struct mutex mutex;
807 struct completion done;
808 void *reply;
809 u8 *sensebuf;
810 u8 iou_rc;
811 u16 state;
812 u16 dev_handle;
813 u16 ioc_status;
814 u32 ioc_loginfo;
815 u8 is_waiting;
816 u8 is_sense;
817 u8 retry_count;
818 u16 host_tag;
819
820 void (*callback)(struct mpi3mr_ioc *mrioc,
821 struct mpi3mr_drv_cmd *drv_cmd);
822};
823
824/**
825 * struct dma_memory_desc - memory descriptor structure to store
826 * virtual address, dma address and size for any generic dma
827 * memory allocations in the driver.
828 *
829 * @size: buffer size
830 * @addr: virtual address
831 * @dma_addr: dma address
832 */
833struct dma_memory_desc {
834 u32 size;
835 void *addr;
836 dma_addr_t dma_addr;
837};
838
839
840/**
841 * struct chain_element - memory descriptor structure to store
842 * virtual and dma addresses for chain elements.
843 *
844 * @addr: virtual address
845 * @dma_addr: dma address
846 */
847struct chain_element {
848 void *addr;
849 dma_addr_t dma_addr;
850};
851
852/**
853 * struct scmd_priv - SCSI command private data
854 *
855 * @host_tag: Host tag specific to operational queue
856 * @in_lld_scope: Command in LLD scope or not
857 * @meta_sg_valid: DIX command with meta data SGL or not
858 * @scmd: SCSI Command pointer
859 * @req_q_idx: Operational request queue index
860 * @chain_idx: Chain frame index
861 * @meta_chain_idx: Chain frame index of meta data SGL
862 * @mpi3mr_scsiio_req: MPI SCSI IO request
863 */
864struct scmd_priv {
865 u16 host_tag;
866 u8 in_lld_scope;
867 u8 meta_sg_valid;
868 struct scsi_cmnd *scmd;
869 u16 req_q_idx;
870 int chain_idx;
871 int meta_chain_idx;
872 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
873};
874
875/**
876 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
877 * private data
878 *
879 * @list: List pointer
880 * @pdev: PCI device pointer
881 * @shost: Scsi_Host pointer
882 * @id: Controller ID
883 * @cpu_count: Number of online CPUs
884 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
885 * @name: Controller ASCII name
886 * @driver_name: Driver ASCII name
887 * @sysif_regs: System interface registers virtual address
888 * @sysif_regs_phys: System interface registers physical address
889 * @bars: PCI BARS
890 * @dma_mask: DMA mask
891 * @msix_count: Number of MSIX vectors used
892 * @intr_enabled: Is interrupts enabled
893 * @num_admin_req: Number of admin requests
894 * @admin_req_q_sz: Admin request queue size
895 * @admin_req_pi: Admin request queue producer index
896 * @admin_req_ci: Admin request queue consumer index
897 * @admin_req_base: Admin request queue base virtual address
898 * @admin_req_dma: Admin request queue base dma address
899 * @admin_req_lock: Admin queue access lock
900 * @num_admin_replies: Number of admin replies
901 * @admin_reply_q_sz: Admin reply queue size
902 * @admin_reply_ci: Admin reply queue consumer index
903 * @admin_reply_ephase:Admin reply queue expected phase
904 * @admin_reply_base: Admin reply queue base virtual address
905 * @admin_reply_dma: Admin reply queue base dma address
906 * @ready_timeout: Controller ready timeout
907 * @intr_info: Interrupt cookie pointer
908 * @intr_info_count: Number of interrupt cookies
909 * @is_intr_info_set: Flag to indicate intr info is setup
910 * @num_queues: Number of operational queues
911 * @num_op_req_q: Number of operational request queues
912 * @req_qinfo: Operational request queue info pointer
913 * @num_op_reply_q: Number of operational reply queues
914 * @op_reply_qinfo: Operational reply queue info pointer
915 * @init_cmds: Command tracker for initialization commands
916 * @cfg_cmds: Command tracker for configuration requests
917 * @facts: Cached IOC facts data
918 * @op_reply_desc_sz: Operational reply descriptor size
919 * @num_reply_bufs: Number of reply buffers allocated
920 * @reply_buf_pool: Reply buffer pool
921 * @reply_buf: Reply buffer base virtual address
922 * @reply_buf_dma: Reply buffer DMA address
923 * @reply_buf_dma_max_address: Reply DMA address max limit
924 * @reply_free_qsz: Reply free queue size
925 * @reply_free_q_pool: Reply free queue pool
926 * @reply_free_q: Reply free queue base virtual address
927 * @reply_free_q_dma: Reply free queue base DMA address
928 * @reply_free_queue_lock: Reply free queue lock
929 * @reply_free_queue_host_index: Reply free queue host index
930 * @num_sense_bufs: Number of sense buffers
931 * @sense_buf_pool: Sense buffer pool
932 * @sense_buf: Sense buffer base virtual address
933 * @sense_buf_dma: Sense buffer base DMA address
934 * @sense_buf_q_sz: Sense buffer queue size
935 * @sense_buf_q_pool: Sense buffer queue pool
936 * @sense_buf_q: Sense buffer queue virtual address
937 * @sense_buf_q_dma: Sense buffer queue DMA address
938 * @sbq_lock: Sense buffer queue lock
939 * @sbq_host_index: Sense buffer queuehost index
940 * @event_masks: Event mask bitmap
941 * @fwevt_worker_name: Firmware event worker thread name
942 * @fwevt_worker_thread: Firmware event worker thread
943 * @fwevt_lock: Firmware event lock
944 * @fwevt_list: Firmware event list
945 * @watchdog_work_q_name: Fault watchdog worker thread name
946 * @watchdog_work_q: Fault watchdog worker thread
947 * @watchdog_work: Fault watchdog work
948 * @watchdog_lock: Fault watchdog lock
949 * @is_driver_loading: Is driver still loading
950 * @scan_started: Async scan started
951 * @scan_failed: Asycn scan failed
952 * @stop_drv_processing: Stop all command processing
953 * @device_refresh_on: Don't process the events until devices are refreshed
954 * @max_host_ios: Maximum host I/O count
955 * @chain_buf_count: Chain buffer count
956 * @chain_buf_pool: Chain buffer pool
957 * @chain_sgl_list: Chain SGL list
958 * @chain_bitmap_sz: Chain buffer allocator bitmap size
959 * @chain_bitmap: Chain buffer allocator bitmap
960 * @chain_buf_lock: Chain buffer list lock
961 * @bsg_cmds: Command tracker for BSG command
962 * @host_tm_cmds: Command tracker for task management commands
963 * @dev_rmhs_cmds: Command tracker for device removal commands
964 * @evtack_cmds: Command tracker for event ack commands
965 * @devrem_bitmap_sz: Device removal bitmap size
966 * @devrem_bitmap: Device removal bitmap
967 * @dev_handle_bitmap_sz: Device handle bitmap size
968 * @removepend_bitmap: Remove pending bitmap
969 * @delayed_rmhs_list: Delayed device removal list
970 * @evtack_cmds_bitmap_sz: Event Ack bitmap size
971 * @evtack_cmds_bitmap: Event Ack bitmap
972 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
973 * @ts_update_counter: Timestamp update counter
974 * @reset_in_progress: Reset in progress flag
975 * @unrecoverable: Controller unrecoverable flag
976 * @prev_reset_result: Result of previous reset
977 * @reset_mutex: Controller reset mutex
978 * @reset_waitq: Controller reset wait queue
979 * @prepare_for_reset: Prepare for reset event received
980 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
981 * @prp_list_virt: NVMe encapsulated PRP list virtual base
982 * @prp_list_dma: NVMe encapsulated PRP list DMA
983 * @prp_sz: NVME encapsulated PRP list size
984 * @diagsave_timeout: Diagnostic information save timeout
985 * @logging_level: Controller debug logging level
986 * @flush_io_count: I/O count to flush after reset
987 * @current_event: Firmware event currently in process
988 * @driver_info: Driver, Kernel, OS information to firmware
989 * @change_count: Topology change count
990 * @pel_enabled: Persistent Event Log(PEL) enabled or not
991 * @pel_abort_requested: PEL abort is requested or not
992 * @pel_class: PEL Class identifier
993 * @pel_locale: PEL Locale identifier
994 * @pel_cmds: Command tracker for PEL wait command
995 * @pel_abort_cmd: Command tracker for PEL abort command
996 * @pel_newest_seqnum: Newest PEL sequenece number
997 * @pel_seqnum_virt: PEL sequence number virtual address
998 * @pel_seqnum_dma: PEL sequence number DMA address
999 * @pel_seqnum_sz: PEL sequenece number size
1000 * @op_reply_q_offset: Operational reply queue offset with MSIx
1001 * @default_qcount: Total Default queues
1002 * @active_poll_qcount: Currently active poll queue count
1003 * @requested_poll_qcount: User requested poll queue count
1004 * @bsg_dev: BSG device structure
1005 * @bsg_queue: Request queue for BSG device
1006 * @stop_bsgs: Stop BSG request flag
1007 * @logdata_buf: Circular buffer to store log data entries
1008 * @logdata_buf_idx: Index of entry in buffer to store
1009 * @logdata_entry_sz: log data entry size
1010 * @pend_large_data_sz: Counter to track pending large data
1011 * @io_throttle_data_length: I/O size to track in 512b blocks
1012 * @io_throttle_high: I/O size to start throttle in 512b blocks
1013 * @io_throttle_low: I/O size to stop throttle in 512b blocks
1014 * @num_io_throttle_group: Maximum number of throttle groups
1015 * @throttle_groups: Pointer to throttle group info structures
1016 * @cfg_page: Default memory for configuration pages
1017 * @cfg_page_dma: Configuration page DMA address
1018 * @cfg_page_sz: Default configuration page memory size
1019 * @sas_transport_enabled: SAS transport enabled or not
1020 * @scsi_device_channel: Channel ID for SCSI devices
1021 * @transport_cmds: Command tracker for SAS transport commands
1022 * @sas_hba: SAS node for the controller
1023 * @sas_expander_list: SAS node list of expanders
1024 * @sas_node_lock: Lock to protect SAS node list
1025 * @hba_port_table_list: List of HBA Ports
1026 * @enclosure_list: List of Enclosure objects
1027 */
1028struct mpi3mr_ioc {
1029 struct list_head list;
1030 struct pci_dev *pdev;
1031 struct Scsi_Host *shost;
1032 u8 id;
1033 int cpu_count;
1034 bool enable_segqueue;
1035 u32 irqpoll_sleep;
1036
1037 char name[MPI3MR_NAME_LENGTH];
1038 char driver_name[MPI3MR_NAME_LENGTH];
1039
1040 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
1041 resource_size_t sysif_regs_phys;
1042 int bars;
1043 u64 dma_mask;
1044
1045 u16 msix_count;
1046 u8 intr_enabled;
1047
1048 u16 num_admin_req;
1049 u32 admin_req_q_sz;
1050 u16 admin_req_pi;
1051 u16 admin_req_ci;
1052 void *admin_req_base;
1053 dma_addr_t admin_req_dma;
1054 spinlock_t admin_req_lock;
1055
1056 u16 num_admin_replies;
1057 u32 admin_reply_q_sz;
1058 u16 admin_reply_ci;
1059 u8 admin_reply_ephase;
1060 void *admin_reply_base;
1061 dma_addr_t admin_reply_dma;
1062
1063 u32 ready_timeout;
1064
1065 struct mpi3mr_intr_info *intr_info;
1066 u16 intr_info_count;
1067 bool is_intr_info_set;
1068
1069 u16 num_queues;
1070 u16 num_op_req_q;
1071 struct op_req_qinfo *req_qinfo;
1072
1073 u16 num_op_reply_q;
1074 struct op_reply_qinfo *op_reply_qinfo;
1075
1076 struct mpi3mr_drv_cmd init_cmds;
1077 struct mpi3mr_drv_cmd cfg_cmds;
1078 struct mpi3mr_ioc_facts facts;
1079 u16 op_reply_desc_sz;
1080
1081 u32 num_reply_bufs;
1082 struct dma_pool *reply_buf_pool;
1083 u8 *reply_buf;
1084 dma_addr_t reply_buf_dma;
1085 dma_addr_t reply_buf_dma_max_address;
1086
1087 u16 reply_free_qsz;
1088 u16 reply_sz;
1089 struct dma_pool *reply_free_q_pool;
1090 __le64 *reply_free_q;
1091 dma_addr_t reply_free_q_dma;
1092 spinlock_t reply_free_queue_lock;
1093 u32 reply_free_queue_host_index;
1094
1095 u32 num_sense_bufs;
1096 struct dma_pool *sense_buf_pool;
1097 u8 *sense_buf;
1098 dma_addr_t sense_buf_dma;
1099
1100 u16 sense_buf_q_sz;
1101 struct dma_pool *sense_buf_q_pool;
1102 __le64 *sense_buf_q;
1103 dma_addr_t sense_buf_q_dma;
1104 spinlock_t sbq_lock;
1105 u32 sbq_host_index;
1106 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
1107
1108 char fwevt_worker_name[MPI3MR_NAME_LENGTH];
1109 struct workqueue_struct *fwevt_worker_thread;
1110 spinlock_t fwevt_lock;
1111 struct list_head fwevt_list;
1112
1113 char watchdog_work_q_name[20];
1114 struct workqueue_struct *watchdog_work_q;
1115 struct delayed_work watchdog_work;
1116 spinlock_t watchdog_lock;
1117
1118 u8 is_driver_loading;
1119 u8 scan_started;
1120 u16 scan_failed;
1121 u8 stop_drv_processing;
1122 u8 device_refresh_on;
1123
1124 u16 max_host_ios;
1125 spinlock_t tgtdev_lock;
1126 struct list_head tgtdev_list;
1127
1128 u32 chain_buf_count;
1129 struct dma_pool *chain_buf_pool;
1130 struct chain_element *chain_sgl_list;
1131 u16 chain_bitmap_sz;
1132 void *chain_bitmap;
1133 spinlock_t chain_buf_lock;
1134
1135 struct mpi3mr_drv_cmd bsg_cmds;
1136 struct mpi3mr_drv_cmd host_tm_cmds;
1137 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
1138 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
1139 u16 devrem_bitmap_sz;
1140 void *devrem_bitmap;
1141 u16 dev_handle_bitmap_sz;
1142 void *removepend_bitmap;
1143 struct list_head delayed_rmhs_list;
1144 u16 evtack_cmds_bitmap_sz;
1145 void *evtack_cmds_bitmap;
1146 struct list_head delayed_evtack_cmds_list;
1147
1148 u32 ts_update_counter;
1149 u8 reset_in_progress;
1150 u8 unrecoverable;
1151 int prev_reset_result;
1152 struct mutex reset_mutex;
1153 wait_queue_head_t reset_waitq;
1154
1155 u8 prepare_for_reset;
1156 u16 prepare_for_reset_timeout_counter;
1157
1158 void *prp_list_virt;
1159 dma_addr_t prp_list_dma;
1160 u32 prp_sz;
1161
1162 u16 diagsave_timeout;
1163 int logging_level;
1164 u16 flush_io_count;
1165
1166 struct mpi3mr_fwevt *current_event;
1167 struct mpi3_driver_info_layout driver_info;
1168 u16 change_count;
1169
1170 u8 pel_enabled;
1171 u8 pel_abort_requested;
1172 u8 pel_class;
1173 u16 pel_locale;
1174 struct mpi3mr_drv_cmd pel_cmds;
1175 struct mpi3mr_drv_cmd pel_abort_cmd;
1176
1177 u32 pel_newest_seqnum;
1178 void *pel_seqnum_virt;
1179 dma_addr_t pel_seqnum_dma;
1180 u32 pel_seqnum_sz;
1181
1182 u16 op_reply_q_offset;
1183 u16 default_qcount;
1184 u16 active_poll_qcount;
1185 u16 requested_poll_qcount;
1186
1187 struct device bsg_dev;
1188 struct request_queue *bsg_queue;
1189 u8 stop_bsgs;
1190 u8 *logdata_buf;
1191 u16 logdata_buf_idx;
1192 u16 logdata_entry_sz;
1193
1194 atomic_t pend_large_data_sz;
1195 u32 io_throttle_data_length;
1196 u32 io_throttle_high;
1197 u32 io_throttle_low;
1198 u16 num_io_throttle_group;
1199 struct mpi3mr_throttle_group_info *throttle_groups;
1200
1201 void *cfg_page;
1202 dma_addr_t cfg_page_dma;
1203 u16 cfg_page_sz;
1204
1205 u8 sas_transport_enabled;
1206 u8 scsi_device_channel;
1207 struct mpi3mr_drv_cmd transport_cmds;
1208 struct mpi3mr_sas_node sas_hba;
1209 struct list_head sas_expander_list;
1210 spinlock_t sas_node_lock;
1211 struct list_head hba_port_table_list;
1212 struct list_head enclosure_list;
1213};
1214
1215/**
1216 * struct mpi3mr_fwevt - Firmware event structure.
1217 *
1218 * @list: list head
1219 * @work: Work structure
1220 * @mrioc: Adapter instance reference
1221 * @event_id: MPI3 firmware event ID
1222 * @send_ack: Event acknowledgment required or not
1223 * @process_evt: Bottomhalf processing required or not
1224 * @evt_ctx: Event context to send in Ack
1225 * @event_data_size: size of the event data in bytes
1226 * @pending_at_sml: waiting for device add/remove API to complete
1227 * @discard: discard this event
1228 * @ref_count: kref count
1229 * @event_data: Actual MPI3 event data
1230 */
1231struct mpi3mr_fwevt {
1232 struct list_head list;
1233 struct work_struct work;
1234 struct mpi3mr_ioc *mrioc;
1235 u16 event_id;
1236 bool send_ack;
1237 bool process_evt;
1238 u32 evt_ctx;
1239 u16 event_data_size;
1240 bool pending_at_sml;
1241 bool discard;
1242 struct kref ref_count;
1243 char event_data[] __aligned(4);
1244};
1245
1246
1247/**
1248 * struct delayed_dev_rmhs_node - Delayed device removal node
1249 *
1250 * @list: list head
1251 * @handle: Device handle
1252 * @iou_rc: IO Unit Control Reason Code
1253 */
1254struct delayed_dev_rmhs_node {
1255 struct list_head list;
1256 u16 handle;
1257 u8 iou_rc;
1258};
1259
1260/**
1261 * struct delayed_evt_ack_node - Delayed event ack node
1262 * @list: list head
1263 * @event: MPI3 event ID
1264 * @event_ctx: event context
1265 */
1266struct delayed_evt_ack_node {
1267 struct list_head list;
1268 u8 event;
1269 u32 event_ctx;
1270};
1271
1272int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1273void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1274int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1275int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1276void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1277int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1278int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1279u16 admin_req_sz, u8 ignore_reset);
1280int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1281 struct op_req_qinfo *opreqq, u8 *req);
1282void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1283 dma_addr_t dma_addr);
1284void mpi3mr_build_zero_len_sge(void *paddr);
1285void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1286 dma_addr_t phys_addr);
1287void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1288 dma_addr_t phys_addr);
1289void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1290 u64 sense_buf_dma);
1291
1292void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1293void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1294void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1295 struct mpi3_event_notification_reply *event_reply);
1296void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1297 struct mpi3_default_reply_descriptor *reply_desc,
1298 u64 *reply_dma, u16 qidx);
1299void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1300void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1301
1302int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1303 u32 reset_reason, u8 snapdump);
1304void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1305void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1306
1307enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1308int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1309 u32 event_ctx);
1310
1311void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1312void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1313void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1314void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1315void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
1316void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1317void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1318void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1319void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1320int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1321 struct op_reply_qinfo *op_reply_q);
1322int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1323void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1324void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1325int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1326 u16 handle, uint lun, u16 htag, ulong timeout,
1327 struct mpi3mr_drv_cmd *drv_cmd,
1328 u8 *resp_code, struct scsi_cmnd *scmd);
1329struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1330 struct mpi3mr_ioc *mrioc, u16 handle);
1331void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1332 struct mpi3mr_drv_cmd *drv_cmd);
1333int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1334 struct mpi3mr_drv_cmd *drv_cmd);
1335void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,
1336 u16 event_data_size);
1337struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(
1338 struct mpi3mr_ioc *mrioc, u16 handle);
1339extern const struct attribute_group *mpi3mr_host_groups[];
1340extern const struct attribute_group *mpi3mr_dev_groups[];
1341
1342extern struct sas_function_template mpi3mr_transport_functions;
1343extern struct scsi_transport_template *mpi3mr_transport_template;
1344
1345int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1346 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);
1347int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1348 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
1349 u32 form_spec);
1350int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1351 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
1352 u32 form_spec);
1353int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1354 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
1355 u32 form_spec);
1356int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1357 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
1358 u32 form_spec);
1359int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1360 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
1361 u32 form_spec);
1362int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
1363 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);
1364int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1365 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1366int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1367 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1368int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
1369 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);
1370
1371u8 mpi3mr_is_expander_device(u16 device_info);
1372int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle);
1373void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address,
1374 struct mpi3mr_hba_port *hba_port);
1375struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc
1376 *mrioc, u16 handle);
1377struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc,
1378 u8 port_id);
1379void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc);
1380void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc);
1381void mpi3mr_update_links(struct mpi3mr_ioc *mrioc,
1382 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate,
1383 struct mpi3mr_hba_port *hba_port);
1384void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,
1385 struct mpi3mr_tgt_dev *tgtdev);
1386int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,
1387 struct mpi3mr_tgt_dev *tgtdev);
1388void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc,
1389 struct mpi3mr_tgt_dev *tgtdev);
1390struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy(
1391 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy);
1392void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,
1393 bool device_add);
1394void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc);
1395void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc);
1396void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc);
1397void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc);
1398void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc);
1399void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc);
1400#endif /*MPI3MR_H_INCLUDED*/