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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microsemi Switchtec(tm) PCIe Management Driver
4 * Copyright (c) 2017, Microsemi Corporation
5 */
6
7#include <linux/switchtec.h>
8#include <linux/switchtec_ioctl.h>
9
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/fs.h>
13#include <linux/uaccess.h>
14#include <linux/poll.h>
15#include <linux/wait.h>
16#include <linux/io-64-nonatomic-lo-hi.h>
17#include <linux/nospec.h>
18
19MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
20MODULE_VERSION("0.1");
21MODULE_LICENSE("GPL");
22MODULE_AUTHOR("Microsemi Corporation");
23
24static int max_devices = 16;
25module_param(max_devices, int, 0644);
26MODULE_PARM_DESC(max_devices, "max number of switchtec device instances");
27
28static bool use_dma_mrpc = true;
29module_param(use_dma_mrpc, bool, 0644);
30MODULE_PARM_DESC(use_dma_mrpc,
31 "Enable the use of the DMA MRPC feature");
32
33static int nirqs = 32;
34module_param(nirqs, int, 0644);
35MODULE_PARM_DESC(nirqs, "number of interrupts to allocate (more may be useful for NTB applications)");
36
37static dev_t switchtec_devt;
38static DEFINE_IDA(switchtec_minor_ida);
39
40struct class *switchtec_class;
41EXPORT_SYMBOL_GPL(switchtec_class);
42
43enum mrpc_state {
44 MRPC_IDLE = 0,
45 MRPC_QUEUED,
46 MRPC_RUNNING,
47 MRPC_DONE,
48};
49
50struct switchtec_user {
51 struct switchtec_dev *stdev;
52
53 enum mrpc_state state;
54
55 wait_queue_head_t cmd_comp;
56 struct kref kref;
57 struct list_head list;
58
59 bool cmd_done;
60 u32 cmd;
61 u32 status;
62 u32 return_code;
63 size_t data_len;
64 size_t read_len;
65 unsigned char data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
66 int event_cnt;
67};
68
69static struct switchtec_user *stuser_create(struct switchtec_dev *stdev)
70{
71 struct switchtec_user *stuser;
72
73 stuser = kzalloc(sizeof(*stuser), GFP_KERNEL);
74 if (!stuser)
75 return ERR_PTR(-ENOMEM);
76
77 get_device(&stdev->dev);
78 stuser->stdev = stdev;
79 kref_init(&stuser->kref);
80 INIT_LIST_HEAD(&stuser->list);
81 init_waitqueue_head(&stuser->cmd_comp);
82 stuser->event_cnt = atomic_read(&stdev->event_cnt);
83
84 dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
85
86 return stuser;
87}
88
89static void stuser_free(struct kref *kref)
90{
91 struct switchtec_user *stuser;
92
93 stuser = container_of(kref, struct switchtec_user, kref);
94
95 dev_dbg(&stuser->stdev->dev, "%s: %p\n", __func__, stuser);
96
97 put_device(&stuser->stdev->dev);
98 kfree(stuser);
99}
100
101static void stuser_put(struct switchtec_user *stuser)
102{
103 kref_put(&stuser->kref, stuser_free);
104}
105
106static void stuser_set_state(struct switchtec_user *stuser,
107 enum mrpc_state state)
108{
109 /* requires the mrpc_mutex to already be held when called */
110
111 const char * const state_names[] = {
112 [MRPC_IDLE] = "IDLE",
113 [MRPC_QUEUED] = "QUEUED",
114 [MRPC_RUNNING] = "RUNNING",
115 [MRPC_DONE] = "DONE",
116 };
117
118 stuser->state = state;
119
120 dev_dbg(&stuser->stdev->dev, "stuser state %p -> %s",
121 stuser, state_names[state]);
122}
123
124static void mrpc_complete_cmd(struct switchtec_dev *stdev);
125
126static void flush_wc_buf(struct switchtec_dev *stdev)
127{
128 struct ntb_dbmsg_regs __iomem *mmio_dbmsg;
129
130 /*
131 * odb (outbound doorbell) register is processed by low latency
132 * hardware and w/o side effect
133 */
134 mmio_dbmsg = (void __iomem *)stdev->mmio_ntb +
135 SWITCHTEC_NTB_REG_DBMSG_OFFSET;
136 ioread32(&mmio_dbmsg->odb);
137}
138
139static void mrpc_cmd_submit(struct switchtec_dev *stdev)
140{
141 /* requires the mrpc_mutex to already be held when called */
142
143 struct switchtec_user *stuser;
144
145 if (stdev->mrpc_busy)
146 return;
147
148 if (list_empty(&stdev->mrpc_queue))
149 return;
150
151 stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
152 list);
153
154 if (stdev->dma_mrpc) {
155 stdev->dma_mrpc->status = SWITCHTEC_MRPC_STATUS_INPROGRESS;
156 memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);
157 }
158
159 stuser_set_state(stuser, MRPC_RUNNING);
160 stdev->mrpc_busy = 1;
161 memcpy_toio(&stdev->mmio_mrpc->input_data,
162 stuser->data, stuser->data_len);
163 flush_wc_buf(stdev);
164 iowrite32(stuser->cmd, &stdev->mmio_mrpc->cmd);
165
166 schedule_delayed_work(&stdev->mrpc_timeout,
167 msecs_to_jiffies(500));
168}
169
170static int mrpc_queue_cmd(struct switchtec_user *stuser)
171{
172 /* requires the mrpc_mutex to already be held when called */
173
174 struct switchtec_dev *stdev = stuser->stdev;
175
176 kref_get(&stuser->kref);
177 stuser->read_len = sizeof(stuser->data);
178 stuser_set_state(stuser, MRPC_QUEUED);
179 stuser->cmd_done = false;
180 list_add_tail(&stuser->list, &stdev->mrpc_queue);
181
182 mrpc_cmd_submit(stdev);
183
184 return 0;
185}
186
187static void mrpc_complete_cmd(struct switchtec_dev *stdev)
188{
189 /* requires the mrpc_mutex to already be held when called */
190 struct switchtec_user *stuser;
191
192 if (list_empty(&stdev->mrpc_queue))
193 return;
194
195 stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
196 list);
197
198 if (stdev->dma_mrpc)
199 stuser->status = stdev->dma_mrpc->status;
200 else
201 stuser->status = ioread32(&stdev->mmio_mrpc->status);
202
203 if (stuser->status == SWITCHTEC_MRPC_STATUS_INPROGRESS)
204 return;
205
206 stuser_set_state(stuser, MRPC_DONE);
207 stuser->return_code = 0;
208
209 if (stuser->status != SWITCHTEC_MRPC_STATUS_DONE)
210 goto out;
211
212 if (stdev->dma_mrpc)
213 stuser->return_code = stdev->dma_mrpc->rtn_code;
214 else
215 stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value);
216 if (stuser->return_code != 0)
217 goto out;
218
219 if (stdev->dma_mrpc)
220 memcpy(stuser->data, &stdev->dma_mrpc->data,
221 stuser->read_len);
222 else
223 memcpy_fromio(stuser->data, &stdev->mmio_mrpc->output_data,
224 stuser->read_len);
225out:
226 stuser->cmd_done = true;
227 wake_up_interruptible(&stuser->cmd_comp);
228 list_del_init(&stuser->list);
229 stuser_put(stuser);
230 stdev->mrpc_busy = 0;
231
232 mrpc_cmd_submit(stdev);
233}
234
235static void mrpc_event_work(struct work_struct *work)
236{
237 struct switchtec_dev *stdev;
238
239 stdev = container_of(work, struct switchtec_dev, mrpc_work);
240
241 dev_dbg(&stdev->dev, "%s\n", __func__);
242
243 mutex_lock(&stdev->mrpc_mutex);
244 cancel_delayed_work(&stdev->mrpc_timeout);
245 mrpc_complete_cmd(stdev);
246 mutex_unlock(&stdev->mrpc_mutex);
247}
248
249static void mrpc_timeout_work(struct work_struct *work)
250{
251 struct switchtec_dev *stdev;
252 u32 status;
253
254 stdev = container_of(work, struct switchtec_dev, mrpc_timeout.work);
255
256 dev_dbg(&stdev->dev, "%s\n", __func__);
257
258 mutex_lock(&stdev->mrpc_mutex);
259
260 if (stdev->dma_mrpc)
261 status = stdev->dma_mrpc->status;
262 else
263 status = ioread32(&stdev->mmio_mrpc->status);
264 if (status == SWITCHTEC_MRPC_STATUS_INPROGRESS) {
265 schedule_delayed_work(&stdev->mrpc_timeout,
266 msecs_to_jiffies(500));
267 goto out;
268 }
269
270 mrpc_complete_cmd(stdev);
271out:
272 mutex_unlock(&stdev->mrpc_mutex);
273}
274
275static ssize_t device_version_show(struct device *dev,
276 struct device_attribute *attr, char *buf)
277{
278 struct switchtec_dev *stdev = to_stdev(dev);
279 u32 ver;
280
281 ver = ioread32(&stdev->mmio_sys_info->device_version);
282
283 return sysfs_emit(buf, "%x\n", ver);
284}
285static DEVICE_ATTR_RO(device_version);
286
287static ssize_t fw_version_show(struct device *dev,
288 struct device_attribute *attr, char *buf)
289{
290 struct switchtec_dev *stdev = to_stdev(dev);
291 u32 ver;
292
293 ver = ioread32(&stdev->mmio_sys_info->firmware_version);
294
295 return sysfs_emit(buf, "%08x\n", ver);
296}
297static DEVICE_ATTR_RO(fw_version);
298
299static ssize_t io_string_show(char *buf, void __iomem *attr, size_t len)
300{
301 int i;
302
303 memcpy_fromio(buf, attr, len);
304 buf[len] = '\n';
305 buf[len + 1] = 0;
306
307 for (i = len - 1; i > 0; i--) {
308 if (buf[i] != ' ')
309 break;
310 buf[i] = '\n';
311 buf[i + 1] = 0;
312 }
313
314 return strlen(buf);
315}
316
317#define DEVICE_ATTR_SYS_INFO_STR(field) \
318static ssize_t field ## _show(struct device *dev, \
319 struct device_attribute *attr, char *buf) \
320{ \
321 struct switchtec_dev *stdev = to_stdev(dev); \
322 struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \
323 if (stdev->gen == SWITCHTEC_GEN3) \
324 return io_string_show(buf, &si->gen3.field, \
325 sizeof(si->gen3.field)); \
326 else if (stdev->gen == SWITCHTEC_GEN4) \
327 return io_string_show(buf, &si->gen4.field, \
328 sizeof(si->gen4.field)); \
329 else \
330 return -ENOTSUPP; \
331} \
332\
333static DEVICE_ATTR_RO(field)
334
335DEVICE_ATTR_SYS_INFO_STR(vendor_id);
336DEVICE_ATTR_SYS_INFO_STR(product_id);
337DEVICE_ATTR_SYS_INFO_STR(product_revision);
338
339static ssize_t component_vendor_show(struct device *dev,
340 struct device_attribute *attr, char *buf)
341{
342 struct switchtec_dev *stdev = to_stdev(dev);
343 struct sys_info_regs __iomem *si = stdev->mmio_sys_info;
344
345 /* component_vendor field not supported after gen3 */
346 if (stdev->gen != SWITCHTEC_GEN3)
347 return sysfs_emit(buf, "none\n");
348
349 return io_string_show(buf, &si->gen3.component_vendor,
350 sizeof(si->gen3.component_vendor));
351}
352static DEVICE_ATTR_RO(component_vendor);
353
354static ssize_t component_id_show(struct device *dev,
355 struct device_attribute *attr, char *buf)
356{
357 struct switchtec_dev *stdev = to_stdev(dev);
358 int id = ioread16(&stdev->mmio_sys_info->gen3.component_id);
359
360 /* component_id field not supported after gen3 */
361 if (stdev->gen != SWITCHTEC_GEN3)
362 return sysfs_emit(buf, "none\n");
363
364 return sysfs_emit(buf, "PM%04X\n", id);
365}
366static DEVICE_ATTR_RO(component_id);
367
368static ssize_t component_revision_show(struct device *dev,
369 struct device_attribute *attr, char *buf)
370{
371 struct switchtec_dev *stdev = to_stdev(dev);
372 int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision);
373
374 /* component_revision field not supported after gen3 */
375 if (stdev->gen != SWITCHTEC_GEN3)
376 return sysfs_emit(buf, "255\n");
377
378 return sysfs_emit(buf, "%d\n", rev);
379}
380static DEVICE_ATTR_RO(component_revision);
381
382static ssize_t partition_show(struct device *dev,
383 struct device_attribute *attr, char *buf)
384{
385 struct switchtec_dev *stdev = to_stdev(dev);
386
387 return sysfs_emit(buf, "%d\n", stdev->partition);
388}
389static DEVICE_ATTR_RO(partition);
390
391static ssize_t partition_count_show(struct device *dev,
392 struct device_attribute *attr, char *buf)
393{
394 struct switchtec_dev *stdev = to_stdev(dev);
395
396 return sysfs_emit(buf, "%d\n", stdev->partition_count);
397}
398static DEVICE_ATTR_RO(partition_count);
399
400static struct attribute *switchtec_device_attrs[] = {
401 &dev_attr_device_version.attr,
402 &dev_attr_fw_version.attr,
403 &dev_attr_vendor_id.attr,
404 &dev_attr_product_id.attr,
405 &dev_attr_product_revision.attr,
406 &dev_attr_component_vendor.attr,
407 &dev_attr_component_id.attr,
408 &dev_attr_component_revision.attr,
409 &dev_attr_partition.attr,
410 &dev_attr_partition_count.attr,
411 NULL,
412};
413
414ATTRIBUTE_GROUPS(switchtec_device);
415
416static int switchtec_dev_open(struct inode *inode, struct file *filp)
417{
418 struct switchtec_dev *stdev;
419 struct switchtec_user *stuser;
420
421 stdev = container_of(inode->i_cdev, struct switchtec_dev, cdev);
422
423 stuser = stuser_create(stdev);
424 if (IS_ERR(stuser))
425 return PTR_ERR(stuser);
426
427 filp->private_data = stuser;
428 stream_open(inode, filp);
429
430 dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
431
432 return 0;
433}
434
435static int switchtec_dev_release(struct inode *inode, struct file *filp)
436{
437 struct switchtec_user *stuser = filp->private_data;
438
439 stuser_put(stuser);
440
441 return 0;
442}
443
444static int lock_mutex_and_test_alive(struct switchtec_dev *stdev)
445{
446 if (mutex_lock_interruptible(&stdev->mrpc_mutex))
447 return -EINTR;
448
449 if (!stdev->alive) {
450 mutex_unlock(&stdev->mrpc_mutex);
451 return -ENODEV;
452 }
453
454 return 0;
455}
456
457static ssize_t switchtec_dev_write(struct file *filp, const char __user *data,
458 size_t size, loff_t *off)
459{
460 struct switchtec_user *stuser = filp->private_data;
461 struct switchtec_dev *stdev = stuser->stdev;
462 int rc;
463
464 if (size < sizeof(stuser->cmd) ||
465 size > sizeof(stuser->cmd) + sizeof(stuser->data))
466 return -EINVAL;
467
468 stuser->data_len = size - sizeof(stuser->cmd);
469
470 rc = lock_mutex_and_test_alive(stdev);
471 if (rc)
472 return rc;
473
474 if (stuser->state != MRPC_IDLE) {
475 rc = -EBADE;
476 goto out;
477 }
478
479 rc = copy_from_user(&stuser->cmd, data, sizeof(stuser->cmd));
480 if (rc) {
481 rc = -EFAULT;
482 goto out;
483 }
484 if (((MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_WRITE) ||
485 (MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_READ)) &&
486 !capable(CAP_SYS_ADMIN)) {
487 rc = -EPERM;
488 goto out;
489 }
490
491 data += sizeof(stuser->cmd);
492 rc = copy_from_user(&stuser->data, data, size - sizeof(stuser->cmd));
493 if (rc) {
494 rc = -EFAULT;
495 goto out;
496 }
497
498 rc = mrpc_queue_cmd(stuser);
499
500out:
501 mutex_unlock(&stdev->mrpc_mutex);
502
503 if (rc)
504 return rc;
505
506 return size;
507}
508
509static ssize_t switchtec_dev_read(struct file *filp, char __user *data,
510 size_t size, loff_t *off)
511{
512 struct switchtec_user *stuser = filp->private_data;
513 struct switchtec_dev *stdev = stuser->stdev;
514 int rc;
515
516 if (size < sizeof(stuser->cmd) ||
517 size > sizeof(stuser->cmd) + sizeof(stuser->data))
518 return -EINVAL;
519
520 rc = lock_mutex_and_test_alive(stdev);
521 if (rc)
522 return rc;
523
524 if (stuser->state == MRPC_IDLE) {
525 mutex_unlock(&stdev->mrpc_mutex);
526 return -EBADE;
527 }
528
529 stuser->read_len = size - sizeof(stuser->return_code);
530
531 mutex_unlock(&stdev->mrpc_mutex);
532
533 if (filp->f_flags & O_NONBLOCK) {
534 if (!stuser->cmd_done)
535 return -EAGAIN;
536 } else {
537 rc = wait_event_interruptible(stuser->cmd_comp,
538 stuser->cmd_done);
539 if (rc < 0)
540 return rc;
541 }
542
543 rc = lock_mutex_and_test_alive(stdev);
544 if (rc)
545 return rc;
546
547 if (stuser->state != MRPC_DONE) {
548 mutex_unlock(&stdev->mrpc_mutex);
549 return -EBADE;
550 }
551
552 rc = copy_to_user(data, &stuser->return_code,
553 sizeof(stuser->return_code));
554 if (rc) {
555 rc = -EFAULT;
556 goto out;
557 }
558
559 data += sizeof(stuser->return_code);
560 rc = copy_to_user(data, &stuser->data,
561 size - sizeof(stuser->return_code));
562 if (rc) {
563 rc = -EFAULT;
564 goto out;
565 }
566
567 stuser_set_state(stuser, MRPC_IDLE);
568
569out:
570 mutex_unlock(&stdev->mrpc_mutex);
571
572 if (stuser->status == SWITCHTEC_MRPC_STATUS_DONE)
573 return size;
574 else if (stuser->status == SWITCHTEC_MRPC_STATUS_INTERRUPTED)
575 return -ENXIO;
576 else
577 return -EBADMSG;
578}
579
580static __poll_t switchtec_dev_poll(struct file *filp, poll_table *wait)
581{
582 struct switchtec_user *stuser = filp->private_data;
583 struct switchtec_dev *stdev = stuser->stdev;
584 __poll_t ret = 0;
585
586 poll_wait(filp, &stuser->cmd_comp, wait);
587 poll_wait(filp, &stdev->event_wq, wait);
588
589 if (lock_mutex_and_test_alive(stdev))
590 return EPOLLIN | EPOLLRDHUP | EPOLLOUT | EPOLLERR | EPOLLHUP;
591
592 mutex_unlock(&stdev->mrpc_mutex);
593
594 if (stuser->cmd_done)
595 ret |= EPOLLIN | EPOLLRDNORM;
596
597 if (stuser->event_cnt != atomic_read(&stdev->event_cnt))
598 ret |= EPOLLPRI | EPOLLRDBAND;
599
600 return ret;
601}
602
603static int ioctl_flash_info(struct switchtec_dev *stdev,
604 struct switchtec_ioctl_flash_info __user *uinfo)
605{
606 struct switchtec_ioctl_flash_info info = {0};
607 struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;
608
609 if (stdev->gen == SWITCHTEC_GEN3) {
610 info.flash_length = ioread32(&fi->gen3.flash_length);
611 info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3;
612 } else if (stdev->gen == SWITCHTEC_GEN4) {
613 info.flash_length = ioread32(&fi->gen4.flash_length);
614 info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN4;
615 } else {
616 return -ENOTSUPP;
617 }
618
619 if (copy_to_user(uinfo, &info, sizeof(info)))
620 return -EFAULT;
621
622 return 0;
623}
624
625static void set_fw_info_part(struct switchtec_ioctl_flash_part_info *info,
626 struct partition_info __iomem *pi)
627{
628 info->address = ioread32(&pi->address);
629 info->length = ioread32(&pi->length);
630}
631
632static int flash_part_info_gen3(struct switchtec_dev *stdev,
633 struct switchtec_ioctl_flash_part_info *info)
634{
635 struct flash_info_regs_gen3 __iomem *fi =
636 &stdev->mmio_flash_info->gen3;
637 struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3;
638 u32 active_addr = -1;
639
640 switch (info->flash_partition) {
641 case SWITCHTEC_IOCTL_PART_CFG0:
642 active_addr = ioread32(&fi->active_cfg);
643 set_fw_info_part(info, &fi->cfg0);
644 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG0_RUNNING)
645 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
646 break;
647 case SWITCHTEC_IOCTL_PART_CFG1:
648 active_addr = ioread32(&fi->active_cfg);
649 set_fw_info_part(info, &fi->cfg1);
650 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG1_RUNNING)
651 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
652 break;
653 case SWITCHTEC_IOCTL_PART_IMG0:
654 active_addr = ioread32(&fi->active_img);
655 set_fw_info_part(info, &fi->img0);
656 if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG0_RUNNING)
657 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
658 break;
659 case SWITCHTEC_IOCTL_PART_IMG1:
660 active_addr = ioread32(&fi->active_img);
661 set_fw_info_part(info, &fi->img1);
662 if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG1_RUNNING)
663 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
664 break;
665 case SWITCHTEC_IOCTL_PART_NVLOG:
666 set_fw_info_part(info, &fi->nvlog);
667 break;
668 case SWITCHTEC_IOCTL_PART_VENDOR0:
669 set_fw_info_part(info, &fi->vendor[0]);
670 break;
671 case SWITCHTEC_IOCTL_PART_VENDOR1:
672 set_fw_info_part(info, &fi->vendor[1]);
673 break;
674 case SWITCHTEC_IOCTL_PART_VENDOR2:
675 set_fw_info_part(info, &fi->vendor[2]);
676 break;
677 case SWITCHTEC_IOCTL_PART_VENDOR3:
678 set_fw_info_part(info, &fi->vendor[3]);
679 break;
680 case SWITCHTEC_IOCTL_PART_VENDOR4:
681 set_fw_info_part(info, &fi->vendor[4]);
682 break;
683 case SWITCHTEC_IOCTL_PART_VENDOR5:
684 set_fw_info_part(info, &fi->vendor[5]);
685 break;
686 case SWITCHTEC_IOCTL_PART_VENDOR6:
687 set_fw_info_part(info, &fi->vendor[6]);
688 break;
689 case SWITCHTEC_IOCTL_PART_VENDOR7:
690 set_fw_info_part(info, &fi->vendor[7]);
691 break;
692 default:
693 return -EINVAL;
694 }
695
696 if (info->address == active_addr)
697 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
698
699 return 0;
700}
701
702static int flash_part_info_gen4(struct switchtec_dev *stdev,
703 struct switchtec_ioctl_flash_part_info *info)
704{
705 struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4;
706 struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4;
707 struct active_partition_info_gen4 __iomem *af = &fi->active_flag;
708
709 switch (info->flash_partition) {
710 case SWITCHTEC_IOCTL_PART_MAP_0:
711 set_fw_info_part(info, &fi->map0);
712 break;
713 case SWITCHTEC_IOCTL_PART_MAP_1:
714 set_fw_info_part(info, &fi->map1);
715 break;
716 case SWITCHTEC_IOCTL_PART_KEY_0:
717 set_fw_info_part(info, &fi->key0);
718 if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY0_ACTIVE)
719 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
720 if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY0_RUNNING)
721 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
722 break;
723 case SWITCHTEC_IOCTL_PART_KEY_1:
724 set_fw_info_part(info, &fi->key1);
725 if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY1_ACTIVE)
726 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
727 if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY1_RUNNING)
728 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
729 break;
730 case SWITCHTEC_IOCTL_PART_BL2_0:
731 set_fw_info_part(info, &fi->bl2_0);
732 if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_0_ACTIVE)
733 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
734 if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_0_RUNNING)
735 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
736 break;
737 case SWITCHTEC_IOCTL_PART_BL2_1:
738 set_fw_info_part(info, &fi->bl2_1);
739 if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_1_ACTIVE)
740 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
741 if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_1_RUNNING)
742 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
743 break;
744 case SWITCHTEC_IOCTL_PART_CFG0:
745 set_fw_info_part(info, &fi->cfg0);
746 if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG0_ACTIVE)
747 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
748 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG0_RUNNING)
749 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
750 break;
751 case SWITCHTEC_IOCTL_PART_CFG1:
752 set_fw_info_part(info, &fi->cfg1);
753 if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG1_ACTIVE)
754 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
755 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG1_RUNNING)
756 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
757 break;
758 case SWITCHTEC_IOCTL_PART_IMG0:
759 set_fw_info_part(info, &fi->img0);
760 if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG0_ACTIVE)
761 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
762 if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG0_RUNNING)
763 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
764 break;
765 case SWITCHTEC_IOCTL_PART_IMG1:
766 set_fw_info_part(info, &fi->img1);
767 if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG1_ACTIVE)
768 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
769 if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG1_RUNNING)
770 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
771 break;
772 case SWITCHTEC_IOCTL_PART_NVLOG:
773 set_fw_info_part(info, &fi->nvlog);
774 break;
775 case SWITCHTEC_IOCTL_PART_VENDOR0:
776 set_fw_info_part(info, &fi->vendor[0]);
777 break;
778 case SWITCHTEC_IOCTL_PART_VENDOR1:
779 set_fw_info_part(info, &fi->vendor[1]);
780 break;
781 case SWITCHTEC_IOCTL_PART_VENDOR2:
782 set_fw_info_part(info, &fi->vendor[2]);
783 break;
784 case SWITCHTEC_IOCTL_PART_VENDOR3:
785 set_fw_info_part(info, &fi->vendor[3]);
786 break;
787 case SWITCHTEC_IOCTL_PART_VENDOR4:
788 set_fw_info_part(info, &fi->vendor[4]);
789 break;
790 case SWITCHTEC_IOCTL_PART_VENDOR5:
791 set_fw_info_part(info, &fi->vendor[5]);
792 break;
793 case SWITCHTEC_IOCTL_PART_VENDOR6:
794 set_fw_info_part(info, &fi->vendor[6]);
795 break;
796 case SWITCHTEC_IOCTL_PART_VENDOR7:
797 set_fw_info_part(info, &fi->vendor[7]);
798 break;
799 default:
800 return -EINVAL;
801 }
802
803 return 0;
804}
805
806static int ioctl_flash_part_info(struct switchtec_dev *stdev,
807 struct switchtec_ioctl_flash_part_info __user *uinfo)
808{
809 int ret;
810 struct switchtec_ioctl_flash_part_info info = {0};
811
812 if (copy_from_user(&info, uinfo, sizeof(info)))
813 return -EFAULT;
814
815 if (stdev->gen == SWITCHTEC_GEN3) {
816 ret = flash_part_info_gen3(stdev, &info);
817 if (ret)
818 return ret;
819 } else if (stdev->gen == SWITCHTEC_GEN4) {
820 ret = flash_part_info_gen4(stdev, &info);
821 if (ret)
822 return ret;
823 } else {
824 return -ENOTSUPP;
825 }
826
827 if (copy_to_user(uinfo, &info, sizeof(info)))
828 return -EFAULT;
829
830 return 0;
831}
832
833static int ioctl_event_summary(struct switchtec_dev *stdev,
834 struct switchtec_user *stuser,
835 struct switchtec_ioctl_event_summary __user *usum,
836 size_t size)
837{
838 struct switchtec_ioctl_event_summary *s;
839 int i;
840 u32 reg;
841 int ret = 0;
842
843 s = kzalloc(sizeof(*s), GFP_KERNEL);
844 if (!s)
845 return -ENOMEM;
846
847 s->global = ioread32(&stdev->mmio_sw_event->global_summary);
848 s->part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap);
849 s->local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary);
850
851 for (i = 0; i < stdev->partition_count; i++) {
852 reg = ioread32(&stdev->mmio_part_cfg_all[i].part_event_summary);
853 s->part[i] = reg;
854 }
855
856 for (i = 0; i < stdev->pff_csr_count; i++) {
857 reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary);
858 s->pff[i] = reg;
859 }
860
861 if (copy_to_user(usum, s, size)) {
862 ret = -EFAULT;
863 goto error_case;
864 }
865
866 stuser->event_cnt = atomic_read(&stdev->event_cnt);
867
868error_case:
869 kfree(s);
870 return ret;
871}
872
873static u32 __iomem *global_ev_reg(struct switchtec_dev *stdev,
874 size_t offset, int index)
875{
876 return (void __iomem *)stdev->mmio_sw_event + offset;
877}
878
879static u32 __iomem *part_ev_reg(struct switchtec_dev *stdev,
880 size_t offset, int index)
881{
882 return (void __iomem *)&stdev->mmio_part_cfg_all[index] + offset;
883}
884
885static u32 __iomem *pff_ev_reg(struct switchtec_dev *stdev,
886 size_t offset, int index)
887{
888 return (void __iomem *)&stdev->mmio_pff_csr[index] + offset;
889}
890
891#define EV_GLB(i, r)[i] = {offsetof(struct sw_event_regs, r), global_ev_reg}
892#define EV_PAR(i, r)[i] = {offsetof(struct part_cfg_regs, r), part_ev_reg}
893#define EV_PFF(i, r)[i] = {offsetof(struct pff_csr_regs, r), pff_ev_reg}
894
895static const struct event_reg {
896 size_t offset;
897 u32 __iomem *(*map_reg)(struct switchtec_dev *stdev,
898 size_t offset, int index);
899} event_regs[] = {
900 EV_GLB(SWITCHTEC_IOCTL_EVENT_STACK_ERROR, stack_error_event_hdr),
901 EV_GLB(SWITCHTEC_IOCTL_EVENT_PPU_ERROR, ppu_error_event_hdr),
902 EV_GLB(SWITCHTEC_IOCTL_EVENT_ISP_ERROR, isp_error_event_hdr),
903 EV_GLB(SWITCHTEC_IOCTL_EVENT_SYS_RESET, sys_reset_event_hdr),
904 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_EXC, fw_exception_hdr),
905 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NMI, fw_nmi_hdr),
906 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NON_FATAL, fw_non_fatal_hdr),
907 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_FATAL, fw_fatal_hdr),
908 EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP, twi_mrpc_comp_hdr),
909 EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP_ASYNC,
910 twi_mrpc_comp_async_hdr),
911 EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP, cli_mrpc_comp_hdr),
912 EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP_ASYNC,
913 cli_mrpc_comp_async_hdr),
914 EV_GLB(SWITCHTEC_IOCTL_EVENT_GPIO_INT, gpio_interrupt_hdr),
915 EV_GLB(SWITCHTEC_IOCTL_EVENT_GFMS, gfms_event_hdr),
916 EV_PAR(SWITCHTEC_IOCTL_EVENT_PART_RESET, part_reset_hdr),
917 EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),
918 EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),
919 EV_PAR(SWITCHTEC_IOCTL_EVENT_DYN_PART_BIND_COMP, dyn_binding_hdr),
920 EV_PAR(SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY,
921 intercomm_notify_hdr),
922 EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_P2P, aer_in_p2p_hdr),
923 EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_VEP, aer_in_vep_hdr),
924 EV_PFF(SWITCHTEC_IOCTL_EVENT_DPC, dpc_hdr),
925 EV_PFF(SWITCHTEC_IOCTL_EVENT_CTS, cts_hdr),
926 EV_PFF(SWITCHTEC_IOCTL_EVENT_UEC, uec_hdr),
927 EV_PFF(SWITCHTEC_IOCTL_EVENT_HOTPLUG, hotplug_hdr),
928 EV_PFF(SWITCHTEC_IOCTL_EVENT_IER, ier_hdr),
929 EV_PFF(SWITCHTEC_IOCTL_EVENT_THRESH, threshold_hdr),
930 EV_PFF(SWITCHTEC_IOCTL_EVENT_POWER_MGMT, power_mgmt_hdr),
931 EV_PFF(SWITCHTEC_IOCTL_EVENT_TLP_THROTTLING, tlp_throttling_hdr),
932 EV_PFF(SWITCHTEC_IOCTL_EVENT_FORCE_SPEED, force_speed_hdr),
933 EV_PFF(SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT, credit_timeout_hdr),
934 EV_PFF(SWITCHTEC_IOCTL_EVENT_LINK_STATE, link_state_hdr),
935};
936
937static u32 __iomem *event_hdr_addr(struct switchtec_dev *stdev,
938 int event_id, int index)
939{
940 size_t off;
941
942 if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
943 return (u32 __iomem *)ERR_PTR(-EINVAL);
944
945 off = event_regs[event_id].offset;
946
947 if (event_regs[event_id].map_reg == part_ev_reg) {
948 if (index == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
949 index = stdev->partition;
950 else if (index < 0 || index >= stdev->partition_count)
951 return (u32 __iomem *)ERR_PTR(-EINVAL);
952 } else if (event_regs[event_id].map_reg == pff_ev_reg) {
953 if (index < 0 || index >= stdev->pff_csr_count)
954 return (u32 __iomem *)ERR_PTR(-EINVAL);
955 }
956
957 return event_regs[event_id].map_reg(stdev, off, index);
958}
959
960static int event_ctl(struct switchtec_dev *stdev,
961 struct switchtec_ioctl_event_ctl *ctl)
962{
963 int i;
964 u32 __iomem *reg;
965 u32 hdr;
966
967 reg = event_hdr_addr(stdev, ctl->event_id, ctl->index);
968 if (IS_ERR(reg))
969 return PTR_ERR(reg);
970
971 hdr = ioread32(reg);
972 for (i = 0; i < ARRAY_SIZE(ctl->data); i++)
973 ctl->data[i] = ioread32(®[i + 1]);
974
975 ctl->occurred = hdr & SWITCHTEC_EVENT_OCCURRED;
976 ctl->count = (hdr >> 5) & 0xFF;
977
978 if (!(ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_CLEAR))
979 hdr &= ~SWITCHTEC_EVENT_CLEAR;
980 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL)
981 hdr |= SWITCHTEC_EVENT_EN_IRQ;
982 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_POLL)
983 hdr &= ~SWITCHTEC_EVENT_EN_IRQ;
984 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG)
985 hdr |= SWITCHTEC_EVENT_EN_LOG;
986 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_LOG)
987 hdr &= ~SWITCHTEC_EVENT_EN_LOG;
988 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI)
989 hdr |= SWITCHTEC_EVENT_EN_CLI;
990 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_CLI)
991 hdr &= ~SWITCHTEC_EVENT_EN_CLI;
992 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL)
993 hdr |= SWITCHTEC_EVENT_FATAL;
994 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_FATAL)
995 hdr &= ~SWITCHTEC_EVENT_FATAL;
996
997 if (ctl->flags)
998 iowrite32(hdr, reg);
999
1000 ctl->flags = 0;
1001 if (hdr & SWITCHTEC_EVENT_EN_IRQ)
1002 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL;
1003 if (hdr & SWITCHTEC_EVENT_EN_LOG)
1004 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG;
1005 if (hdr & SWITCHTEC_EVENT_EN_CLI)
1006 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI;
1007 if (hdr & SWITCHTEC_EVENT_FATAL)
1008 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL;
1009
1010 return 0;
1011}
1012
1013static int ioctl_event_ctl(struct switchtec_dev *stdev,
1014 struct switchtec_ioctl_event_ctl __user *uctl)
1015{
1016 int ret;
1017 int nr_idxs;
1018 unsigned int event_flags;
1019 struct switchtec_ioctl_event_ctl ctl;
1020
1021 if (copy_from_user(&ctl, uctl, sizeof(ctl)))
1022 return -EFAULT;
1023
1024 if (ctl.event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
1025 return -EINVAL;
1026
1027 if (ctl.flags & SWITCHTEC_IOCTL_EVENT_FLAG_UNUSED)
1028 return -EINVAL;
1029
1030 if (ctl.index == SWITCHTEC_IOCTL_EVENT_IDX_ALL) {
1031 if (event_regs[ctl.event_id].map_reg == global_ev_reg)
1032 nr_idxs = 1;
1033 else if (event_regs[ctl.event_id].map_reg == part_ev_reg)
1034 nr_idxs = stdev->partition_count;
1035 else if (event_regs[ctl.event_id].map_reg == pff_ev_reg)
1036 nr_idxs = stdev->pff_csr_count;
1037 else
1038 return -EINVAL;
1039
1040 event_flags = ctl.flags;
1041 for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) {
1042 ctl.flags = event_flags;
1043 ret = event_ctl(stdev, &ctl);
1044 if (ret < 0)
1045 return ret;
1046 }
1047 } else {
1048 ret = event_ctl(stdev, &ctl);
1049 if (ret < 0)
1050 return ret;
1051 }
1052
1053 if (copy_to_user(uctl, &ctl, sizeof(ctl)))
1054 return -EFAULT;
1055
1056 return 0;
1057}
1058
1059static int ioctl_pff_to_port(struct switchtec_dev *stdev,
1060 struct switchtec_ioctl_pff_port __user *up)
1061{
1062 int i, part;
1063 u32 reg;
1064 struct part_cfg_regs __iomem *pcfg;
1065 struct switchtec_ioctl_pff_port p;
1066
1067 if (copy_from_user(&p, up, sizeof(p)))
1068 return -EFAULT;
1069
1070 p.port = -1;
1071 for (part = 0; part < stdev->partition_count; part++) {
1072 pcfg = &stdev->mmio_part_cfg_all[part];
1073 p.partition = part;
1074
1075 reg = ioread32(&pcfg->usp_pff_inst_id);
1076 if (reg == p.pff) {
1077 p.port = 0;
1078 break;
1079 }
1080
1081 reg = ioread32(&pcfg->vep_pff_inst_id);
1082 if (reg == p.pff) {
1083 p.port = SWITCHTEC_IOCTL_PFF_VEP;
1084 break;
1085 }
1086
1087 for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1088 reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1089 if (reg != p.pff)
1090 continue;
1091
1092 p.port = i + 1;
1093 break;
1094 }
1095
1096 if (p.port != -1)
1097 break;
1098 }
1099
1100 if (copy_to_user(up, &p, sizeof(p)))
1101 return -EFAULT;
1102
1103 return 0;
1104}
1105
1106static int ioctl_port_to_pff(struct switchtec_dev *stdev,
1107 struct switchtec_ioctl_pff_port __user *up)
1108{
1109 struct switchtec_ioctl_pff_port p;
1110 struct part_cfg_regs __iomem *pcfg;
1111
1112 if (copy_from_user(&p, up, sizeof(p)))
1113 return -EFAULT;
1114
1115 if (p.partition == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
1116 pcfg = stdev->mmio_part_cfg;
1117 else if (p.partition < stdev->partition_count)
1118 pcfg = &stdev->mmio_part_cfg_all[p.partition];
1119 else
1120 return -EINVAL;
1121
1122 switch (p.port) {
1123 case 0:
1124 p.pff = ioread32(&pcfg->usp_pff_inst_id);
1125 break;
1126 case SWITCHTEC_IOCTL_PFF_VEP:
1127 p.pff = ioread32(&pcfg->vep_pff_inst_id);
1128 break;
1129 default:
1130 if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id))
1131 return -EINVAL;
1132 p.port = array_index_nospec(p.port,
1133 ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1);
1134 p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]);
1135 break;
1136 }
1137
1138 if (copy_to_user(up, &p, sizeof(p)))
1139 return -EFAULT;
1140
1141 return 0;
1142}
1143
1144static long switchtec_dev_ioctl(struct file *filp, unsigned int cmd,
1145 unsigned long arg)
1146{
1147 struct switchtec_user *stuser = filp->private_data;
1148 struct switchtec_dev *stdev = stuser->stdev;
1149 int rc;
1150 void __user *argp = (void __user *)arg;
1151
1152 rc = lock_mutex_and_test_alive(stdev);
1153 if (rc)
1154 return rc;
1155
1156 switch (cmd) {
1157 case SWITCHTEC_IOCTL_FLASH_INFO:
1158 rc = ioctl_flash_info(stdev, argp);
1159 break;
1160 case SWITCHTEC_IOCTL_FLASH_PART_INFO:
1161 rc = ioctl_flash_part_info(stdev, argp);
1162 break;
1163 case SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY:
1164 rc = ioctl_event_summary(stdev, stuser, argp,
1165 sizeof(struct switchtec_ioctl_event_summary_legacy));
1166 break;
1167 case SWITCHTEC_IOCTL_EVENT_CTL:
1168 rc = ioctl_event_ctl(stdev, argp);
1169 break;
1170 case SWITCHTEC_IOCTL_PFF_TO_PORT:
1171 rc = ioctl_pff_to_port(stdev, argp);
1172 break;
1173 case SWITCHTEC_IOCTL_PORT_TO_PFF:
1174 rc = ioctl_port_to_pff(stdev, argp);
1175 break;
1176 case SWITCHTEC_IOCTL_EVENT_SUMMARY:
1177 rc = ioctl_event_summary(stdev, stuser, argp,
1178 sizeof(struct switchtec_ioctl_event_summary));
1179 break;
1180 default:
1181 rc = -ENOTTY;
1182 break;
1183 }
1184
1185 mutex_unlock(&stdev->mrpc_mutex);
1186 return rc;
1187}
1188
1189static const struct file_operations switchtec_fops = {
1190 .owner = THIS_MODULE,
1191 .open = switchtec_dev_open,
1192 .release = switchtec_dev_release,
1193 .write = switchtec_dev_write,
1194 .read = switchtec_dev_read,
1195 .poll = switchtec_dev_poll,
1196 .unlocked_ioctl = switchtec_dev_ioctl,
1197 .compat_ioctl = compat_ptr_ioctl,
1198};
1199
1200static void link_event_work(struct work_struct *work)
1201{
1202 struct switchtec_dev *stdev;
1203
1204 stdev = container_of(work, struct switchtec_dev, link_event_work);
1205
1206 if (stdev->link_notifier)
1207 stdev->link_notifier(stdev);
1208}
1209
1210static void check_link_state_events(struct switchtec_dev *stdev)
1211{
1212 int idx;
1213 u32 reg;
1214 int count;
1215 int occurred = 0;
1216
1217 for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1218 reg = ioread32(&stdev->mmio_pff_csr[idx].link_state_hdr);
1219 dev_dbg(&stdev->dev, "link_state: %d->%08x\n", idx, reg);
1220 count = (reg >> 5) & 0xFF;
1221
1222 if (count != stdev->link_event_count[idx]) {
1223 occurred = 1;
1224 stdev->link_event_count[idx] = count;
1225 }
1226 }
1227
1228 if (occurred)
1229 schedule_work(&stdev->link_event_work);
1230}
1231
1232static void enable_link_state_events(struct switchtec_dev *stdev)
1233{
1234 int idx;
1235
1236 for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1237 iowrite32(SWITCHTEC_EVENT_CLEAR |
1238 SWITCHTEC_EVENT_EN_IRQ,
1239 &stdev->mmio_pff_csr[idx].link_state_hdr);
1240 }
1241}
1242
1243static void enable_dma_mrpc(struct switchtec_dev *stdev)
1244{
1245 writeq(stdev->dma_mrpc_dma_addr, &stdev->mmio_mrpc->dma_addr);
1246 flush_wc_buf(stdev);
1247 iowrite32(SWITCHTEC_DMA_MRPC_EN, &stdev->mmio_mrpc->dma_en);
1248}
1249
1250static void stdev_release(struct device *dev)
1251{
1252 struct switchtec_dev *stdev = to_stdev(dev);
1253
1254 if (stdev->dma_mrpc) {
1255 iowrite32(0, &stdev->mmio_mrpc->dma_en);
1256 flush_wc_buf(stdev);
1257 writeq(0, &stdev->mmio_mrpc->dma_addr);
1258 dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc),
1259 stdev->dma_mrpc, stdev->dma_mrpc_dma_addr);
1260 }
1261 kfree(stdev);
1262}
1263
1264static void stdev_kill(struct switchtec_dev *stdev)
1265{
1266 struct switchtec_user *stuser, *tmpuser;
1267
1268 pci_clear_master(stdev->pdev);
1269
1270 cancel_delayed_work_sync(&stdev->mrpc_timeout);
1271
1272 /* Mark the hardware as unavailable and complete all completions */
1273 mutex_lock(&stdev->mrpc_mutex);
1274 stdev->alive = false;
1275
1276 /* Wake up and kill any users waiting on an MRPC request */
1277 list_for_each_entry_safe(stuser, tmpuser, &stdev->mrpc_queue, list) {
1278 stuser->cmd_done = true;
1279 wake_up_interruptible(&stuser->cmd_comp);
1280 list_del_init(&stuser->list);
1281 stuser_put(stuser);
1282 }
1283
1284 mutex_unlock(&stdev->mrpc_mutex);
1285
1286 /* Wake up any users waiting on event_wq */
1287 wake_up_interruptible(&stdev->event_wq);
1288}
1289
1290static struct switchtec_dev *stdev_create(struct pci_dev *pdev)
1291{
1292 struct switchtec_dev *stdev;
1293 int minor;
1294 struct device *dev;
1295 struct cdev *cdev;
1296 int rc;
1297
1298 stdev = kzalloc_node(sizeof(*stdev), GFP_KERNEL,
1299 dev_to_node(&pdev->dev));
1300 if (!stdev)
1301 return ERR_PTR(-ENOMEM);
1302
1303 stdev->alive = true;
1304 stdev->pdev = pdev;
1305 INIT_LIST_HEAD(&stdev->mrpc_queue);
1306 mutex_init(&stdev->mrpc_mutex);
1307 stdev->mrpc_busy = 0;
1308 INIT_WORK(&stdev->mrpc_work, mrpc_event_work);
1309 INIT_DELAYED_WORK(&stdev->mrpc_timeout, mrpc_timeout_work);
1310 INIT_WORK(&stdev->link_event_work, link_event_work);
1311 init_waitqueue_head(&stdev->event_wq);
1312 atomic_set(&stdev->event_cnt, 0);
1313
1314 dev = &stdev->dev;
1315 device_initialize(dev);
1316 dev->class = switchtec_class;
1317 dev->parent = &pdev->dev;
1318 dev->groups = switchtec_device_groups;
1319 dev->release = stdev_release;
1320
1321 minor = ida_simple_get(&switchtec_minor_ida, 0, 0,
1322 GFP_KERNEL);
1323 if (minor < 0) {
1324 rc = minor;
1325 goto err_put;
1326 }
1327
1328 dev->devt = MKDEV(MAJOR(switchtec_devt), minor);
1329 dev_set_name(dev, "switchtec%d", minor);
1330
1331 cdev = &stdev->cdev;
1332 cdev_init(cdev, &switchtec_fops);
1333 cdev->owner = THIS_MODULE;
1334
1335 return stdev;
1336
1337err_put:
1338 put_device(&stdev->dev);
1339 return ERR_PTR(rc);
1340}
1341
1342static int mask_event(struct switchtec_dev *stdev, int eid, int idx)
1343{
1344 size_t off = event_regs[eid].offset;
1345 u32 __iomem *hdr_reg;
1346 u32 hdr;
1347
1348 hdr_reg = event_regs[eid].map_reg(stdev, off, idx);
1349 hdr = ioread32(hdr_reg);
1350
1351 if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ))
1352 return 0;
1353
1354 dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr);
1355 hdr &= ~(SWITCHTEC_EVENT_EN_IRQ | SWITCHTEC_EVENT_OCCURRED);
1356 iowrite32(hdr, hdr_reg);
1357
1358 return 1;
1359}
1360
1361static int mask_all_events(struct switchtec_dev *stdev, int eid)
1362{
1363 int idx;
1364 int count = 0;
1365
1366 if (event_regs[eid].map_reg == part_ev_reg) {
1367 for (idx = 0; idx < stdev->partition_count; idx++)
1368 count += mask_event(stdev, eid, idx);
1369 } else if (event_regs[eid].map_reg == pff_ev_reg) {
1370 for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1371 if (!stdev->pff_local[idx])
1372 continue;
1373
1374 count += mask_event(stdev, eid, idx);
1375 }
1376 } else {
1377 count += mask_event(stdev, eid, 0);
1378 }
1379
1380 return count;
1381}
1382
1383static irqreturn_t switchtec_event_isr(int irq, void *dev)
1384{
1385 struct switchtec_dev *stdev = dev;
1386 u32 reg;
1387 irqreturn_t ret = IRQ_NONE;
1388 int eid, event_count = 0;
1389
1390 reg = ioread32(&stdev->mmio_part_cfg->mrpc_comp_hdr);
1391 if (reg & SWITCHTEC_EVENT_OCCURRED) {
1392 dev_dbg(&stdev->dev, "%s: mrpc comp\n", __func__);
1393 ret = IRQ_HANDLED;
1394 schedule_work(&stdev->mrpc_work);
1395 iowrite32(reg, &stdev->mmio_part_cfg->mrpc_comp_hdr);
1396 }
1397
1398 check_link_state_events(stdev);
1399
1400 for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {
1401 if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE ||
1402 eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)
1403 continue;
1404
1405 event_count += mask_all_events(stdev, eid);
1406 }
1407
1408 if (event_count) {
1409 atomic_inc(&stdev->event_cnt);
1410 wake_up_interruptible(&stdev->event_wq);
1411 dev_dbg(&stdev->dev, "%s: %d events\n", __func__,
1412 event_count);
1413 return IRQ_HANDLED;
1414 }
1415
1416 return ret;
1417}
1418
1419
1420static irqreturn_t switchtec_dma_mrpc_isr(int irq, void *dev)
1421{
1422 struct switchtec_dev *stdev = dev;
1423 irqreturn_t ret = IRQ_NONE;
1424
1425 iowrite32(SWITCHTEC_EVENT_CLEAR |
1426 SWITCHTEC_EVENT_EN_IRQ,
1427 &stdev->mmio_part_cfg->mrpc_comp_hdr);
1428 schedule_work(&stdev->mrpc_work);
1429
1430 ret = IRQ_HANDLED;
1431 return ret;
1432}
1433
1434static int switchtec_init_isr(struct switchtec_dev *stdev)
1435{
1436 int nvecs;
1437 int event_irq;
1438 int dma_mrpc_irq;
1439 int rc;
1440
1441 if (nirqs < 4)
1442 nirqs = 4;
1443
1444 nvecs = pci_alloc_irq_vectors(stdev->pdev, 1, nirqs,
1445 PCI_IRQ_MSIX | PCI_IRQ_MSI |
1446 PCI_IRQ_VIRTUAL);
1447 if (nvecs < 0)
1448 return nvecs;
1449
1450 event_irq = ioread16(&stdev->mmio_part_cfg->vep_vector_number);
1451 if (event_irq < 0 || event_irq >= nvecs)
1452 return -EFAULT;
1453
1454 event_irq = pci_irq_vector(stdev->pdev, event_irq);
1455 if (event_irq < 0)
1456 return event_irq;
1457
1458 rc = devm_request_irq(&stdev->pdev->dev, event_irq,
1459 switchtec_event_isr, 0,
1460 KBUILD_MODNAME, stdev);
1461
1462 if (rc)
1463 return rc;
1464
1465 if (!stdev->dma_mrpc)
1466 return rc;
1467
1468 dma_mrpc_irq = ioread32(&stdev->mmio_mrpc->dma_vector);
1469 if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs)
1470 return -EFAULT;
1471
1472 dma_mrpc_irq = pci_irq_vector(stdev->pdev, dma_mrpc_irq);
1473 if (dma_mrpc_irq < 0)
1474 return dma_mrpc_irq;
1475
1476 rc = devm_request_irq(&stdev->pdev->dev, dma_mrpc_irq,
1477 switchtec_dma_mrpc_isr, 0,
1478 KBUILD_MODNAME, stdev);
1479
1480 return rc;
1481}
1482
1483static void init_pff(struct switchtec_dev *stdev)
1484{
1485 int i;
1486 u32 reg;
1487 struct part_cfg_regs __iomem *pcfg = stdev->mmio_part_cfg;
1488
1489 for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
1490 reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
1491 if (reg != PCI_VENDOR_ID_MICROSEMI)
1492 break;
1493 }
1494
1495 stdev->pff_csr_count = i;
1496
1497 reg = ioread32(&pcfg->usp_pff_inst_id);
1498 if (reg < stdev->pff_csr_count)
1499 stdev->pff_local[reg] = 1;
1500
1501 reg = ioread32(&pcfg->vep_pff_inst_id);
1502 if (reg < stdev->pff_csr_count)
1503 stdev->pff_local[reg] = 1;
1504
1505 for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1506 reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1507 if (reg < stdev->pff_csr_count)
1508 stdev->pff_local[reg] = 1;
1509 }
1510}
1511
1512static int switchtec_init_pci(struct switchtec_dev *stdev,
1513 struct pci_dev *pdev)
1514{
1515 int rc;
1516 void __iomem *map;
1517 unsigned long res_start, res_len;
1518 u32 __iomem *part_id;
1519
1520 rc = pcim_enable_device(pdev);
1521 if (rc)
1522 return rc;
1523
1524 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1525 if (rc)
1526 return rc;
1527
1528 pci_set_master(pdev);
1529
1530 res_start = pci_resource_start(pdev, 0);
1531 res_len = pci_resource_len(pdev, 0);
1532
1533 if (!devm_request_mem_region(&pdev->dev, res_start,
1534 res_len, KBUILD_MODNAME))
1535 return -EBUSY;
1536
1537 stdev->mmio_mrpc = devm_ioremap_wc(&pdev->dev, res_start,
1538 SWITCHTEC_GAS_TOP_CFG_OFFSET);
1539 if (!stdev->mmio_mrpc)
1540 return -ENOMEM;
1541
1542 map = devm_ioremap(&pdev->dev,
1543 res_start + SWITCHTEC_GAS_TOP_CFG_OFFSET,
1544 res_len - SWITCHTEC_GAS_TOP_CFG_OFFSET);
1545 if (!map)
1546 return -ENOMEM;
1547
1548 stdev->mmio = map - SWITCHTEC_GAS_TOP_CFG_OFFSET;
1549 stdev->mmio_sw_event = stdev->mmio + SWITCHTEC_GAS_SW_EVENT_OFFSET;
1550 stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
1551 stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET;
1552 stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET;
1553
1554 if (stdev->gen == SWITCHTEC_GEN3)
1555 part_id = &stdev->mmio_sys_info->gen3.partition_id;
1556 else if (stdev->gen == SWITCHTEC_GEN4)
1557 part_id = &stdev->mmio_sys_info->gen4.partition_id;
1558 else
1559 return -ENOTSUPP;
1560
1561 stdev->partition = ioread8(part_id);
1562 stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count);
1563 stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET;
1564 stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition];
1565 stdev->mmio_pff_csr = stdev->mmio + SWITCHTEC_GAS_PFF_CSR_OFFSET;
1566
1567 if (stdev->partition_count < 1)
1568 stdev->partition_count = 1;
1569
1570 init_pff(stdev);
1571
1572 pci_set_drvdata(pdev, stdev);
1573
1574 if (!use_dma_mrpc)
1575 return 0;
1576
1577 if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)
1578 return 0;
1579
1580 stdev->dma_mrpc = dma_alloc_coherent(&stdev->pdev->dev,
1581 sizeof(*stdev->dma_mrpc),
1582 &stdev->dma_mrpc_dma_addr,
1583 GFP_KERNEL);
1584 if (stdev->dma_mrpc == NULL)
1585 return -ENOMEM;
1586
1587 return 0;
1588}
1589
1590static int switchtec_pci_probe(struct pci_dev *pdev,
1591 const struct pci_device_id *id)
1592{
1593 struct switchtec_dev *stdev;
1594 int rc;
1595
1596 if (pdev->class == (PCI_CLASS_BRIDGE_OTHER << 8))
1597 request_module_nowait("ntb_hw_switchtec");
1598
1599 stdev = stdev_create(pdev);
1600 if (IS_ERR(stdev))
1601 return PTR_ERR(stdev);
1602
1603 stdev->gen = id->driver_data;
1604
1605 rc = switchtec_init_pci(stdev, pdev);
1606 if (rc)
1607 goto err_put;
1608
1609 rc = switchtec_init_isr(stdev);
1610 if (rc) {
1611 dev_err(&stdev->dev, "failed to init isr.\n");
1612 goto err_put;
1613 }
1614
1615 iowrite32(SWITCHTEC_EVENT_CLEAR |
1616 SWITCHTEC_EVENT_EN_IRQ,
1617 &stdev->mmio_part_cfg->mrpc_comp_hdr);
1618 enable_link_state_events(stdev);
1619
1620 if (stdev->dma_mrpc)
1621 enable_dma_mrpc(stdev);
1622
1623 rc = cdev_device_add(&stdev->cdev, &stdev->dev);
1624 if (rc)
1625 goto err_devadd;
1626
1627 dev_info(&stdev->dev, "Management device registered.\n");
1628
1629 return 0;
1630
1631err_devadd:
1632 stdev_kill(stdev);
1633err_put:
1634 ida_simple_remove(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1635 put_device(&stdev->dev);
1636 return rc;
1637}
1638
1639static void switchtec_pci_remove(struct pci_dev *pdev)
1640{
1641 struct switchtec_dev *stdev = pci_get_drvdata(pdev);
1642
1643 pci_set_drvdata(pdev, NULL);
1644
1645 cdev_device_del(&stdev->cdev, &stdev->dev);
1646 ida_simple_remove(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1647 dev_info(&stdev->dev, "unregistered.\n");
1648 stdev_kill(stdev);
1649 put_device(&stdev->dev);
1650}
1651
1652#define SWITCHTEC_PCI_DEVICE(device_id, gen) \
1653 { \
1654 .vendor = PCI_VENDOR_ID_MICROSEMI, \
1655 .device = device_id, \
1656 .subvendor = PCI_ANY_ID, \
1657 .subdevice = PCI_ANY_ID, \
1658 .class = (PCI_CLASS_MEMORY_OTHER << 8), \
1659 .class_mask = 0xFFFFFFFF, \
1660 .driver_data = gen, \
1661 }, \
1662 { \
1663 .vendor = PCI_VENDOR_ID_MICROSEMI, \
1664 .device = device_id, \
1665 .subvendor = PCI_ANY_ID, \
1666 .subdevice = PCI_ANY_ID, \
1667 .class = (PCI_CLASS_BRIDGE_OTHER << 8), \
1668 .class_mask = 0xFFFFFFFF, \
1669 .driver_data = gen, \
1670 }
1671
1672static const struct pci_device_id switchtec_pci_tbl[] = {
1673 SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3), //PFX 24xG3
1674 SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3), //PFX 32xG3
1675 SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3), //PFX 48xG3
1676 SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3), //PFX 64xG3
1677 SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3), //PFX 80xG3
1678 SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3), //PFX 96xG3
1679 SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3), //PSX 24xG3
1680 SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3), //PSX 32xG3
1681 SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3), //PSX 48xG3
1682 SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3), //PSX 64xG3
1683 SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3), //PSX 80xG3
1684 SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3), //PSX 96xG3
1685 SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3), //PAX 24XG3
1686 SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3), //PAX 32XG3
1687 SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3), //PAX 48XG3
1688 SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3), //PAX 64XG3
1689 SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3), //PAX 80XG3
1690 SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3), //PAX 96XG3
1691 SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3), //PFXL 24XG3
1692 SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3), //PFXL 32XG3
1693 SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3), //PFXL 48XG3
1694 SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3), //PFXL 64XG3
1695 SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3), //PFXL 80XG3
1696 SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3), //PFXL 96XG3
1697 SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3), //PFXI 24XG3
1698 SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3), //PFXI 32XG3
1699 SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3), //PFXI 48XG3
1700 SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3), //PFXI 64XG3
1701 SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3), //PFXI 80XG3
1702 SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3), //PFXI 96XG3
1703 SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4), //PFX 100XG4
1704 SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4), //PFX 84XG4
1705 SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4), //PFX 68XG4
1706 SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4), //PFX 52XG4
1707 SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4), //PFX 36XG4
1708 SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4), //PFX 28XG4
1709 SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4), //PSX 100XG4
1710 SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4), //PSX 84XG4
1711 SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4), //PSX 68XG4
1712 SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4), //PSX 52XG4
1713 SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4), //PSX 36XG4
1714 SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4), //PSX 28XG4
1715 SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4), //PAX 100XG4
1716 SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4), //PAX 84XG4
1717 SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4), //PAX 68XG4
1718 SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4), //PAX 52XG4
1719 SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4), //PAX 36XG4
1720 SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4), //PAX 28XG4
1721 {0}
1722};
1723MODULE_DEVICE_TABLE(pci, switchtec_pci_tbl);
1724
1725static struct pci_driver switchtec_pci_driver = {
1726 .name = KBUILD_MODNAME,
1727 .id_table = switchtec_pci_tbl,
1728 .probe = switchtec_pci_probe,
1729 .remove = switchtec_pci_remove,
1730};
1731
1732static int __init switchtec_init(void)
1733{
1734 int rc;
1735
1736 rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices,
1737 "switchtec");
1738 if (rc)
1739 return rc;
1740
1741 switchtec_class = class_create(THIS_MODULE, "switchtec");
1742 if (IS_ERR(switchtec_class)) {
1743 rc = PTR_ERR(switchtec_class);
1744 goto err_create_class;
1745 }
1746
1747 rc = pci_register_driver(&switchtec_pci_driver);
1748 if (rc)
1749 goto err_pci_register;
1750
1751 pr_info(KBUILD_MODNAME ": loaded.\n");
1752
1753 return 0;
1754
1755err_pci_register:
1756 class_destroy(switchtec_class);
1757
1758err_create_class:
1759 unregister_chrdev_region(switchtec_devt, max_devices);
1760
1761 return rc;
1762}
1763module_init(switchtec_init);
1764
1765static void __exit switchtec_exit(void)
1766{
1767 pci_unregister_driver(&switchtec_pci_driver);
1768 class_destroy(switchtec_class);
1769 unregister_chrdev_region(switchtec_devt, max_devices);
1770 ida_destroy(&switchtec_minor_ida);
1771
1772 pr_info(KBUILD_MODNAME ": unloaded.\n");
1773}
1774module_exit(switchtec_exit);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microsemi Switchtec(tm) PCIe Management Driver
4 * Copyright (c) 2017, Microsemi Corporation
5 */
6
7#include <linux/switchtec.h>
8#include <linux/switchtec_ioctl.h>
9
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/fs.h>
13#include <linux/uaccess.h>
14#include <linux/poll.h>
15#include <linux/wait.h>
16#include <linux/io-64-nonatomic-lo-hi.h>
17#include <linux/nospec.h>
18
19MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
20MODULE_VERSION("0.1");
21MODULE_LICENSE("GPL");
22MODULE_AUTHOR("Microsemi Corporation");
23
24static int max_devices = 16;
25module_param(max_devices, int, 0644);
26MODULE_PARM_DESC(max_devices, "max number of switchtec device instances");
27
28static bool use_dma_mrpc = true;
29module_param(use_dma_mrpc, bool, 0644);
30MODULE_PARM_DESC(use_dma_mrpc,
31 "Enable the use of the DMA MRPC feature");
32
33static int nirqs = 32;
34module_param(nirqs, int, 0644);
35MODULE_PARM_DESC(nirqs, "number of interrupts to allocate (more may be useful for NTB applications)");
36
37static dev_t switchtec_devt;
38static DEFINE_IDA(switchtec_minor_ida);
39
40struct class *switchtec_class;
41EXPORT_SYMBOL_GPL(switchtec_class);
42
43enum mrpc_state {
44 MRPC_IDLE = 0,
45 MRPC_QUEUED,
46 MRPC_RUNNING,
47 MRPC_DONE,
48 MRPC_IO_ERROR,
49};
50
51struct switchtec_user {
52 struct switchtec_dev *stdev;
53
54 enum mrpc_state state;
55
56 wait_queue_head_t cmd_comp;
57 struct kref kref;
58 struct list_head list;
59
60 bool cmd_done;
61 u32 cmd;
62 u32 status;
63 u32 return_code;
64 size_t data_len;
65 size_t read_len;
66 unsigned char data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
67 int event_cnt;
68};
69
70/*
71 * The MMIO reads to the device_id register should always return the device ID
72 * of the device, otherwise the firmware is probably stuck or unreachable
73 * due to a firmware reset which clears PCI state including the BARs and Memory
74 * Space Enable bits.
75 */
76static int is_firmware_running(struct switchtec_dev *stdev)
77{
78 u32 device = ioread32(&stdev->mmio_sys_info->device_id);
79
80 return stdev->pdev->device == device;
81}
82
83static struct switchtec_user *stuser_create(struct switchtec_dev *stdev)
84{
85 struct switchtec_user *stuser;
86
87 stuser = kzalloc(sizeof(*stuser), GFP_KERNEL);
88 if (!stuser)
89 return ERR_PTR(-ENOMEM);
90
91 get_device(&stdev->dev);
92 stuser->stdev = stdev;
93 kref_init(&stuser->kref);
94 INIT_LIST_HEAD(&stuser->list);
95 init_waitqueue_head(&stuser->cmd_comp);
96 stuser->event_cnt = atomic_read(&stdev->event_cnt);
97
98 dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
99
100 return stuser;
101}
102
103static void stuser_free(struct kref *kref)
104{
105 struct switchtec_user *stuser;
106
107 stuser = container_of(kref, struct switchtec_user, kref);
108
109 dev_dbg(&stuser->stdev->dev, "%s: %p\n", __func__, stuser);
110
111 put_device(&stuser->stdev->dev);
112 kfree(stuser);
113}
114
115static void stuser_put(struct switchtec_user *stuser)
116{
117 kref_put(&stuser->kref, stuser_free);
118}
119
120static void stuser_set_state(struct switchtec_user *stuser,
121 enum mrpc_state state)
122{
123 /* requires the mrpc_mutex to already be held when called */
124
125 static const char * const state_names[] = {
126 [MRPC_IDLE] = "IDLE",
127 [MRPC_QUEUED] = "QUEUED",
128 [MRPC_RUNNING] = "RUNNING",
129 [MRPC_DONE] = "DONE",
130 [MRPC_IO_ERROR] = "IO_ERROR",
131 };
132
133 stuser->state = state;
134
135 dev_dbg(&stuser->stdev->dev, "stuser state %p -> %s",
136 stuser, state_names[state]);
137}
138
139static void mrpc_complete_cmd(struct switchtec_dev *stdev);
140
141static void flush_wc_buf(struct switchtec_dev *stdev)
142{
143 struct ntb_dbmsg_regs __iomem *mmio_dbmsg;
144
145 /*
146 * odb (outbound doorbell) register is processed by low latency
147 * hardware and w/o side effect
148 */
149 mmio_dbmsg = (void __iomem *)stdev->mmio_ntb +
150 SWITCHTEC_NTB_REG_DBMSG_OFFSET;
151 ioread32(&mmio_dbmsg->odb);
152}
153
154static void mrpc_cmd_submit(struct switchtec_dev *stdev)
155{
156 /* requires the mrpc_mutex to already be held when called */
157
158 struct switchtec_user *stuser;
159
160 if (stdev->mrpc_busy)
161 return;
162
163 if (list_empty(&stdev->mrpc_queue))
164 return;
165
166 stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
167 list);
168
169 if (stdev->dma_mrpc) {
170 stdev->dma_mrpc->status = SWITCHTEC_MRPC_STATUS_INPROGRESS;
171 memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);
172 }
173
174 stuser_set_state(stuser, MRPC_RUNNING);
175 stdev->mrpc_busy = 1;
176 memcpy_toio(&stdev->mmio_mrpc->input_data,
177 stuser->data, stuser->data_len);
178 flush_wc_buf(stdev);
179 iowrite32(stuser->cmd, &stdev->mmio_mrpc->cmd);
180
181 schedule_delayed_work(&stdev->mrpc_timeout,
182 msecs_to_jiffies(500));
183}
184
185static int mrpc_queue_cmd(struct switchtec_user *stuser)
186{
187 /* requires the mrpc_mutex to already be held when called */
188
189 struct switchtec_dev *stdev = stuser->stdev;
190
191 kref_get(&stuser->kref);
192 stuser->read_len = sizeof(stuser->data);
193 stuser_set_state(stuser, MRPC_QUEUED);
194 stuser->cmd_done = false;
195 list_add_tail(&stuser->list, &stdev->mrpc_queue);
196
197 mrpc_cmd_submit(stdev);
198
199 return 0;
200}
201
202static void mrpc_cleanup_cmd(struct switchtec_dev *stdev)
203{
204 /* requires the mrpc_mutex to already be held when called */
205
206 struct switchtec_user *stuser = list_entry(stdev->mrpc_queue.next,
207 struct switchtec_user, list);
208
209 stuser->cmd_done = true;
210 wake_up_interruptible(&stuser->cmd_comp);
211 list_del_init(&stuser->list);
212 stuser_put(stuser);
213 stdev->mrpc_busy = 0;
214
215 mrpc_cmd_submit(stdev);
216}
217
218static void mrpc_complete_cmd(struct switchtec_dev *stdev)
219{
220 /* requires the mrpc_mutex to already be held when called */
221
222 struct switchtec_user *stuser;
223
224 if (list_empty(&stdev->mrpc_queue))
225 return;
226
227 stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
228 list);
229
230 if (stdev->dma_mrpc)
231 stuser->status = stdev->dma_mrpc->status;
232 else
233 stuser->status = ioread32(&stdev->mmio_mrpc->status);
234
235 if (stuser->status == SWITCHTEC_MRPC_STATUS_INPROGRESS)
236 return;
237
238 stuser_set_state(stuser, MRPC_DONE);
239 stuser->return_code = 0;
240
241 if (stuser->status != SWITCHTEC_MRPC_STATUS_DONE &&
242 stuser->status != SWITCHTEC_MRPC_STATUS_ERROR)
243 goto out;
244
245 if (stdev->dma_mrpc)
246 stuser->return_code = stdev->dma_mrpc->rtn_code;
247 else
248 stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value);
249 if (stuser->return_code != 0)
250 goto out;
251
252 if (stdev->dma_mrpc)
253 memcpy(stuser->data, &stdev->dma_mrpc->data,
254 stuser->read_len);
255 else
256 memcpy_fromio(stuser->data, &stdev->mmio_mrpc->output_data,
257 stuser->read_len);
258out:
259 mrpc_cleanup_cmd(stdev);
260}
261
262static void mrpc_event_work(struct work_struct *work)
263{
264 struct switchtec_dev *stdev;
265
266 stdev = container_of(work, struct switchtec_dev, mrpc_work);
267
268 dev_dbg(&stdev->dev, "%s\n", __func__);
269
270 mutex_lock(&stdev->mrpc_mutex);
271 cancel_delayed_work(&stdev->mrpc_timeout);
272 mrpc_complete_cmd(stdev);
273 mutex_unlock(&stdev->mrpc_mutex);
274}
275
276static void mrpc_error_complete_cmd(struct switchtec_dev *stdev)
277{
278 /* requires the mrpc_mutex to already be held when called */
279
280 struct switchtec_user *stuser;
281
282 if (list_empty(&stdev->mrpc_queue))
283 return;
284
285 stuser = list_entry(stdev->mrpc_queue.next,
286 struct switchtec_user, list);
287
288 stuser_set_state(stuser, MRPC_IO_ERROR);
289
290 mrpc_cleanup_cmd(stdev);
291}
292
293static void mrpc_timeout_work(struct work_struct *work)
294{
295 struct switchtec_dev *stdev;
296 u32 status;
297
298 stdev = container_of(work, struct switchtec_dev, mrpc_timeout.work);
299
300 dev_dbg(&stdev->dev, "%s\n", __func__);
301
302 mutex_lock(&stdev->mrpc_mutex);
303
304 if (!is_firmware_running(stdev)) {
305 mrpc_error_complete_cmd(stdev);
306 goto out;
307 }
308
309 if (stdev->dma_mrpc)
310 status = stdev->dma_mrpc->status;
311 else
312 status = ioread32(&stdev->mmio_mrpc->status);
313 if (status == SWITCHTEC_MRPC_STATUS_INPROGRESS) {
314 schedule_delayed_work(&stdev->mrpc_timeout,
315 msecs_to_jiffies(500));
316 goto out;
317 }
318
319 mrpc_complete_cmd(stdev);
320out:
321 mutex_unlock(&stdev->mrpc_mutex);
322}
323
324static ssize_t device_version_show(struct device *dev,
325 struct device_attribute *attr, char *buf)
326{
327 struct switchtec_dev *stdev = to_stdev(dev);
328 u32 ver;
329
330 ver = ioread32(&stdev->mmio_sys_info->device_version);
331
332 return sysfs_emit(buf, "%x\n", ver);
333}
334static DEVICE_ATTR_RO(device_version);
335
336static ssize_t fw_version_show(struct device *dev,
337 struct device_attribute *attr, char *buf)
338{
339 struct switchtec_dev *stdev = to_stdev(dev);
340 u32 ver;
341
342 ver = ioread32(&stdev->mmio_sys_info->firmware_version);
343
344 return sysfs_emit(buf, "%08x\n", ver);
345}
346static DEVICE_ATTR_RO(fw_version);
347
348static ssize_t io_string_show(char *buf, void __iomem *attr, size_t len)
349{
350 int i;
351
352 memcpy_fromio(buf, attr, len);
353 buf[len] = '\n';
354 buf[len + 1] = 0;
355
356 for (i = len - 1; i > 0; i--) {
357 if (buf[i] != ' ')
358 break;
359 buf[i] = '\n';
360 buf[i + 1] = 0;
361 }
362
363 return strlen(buf);
364}
365
366#define DEVICE_ATTR_SYS_INFO_STR(field) \
367static ssize_t field ## _show(struct device *dev, \
368 struct device_attribute *attr, char *buf) \
369{ \
370 struct switchtec_dev *stdev = to_stdev(dev); \
371 struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \
372 if (stdev->gen == SWITCHTEC_GEN3) \
373 return io_string_show(buf, &si->gen3.field, \
374 sizeof(si->gen3.field)); \
375 else if (stdev->gen == SWITCHTEC_GEN4) \
376 return io_string_show(buf, &si->gen4.field, \
377 sizeof(si->gen4.field)); \
378 else \
379 return -EOPNOTSUPP; \
380} \
381\
382static DEVICE_ATTR_RO(field)
383
384DEVICE_ATTR_SYS_INFO_STR(vendor_id);
385DEVICE_ATTR_SYS_INFO_STR(product_id);
386DEVICE_ATTR_SYS_INFO_STR(product_revision);
387
388static ssize_t component_vendor_show(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 struct switchtec_dev *stdev = to_stdev(dev);
392 struct sys_info_regs __iomem *si = stdev->mmio_sys_info;
393
394 /* component_vendor field not supported after gen3 */
395 if (stdev->gen != SWITCHTEC_GEN3)
396 return sysfs_emit(buf, "none\n");
397
398 return io_string_show(buf, &si->gen3.component_vendor,
399 sizeof(si->gen3.component_vendor));
400}
401static DEVICE_ATTR_RO(component_vendor);
402
403static ssize_t component_id_show(struct device *dev,
404 struct device_attribute *attr, char *buf)
405{
406 struct switchtec_dev *stdev = to_stdev(dev);
407 int id = ioread16(&stdev->mmio_sys_info->gen3.component_id);
408
409 /* component_id field not supported after gen3 */
410 if (stdev->gen != SWITCHTEC_GEN3)
411 return sysfs_emit(buf, "none\n");
412
413 return sysfs_emit(buf, "PM%04X\n", id);
414}
415static DEVICE_ATTR_RO(component_id);
416
417static ssize_t component_revision_show(struct device *dev,
418 struct device_attribute *attr, char *buf)
419{
420 struct switchtec_dev *stdev = to_stdev(dev);
421 int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision);
422
423 /* component_revision field not supported after gen3 */
424 if (stdev->gen != SWITCHTEC_GEN3)
425 return sysfs_emit(buf, "255\n");
426
427 return sysfs_emit(buf, "%d\n", rev);
428}
429static DEVICE_ATTR_RO(component_revision);
430
431static ssize_t partition_show(struct device *dev,
432 struct device_attribute *attr, char *buf)
433{
434 struct switchtec_dev *stdev = to_stdev(dev);
435
436 return sysfs_emit(buf, "%d\n", stdev->partition);
437}
438static DEVICE_ATTR_RO(partition);
439
440static ssize_t partition_count_show(struct device *dev,
441 struct device_attribute *attr, char *buf)
442{
443 struct switchtec_dev *stdev = to_stdev(dev);
444
445 return sysfs_emit(buf, "%d\n", stdev->partition_count);
446}
447static DEVICE_ATTR_RO(partition_count);
448
449static struct attribute *switchtec_device_attrs[] = {
450 &dev_attr_device_version.attr,
451 &dev_attr_fw_version.attr,
452 &dev_attr_vendor_id.attr,
453 &dev_attr_product_id.attr,
454 &dev_attr_product_revision.attr,
455 &dev_attr_component_vendor.attr,
456 &dev_attr_component_id.attr,
457 &dev_attr_component_revision.attr,
458 &dev_attr_partition.attr,
459 &dev_attr_partition_count.attr,
460 NULL,
461};
462
463ATTRIBUTE_GROUPS(switchtec_device);
464
465static int switchtec_dev_open(struct inode *inode, struct file *filp)
466{
467 struct switchtec_dev *stdev;
468 struct switchtec_user *stuser;
469
470 stdev = container_of(inode->i_cdev, struct switchtec_dev, cdev);
471
472 stuser = stuser_create(stdev);
473 if (IS_ERR(stuser))
474 return PTR_ERR(stuser);
475
476 filp->private_data = stuser;
477 stream_open(inode, filp);
478
479 dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
480
481 return 0;
482}
483
484static int switchtec_dev_release(struct inode *inode, struct file *filp)
485{
486 struct switchtec_user *stuser = filp->private_data;
487
488 stuser_put(stuser);
489
490 return 0;
491}
492
493static int lock_mutex_and_test_alive(struct switchtec_dev *stdev)
494{
495 if (mutex_lock_interruptible(&stdev->mrpc_mutex))
496 return -EINTR;
497
498 if (!stdev->alive) {
499 mutex_unlock(&stdev->mrpc_mutex);
500 return -ENODEV;
501 }
502
503 return 0;
504}
505
506static ssize_t switchtec_dev_write(struct file *filp, const char __user *data,
507 size_t size, loff_t *off)
508{
509 struct switchtec_user *stuser = filp->private_data;
510 struct switchtec_dev *stdev = stuser->stdev;
511 int rc;
512
513 if (size < sizeof(stuser->cmd) ||
514 size > sizeof(stuser->cmd) + sizeof(stuser->data))
515 return -EINVAL;
516
517 stuser->data_len = size - sizeof(stuser->cmd);
518
519 rc = lock_mutex_and_test_alive(stdev);
520 if (rc)
521 return rc;
522
523 if (stuser->state != MRPC_IDLE) {
524 rc = -EBADE;
525 goto out;
526 }
527
528 rc = copy_from_user(&stuser->cmd, data, sizeof(stuser->cmd));
529 if (rc) {
530 rc = -EFAULT;
531 goto out;
532 }
533 if (((MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_WRITE) ||
534 (MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_READ)) &&
535 !capable(CAP_SYS_ADMIN)) {
536 rc = -EPERM;
537 goto out;
538 }
539
540 data += sizeof(stuser->cmd);
541 rc = copy_from_user(&stuser->data, data, size - sizeof(stuser->cmd));
542 if (rc) {
543 rc = -EFAULT;
544 goto out;
545 }
546
547 rc = mrpc_queue_cmd(stuser);
548
549out:
550 mutex_unlock(&stdev->mrpc_mutex);
551
552 if (rc)
553 return rc;
554
555 return size;
556}
557
558static ssize_t switchtec_dev_read(struct file *filp, char __user *data,
559 size_t size, loff_t *off)
560{
561 struct switchtec_user *stuser = filp->private_data;
562 struct switchtec_dev *stdev = stuser->stdev;
563 int rc;
564
565 if (size < sizeof(stuser->cmd) ||
566 size > sizeof(stuser->cmd) + sizeof(stuser->data))
567 return -EINVAL;
568
569 rc = lock_mutex_and_test_alive(stdev);
570 if (rc)
571 return rc;
572
573 if (stuser->state == MRPC_IDLE) {
574 mutex_unlock(&stdev->mrpc_mutex);
575 return -EBADE;
576 }
577
578 stuser->read_len = size - sizeof(stuser->return_code);
579
580 mutex_unlock(&stdev->mrpc_mutex);
581
582 if (filp->f_flags & O_NONBLOCK) {
583 if (!stuser->cmd_done)
584 return -EAGAIN;
585 } else {
586 rc = wait_event_interruptible(stuser->cmd_comp,
587 stuser->cmd_done);
588 if (rc < 0)
589 return rc;
590 }
591
592 rc = lock_mutex_and_test_alive(stdev);
593 if (rc)
594 return rc;
595
596 if (stuser->state == MRPC_IO_ERROR) {
597 mutex_unlock(&stdev->mrpc_mutex);
598 return -EIO;
599 }
600
601 if (stuser->state != MRPC_DONE) {
602 mutex_unlock(&stdev->mrpc_mutex);
603 return -EBADE;
604 }
605
606 rc = copy_to_user(data, &stuser->return_code,
607 sizeof(stuser->return_code));
608 if (rc) {
609 rc = -EFAULT;
610 goto out;
611 }
612
613 data += sizeof(stuser->return_code);
614 rc = copy_to_user(data, &stuser->data,
615 size - sizeof(stuser->return_code));
616 if (rc) {
617 rc = -EFAULT;
618 goto out;
619 }
620
621 stuser_set_state(stuser, MRPC_IDLE);
622
623out:
624 mutex_unlock(&stdev->mrpc_mutex);
625
626 if (stuser->status == SWITCHTEC_MRPC_STATUS_DONE ||
627 stuser->status == SWITCHTEC_MRPC_STATUS_ERROR)
628 return size;
629 else if (stuser->status == SWITCHTEC_MRPC_STATUS_INTERRUPTED)
630 return -ENXIO;
631 else
632 return -EBADMSG;
633}
634
635static __poll_t switchtec_dev_poll(struct file *filp, poll_table *wait)
636{
637 struct switchtec_user *stuser = filp->private_data;
638 struct switchtec_dev *stdev = stuser->stdev;
639 __poll_t ret = 0;
640
641 poll_wait(filp, &stuser->cmd_comp, wait);
642 poll_wait(filp, &stdev->event_wq, wait);
643
644 if (lock_mutex_and_test_alive(stdev))
645 return EPOLLIN | EPOLLRDHUP | EPOLLOUT | EPOLLERR | EPOLLHUP;
646
647 mutex_unlock(&stdev->mrpc_mutex);
648
649 if (stuser->cmd_done)
650 ret |= EPOLLIN | EPOLLRDNORM;
651
652 if (stuser->event_cnt != atomic_read(&stdev->event_cnt))
653 ret |= EPOLLPRI | EPOLLRDBAND;
654
655 return ret;
656}
657
658static int ioctl_flash_info(struct switchtec_dev *stdev,
659 struct switchtec_ioctl_flash_info __user *uinfo)
660{
661 struct switchtec_ioctl_flash_info info = {0};
662 struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;
663
664 if (stdev->gen == SWITCHTEC_GEN3) {
665 info.flash_length = ioread32(&fi->gen3.flash_length);
666 info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3;
667 } else if (stdev->gen == SWITCHTEC_GEN4) {
668 info.flash_length = ioread32(&fi->gen4.flash_length);
669 info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN4;
670 } else {
671 return -EOPNOTSUPP;
672 }
673
674 if (copy_to_user(uinfo, &info, sizeof(info)))
675 return -EFAULT;
676
677 return 0;
678}
679
680static void set_fw_info_part(struct switchtec_ioctl_flash_part_info *info,
681 struct partition_info __iomem *pi)
682{
683 info->address = ioread32(&pi->address);
684 info->length = ioread32(&pi->length);
685}
686
687static int flash_part_info_gen3(struct switchtec_dev *stdev,
688 struct switchtec_ioctl_flash_part_info *info)
689{
690 struct flash_info_regs_gen3 __iomem *fi =
691 &stdev->mmio_flash_info->gen3;
692 struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3;
693 u32 active_addr = -1;
694
695 switch (info->flash_partition) {
696 case SWITCHTEC_IOCTL_PART_CFG0:
697 active_addr = ioread32(&fi->active_cfg);
698 set_fw_info_part(info, &fi->cfg0);
699 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG0_RUNNING)
700 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
701 break;
702 case SWITCHTEC_IOCTL_PART_CFG1:
703 active_addr = ioread32(&fi->active_cfg);
704 set_fw_info_part(info, &fi->cfg1);
705 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG1_RUNNING)
706 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
707 break;
708 case SWITCHTEC_IOCTL_PART_IMG0:
709 active_addr = ioread32(&fi->active_img);
710 set_fw_info_part(info, &fi->img0);
711 if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG0_RUNNING)
712 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
713 break;
714 case SWITCHTEC_IOCTL_PART_IMG1:
715 active_addr = ioread32(&fi->active_img);
716 set_fw_info_part(info, &fi->img1);
717 if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG1_RUNNING)
718 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
719 break;
720 case SWITCHTEC_IOCTL_PART_NVLOG:
721 set_fw_info_part(info, &fi->nvlog);
722 break;
723 case SWITCHTEC_IOCTL_PART_VENDOR0:
724 set_fw_info_part(info, &fi->vendor[0]);
725 break;
726 case SWITCHTEC_IOCTL_PART_VENDOR1:
727 set_fw_info_part(info, &fi->vendor[1]);
728 break;
729 case SWITCHTEC_IOCTL_PART_VENDOR2:
730 set_fw_info_part(info, &fi->vendor[2]);
731 break;
732 case SWITCHTEC_IOCTL_PART_VENDOR3:
733 set_fw_info_part(info, &fi->vendor[3]);
734 break;
735 case SWITCHTEC_IOCTL_PART_VENDOR4:
736 set_fw_info_part(info, &fi->vendor[4]);
737 break;
738 case SWITCHTEC_IOCTL_PART_VENDOR5:
739 set_fw_info_part(info, &fi->vendor[5]);
740 break;
741 case SWITCHTEC_IOCTL_PART_VENDOR6:
742 set_fw_info_part(info, &fi->vendor[6]);
743 break;
744 case SWITCHTEC_IOCTL_PART_VENDOR7:
745 set_fw_info_part(info, &fi->vendor[7]);
746 break;
747 default:
748 return -EINVAL;
749 }
750
751 if (info->address == active_addr)
752 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
753
754 return 0;
755}
756
757static int flash_part_info_gen4(struct switchtec_dev *stdev,
758 struct switchtec_ioctl_flash_part_info *info)
759{
760 struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4;
761 struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4;
762 struct active_partition_info_gen4 __iomem *af = &fi->active_flag;
763
764 switch (info->flash_partition) {
765 case SWITCHTEC_IOCTL_PART_MAP_0:
766 set_fw_info_part(info, &fi->map0);
767 break;
768 case SWITCHTEC_IOCTL_PART_MAP_1:
769 set_fw_info_part(info, &fi->map1);
770 break;
771 case SWITCHTEC_IOCTL_PART_KEY_0:
772 set_fw_info_part(info, &fi->key0);
773 if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY0_ACTIVE)
774 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
775 if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY0_RUNNING)
776 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
777 break;
778 case SWITCHTEC_IOCTL_PART_KEY_1:
779 set_fw_info_part(info, &fi->key1);
780 if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY1_ACTIVE)
781 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
782 if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY1_RUNNING)
783 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
784 break;
785 case SWITCHTEC_IOCTL_PART_BL2_0:
786 set_fw_info_part(info, &fi->bl2_0);
787 if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_0_ACTIVE)
788 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
789 if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_0_RUNNING)
790 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
791 break;
792 case SWITCHTEC_IOCTL_PART_BL2_1:
793 set_fw_info_part(info, &fi->bl2_1);
794 if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_1_ACTIVE)
795 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
796 if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_1_RUNNING)
797 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
798 break;
799 case SWITCHTEC_IOCTL_PART_CFG0:
800 set_fw_info_part(info, &fi->cfg0);
801 if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG0_ACTIVE)
802 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
803 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG0_RUNNING)
804 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
805 break;
806 case SWITCHTEC_IOCTL_PART_CFG1:
807 set_fw_info_part(info, &fi->cfg1);
808 if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG1_ACTIVE)
809 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
810 if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG1_RUNNING)
811 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
812 break;
813 case SWITCHTEC_IOCTL_PART_IMG0:
814 set_fw_info_part(info, &fi->img0);
815 if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG0_ACTIVE)
816 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
817 if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG0_RUNNING)
818 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
819 break;
820 case SWITCHTEC_IOCTL_PART_IMG1:
821 set_fw_info_part(info, &fi->img1);
822 if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG1_ACTIVE)
823 info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
824 if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG1_RUNNING)
825 info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
826 break;
827 case SWITCHTEC_IOCTL_PART_NVLOG:
828 set_fw_info_part(info, &fi->nvlog);
829 break;
830 case SWITCHTEC_IOCTL_PART_VENDOR0:
831 set_fw_info_part(info, &fi->vendor[0]);
832 break;
833 case SWITCHTEC_IOCTL_PART_VENDOR1:
834 set_fw_info_part(info, &fi->vendor[1]);
835 break;
836 case SWITCHTEC_IOCTL_PART_VENDOR2:
837 set_fw_info_part(info, &fi->vendor[2]);
838 break;
839 case SWITCHTEC_IOCTL_PART_VENDOR3:
840 set_fw_info_part(info, &fi->vendor[3]);
841 break;
842 case SWITCHTEC_IOCTL_PART_VENDOR4:
843 set_fw_info_part(info, &fi->vendor[4]);
844 break;
845 case SWITCHTEC_IOCTL_PART_VENDOR5:
846 set_fw_info_part(info, &fi->vendor[5]);
847 break;
848 case SWITCHTEC_IOCTL_PART_VENDOR6:
849 set_fw_info_part(info, &fi->vendor[6]);
850 break;
851 case SWITCHTEC_IOCTL_PART_VENDOR7:
852 set_fw_info_part(info, &fi->vendor[7]);
853 break;
854 default:
855 return -EINVAL;
856 }
857
858 return 0;
859}
860
861static int ioctl_flash_part_info(struct switchtec_dev *stdev,
862 struct switchtec_ioctl_flash_part_info __user *uinfo)
863{
864 int ret;
865 struct switchtec_ioctl_flash_part_info info = {0};
866
867 if (copy_from_user(&info, uinfo, sizeof(info)))
868 return -EFAULT;
869
870 if (stdev->gen == SWITCHTEC_GEN3) {
871 ret = flash_part_info_gen3(stdev, &info);
872 if (ret)
873 return ret;
874 } else if (stdev->gen == SWITCHTEC_GEN4) {
875 ret = flash_part_info_gen4(stdev, &info);
876 if (ret)
877 return ret;
878 } else {
879 return -EOPNOTSUPP;
880 }
881
882 if (copy_to_user(uinfo, &info, sizeof(info)))
883 return -EFAULT;
884
885 return 0;
886}
887
888static int ioctl_event_summary(struct switchtec_dev *stdev,
889 struct switchtec_user *stuser,
890 struct switchtec_ioctl_event_summary __user *usum,
891 size_t size)
892{
893 struct switchtec_ioctl_event_summary *s;
894 int i;
895 u32 reg;
896 int ret = 0;
897
898 s = kzalloc(sizeof(*s), GFP_KERNEL);
899 if (!s)
900 return -ENOMEM;
901
902 s->global = ioread32(&stdev->mmio_sw_event->global_summary);
903 s->part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap);
904 s->local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary);
905
906 for (i = 0; i < stdev->partition_count; i++) {
907 reg = ioread32(&stdev->mmio_part_cfg_all[i].part_event_summary);
908 s->part[i] = reg;
909 }
910
911 for (i = 0; i < stdev->pff_csr_count; i++) {
912 reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary);
913 s->pff[i] = reg;
914 }
915
916 if (copy_to_user(usum, s, size)) {
917 ret = -EFAULT;
918 goto error_case;
919 }
920
921 stuser->event_cnt = atomic_read(&stdev->event_cnt);
922
923error_case:
924 kfree(s);
925 return ret;
926}
927
928static u32 __iomem *global_ev_reg(struct switchtec_dev *stdev,
929 size_t offset, int index)
930{
931 return (void __iomem *)stdev->mmio_sw_event + offset;
932}
933
934static u32 __iomem *part_ev_reg(struct switchtec_dev *stdev,
935 size_t offset, int index)
936{
937 return (void __iomem *)&stdev->mmio_part_cfg_all[index] + offset;
938}
939
940static u32 __iomem *pff_ev_reg(struct switchtec_dev *stdev,
941 size_t offset, int index)
942{
943 return (void __iomem *)&stdev->mmio_pff_csr[index] + offset;
944}
945
946#define EV_GLB(i, r)[i] = {offsetof(struct sw_event_regs, r), global_ev_reg}
947#define EV_PAR(i, r)[i] = {offsetof(struct part_cfg_regs, r), part_ev_reg}
948#define EV_PFF(i, r)[i] = {offsetof(struct pff_csr_regs, r), pff_ev_reg}
949
950static const struct event_reg {
951 size_t offset;
952 u32 __iomem *(*map_reg)(struct switchtec_dev *stdev,
953 size_t offset, int index);
954} event_regs[] = {
955 EV_GLB(SWITCHTEC_IOCTL_EVENT_STACK_ERROR, stack_error_event_hdr),
956 EV_GLB(SWITCHTEC_IOCTL_EVENT_PPU_ERROR, ppu_error_event_hdr),
957 EV_GLB(SWITCHTEC_IOCTL_EVENT_ISP_ERROR, isp_error_event_hdr),
958 EV_GLB(SWITCHTEC_IOCTL_EVENT_SYS_RESET, sys_reset_event_hdr),
959 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_EXC, fw_exception_hdr),
960 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NMI, fw_nmi_hdr),
961 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NON_FATAL, fw_non_fatal_hdr),
962 EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_FATAL, fw_fatal_hdr),
963 EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP, twi_mrpc_comp_hdr),
964 EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP_ASYNC,
965 twi_mrpc_comp_async_hdr),
966 EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP, cli_mrpc_comp_hdr),
967 EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP_ASYNC,
968 cli_mrpc_comp_async_hdr),
969 EV_GLB(SWITCHTEC_IOCTL_EVENT_GPIO_INT, gpio_interrupt_hdr),
970 EV_GLB(SWITCHTEC_IOCTL_EVENT_GFMS, gfms_event_hdr),
971 EV_PAR(SWITCHTEC_IOCTL_EVENT_PART_RESET, part_reset_hdr),
972 EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),
973 EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),
974 EV_PAR(SWITCHTEC_IOCTL_EVENT_DYN_PART_BIND_COMP, dyn_binding_hdr),
975 EV_PAR(SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY,
976 intercomm_notify_hdr),
977 EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_P2P, aer_in_p2p_hdr),
978 EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_VEP, aer_in_vep_hdr),
979 EV_PFF(SWITCHTEC_IOCTL_EVENT_DPC, dpc_hdr),
980 EV_PFF(SWITCHTEC_IOCTL_EVENT_CTS, cts_hdr),
981 EV_PFF(SWITCHTEC_IOCTL_EVENT_UEC, uec_hdr),
982 EV_PFF(SWITCHTEC_IOCTL_EVENT_HOTPLUG, hotplug_hdr),
983 EV_PFF(SWITCHTEC_IOCTL_EVENT_IER, ier_hdr),
984 EV_PFF(SWITCHTEC_IOCTL_EVENT_THRESH, threshold_hdr),
985 EV_PFF(SWITCHTEC_IOCTL_EVENT_POWER_MGMT, power_mgmt_hdr),
986 EV_PFF(SWITCHTEC_IOCTL_EVENT_TLP_THROTTLING, tlp_throttling_hdr),
987 EV_PFF(SWITCHTEC_IOCTL_EVENT_FORCE_SPEED, force_speed_hdr),
988 EV_PFF(SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT, credit_timeout_hdr),
989 EV_PFF(SWITCHTEC_IOCTL_EVENT_LINK_STATE, link_state_hdr),
990};
991
992static u32 __iomem *event_hdr_addr(struct switchtec_dev *stdev,
993 int event_id, int index)
994{
995 size_t off;
996
997 if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
998 return (u32 __iomem *)ERR_PTR(-EINVAL);
999
1000 off = event_regs[event_id].offset;
1001
1002 if (event_regs[event_id].map_reg == part_ev_reg) {
1003 if (index == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
1004 index = stdev->partition;
1005 else if (index < 0 || index >= stdev->partition_count)
1006 return (u32 __iomem *)ERR_PTR(-EINVAL);
1007 } else if (event_regs[event_id].map_reg == pff_ev_reg) {
1008 if (index < 0 || index >= stdev->pff_csr_count)
1009 return (u32 __iomem *)ERR_PTR(-EINVAL);
1010 }
1011
1012 return event_regs[event_id].map_reg(stdev, off, index);
1013}
1014
1015static int event_ctl(struct switchtec_dev *stdev,
1016 struct switchtec_ioctl_event_ctl *ctl)
1017{
1018 int i;
1019 u32 __iomem *reg;
1020 u32 hdr;
1021
1022 reg = event_hdr_addr(stdev, ctl->event_id, ctl->index);
1023 if (IS_ERR(reg))
1024 return PTR_ERR(reg);
1025
1026 hdr = ioread32(reg);
1027 if (hdr & SWITCHTEC_EVENT_NOT_SUPP)
1028 return -EOPNOTSUPP;
1029
1030 for (i = 0; i < ARRAY_SIZE(ctl->data); i++)
1031 ctl->data[i] = ioread32(®[i + 1]);
1032
1033 ctl->occurred = hdr & SWITCHTEC_EVENT_OCCURRED;
1034 ctl->count = (hdr >> 5) & 0xFF;
1035
1036 if (!(ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_CLEAR))
1037 hdr &= ~SWITCHTEC_EVENT_CLEAR;
1038 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL)
1039 hdr |= SWITCHTEC_EVENT_EN_IRQ;
1040 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_POLL)
1041 hdr &= ~SWITCHTEC_EVENT_EN_IRQ;
1042 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG)
1043 hdr |= SWITCHTEC_EVENT_EN_LOG;
1044 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_LOG)
1045 hdr &= ~SWITCHTEC_EVENT_EN_LOG;
1046 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI)
1047 hdr |= SWITCHTEC_EVENT_EN_CLI;
1048 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_CLI)
1049 hdr &= ~SWITCHTEC_EVENT_EN_CLI;
1050 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL)
1051 hdr |= SWITCHTEC_EVENT_FATAL;
1052 if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_FATAL)
1053 hdr &= ~SWITCHTEC_EVENT_FATAL;
1054
1055 if (ctl->flags)
1056 iowrite32(hdr, reg);
1057
1058 ctl->flags = 0;
1059 if (hdr & SWITCHTEC_EVENT_EN_IRQ)
1060 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL;
1061 if (hdr & SWITCHTEC_EVENT_EN_LOG)
1062 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG;
1063 if (hdr & SWITCHTEC_EVENT_EN_CLI)
1064 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI;
1065 if (hdr & SWITCHTEC_EVENT_FATAL)
1066 ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL;
1067
1068 return 0;
1069}
1070
1071static int ioctl_event_ctl(struct switchtec_dev *stdev,
1072 struct switchtec_ioctl_event_ctl __user *uctl)
1073{
1074 int ret;
1075 int nr_idxs;
1076 unsigned int event_flags;
1077 struct switchtec_ioctl_event_ctl ctl;
1078
1079 if (copy_from_user(&ctl, uctl, sizeof(ctl)))
1080 return -EFAULT;
1081
1082 if (ctl.event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
1083 return -EINVAL;
1084
1085 if (ctl.flags & SWITCHTEC_IOCTL_EVENT_FLAG_UNUSED)
1086 return -EINVAL;
1087
1088 if (ctl.index == SWITCHTEC_IOCTL_EVENT_IDX_ALL) {
1089 if (event_regs[ctl.event_id].map_reg == global_ev_reg)
1090 nr_idxs = 1;
1091 else if (event_regs[ctl.event_id].map_reg == part_ev_reg)
1092 nr_idxs = stdev->partition_count;
1093 else if (event_regs[ctl.event_id].map_reg == pff_ev_reg)
1094 nr_idxs = stdev->pff_csr_count;
1095 else
1096 return -EINVAL;
1097
1098 event_flags = ctl.flags;
1099 for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) {
1100 ctl.flags = event_flags;
1101 ret = event_ctl(stdev, &ctl);
1102 if (ret < 0 && ret != -EOPNOTSUPP)
1103 return ret;
1104 }
1105 } else {
1106 ret = event_ctl(stdev, &ctl);
1107 if (ret < 0)
1108 return ret;
1109 }
1110
1111 if (copy_to_user(uctl, &ctl, sizeof(ctl)))
1112 return -EFAULT;
1113
1114 return 0;
1115}
1116
1117static int ioctl_pff_to_port(struct switchtec_dev *stdev,
1118 struct switchtec_ioctl_pff_port __user *up)
1119{
1120 int i, part;
1121 u32 reg;
1122 struct part_cfg_regs __iomem *pcfg;
1123 struct switchtec_ioctl_pff_port p;
1124
1125 if (copy_from_user(&p, up, sizeof(p)))
1126 return -EFAULT;
1127
1128 p.port = -1;
1129 for (part = 0; part < stdev->partition_count; part++) {
1130 pcfg = &stdev->mmio_part_cfg_all[part];
1131 p.partition = part;
1132
1133 reg = ioread32(&pcfg->usp_pff_inst_id);
1134 if (reg == p.pff) {
1135 p.port = 0;
1136 break;
1137 }
1138
1139 reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;
1140 if (reg == p.pff) {
1141 p.port = SWITCHTEC_IOCTL_PFF_VEP;
1142 break;
1143 }
1144
1145 for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1146 reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1147 if (reg != p.pff)
1148 continue;
1149
1150 p.port = i + 1;
1151 break;
1152 }
1153
1154 if (p.port != -1)
1155 break;
1156 }
1157
1158 if (copy_to_user(up, &p, sizeof(p)))
1159 return -EFAULT;
1160
1161 return 0;
1162}
1163
1164static int ioctl_port_to_pff(struct switchtec_dev *stdev,
1165 struct switchtec_ioctl_pff_port __user *up)
1166{
1167 struct switchtec_ioctl_pff_port p;
1168 struct part_cfg_regs __iomem *pcfg;
1169
1170 if (copy_from_user(&p, up, sizeof(p)))
1171 return -EFAULT;
1172
1173 if (p.partition == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
1174 pcfg = stdev->mmio_part_cfg;
1175 else if (p.partition < stdev->partition_count)
1176 pcfg = &stdev->mmio_part_cfg_all[p.partition];
1177 else
1178 return -EINVAL;
1179
1180 switch (p.port) {
1181 case 0:
1182 p.pff = ioread32(&pcfg->usp_pff_inst_id);
1183 break;
1184 case SWITCHTEC_IOCTL_PFF_VEP:
1185 p.pff = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;
1186 break;
1187 default:
1188 if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id))
1189 return -EINVAL;
1190 p.port = array_index_nospec(p.port,
1191 ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1);
1192 p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]);
1193 break;
1194 }
1195
1196 if (copy_to_user(up, &p, sizeof(p)))
1197 return -EFAULT;
1198
1199 return 0;
1200}
1201
1202static long switchtec_dev_ioctl(struct file *filp, unsigned int cmd,
1203 unsigned long arg)
1204{
1205 struct switchtec_user *stuser = filp->private_data;
1206 struct switchtec_dev *stdev = stuser->stdev;
1207 int rc;
1208 void __user *argp = (void __user *)arg;
1209
1210 rc = lock_mutex_and_test_alive(stdev);
1211 if (rc)
1212 return rc;
1213
1214 switch (cmd) {
1215 case SWITCHTEC_IOCTL_FLASH_INFO:
1216 rc = ioctl_flash_info(stdev, argp);
1217 break;
1218 case SWITCHTEC_IOCTL_FLASH_PART_INFO:
1219 rc = ioctl_flash_part_info(stdev, argp);
1220 break;
1221 case SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY:
1222 rc = ioctl_event_summary(stdev, stuser, argp,
1223 sizeof(struct switchtec_ioctl_event_summary_legacy));
1224 break;
1225 case SWITCHTEC_IOCTL_EVENT_CTL:
1226 rc = ioctl_event_ctl(stdev, argp);
1227 break;
1228 case SWITCHTEC_IOCTL_PFF_TO_PORT:
1229 rc = ioctl_pff_to_port(stdev, argp);
1230 break;
1231 case SWITCHTEC_IOCTL_PORT_TO_PFF:
1232 rc = ioctl_port_to_pff(stdev, argp);
1233 break;
1234 case SWITCHTEC_IOCTL_EVENT_SUMMARY:
1235 rc = ioctl_event_summary(stdev, stuser, argp,
1236 sizeof(struct switchtec_ioctl_event_summary));
1237 break;
1238 default:
1239 rc = -ENOTTY;
1240 break;
1241 }
1242
1243 mutex_unlock(&stdev->mrpc_mutex);
1244 return rc;
1245}
1246
1247static const struct file_operations switchtec_fops = {
1248 .owner = THIS_MODULE,
1249 .open = switchtec_dev_open,
1250 .release = switchtec_dev_release,
1251 .write = switchtec_dev_write,
1252 .read = switchtec_dev_read,
1253 .poll = switchtec_dev_poll,
1254 .unlocked_ioctl = switchtec_dev_ioctl,
1255 .compat_ioctl = compat_ptr_ioctl,
1256};
1257
1258static void link_event_work(struct work_struct *work)
1259{
1260 struct switchtec_dev *stdev;
1261
1262 stdev = container_of(work, struct switchtec_dev, link_event_work);
1263
1264 if (stdev->link_notifier)
1265 stdev->link_notifier(stdev);
1266}
1267
1268static void check_link_state_events(struct switchtec_dev *stdev)
1269{
1270 int idx;
1271 u32 reg;
1272 int count;
1273 int occurred = 0;
1274
1275 for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1276 reg = ioread32(&stdev->mmio_pff_csr[idx].link_state_hdr);
1277 dev_dbg(&stdev->dev, "link_state: %d->%08x\n", idx, reg);
1278 count = (reg >> 5) & 0xFF;
1279
1280 if (count != stdev->link_event_count[idx]) {
1281 occurred = 1;
1282 stdev->link_event_count[idx] = count;
1283 }
1284 }
1285
1286 if (occurred)
1287 schedule_work(&stdev->link_event_work);
1288}
1289
1290static void enable_link_state_events(struct switchtec_dev *stdev)
1291{
1292 int idx;
1293
1294 for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1295 iowrite32(SWITCHTEC_EVENT_CLEAR |
1296 SWITCHTEC_EVENT_EN_IRQ,
1297 &stdev->mmio_pff_csr[idx].link_state_hdr);
1298 }
1299}
1300
1301static void enable_dma_mrpc(struct switchtec_dev *stdev)
1302{
1303 writeq(stdev->dma_mrpc_dma_addr, &stdev->mmio_mrpc->dma_addr);
1304 flush_wc_buf(stdev);
1305 iowrite32(SWITCHTEC_DMA_MRPC_EN, &stdev->mmio_mrpc->dma_en);
1306}
1307
1308static void stdev_release(struct device *dev)
1309{
1310 struct switchtec_dev *stdev = to_stdev(dev);
1311
1312 if (stdev->dma_mrpc) {
1313 iowrite32(0, &stdev->mmio_mrpc->dma_en);
1314 flush_wc_buf(stdev);
1315 writeq(0, &stdev->mmio_mrpc->dma_addr);
1316 dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc),
1317 stdev->dma_mrpc, stdev->dma_mrpc_dma_addr);
1318 }
1319 kfree(stdev);
1320}
1321
1322static void stdev_kill(struct switchtec_dev *stdev)
1323{
1324 struct switchtec_user *stuser, *tmpuser;
1325
1326 pci_clear_master(stdev->pdev);
1327
1328 cancel_delayed_work_sync(&stdev->mrpc_timeout);
1329
1330 /* Mark the hardware as unavailable and complete all completions */
1331 mutex_lock(&stdev->mrpc_mutex);
1332 stdev->alive = false;
1333
1334 /* Wake up and kill any users waiting on an MRPC request */
1335 list_for_each_entry_safe(stuser, tmpuser, &stdev->mrpc_queue, list) {
1336 stuser->cmd_done = true;
1337 wake_up_interruptible(&stuser->cmd_comp);
1338 list_del_init(&stuser->list);
1339 stuser_put(stuser);
1340 }
1341
1342 mutex_unlock(&stdev->mrpc_mutex);
1343
1344 /* Wake up any users waiting on event_wq */
1345 wake_up_interruptible(&stdev->event_wq);
1346}
1347
1348static struct switchtec_dev *stdev_create(struct pci_dev *pdev)
1349{
1350 struct switchtec_dev *stdev;
1351 int minor;
1352 struct device *dev;
1353 struct cdev *cdev;
1354 int rc;
1355
1356 stdev = kzalloc_node(sizeof(*stdev), GFP_KERNEL,
1357 dev_to_node(&pdev->dev));
1358 if (!stdev)
1359 return ERR_PTR(-ENOMEM);
1360
1361 stdev->alive = true;
1362 stdev->pdev = pdev;
1363 INIT_LIST_HEAD(&stdev->mrpc_queue);
1364 mutex_init(&stdev->mrpc_mutex);
1365 stdev->mrpc_busy = 0;
1366 INIT_WORK(&stdev->mrpc_work, mrpc_event_work);
1367 INIT_DELAYED_WORK(&stdev->mrpc_timeout, mrpc_timeout_work);
1368 INIT_WORK(&stdev->link_event_work, link_event_work);
1369 init_waitqueue_head(&stdev->event_wq);
1370 atomic_set(&stdev->event_cnt, 0);
1371
1372 dev = &stdev->dev;
1373 device_initialize(dev);
1374 dev->class = switchtec_class;
1375 dev->parent = &pdev->dev;
1376 dev->groups = switchtec_device_groups;
1377 dev->release = stdev_release;
1378
1379 minor = ida_alloc(&switchtec_minor_ida, GFP_KERNEL);
1380 if (minor < 0) {
1381 rc = minor;
1382 goto err_put;
1383 }
1384
1385 dev->devt = MKDEV(MAJOR(switchtec_devt), minor);
1386 dev_set_name(dev, "switchtec%d", minor);
1387
1388 cdev = &stdev->cdev;
1389 cdev_init(cdev, &switchtec_fops);
1390 cdev->owner = THIS_MODULE;
1391
1392 return stdev;
1393
1394err_put:
1395 put_device(&stdev->dev);
1396 return ERR_PTR(rc);
1397}
1398
1399static int mask_event(struct switchtec_dev *stdev, int eid, int idx)
1400{
1401 size_t off = event_regs[eid].offset;
1402 u32 __iomem *hdr_reg;
1403 u32 hdr;
1404
1405 hdr_reg = event_regs[eid].map_reg(stdev, off, idx);
1406 hdr = ioread32(hdr_reg);
1407
1408 if (hdr & SWITCHTEC_EVENT_NOT_SUPP)
1409 return 0;
1410
1411 if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ))
1412 return 0;
1413
1414 dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr);
1415 hdr &= ~(SWITCHTEC_EVENT_EN_IRQ | SWITCHTEC_EVENT_OCCURRED);
1416 iowrite32(hdr, hdr_reg);
1417
1418 return 1;
1419}
1420
1421static int mask_all_events(struct switchtec_dev *stdev, int eid)
1422{
1423 int idx;
1424 int count = 0;
1425
1426 if (event_regs[eid].map_reg == part_ev_reg) {
1427 for (idx = 0; idx < stdev->partition_count; idx++)
1428 count += mask_event(stdev, eid, idx);
1429 } else if (event_regs[eid].map_reg == pff_ev_reg) {
1430 for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1431 if (!stdev->pff_local[idx])
1432 continue;
1433
1434 count += mask_event(stdev, eid, idx);
1435 }
1436 } else {
1437 count += mask_event(stdev, eid, 0);
1438 }
1439
1440 return count;
1441}
1442
1443static irqreturn_t switchtec_event_isr(int irq, void *dev)
1444{
1445 struct switchtec_dev *stdev = dev;
1446 u32 reg;
1447 irqreturn_t ret = IRQ_NONE;
1448 int eid, event_count = 0;
1449
1450 reg = ioread32(&stdev->mmio_part_cfg->mrpc_comp_hdr);
1451 if (reg & SWITCHTEC_EVENT_OCCURRED) {
1452 dev_dbg(&stdev->dev, "%s: mrpc comp\n", __func__);
1453 ret = IRQ_HANDLED;
1454 schedule_work(&stdev->mrpc_work);
1455 iowrite32(reg, &stdev->mmio_part_cfg->mrpc_comp_hdr);
1456 }
1457
1458 check_link_state_events(stdev);
1459
1460 for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {
1461 if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE ||
1462 eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)
1463 continue;
1464
1465 event_count += mask_all_events(stdev, eid);
1466 }
1467
1468 if (event_count) {
1469 atomic_inc(&stdev->event_cnt);
1470 wake_up_interruptible(&stdev->event_wq);
1471 dev_dbg(&stdev->dev, "%s: %d events\n", __func__,
1472 event_count);
1473 return IRQ_HANDLED;
1474 }
1475
1476 return ret;
1477}
1478
1479
1480static irqreturn_t switchtec_dma_mrpc_isr(int irq, void *dev)
1481{
1482 struct switchtec_dev *stdev = dev;
1483 irqreturn_t ret = IRQ_NONE;
1484
1485 iowrite32(SWITCHTEC_EVENT_CLEAR |
1486 SWITCHTEC_EVENT_EN_IRQ,
1487 &stdev->mmio_part_cfg->mrpc_comp_hdr);
1488 schedule_work(&stdev->mrpc_work);
1489
1490 ret = IRQ_HANDLED;
1491 return ret;
1492}
1493
1494static int switchtec_init_isr(struct switchtec_dev *stdev)
1495{
1496 int nvecs;
1497 int event_irq;
1498 int dma_mrpc_irq;
1499 int rc;
1500
1501 if (nirqs < 4)
1502 nirqs = 4;
1503
1504 nvecs = pci_alloc_irq_vectors(stdev->pdev, 1, nirqs,
1505 PCI_IRQ_MSIX | PCI_IRQ_MSI |
1506 PCI_IRQ_VIRTUAL);
1507 if (nvecs < 0)
1508 return nvecs;
1509
1510 event_irq = ioread16(&stdev->mmio_part_cfg->vep_vector_number);
1511 if (event_irq < 0 || event_irq >= nvecs)
1512 return -EFAULT;
1513
1514 event_irq = pci_irq_vector(stdev->pdev, event_irq);
1515 if (event_irq < 0)
1516 return event_irq;
1517
1518 rc = devm_request_irq(&stdev->pdev->dev, event_irq,
1519 switchtec_event_isr, 0,
1520 KBUILD_MODNAME, stdev);
1521
1522 if (rc)
1523 return rc;
1524
1525 if (!stdev->dma_mrpc)
1526 return rc;
1527
1528 dma_mrpc_irq = ioread32(&stdev->mmio_mrpc->dma_vector);
1529 if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs)
1530 return -EFAULT;
1531
1532 dma_mrpc_irq = pci_irq_vector(stdev->pdev, dma_mrpc_irq);
1533 if (dma_mrpc_irq < 0)
1534 return dma_mrpc_irq;
1535
1536 rc = devm_request_irq(&stdev->pdev->dev, dma_mrpc_irq,
1537 switchtec_dma_mrpc_isr, 0,
1538 KBUILD_MODNAME, stdev);
1539
1540 return rc;
1541}
1542
1543static void init_pff(struct switchtec_dev *stdev)
1544{
1545 int i;
1546 u32 reg;
1547 struct part_cfg_regs __iomem *pcfg = stdev->mmio_part_cfg;
1548
1549 for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
1550 reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
1551 if (reg != PCI_VENDOR_ID_MICROSEMI)
1552 break;
1553 }
1554
1555 stdev->pff_csr_count = i;
1556
1557 reg = ioread32(&pcfg->usp_pff_inst_id);
1558 if (reg < stdev->pff_csr_count)
1559 stdev->pff_local[reg] = 1;
1560
1561 reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;
1562 if (reg < stdev->pff_csr_count)
1563 stdev->pff_local[reg] = 1;
1564
1565 for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1566 reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1567 if (reg < stdev->pff_csr_count)
1568 stdev->pff_local[reg] = 1;
1569 }
1570}
1571
1572static int switchtec_init_pci(struct switchtec_dev *stdev,
1573 struct pci_dev *pdev)
1574{
1575 int rc;
1576 void __iomem *map;
1577 unsigned long res_start, res_len;
1578 u32 __iomem *part_id;
1579
1580 rc = pcim_enable_device(pdev);
1581 if (rc)
1582 return rc;
1583
1584 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1585 if (rc)
1586 return rc;
1587
1588 pci_set_master(pdev);
1589
1590 res_start = pci_resource_start(pdev, 0);
1591 res_len = pci_resource_len(pdev, 0);
1592
1593 if (!devm_request_mem_region(&pdev->dev, res_start,
1594 res_len, KBUILD_MODNAME))
1595 return -EBUSY;
1596
1597 stdev->mmio_mrpc = devm_ioremap_wc(&pdev->dev, res_start,
1598 SWITCHTEC_GAS_TOP_CFG_OFFSET);
1599 if (!stdev->mmio_mrpc)
1600 return -ENOMEM;
1601
1602 map = devm_ioremap(&pdev->dev,
1603 res_start + SWITCHTEC_GAS_TOP_CFG_OFFSET,
1604 res_len - SWITCHTEC_GAS_TOP_CFG_OFFSET);
1605 if (!map)
1606 return -ENOMEM;
1607
1608 stdev->mmio = map - SWITCHTEC_GAS_TOP_CFG_OFFSET;
1609 stdev->mmio_sw_event = stdev->mmio + SWITCHTEC_GAS_SW_EVENT_OFFSET;
1610 stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
1611 stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET;
1612 stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET;
1613
1614 if (stdev->gen == SWITCHTEC_GEN3)
1615 part_id = &stdev->mmio_sys_info->gen3.partition_id;
1616 else if (stdev->gen == SWITCHTEC_GEN4)
1617 part_id = &stdev->mmio_sys_info->gen4.partition_id;
1618 else
1619 return -EOPNOTSUPP;
1620
1621 stdev->partition = ioread8(part_id);
1622 stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count);
1623 stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET;
1624 stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition];
1625 stdev->mmio_pff_csr = stdev->mmio + SWITCHTEC_GAS_PFF_CSR_OFFSET;
1626
1627 if (stdev->partition_count < 1)
1628 stdev->partition_count = 1;
1629
1630 init_pff(stdev);
1631
1632 pci_set_drvdata(pdev, stdev);
1633
1634 if (!use_dma_mrpc)
1635 return 0;
1636
1637 if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)
1638 return 0;
1639
1640 stdev->dma_mrpc = dma_alloc_coherent(&stdev->pdev->dev,
1641 sizeof(*stdev->dma_mrpc),
1642 &stdev->dma_mrpc_dma_addr,
1643 GFP_KERNEL);
1644 if (stdev->dma_mrpc == NULL)
1645 return -ENOMEM;
1646
1647 return 0;
1648}
1649
1650static int switchtec_pci_probe(struct pci_dev *pdev,
1651 const struct pci_device_id *id)
1652{
1653 struct switchtec_dev *stdev;
1654 int rc;
1655
1656 if (pdev->class == (PCI_CLASS_BRIDGE_OTHER << 8))
1657 request_module_nowait("ntb_hw_switchtec");
1658
1659 stdev = stdev_create(pdev);
1660 if (IS_ERR(stdev))
1661 return PTR_ERR(stdev);
1662
1663 stdev->gen = id->driver_data;
1664
1665 rc = switchtec_init_pci(stdev, pdev);
1666 if (rc)
1667 goto err_put;
1668
1669 rc = switchtec_init_isr(stdev);
1670 if (rc) {
1671 dev_err(&stdev->dev, "failed to init isr.\n");
1672 goto err_put;
1673 }
1674
1675 iowrite32(SWITCHTEC_EVENT_CLEAR |
1676 SWITCHTEC_EVENT_EN_IRQ,
1677 &stdev->mmio_part_cfg->mrpc_comp_hdr);
1678 enable_link_state_events(stdev);
1679
1680 if (stdev->dma_mrpc)
1681 enable_dma_mrpc(stdev);
1682
1683 rc = cdev_device_add(&stdev->cdev, &stdev->dev);
1684 if (rc)
1685 goto err_devadd;
1686
1687 dev_info(&stdev->dev, "Management device registered.\n");
1688
1689 return 0;
1690
1691err_devadd:
1692 stdev_kill(stdev);
1693err_put:
1694 ida_free(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1695 put_device(&stdev->dev);
1696 return rc;
1697}
1698
1699static void switchtec_pci_remove(struct pci_dev *pdev)
1700{
1701 struct switchtec_dev *stdev = pci_get_drvdata(pdev);
1702
1703 pci_set_drvdata(pdev, NULL);
1704
1705 cdev_device_del(&stdev->cdev, &stdev->dev);
1706 ida_free(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1707 dev_info(&stdev->dev, "unregistered.\n");
1708 stdev_kill(stdev);
1709 put_device(&stdev->dev);
1710}
1711
1712#define SWITCHTEC_PCI_DEVICE(device_id, gen) \
1713 { \
1714 .vendor = PCI_VENDOR_ID_MICROSEMI, \
1715 .device = device_id, \
1716 .subvendor = PCI_ANY_ID, \
1717 .subdevice = PCI_ANY_ID, \
1718 .class = (PCI_CLASS_MEMORY_OTHER << 8), \
1719 .class_mask = 0xFFFFFFFF, \
1720 .driver_data = gen, \
1721 }, \
1722 { \
1723 .vendor = PCI_VENDOR_ID_MICROSEMI, \
1724 .device = device_id, \
1725 .subvendor = PCI_ANY_ID, \
1726 .subdevice = PCI_ANY_ID, \
1727 .class = (PCI_CLASS_BRIDGE_OTHER << 8), \
1728 .class_mask = 0xFFFFFFFF, \
1729 .driver_data = gen, \
1730 }
1731
1732static const struct pci_device_id switchtec_pci_tbl[] = {
1733 SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3), //PFX 24xG3
1734 SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3), //PFX 32xG3
1735 SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3), //PFX 48xG3
1736 SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3), //PFX 64xG3
1737 SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3), //PFX 80xG3
1738 SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3), //PFX 96xG3
1739 SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3), //PSX 24xG3
1740 SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3), //PSX 32xG3
1741 SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3), //PSX 48xG3
1742 SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3), //PSX 64xG3
1743 SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3), //PSX 80xG3
1744 SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3), //PSX 96xG3
1745 SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3), //PAX 24XG3
1746 SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3), //PAX 32XG3
1747 SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3), //PAX 48XG3
1748 SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3), //PAX 64XG3
1749 SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3), //PAX 80XG3
1750 SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3), //PAX 96XG3
1751 SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3), //PFXL 24XG3
1752 SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3), //PFXL 32XG3
1753 SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3), //PFXL 48XG3
1754 SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3), //PFXL 64XG3
1755 SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3), //PFXL 80XG3
1756 SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3), //PFXL 96XG3
1757 SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3), //PFXI 24XG3
1758 SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3), //PFXI 32XG3
1759 SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3), //PFXI 48XG3
1760 SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3), //PFXI 64XG3
1761 SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3), //PFXI 80XG3
1762 SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3), //PFXI 96XG3
1763 SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4), //PFX 100XG4
1764 SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4), //PFX 84XG4
1765 SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4), //PFX 68XG4
1766 SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4), //PFX 52XG4
1767 SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4), //PFX 36XG4
1768 SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4), //PFX 28XG4
1769 SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4), //PSX 100XG4
1770 SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4), //PSX 84XG4
1771 SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4), //PSX 68XG4
1772 SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4), //PSX 52XG4
1773 SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4), //PSX 36XG4
1774 SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4), //PSX 28XG4
1775 SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4), //PAX 100XG4
1776 SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4), //PAX 84XG4
1777 SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4), //PAX 68XG4
1778 SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4), //PAX 52XG4
1779 SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4), //PAX 36XG4
1780 SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4), //PAX 28XG4
1781 SWITCHTEC_PCI_DEVICE(0x4352, SWITCHTEC_GEN4), //PFXA 52XG4
1782 SWITCHTEC_PCI_DEVICE(0x4336, SWITCHTEC_GEN4), //PFXA 36XG4
1783 SWITCHTEC_PCI_DEVICE(0x4328, SWITCHTEC_GEN4), //PFXA 28XG4
1784 SWITCHTEC_PCI_DEVICE(0x4452, SWITCHTEC_GEN4), //PSXA 52XG4
1785 SWITCHTEC_PCI_DEVICE(0x4436, SWITCHTEC_GEN4), //PSXA 36XG4
1786 SWITCHTEC_PCI_DEVICE(0x4428, SWITCHTEC_GEN4), //PSXA 28XG4
1787 SWITCHTEC_PCI_DEVICE(0x4552, SWITCHTEC_GEN4), //PAXA 52XG4
1788 SWITCHTEC_PCI_DEVICE(0x4536, SWITCHTEC_GEN4), //PAXA 36XG4
1789 SWITCHTEC_PCI_DEVICE(0x4528, SWITCHTEC_GEN4), //PAXA 28XG4
1790 {0}
1791};
1792MODULE_DEVICE_TABLE(pci, switchtec_pci_tbl);
1793
1794static struct pci_driver switchtec_pci_driver = {
1795 .name = KBUILD_MODNAME,
1796 .id_table = switchtec_pci_tbl,
1797 .probe = switchtec_pci_probe,
1798 .remove = switchtec_pci_remove,
1799};
1800
1801static int __init switchtec_init(void)
1802{
1803 int rc;
1804
1805 rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices,
1806 "switchtec");
1807 if (rc)
1808 return rc;
1809
1810 switchtec_class = class_create(THIS_MODULE, "switchtec");
1811 if (IS_ERR(switchtec_class)) {
1812 rc = PTR_ERR(switchtec_class);
1813 goto err_create_class;
1814 }
1815
1816 rc = pci_register_driver(&switchtec_pci_driver);
1817 if (rc)
1818 goto err_pci_register;
1819
1820 pr_info(KBUILD_MODNAME ": loaded.\n");
1821
1822 return 0;
1823
1824err_pci_register:
1825 class_destroy(switchtec_class);
1826
1827err_create_class:
1828 unregister_chrdev_region(switchtec_devt, max_devices);
1829
1830 return rc;
1831}
1832module_init(switchtec_init);
1833
1834static void __exit switchtec_exit(void)
1835{
1836 pci_unregister_driver(&switchtec_pci_driver);
1837 class_destroy(switchtec_class);
1838 unregister_chrdev_region(switchtec_devt, max_devices);
1839 ida_destroy(&switchtec_minor_ida);
1840
1841 pr_info(KBUILD_MODNAME ": unloaded.\n");
1842}
1843module_exit(switchtec_exit);