1/*
   2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3 * Copyright © 2006-2007 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the next
  14 * paragraph) shall be included in all copies or substantial portions of the
  15 * Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23 * DEALINGS IN THE SOFTWARE.
  24 *
  25 * Authors:
  26 *	Eric Anholt <eric@anholt.net>
  27 */
  28
  29#include <linux/delay.h>
  30#include <linux/export.h>
  31#include <linux/i2c.h>
  32#include <linux/slab.h>
  33
 
  34#include <drm/drm_atomic_helper.h>
  35#include <drm/drm_crtc.h>
  36#include <drm/drm_edid.h>
  37
  38#include "i915_drv.h"
 
  39#include "intel_atomic.h"
  40#include "intel_connector.h"
  41#include "intel_crtc.h"
  42#include "intel_de.h"
  43#include "intel_display_types.h"
  44#include "intel_fifo_underrun.h"
  45#include "intel_gmbus.h"
  46#include "intel_hdmi.h"
  47#include "intel_hotplug.h"
  48#include "intel_panel.h"
  49#include "intel_sdvo.h"
  50#include "intel_sdvo_regs.h"
  51
  52#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  53#define SDVO_RGB_MASK  (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  54#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  55#define SDVO_TV_MASK   (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  56
  57#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  58			SDVO_TV_MASK)
  59
  60#define IS_TV(c)	(c->output_flag & SDVO_TV_MASK)
  61#define IS_TMDS(c)	(c->output_flag & SDVO_TMDS_MASK)
  62#define IS_LVDS(c)	(c->output_flag & SDVO_LVDS_MASK)
  63#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  64#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  65
  66
  67static const char * const tv_format_names[] = {
  68	"NTSC_M"   , "NTSC_J"  , "NTSC_443",
  69	"PAL_B"    , "PAL_D"   , "PAL_G"   ,
  70	"PAL_H"    , "PAL_I"   , "PAL_M"   ,
  71	"PAL_N"    , "PAL_NC"  , "PAL_60"  ,
  72	"SECAM_B"  , "SECAM_D" , "SECAM_G" ,
  73	"SECAM_K"  , "SECAM_K1", "SECAM_L" ,
  74	"SECAM_60"
  75};
  76
  77#define TV_FORMAT_NUM  ARRAY_SIZE(tv_format_names)
  78
  79struct intel_sdvo {
  80	struct intel_encoder base;
  81
  82	struct i2c_adapter *i2c;
  83	u8 slave_addr;
  84
  85	struct i2c_adapter ddc;
  86
  87	/* Register for the SDVO device: SDVOB or SDVOC */
  88	i915_reg_t sdvo_reg;
  89
  90	/* Active outputs controlled by this SDVO output */
  91	u16 controlled_output;
  92
  93	/*
  94	 * Capabilities of the SDVO device returned by
  95	 * intel_sdvo_get_capabilities()
  96	 */
  97	struct intel_sdvo_caps caps;
  98
  99	u8 colorimetry_cap;
 100
 101	/* Pixel clock limitations reported by the SDVO device, in kHz */
 102	int pixel_clock_min, pixel_clock_max;
 103
 104	/*
 105	* For multiple function SDVO device,
 106	* this is for current attached outputs.
 107	*/
 108	u16 attached_output;
 109
 110	/*
 111	 * Hotplug activation bits for this device
 112	 */
 113	u16 hotplug_active;
 114
 115	enum port port;
 116
 117	bool has_hdmi_monitor;
 118	bool has_hdmi_audio;
 119
 120	/* DDC bus used by this SDVO encoder */
 121	u8 ddc_bus;
 122
 123	/*
 124	 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
 125	 */
 126	u8 dtd_sdvo_flags;
 127};
 128
 129struct intel_sdvo_connector {
 130	struct intel_connector base;
 131
 132	/* Mark the type of connector */
 133	u16 output_flag;
 134
 135	/* This contains all current supported TV format */
 136	u8 tv_format_supported[TV_FORMAT_NUM];
 137	int   format_supported_num;
 138	struct drm_property *tv_format;
 139
 140	/* add the property for the SDVO-TV */
 141	struct drm_property *left;
 142	struct drm_property *right;
 143	struct drm_property *top;
 144	struct drm_property *bottom;
 145	struct drm_property *hpos;
 146	struct drm_property *vpos;
 147	struct drm_property *contrast;
 148	struct drm_property *saturation;
 149	struct drm_property *hue;
 150	struct drm_property *sharpness;
 151	struct drm_property *flicker_filter;
 152	struct drm_property *flicker_filter_adaptive;
 153	struct drm_property *flicker_filter_2d;
 154	struct drm_property *tv_chroma_filter;
 155	struct drm_property *tv_luma_filter;
 156	struct drm_property *dot_crawl;
 157
 158	/* add the property for the SDVO-TV/LVDS */
 159	struct drm_property *brightness;
 160
 161	/* this is to get the range of margin.*/
 162	u32 max_hscan, max_vscan;
 163
 164	/**
 165	 * This is set if we treat the device as HDMI, instead of DVI.
 166	 */
 167	bool is_hdmi;
 168};
 169
 170struct intel_sdvo_connector_state {
 171	/* base.base: tv.saturation/contrast/hue/brightness */
 172	struct intel_digital_connector_state base;
 173
 174	struct {
 175		unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
 176		unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
 177		unsigned chroma_filter, luma_filter, dot_crawl;
 178	} tv;
 179};
 180
 181static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
 182{
 183	return container_of(encoder, struct intel_sdvo, base);
 184}
 185
 186static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector)
 187{
 188	return to_sdvo(intel_attached_encoder(connector));
 189}
 190
 191static struct intel_sdvo_connector *
 192to_intel_sdvo_connector(struct drm_connector *connector)
 193{
 194	return container_of(connector, struct intel_sdvo_connector, base.base);
 195}
 196
 197#define to_intel_sdvo_connector_state(conn_state) \
 198	container_of((conn_state), struct intel_sdvo_connector_state, base.base)
 199
 200static bool
 201intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags);
 202static bool
 203intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
 204			      struct intel_sdvo_connector *intel_sdvo_connector,
 205			      int type);
 206static bool
 207intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
 208				   struct intel_sdvo_connector *intel_sdvo_connector);
 209
 210/*
 211 * Writes the SDVOB or SDVOC with the given value, but always writes both
 212 * SDVOB and SDVOC to work around apparent hardware issues (according to
 213 * comments in the BIOS).
 214 */
 215static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 216{
 217	struct drm_device *dev = intel_sdvo->base.base.dev;
 218	struct drm_i915_private *dev_priv = to_i915(dev);
 219	u32 bval = val, cval = val;
 220	int i;
 221
 222	if (HAS_PCH_SPLIT(dev_priv)) {
 223		intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
 224		intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
 225		/*
 226		 * HW workaround, need to write this twice for issue
 227		 * that may result in first write getting masked.
 228		 */
 229		if (HAS_PCH_IBX(dev_priv)) {
 230			intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
 231			intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
 232		}
 233		return;
 234	}
 235
 236	if (intel_sdvo->port == PORT_B)
 237		cval = intel_de_read(dev_priv, GEN3_SDVOC);
 238	else
 239		bval = intel_de_read(dev_priv, GEN3_SDVOB);
 240
 241	/*
 242	 * Write the registers twice for luck. Sometimes,
 243	 * writing them only once doesn't appear to 'stick'.
 244	 * The BIOS does this too. Yay, magic
 245	 */
 246	for (i = 0; i < 2; i++) {
 247		intel_de_write(dev_priv, GEN3_SDVOB, bval);
 248		intel_de_posting_read(dev_priv, GEN3_SDVOB);
 249
 250		intel_de_write(dev_priv, GEN3_SDVOC, cval);
 251		intel_de_posting_read(dev_priv, GEN3_SDVOC);
 252	}
 253}
 254
 255static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
 256{
 257	struct i2c_msg msgs[] = {
 258		{
 259			.addr = intel_sdvo->slave_addr,
 260			.flags = 0,
 261			.len = 1,
 262			.buf = &addr,
 263		},
 264		{
 265			.addr = intel_sdvo->slave_addr,
 266			.flags = I2C_M_RD,
 267			.len = 1,
 268			.buf = ch,
 269		}
 270	};
 271	int ret;
 272
 273	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
 274		return true;
 275
 276	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
 277	return false;
 278}
 279
 280#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
 281
 282/** Mapping of command numbers to names, for debug output */
 283static const struct {
 284	u8 cmd;
 285	const char *name;
 286} __attribute__ ((packed)) sdvo_cmd_names[] = {
 287	SDVO_CMD_NAME_ENTRY(RESET),
 288	SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
 289	SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
 290	SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
 291	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
 292	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
 293	SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
 294	SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
 295	SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
 296	SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
 297	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
 298	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
 299	SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
 300	SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
 301	SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
 302	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
 303	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
 304	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
 305	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
 306	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
 307	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
 308	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
 309	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
 310	SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
 311	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
 312	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
 313	SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
 314	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
 315	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
 316	SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
 317	SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
 318	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
 319	SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
 320	SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
 321	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
 322	SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
 323	SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
 324	SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
 325	SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
 326	SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
 327	SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
 328	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
 329
 330	/* Add the op code for SDVO enhancements */
 331	SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
 332	SDVO_CMD_NAME_ENTRY(GET_HPOS),
 333	SDVO_CMD_NAME_ENTRY(SET_HPOS),
 334	SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
 335	SDVO_CMD_NAME_ENTRY(GET_VPOS),
 336	SDVO_CMD_NAME_ENTRY(SET_VPOS),
 337	SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
 338	SDVO_CMD_NAME_ENTRY(GET_SATURATION),
 339	SDVO_CMD_NAME_ENTRY(SET_SATURATION),
 340	SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
 341	SDVO_CMD_NAME_ENTRY(GET_HUE),
 342	SDVO_CMD_NAME_ENTRY(SET_HUE),
 343	SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
 344	SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
 345	SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
 346	SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
 347	SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
 348	SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
 349	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
 350	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
 351	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
 352	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
 353	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
 354	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
 355	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
 356	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
 357	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
 358	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
 359	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
 360	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
 361	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
 362	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
 363	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
 364	SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
 365	SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
 366	SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
 367	SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
 368	SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
 369	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
 370	SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
 371	SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
 372	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
 373	SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
 374	SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
 375
 376	/* HDMI op code */
 377	SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
 378	SDVO_CMD_NAME_ENTRY(GET_ENCODE),
 379	SDVO_CMD_NAME_ENTRY(SET_ENCODE),
 380	SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
 381	SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
 382	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
 383	SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
 384	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
 385	SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
 386	SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
 387	SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
 388	SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
 389	SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
 390	SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
 391	SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
 392	SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
 393	SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
 394	SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
 395	SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
 396	SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
 397};
 398
 399#undef SDVO_CMD_NAME_ENTRY
 400
 401static const char *sdvo_cmd_name(u8 cmd)
 402{
 403	int i;
 404
 405	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
 406		if (cmd == sdvo_cmd_names[i].cmd)
 407			return sdvo_cmd_names[i].name;
 408	}
 409
 410	return NULL;
 411}
 412
 413#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
 414
 415static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
 416				   const void *args, int args_len)
 417{
 418	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
 419	const char *cmd_name;
 420	int i, pos = 0;
 421	char buffer[64];
 422
 423#define BUF_PRINT(args...) \
 424	pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
 425
 426	for (i = 0; i < args_len; i++) {
 427		BUF_PRINT("%02X ", ((u8 *)args)[i]);
 428	}
 429	for (; i < 8; i++) {
 430		BUF_PRINT("   ");
 431	}
 432
 433	cmd_name = sdvo_cmd_name(cmd);
 434	if (cmd_name)
 435		BUF_PRINT("(%s)", cmd_name);
 436	else
 437		BUF_PRINT("(%02X)", cmd);
 438
 439	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
 440#undef BUF_PRINT
 441
 442	DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
 443}
 444
 445static const char * const cmd_status_names[] = {
 446	[SDVO_CMD_STATUS_POWER_ON] = "Power on",
 447	[SDVO_CMD_STATUS_SUCCESS] = "Success",
 448	[SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
 449	[SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
 450	[SDVO_CMD_STATUS_PENDING] = "Pending",
 451	[SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
 452	[SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
 453};
 454
 455static const char *sdvo_cmd_status(u8 status)
 456{
 457	if (status < ARRAY_SIZE(cmd_status_names))
 458		return cmd_status_names[status];
 459	else
 460		return NULL;
 461}
 462
 463static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
 464				   const void *args, int args_len,
 465				   bool unlocked)
 466{
 467	u8 *buf, status;
 468	struct i2c_msg *msgs;
 469	int i, ret = true;
 470
 471	/* Would be simpler to allocate both in one go ? */
 472	buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
 473	if (!buf)
 474		return false;
 475
 476	msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
 477	if (!msgs) {
 478		kfree(buf);
 479		return false;
 480	}
 481
 482	intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
 483
 484	for (i = 0; i < args_len; i++) {
 485		msgs[i].addr = intel_sdvo->slave_addr;
 486		msgs[i].flags = 0;
 487		msgs[i].len = 2;
 488		msgs[i].buf = buf + 2 *i;
 489		buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
 490		buf[2*i + 1] = ((u8*)args)[i];
 491	}
 492	msgs[i].addr = intel_sdvo->slave_addr;
 493	msgs[i].flags = 0;
 494	msgs[i].len = 2;
 495	msgs[i].buf = buf + 2*i;
 496	buf[2*i + 0] = SDVO_I2C_OPCODE;
 497	buf[2*i + 1] = cmd;
 498
 499	/* the following two are to read the response */
 500	status = SDVO_I2C_CMD_STATUS;
 501	msgs[i+1].addr = intel_sdvo->slave_addr;
 502	msgs[i+1].flags = 0;
 503	msgs[i+1].len = 1;
 504	msgs[i+1].buf = &status;
 505
 506	msgs[i+2].addr = intel_sdvo->slave_addr;
 507	msgs[i+2].flags = I2C_M_RD;
 508	msgs[i+2].len = 1;
 509	msgs[i+2].buf = &status;
 510
 511	if (unlocked)
 512		ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
 513	else
 514		ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
 515	if (ret < 0) {
 516		DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
 517		ret = false;
 518		goto out;
 519	}
 520	if (ret != i+3) {
 521		/* failure in I2C transfer */
 522		DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
 523		ret = false;
 524	}
 525
 526out:
 527	kfree(msgs);
 528	kfree(buf);
 529	return ret;
 530}
 531
 532static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
 533				 const void *args, int args_len)
 534{
 535	return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
 536}
 537
 538static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
 539				     void *response, int response_len)
 540{
 541	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
 542	const char *cmd_status;
 543	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
 544	u8 status;
 545	int i, pos = 0;
 546	char buffer[64];
 547
 548	buffer[0] = '\0';
 549
 550	/*
 551	 * The documentation states that all commands will be
 552	 * processed within 15µs, and that we need only poll
 553	 * the status byte a maximum of 3 times in order for the
 554	 * command to be complete.
 555	 *
 556	 * Check 5 times in case the hardware failed to read the docs.
 557	 *
 558	 * Also beware that the first response by many devices is to
 559	 * reply PENDING and stall for time. TVs are notorious for
 560	 * requiring longer than specified to complete their replies.
 561	 * Originally (in the DDX long ago), the delay was only ever 15ms
 562	 * with an additional delay of 30ms applied for TVs added later after
 563	 * many experiments. To accommodate both sets of delays, we do a
 564	 * sequence of slow checks if the device is falling behind and fails
 565	 * to reply within 5*15µs.
 566	 */
 567	if (!intel_sdvo_read_byte(intel_sdvo,
 568				  SDVO_I2C_CMD_STATUS,
 569				  &status))
 570		goto log_fail;
 571
 572	while ((status == SDVO_CMD_STATUS_PENDING ||
 573		status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
 574		if (retry < 10)
 575			msleep(15);
 576		else
 577			udelay(15);
 578
 579		if (!intel_sdvo_read_byte(intel_sdvo,
 580					  SDVO_I2C_CMD_STATUS,
 581					  &status))
 582			goto log_fail;
 583	}
 584
 585#define BUF_PRINT(args...) \
 586	pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
 587
 588	cmd_status = sdvo_cmd_status(status);
 589	if (cmd_status)
 590		BUF_PRINT("(%s)", cmd_status);
 591	else
 592		BUF_PRINT("(??? %d)", status);
 593
 594	if (status != SDVO_CMD_STATUS_SUCCESS)
 595		goto log_fail;
 596
 597	/* Read the command response */
 598	for (i = 0; i < response_len; i++) {
 599		if (!intel_sdvo_read_byte(intel_sdvo,
 600					  SDVO_I2C_RETURN_0 + i,
 601					  &((u8 *)response)[i]))
 602			goto log_fail;
 603		BUF_PRINT(" %02X", ((u8 *)response)[i]);
 604	}
 605
 606	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
 607#undef BUF_PRINT
 608
 609	DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
 610	return true;
 611
 612log_fail:
 613	DRM_DEBUG_KMS("%s: R: ... failed %s\n",
 614		      SDVO_NAME(intel_sdvo), buffer);
 615	return false;
 616}
 617
 618static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
 619{
 620	if (adjusted_mode->crtc_clock >= 100000)
 621		return 1;
 622	else if (adjusted_mode->crtc_clock >= 50000)
 623		return 2;
 624	else
 625		return 4;
 626}
 627
 628static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
 629						u8 ddc_bus)
 630{
 631	/* This must be the immediately preceding write before the i2c xfer */
 632	return __intel_sdvo_write_cmd(intel_sdvo,
 633				      SDVO_CMD_SET_CONTROL_BUS_SWITCH,
 634				      &ddc_bus, 1, false);
 635}
 636
 637static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
 638{
 639	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
 640		return false;
 641
 642	return intel_sdvo_read_response(intel_sdvo, NULL, 0);
 643}
 644
 645static bool
 646intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
 647{
 648	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
 649		return false;
 650
 651	return intel_sdvo_read_response(intel_sdvo, value, len);
 652}
 653
 654static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
 655{
 656	struct intel_sdvo_set_target_input_args targets = {0};
 657	return intel_sdvo_set_value(intel_sdvo,
 658				    SDVO_CMD_SET_TARGET_INPUT,
 659				    &targets, sizeof(targets));
 660}
 661
 662/*
 663 * Return whether each input is trained.
 664 *
 665 * This function is making an assumption about the layout of the response,
 666 * which should be checked against the docs.
 667 */
 668static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
 669{
 670	struct intel_sdvo_get_trained_inputs_response response;
 671
 672	BUILD_BUG_ON(sizeof(response) != 1);
 673	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
 674				  &response, sizeof(response)))
 675		return false;
 676
 677	*input_1 = response.input0_trained;
 678	*input_2 = response.input1_trained;
 679	return true;
 680}
 681
 682static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
 683					  u16 outputs)
 684{
 685	return intel_sdvo_set_value(intel_sdvo,
 686				    SDVO_CMD_SET_ACTIVE_OUTPUTS,
 687				    &outputs, sizeof(outputs));
 688}
 689
 690static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
 691					  u16 *outputs)
 692{
 693	return intel_sdvo_get_value(intel_sdvo,
 694				    SDVO_CMD_GET_ACTIVE_OUTPUTS,
 695				    outputs, sizeof(*outputs));
 696}
 697
 698static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
 699					       int mode)
 700{
 701	u8 state = SDVO_ENCODER_STATE_ON;
 702
 703	switch (mode) {
 704	case DRM_MODE_DPMS_ON:
 705		state = SDVO_ENCODER_STATE_ON;
 706		break;
 707	case DRM_MODE_DPMS_STANDBY:
 708		state = SDVO_ENCODER_STATE_STANDBY;
 709		break;
 710	case DRM_MODE_DPMS_SUSPEND:
 711		state = SDVO_ENCODER_STATE_SUSPEND;
 712		break;
 713	case DRM_MODE_DPMS_OFF:
 714		state = SDVO_ENCODER_STATE_OFF;
 715		break;
 716	}
 717
 718	return intel_sdvo_set_value(intel_sdvo,
 719				    SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
 720}
 721
 722static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
 723						   int *clock_min,
 724						   int *clock_max)
 725{
 726	struct intel_sdvo_pixel_clock_range clocks;
 727
 728	BUILD_BUG_ON(sizeof(clocks) != 4);
 729	if (!intel_sdvo_get_value(intel_sdvo,
 730				  SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
 731				  &clocks, sizeof(clocks)))
 732		return false;
 733
 734	/* Convert the values from units of 10 kHz to kHz. */
 735	*clock_min = clocks.min * 10;
 736	*clock_max = clocks.max * 10;
 737	return true;
 738}
 739
 740static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
 741					 u16 outputs)
 742{
 743	return intel_sdvo_set_value(intel_sdvo,
 744				    SDVO_CMD_SET_TARGET_OUTPUT,
 745				    &outputs, sizeof(outputs));
 746}
 747
 748static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
 749				  struct intel_sdvo_dtd *dtd)
 750{
 751	return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
 752		intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 753}
 754
 755static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
 756				  struct intel_sdvo_dtd *dtd)
 757{
 758	return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
 759		intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
 760}
 761
 762static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
 763					 struct intel_sdvo_dtd *dtd)
 764{
 765	return intel_sdvo_set_timing(intel_sdvo,
 766				     SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
 767}
 768
 769static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
 770					 struct intel_sdvo_dtd *dtd)
 771{
 772	return intel_sdvo_set_timing(intel_sdvo,
 773				     SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
 774}
 775
 776static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
 777					struct intel_sdvo_dtd *dtd)
 778{
 779	return intel_sdvo_get_timing(intel_sdvo,
 780				     SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 781}
 782
 783static bool
 784intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
 785					 struct intel_sdvo_connector *intel_sdvo_connector,
 786					 u16 clock,
 787					 u16 width,
 788					 u16 height)
 789{
 790	struct intel_sdvo_preferred_input_timing_args args;
 791
 792	memset(&args, 0, sizeof(args));
 793	args.clock = clock;
 794	args.width = width;
 795	args.height = height;
 796	args.interlace = 0;
 797
 798	if (IS_LVDS(intel_sdvo_connector)) {
 799		const struct drm_display_mode *fixed_mode =
 800			intel_sdvo_connector->base.panel.fixed_mode;
 801
 802		if (fixed_mode->hdisplay != width ||
 803		    fixed_mode->vdisplay != height)
 804			args.scaled = 1;
 805	}
 806
 807	return intel_sdvo_set_value(intel_sdvo,
 808				    SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
 809				    &args, sizeof(args));
 810}
 811
 812static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
 813						  struct intel_sdvo_dtd *dtd)
 814{
 815	BUILD_BUG_ON(sizeof(dtd->part1) != 8);
 816	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
 817	return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
 818				    &dtd->part1, sizeof(dtd->part1)) &&
 819		intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
 820				     &dtd->part2, sizeof(dtd->part2));
 821}
 822
 823static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
 824{
 825	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
 826}
 827
 828static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
 829					 const struct drm_display_mode *mode)
 830{
 831	u16 width, height;
 832	u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
 833	u16 h_sync_offset, v_sync_offset;
 834	int mode_clock;
 835
 836	memset(dtd, 0, sizeof(*dtd));
 837
 838	width = mode->hdisplay;
 839	height = mode->vdisplay;
 840
 841	/* do some mode translations */
 842	h_blank_len = mode->htotal - mode->hdisplay;
 843	h_sync_len = mode->hsync_end - mode->hsync_start;
 844
 845	v_blank_len = mode->vtotal - mode->vdisplay;
 846	v_sync_len = mode->vsync_end - mode->vsync_start;
 847
 848	h_sync_offset = mode->hsync_start - mode->hdisplay;
 849	v_sync_offset = mode->vsync_start - mode->vdisplay;
 850
 851	mode_clock = mode->clock;
 852	mode_clock /= 10;
 853	dtd->part1.clock = mode_clock;
 854
 855	dtd->part1.h_active = width & 0xff;
 856	dtd->part1.h_blank = h_blank_len & 0xff;
 857	dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
 858		((h_blank_len >> 8) & 0xf);
 859	dtd->part1.v_active = height & 0xff;
 860	dtd->part1.v_blank = v_blank_len & 0xff;
 861	dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
 862		((v_blank_len >> 8) & 0xf);
 863
 864	dtd->part2.h_sync_off = h_sync_offset & 0xff;
 865	dtd->part2.h_sync_width = h_sync_len & 0xff;
 866	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
 867		(v_sync_len & 0xf);
 868	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
 869		((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
 870		((v_sync_len & 0x30) >> 4);
 871
 872	dtd->part2.dtd_flags = 0x18;
 873	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 874		dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
 875	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 876		dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
 877	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 878		dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
 879
 880	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
 881}
 882
 883static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
 884					 const struct intel_sdvo_dtd *dtd)
 885{
 886	struct drm_display_mode mode = {};
 887
 888	mode.hdisplay = dtd->part1.h_active;
 889	mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
 890	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
 891	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
 892	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
 893	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
 894	mode.htotal = mode.hdisplay + dtd->part1.h_blank;
 895	mode.htotal += (dtd->part1.h_high & 0xf) << 8;
 896
 897	mode.vdisplay = dtd->part1.v_active;
 898	mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
 899	mode.vsync_start = mode.vdisplay;
 900	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
 901	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
 902	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
 903	mode.vsync_end = mode.vsync_start +
 904		(dtd->part2.v_sync_off_width & 0xf);
 905	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
 906	mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
 907	mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
 908
 909	mode.clock = dtd->part1.clock * 10;
 910
 911	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
 912		mode.flags |= DRM_MODE_FLAG_INTERLACE;
 913	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
 914		mode.flags |= DRM_MODE_FLAG_PHSYNC;
 915	else
 916		mode.flags |= DRM_MODE_FLAG_NHSYNC;
 917	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
 918		mode.flags |= DRM_MODE_FLAG_PVSYNC;
 919	else
 920		mode.flags |= DRM_MODE_FLAG_NVSYNC;
 921
 922	drm_mode_set_crtcinfo(&mode, 0);
 923
 924	drm_mode_copy(pmode, &mode);
 925}
 926
 927static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
 928{
 929	struct intel_sdvo_encode encode;
 930
 931	BUILD_BUG_ON(sizeof(encode) != 2);
 932	return intel_sdvo_get_value(intel_sdvo,
 933				  SDVO_CMD_GET_SUPP_ENCODE,
 934				  &encode, sizeof(encode));
 935}
 936
 937static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
 938				  u8 mode)
 939{
 940	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
 941}
 942
 943static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
 944				       u8 mode)
 945{
 946	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
 947}
 948
 949static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
 950					     u8 pixel_repeat)
 951{
 952	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI,
 953				    &pixel_repeat, 1);
 954}
 955
 956static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
 957				       u8 audio_state)
 958{
 959	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
 960				    &audio_state, 1);
 961}
 962
 963static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
 964				     u8 *hbuf_size)
 965{
 966	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
 967				  hbuf_size, 1))
 968		return false;
 969
 970	/* Buffer size is 0 based, hooray! However zero means zero. */
 971	if (*hbuf_size)
 972		(*hbuf_size)++;
 973
 974	return true;
 975}
 976
 977#if 0
 978static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
 979{
 980	int i, j;
 981	u8 set_buf_index[2];
 982	u8 av_split;
 983	u8 buf_size;
 984	u8 buf[48];
 985	u8 *pos;
 986
 987	intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
 988
 989	for (i = 0; i <= av_split; i++) {
 990		set_buf_index[0] = i; set_buf_index[1] = 0;
 991		intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
 992				     set_buf_index, 2);
 993		intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
 994		intel_sdvo_read_response(encoder, &buf_size, 1);
 995
 996		pos = buf;
 997		for (j = 0; j <= buf_size; j += 8) {
 998			intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
 999					     NULL, 0);
1000			intel_sdvo_read_response(encoder, pos, 8);
1001			pos += 8;
1002		}
1003	}
1004}
1005#endif
1006
1007static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
1008				       unsigned int if_index, u8 tx_rate,
1009				       const u8 *data, unsigned int length)
1010{
1011	u8 set_buf_index[2] = { if_index, 0 };
1012	u8 hbuf_size, tmp[8];
1013	int i;
1014
1015	if (!intel_sdvo_set_value(intel_sdvo,
1016				  SDVO_CMD_SET_HBUF_INDEX,
1017				  set_buf_index, 2))
1018		return false;
1019
1020	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1021		return false;
1022
1023	DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1024		      if_index, length, hbuf_size);
1025
1026	if (hbuf_size < length)
1027		return false;
1028
1029	for (i = 0; i < hbuf_size; i += 8) {
1030		memset(tmp, 0, 8);
1031		if (i < length)
1032			memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
1033
1034		if (!intel_sdvo_set_value(intel_sdvo,
1035					  SDVO_CMD_SET_HBUF_DATA,
1036					  tmp, 8))
1037			return false;
1038	}
1039
1040	return intel_sdvo_set_value(intel_sdvo,
1041				    SDVO_CMD_SET_HBUF_TXRATE,
1042				    &tx_rate, 1);
1043}
1044
1045static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
1046					 unsigned int if_index,
1047					 u8 *data, unsigned int length)
1048{
1049	u8 set_buf_index[2] = { if_index, 0 };
1050	u8 hbuf_size, tx_rate, av_split;
1051	int i;
1052
1053	if (!intel_sdvo_get_value(intel_sdvo,
1054				  SDVO_CMD_GET_HBUF_AV_SPLIT,
1055				  &av_split, 1))
1056		return -ENXIO;
1057
1058	if (av_split < if_index)
1059		return 0;
1060
1061	if (!intel_sdvo_set_value(intel_sdvo,
1062				  SDVO_CMD_SET_HBUF_INDEX,
1063				  set_buf_index, 2))
1064		return -ENXIO;
1065
1066	if (!intel_sdvo_get_value(intel_sdvo,
1067				  SDVO_CMD_GET_HBUF_TXRATE,
1068				  &tx_rate, 1))
1069		return -ENXIO;
1070
1071	if (tx_rate == SDVO_HBUF_TX_DISABLED)
1072		return 0;
1073
1074	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1075		return false;
1076
1077	DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1078		      if_index, length, hbuf_size);
1079
1080	hbuf_size = min_t(unsigned int, length, hbuf_size);
1081
1082	for (i = 0; i < hbuf_size; i += 8) {
1083		if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1084			return -ENXIO;
1085		if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1086					      min_t(unsigned int, 8, hbuf_size - i)))
1087			return -ENXIO;
1088	}
1089
1090	return hbuf_size;
1091}
1092
1093static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1094					     struct intel_crtc_state *crtc_state,
1095					     struct drm_connector_state *conn_state)
1096{
1097	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1098	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1099	const struct drm_display_mode *adjusted_mode =
1100		&crtc_state->hw.adjusted_mode;
1101	int ret;
1102
1103	if (!crtc_state->has_hdmi_sink)
1104		return true;
1105
1106	crtc_state->infoframes.enable |=
1107		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1108
1109	ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1110						       conn_state->connector,
1111						       adjusted_mode);
1112	if (ret)
1113		return false;
1114
1115	drm_hdmi_avi_infoframe_quant_range(frame,
1116					   conn_state->connector,
1117					   adjusted_mode,
1118					   crtc_state->limited_color_range ?
1119					   HDMI_QUANTIZATION_RANGE_LIMITED :
1120					   HDMI_QUANTIZATION_RANGE_FULL);
1121
1122	ret = hdmi_avi_infoframe_check(frame);
1123	if (drm_WARN_ON(&dev_priv->drm, ret))
1124		return false;
1125
1126	return true;
1127}
1128
1129static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1130					 const struct intel_crtc_state *crtc_state)
1131{
1132	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1133	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1134	const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1135	ssize_t len;
1136
1137	if ((crtc_state->infoframes.enable &
1138	     intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1139		return true;
1140
1141	if (drm_WARN_ON(&dev_priv->drm,
1142			frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1143		return false;
1144
1145	len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1146	if (drm_WARN_ON(&dev_priv->drm, len < 0))
1147		return false;
1148
1149	return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1150					  SDVO_HBUF_TX_VSYNC,
1151					  sdvo_data, len);
1152}
1153
1154static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1155					 struct intel_crtc_state *crtc_state)
1156{
1157	u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1158	union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1159	ssize_t len;
1160	int ret;
1161
1162	if (!crtc_state->has_hdmi_sink)
1163		return;
1164
1165	len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1166					sdvo_data, sizeof(sdvo_data));
1167	if (len < 0) {
1168		DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1169		return;
1170	} else if (len == 0) {
1171		return;
1172	}
1173
1174	crtc_state->infoframes.enable |=
1175		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1176
1177	ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
1178	if (ret) {
1179		DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1180		return;
1181	}
1182
1183	if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1184		DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1185			      frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1186}
1187
1188static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1189				     const struct drm_connector_state *conn_state)
1190{
1191	struct intel_sdvo_tv_format format;
1192	u32 format_map;
1193
1194	format_map = 1 << conn_state->tv.mode;
1195	memset(&format, 0, sizeof(format));
1196	memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1197
1198	BUILD_BUG_ON(sizeof(format) != 6);
1199	return intel_sdvo_set_value(intel_sdvo,
1200				    SDVO_CMD_SET_TV_FORMAT,
1201				    &format, sizeof(format));
1202}
1203
1204static bool
1205intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1206					const struct drm_display_mode *mode)
1207{
1208	struct intel_sdvo_dtd output_dtd;
1209
1210	if (!intel_sdvo_set_target_output(intel_sdvo,
1211					  intel_sdvo->attached_output))
1212		return false;
1213
1214	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1215	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1216		return false;
1217
1218	return true;
1219}
1220
1221/*
1222 * Asks the sdvo controller for the preferred input mode given the output mode.
1223 * Unfortunately we have to set up the full output mode to do that.
1224 */
1225static bool
1226intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1227				    struct intel_sdvo_connector *intel_sdvo_connector,
1228				    const struct drm_display_mode *mode,
1229				    struct drm_display_mode *adjusted_mode)
1230{
1231	struct intel_sdvo_dtd input_dtd;
1232
1233	/* Reset the input timing to the screen. Assume always input 0. */
1234	if (!intel_sdvo_set_target_input(intel_sdvo))
1235		return false;
1236
1237	if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1238						      intel_sdvo_connector,
1239						      mode->clock / 10,
1240						      mode->hdisplay,
1241						      mode->vdisplay))
1242		return false;
1243
1244	if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1245						   &input_dtd))
1246		return false;
1247
1248	intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1249	intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1250
1251	return true;
1252}
1253
1254static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1255{
1256	struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1257	unsigned dotclock = pipe_config->port_clock;
1258	struct dpll *clock = &pipe_config->dpll;
1259
1260	/*
1261	 * SDVO TV has fixed PLL values depend on its clock range,
1262	 * this mirrors vbios setting.
1263	 */
1264	if (dotclock >= 100000 && dotclock < 140500) {
1265		clock->p1 = 2;
1266		clock->p2 = 10;
1267		clock->n = 3;
1268		clock->m1 = 16;
1269		clock->m2 = 8;
1270	} else if (dotclock >= 140500 && dotclock <= 200000) {
1271		clock->p1 = 1;
1272		clock->p2 = 10;
1273		clock->n = 6;
1274		clock->m1 = 12;
1275		clock->m2 = 8;
1276	} else {
1277		drm_WARN(&dev_priv->drm, 1,
1278			 "SDVO TV clock out of range: %i\n", dotclock);
1279	}
1280
1281	pipe_config->clock_set = true;
1282}
1283
1284static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo,
1285				const struct drm_connector_state *conn_state)
1286{
1287	return sdvo->has_hdmi_monitor &&
1288		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1289}
1290
1291static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
1292					   const struct intel_crtc_state *crtc_state,
1293					   const struct drm_connector_state *conn_state)
1294{
1295	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1296
1297	if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0)
1298		return false;
1299
1300	return intel_hdmi_limited_color_range(crtc_state, conn_state);
1301}
1302
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1303static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1304				     struct intel_crtc_state *pipe_config,
1305				     struct drm_connector_state *conn_state)
1306{
1307	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1308	struct intel_sdvo_connector_state *intel_sdvo_state =
1309		to_intel_sdvo_connector_state(conn_state);
1310	struct intel_sdvo_connector *intel_sdvo_connector =
1311		to_intel_sdvo_connector(conn_state->connector);
1312	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1313	struct drm_display_mode *mode = &pipe_config->hw.mode;
1314
1315	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1316	pipe_config->pipe_bpp = 8*3;
1317	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1318
1319	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1320		pipe_config->has_pch_encoder = true;
1321
1322	/*
1323	 * We need to construct preferred input timings based on our
1324	 * output timings.  To do that, we have to set the output
1325	 * timings, even though this isn't really the right place in
1326	 * the sequence to do it. Oh well.
1327	 */
1328	if (IS_TV(intel_sdvo_connector)) {
1329		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1330			return -EINVAL;
1331
1332		(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1333							   intel_sdvo_connector,
1334							   mode,
1335							   adjusted_mode);
1336		pipe_config->sdvo_tv_clock = true;
1337	} else if (IS_LVDS(intel_sdvo_connector)) {
1338		if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1339							     intel_sdvo_connector->base.panel.fixed_mode))
 
 
 
 
 
 
 
 
1340			return -EINVAL;
1341
1342		(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1343							   intel_sdvo_connector,
1344							   mode,
1345							   adjusted_mode);
1346	}
1347
1348	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1349		return -EINVAL;
1350
1351	/*
1352	 * Make the CRTC code factor in the SDVO pixel multiplier.  The
1353	 * SDVO device will factor out the multiplier during mode_set.
1354	 */
1355	pipe_config->pixel_multiplier =
1356		intel_sdvo_get_pixel_multiplier(adjusted_mode);
1357
1358	pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state);
1359
1360	if (pipe_config->has_hdmi_sink) {
1361		if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO)
1362			pipe_config->has_audio = intel_sdvo->has_hdmi_audio;
1363		else
1364			pipe_config->has_audio =
1365				intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON;
1366	}
1367
1368	pipe_config->limited_color_range =
1369		intel_sdvo_limited_color_range(encoder, pipe_config,
1370					       conn_state);
1371
1372	/* Clock computation needs to happen after pixel multiplier. */
1373	if (IS_TV(intel_sdvo_connector))
1374		i9xx_adjust_sdvo_tv_clock(pipe_config);
1375
1376	if (conn_state->picture_aspect_ratio)
1377		adjusted_mode->picture_aspect_ratio =
1378			conn_state->picture_aspect_ratio;
1379
1380	if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1381					      pipe_config, conn_state)) {
1382		DRM_DEBUG_KMS("bad AVI infoframe\n");
1383		return -EINVAL;
1384	}
1385
1386	return 0;
1387}
1388
1389#define UPDATE_PROPERTY(input, NAME) \
1390	do { \
1391		val = input; \
1392		intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1393	} while (0)
1394
1395static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1396				    const struct intel_sdvo_connector_state *sdvo_state)
1397{
1398	const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1399	struct intel_sdvo_connector *intel_sdvo_conn =
1400		to_intel_sdvo_connector(conn_state->connector);
1401	u16 val;
1402
1403	if (intel_sdvo_conn->left)
1404		UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1405
1406	if (intel_sdvo_conn->top)
1407		UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1408
1409	if (intel_sdvo_conn->hpos)
1410		UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1411
1412	if (intel_sdvo_conn->vpos)
1413		UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1414
1415	if (intel_sdvo_conn->saturation)
1416		UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1417
1418	if (intel_sdvo_conn->contrast)
1419		UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1420
1421	if (intel_sdvo_conn->hue)
1422		UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1423
1424	if (intel_sdvo_conn->brightness)
1425		UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1426
1427	if (intel_sdvo_conn->sharpness)
1428		UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1429
1430	if (intel_sdvo_conn->flicker_filter)
1431		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1432
1433	if (intel_sdvo_conn->flicker_filter_2d)
1434		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1435
1436	if (intel_sdvo_conn->flicker_filter_adaptive)
1437		UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1438
1439	if (intel_sdvo_conn->tv_chroma_filter)
1440		UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1441
1442	if (intel_sdvo_conn->tv_luma_filter)
1443		UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1444
1445	if (intel_sdvo_conn->dot_crawl)
1446		UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1447
1448#undef UPDATE_PROPERTY
1449}
1450
1451static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
1452				  struct intel_encoder *intel_encoder,
1453				  const struct intel_crtc_state *crtc_state,
1454				  const struct drm_connector_state *conn_state)
1455{
1456	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1457	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1458	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1459	const struct intel_sdvo_connector_state *sdvo_state =
1460		to_intel_sdvo_connector_state(conn_state);
1461	const struct intel_sdvo_connector *intel_sdvo_connector =
1462		to_intel_sdvo_connector(conn_state->connector);
1463	const struct drm_display_mode *mode = &crtc_state->hw.mode;
1464	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1465	u32 sdvox;
1466	struct intel_sdvo_in_out_map in_out;
1467	struct intel_sdvo_dtd input_dtd, output_dtd;
1468	int rate;
1469
1470	intel_sdvo_update_props(intel_sdvo, sdvo_state);
1471
1472	/*
1473	 * First, set the input mapping for the first input to our controlled
1474	 * output. This is only correct if we're a single-input device, in
1475	 * which case the first input is the output from the appropriate SDVO
1476	 * channel on the motherboard.  In a two-input device, the first input
1477	 * will be SDVOB and the second SDVOC.
1478	 */
1479	in_out.in0 = intel_sdvo->attached_output;
1480	in_out.in1 = 0;
1481
1482	intel_sdvo_set_value(intel_sdvo,
1483			     SDVO_CMD_SET_IN_OUT_MAP,
1484			     &in_out, sizeof(in_out));
1485
1486	/* Set the output timings to the screen */
1487	if (!intel_sdvo_set_target_output(intel_sdvo,
1488					  intel_sdvo->attached_output))
1489		return;
1490
1491	/* lvds has a special fixed output timing. */
1492	if (IS_LVDS(intel_sdvo_connector))
1493		intel_sdvo_get_dtd_from_mode(&output_dtd,
1494					     intel_sdvo_connector->base.panel.fixed_mode);
1495	else
 
 
1496		intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
 
1497	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1498		drm_info(&dev_priv->drm,
1499			 "Setting output timings on %s failed\n",
1500			 SDVO_NAME(intel_sdvo));
1501
1502	/* Set the input timing to the screen. Assume always input 0. */
1503	if (!intel_sdvo_set_target_input(intel_sdvo))
1504		return;
1505
1506	if (crtc_state->has_hdmi_sink) {
1507		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1508		intel_sdvo_set_colorimetry(intel_sdvo,
1509					   crtc_state->limited_color_range ?
1510					   SDVO_COLORIMETRY_RGB220 :
1511					   SDVO_COLORIMETRY_RGB256);
1512		intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1513		intel_sdvo_set_pixel_replication(intel_sdvo,
1514						 !!(adjusted_mode->flags &
1515						    DRM_MODE_FLAG_DBLCLK));
1516	} else
1517		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1518
1519	if (IS_TV(intel_sdvo_connector) &&
1520	    !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1521		return;
1522
1523	intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1524
1525	if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1526		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1527	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1528		drm_info(&dev_priv->drm,
1529			 "Setting input timings on %s failed\n",
1530			 SDVO_NAME(intel_sdvo));
1531
1532	switch (crtc_state->pixel_multiplier) {
1533	default:
1534		drm_WARN(&dev_priv->drm, 1,
1535			 "unknown pixel multiplier specified\n");
1536		fallthrough;
1537	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1538	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1539	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1540	}
1541	if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1542		return;
1543
1544	/* Set the SDVO control regs. */
1545	if (DISPLAY_VER(dev_priv) >= 4) {
1546		/* The real mode polarity is set by the SDVO commands, using
1547		 * struct intel_sdvo_dtd. */
1548		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1549		if (DISPLAY_VER(dev_priv) < 5)
1550			sdvox |= SDVO_BORDER_ENABLE;
1551	} else {
1552		sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1553		if (intel_sdvo->port == PORT_B)
1554			sdvox &= SDVOB_PRESERVE_MASK;
1555		else
1556			sdvox &= SDVOC_PRESERVE_MASK;
1557		sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1558	}
1559
1560	if (HAS_PCH_CPT(dev_priv))
1561		sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1562	else
1563		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1564
1565	if (DISPLAY_VER(dev_priv) >= 4) {
1566		/* done in crtc_mode_set as the dpll_md reg must be written early */
1567	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1568		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1569		/* done in crtc_mode_set as it lives inside the dpll register */
1570	} else {
1571		sdvox |= (crtc_state->pixel_multiplier - 1)
1572			<< SDVO_PORT_MULTIPLY_SHIFT;
1573	}
1574
1575	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1576	    DISPLAY_VER(dev_priv) < 5)
1577		sdvox |= SDVO_STALL_SELECT;
1578	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1579}
1580
1581static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1582{
1583	struct intel_sdvo_connector *intel_sdvo_connector =
1584		to_intel_sdvo_connector(&connector->base);
1585	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1586	u16 active_outputs = 0;
1587
1588	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1589
1590	return active_outputs & intel_sdvo_connector->output_flag;
1591}
1592
1593bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1594			     i915_reg_t sdvo_reg, enum pipe *pipe)
1595{
1596	u32 val;
1597
1598	val = intel_de_read(dev_priv, sdvo_reg);
1599
1600	/* asserts want to know the pipe even if the port is disabled */
1601	if (HAS_PCH_CPT(dev_priv))
1602		*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1603	else if (IS_CHERRYVIEW(dev_priv))
1604		*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1605	else
1606		*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1607
1608	return val & SDVO_ENABLE;
1609}
1610
1611static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1612				    enum pipe *pipe)
1613{
1614	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1615	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1616	u16 active_outputs = 0;
1617	bool ret;
1618
1619	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1620
1621	ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1622
1623	return ret || active_outputs;
1624}
1625
1626static void intel_sdvo_get_config(struct intel_encoder *encoder,
1627				  struct intel_crtc_state *pipe_config)
1628{
1629	struct drm_device *dev = encoder->base.dev;
1630	struct drm_i915_private *dev_priv = to_i915(dev);
1631	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1632	struct intel_sdvo_dtd dtd;
1633	int encoder_pixel_multiplier = 0;
1634	int dotclock;
1635	u32 flags = 0, sdvox;
1636	u8 val;
1637	bool ret;
1638
1639	pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1640
1641	sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1642
1643	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1644	if (!ret) {
1645		/*
1646		 * Some sdvo encoders are not spec compliant and don't
1647		 * implement the mandatory get_timings function.
1648		 */
1649		drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
1650		pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1651	} else {
1652		if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1653			flags |= DRM_MODE_FLAG_PHSYNC;
1654		else
1655			flags |= DRM_MODE_FLAG_NHSYNC;
1656
1657		if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1658			flags |= DRM_MODE_FLAG_PVSYNC;
1659		else
1660			flags |= DRM_MODE_FLAG_NVSYNC;
1661	}
1662
1663	pipe_config->hw.adjusted_mode.flags |= flags;
1664
1665	/*
1666	 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1667	 * the sdvo port register, on all other platforms it is part of the dpll
1668	 * state. Since the general pipe state readout happens before the
1669	 * encoder->get_config we so already have a valid pixel multplier on all
1670	 * other platfroms.
1671	 */
1672	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1673		pipe_config->pixel_multiplier =
1674			((sdvox & SDVO_PORT_MULTIPLY_MASK)
1675			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1676	}
1677
1678	dotclock = pipe_config->port_clock;
1679
1680	if (pipe_config->pixel_multiplier)
1681		dotclock /= pipe_config->pixel_multiplier;
1682
1683	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1684
1685	/* Cross check the port pixel multiplier with the sdvo encoder state. */
1686	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1687				 &val, 1)) {
1688		switch (val) {
1689		case SDVO_CLOCK_RATE_MULT_1X:
1690			encoder_pixel_multiplier = 1;
1691			break;
1692		case SDVO_CLOCK_RATE_MULT_2X:
1693			encoder_pixel_multiplier = 2;
1694			break;
1695		case SDVO_CLOCK_RATE_MULT_4X:
1696			encoder_pixel_multiplier = 4;
1697			break;
1698		}
1699	}
1700
1701	drm_WARN(dev,
1702		 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1703		 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1704		 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1705
1706	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY,
1707				 &val, 1)) {
1708		if (val == SDVO_COLORIMETRY_RGB220)
1709			pipe_config->limited_color_range = true;
1710	}
1711
1712	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1713				 &val, 1)) {
1714		u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
1715
1716		if ((val & mask) == mask)
1717			pipe_config->has_audio = true;
1718	}
1719
1720	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1721				 &val, 1)) {
1722		if (val == SDVO_ENCODE_HDMI)
1723			pipe_config->has_hdmi_sink = true;
1724	}
1725
1726	intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1727}
1728
1729static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1730{
1731	intel_sdvo_set_audio_state(intel_sdvo, 0);
1732}
1733
1734static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1735				    const struct intel_crtc_state *crtc_state,
1736				    const struct drm_connector_state *conn_state)
1737{
1738	const struct drm_display_mode *adjusted_mode =
1739		&crtc_state->hw.adjusted_mode;
1740	struct drm_connector *connector = conn_state->connector;
1741	u8 *eld = connector->eld;
1742
1743	eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
1744
1745	intel_sdvo_set_audio_state(intel_sdvo, 0);
1746
1747	intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1748				   SDVO_HBUF_TX_DISABLED,
1749				   eld, drm_eld_size(eld));
1750
1751	intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1752				   SDVO_AUDIO_PRESENCE_DETECT);
1753}
1754
1755static void intel_disable_sdvo(struct intel_atomic_state *state,
1756			       struct intel_encoder *encoder,
1757			       const struct intel_crtc_state *old_crtc_state,
1758			       const struct drm_connector_state *conn_state)
1759{
1760	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1761	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1762	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1763	u32 temp;
1764
1765	if (old_crtc_state->has_audio)
1766		intel_sdvo_disable_audio(intel_sdvo);
1767
1768	intel_sdvo_set_active_outputs(intel_sdvo, 0);
1769	if (0)
1770		intel_sdvo_set_encoder_power_state(intel_sdvo,
1771						   DRM_MODE_DPMS_OFF);
1772
1773	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1774
1775	temp &= ~SDVO_ENABLE;
1776	intel_sdvo_write_sdvox(intel_sdvo, temp);
1777
1778	/*
1779	 * HW workaround for IBX, we need to move the port
1780	 * to transcoder A after disabling it to allow the
1781	 * matching DP port to be enabled on transcoder A.
1782	 */
1783	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1784		/*
1785		 * We get CPU/PCH FIFO underruns on the other pipe when
1786		 * doing the workaround. Sweep them under the rug.
1787		 */
1788		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1789		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1790
1791		temp &= ~SDVO_PIPE_SEL_MASK;
1792		temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1793		intel_sdvo_write_sdvox(intel_sdvo, temp);
1794
1795		temp &= ~SDVO_ENABLE;
1796		intel_sdvo_write_sdvox(intel_sdvo, temp);
1797
1798		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1799		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1800		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1801	}
1802}
1803
1804static void pch_disable_sdvo(struct intel_atomic_state *state,
1805			     struct intel_encoder *encoder,
1806			     const struct intel_crtc_state *old_crtc_state,
1807			     const struct drm_connector_state *old_conn_state)
1808{
1809}
1810
1811static void pch_post_disable_sdvo(struct intel_atomic_state *state,
1812				  struct intel_encoder *encoder,
1813				  const struct intel_crtc_state *old_crtc_state,
1814				  const struct drm_connector_state *old_conn_state)
1815{
1816	intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state);
1817}
1818
1819static void intel_enable_sdvo(struct intel_atomic_state *state,
1820			      struct intel_encoder *encoder,
1821			      const struct intel_crtc_state *pipe_config,
1822			      const struct drm_connector_state *conn_state)
1823{
1824	struct drm_device *dev = encoder->base.dev;
1825	struct drm_i915_private *dev_priv = to_i915(dev);
1826	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1827	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
1828	u32 temp;
1829	bool input1, input2;
1830	int i;
1831	bool success;
1832
1833	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1834	temp |= SDVO_ENABLE;
1835	intel_sdvo_write_sdvox(intel_sdvo, temp);
1836
1837	for (i = 0; i < 2; i++)
1838		intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1839
1840	success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1841	/*
1842	 * Warn if the device reported failure to sync.
1843	 *
1844	 * A lot of SDVO devices fail to notify of sync, but it's
1845	 * a given it the status is a success, we succeeded.
1846	 */
1847	if (success && !input1) {
1848		drm_dbg_kms(&dev_priv->drm,
1849			    "First %s output reported failure to "
1850			    "sync\n", SDVO_NAME(intel_sdvo));
1851	}
1852
1853	if (0)
1854		intel_sdvo_set_encoder_power_state(intel_sdvo,
1855						   DRM_MODE_DPMS_ON);
1856	intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1857
1858	if (pipe_config->has_audio)
1859		intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
1860}
1861
1862static enum drm_mode_status
1863intel_sdvo_mode_valid(struct drm_connector *connector,
1864		      struct drm_display_mode *mode)
1865{
1866	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
1867	struct intel_sdvo_connector *intel_sdvo_connector =
1868		to_intel_sdvo_connector(connector);
1869	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1870	bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state);
1871	int clock = mode->clock;
1872
1873	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1874		return MODE_NO_DBLESCAN;
1875
1876
1877	if (clock > max_dotclk)
1878		return MODE_CLOCK_HIGH;
1879
1880	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1881		if (!has_hdmi_sink)
1882			return MODE_CLOCK_LOW;
1883		clock *= 2;
1884	}
1885
1886	if (intel_sdvo->pixel_clock_min > clock)
1887		return MODE_CLOCK_LOW;
1888
1889	if (intel_sdvo->pixel_clock_max < clock)
1890		return MODE_CLOCK_HIGH;
1891
1892	if (IS_LVDS(intel_sdvo_connector)) {
1893		const struct drm_display_mode *fixed_mode =
1894			intel_sdvo_connector->base.panel.fixed_mode;
1895
1896		if (mode->hdisplay > fixed_mode->hdisplay)
1897			return MODE_PANEL;
1898
1899		if (mode->vdisplay > fixed_mode->vdisplay)
1900			return MODE_PANEL;
 
1901	}
1902
1903	return MODE_OK;
1904}
1905
1906static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1907{
1908	BUILD_BUG_ON(sizeof(*caps) != 8);
1909	if (!intel_sdvo_get_value(intel_sdvo,
1910				  SDVO_CMD_GET_DEVICE_CAPS,
1911				  caps, sizeof(*caps)))
1912		return false;
1913
1914	DRM_DEBUG_KMS("SDVO capabilities:\n"
1915		      "  vendor_id: %d\n"
1916		      "  device_id: %d\n"
1917		      "  device_rev_id: %d\n"
1918		      "  sdvo_version_major: %d\n"
1919		      "  sdvo_version_minor: %d\n"
1920		      "  sdvo_inputs_mask: %d\n"
1921		      "  smooth_scaling: %d\n"
1922		      "  sharp_scaling: %d\n"
1923		      "  up_scaling: %d\n"
1924		      "  down_scaling: %d\n"
1925		      "  stall_support: %d\n"
1926		      "  output_flags: %d\n",
1927		      caps->vendor_id,
1928		      caps->device_id,
1929		      caps->device_rev_id,
1930		      caps->sdvo_version_major,
1931		      caps->sdvo_version_minor,
1932		      caps->sdvo_inputs_mask,
1933		      caps->smooth_scaling,
1934		      caps->sharp_scaling,
1935		      caps->up_scaling,
1936		      caps->down_scaling,
1937		      caps->stall_support,
1938		      caps->output_flags);
1939
1940	return true;
1941}
1942
1943static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
1944{
1945	u8 cap;
1946
1947	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP,
1948				  &cap, sizeof(cap)))
1949		return SDVO_COLORIMETRY_RGB256;
1950
1951	return cap;
1952}
1953
1954static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1955{
1956	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1957	u16 hotplug;
1958
1959	if (!I915_HAS_HOTPLUG(dev_priv))
1960		return 0;
1961
1962	/*
1963	 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1964	 * on the line.
1965	 */
1966	if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1967		return 0;
1968
1969	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1970					&hotplug, sizeof(hotplug)))
1971		return 0;
1972
1973	return hotplug;
1974}
1975
1976static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1977{
1978	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1979
1980	intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1981			     &intel_sdvo->hotplug_active, 2);
1982}
1983
1984static enum intel_hotplug_state
1985intel_sdvo_hotplug(struct intel_encoder *encoder,
1986		   struct intel_connector *connector)
1987{
1988	intel_sdvo_enable_hotplug(encoder);
1989
1990	return intel_encoder_hotplug(encoder, connector);
1991}
1992
1993static bool
1994intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1995{
1996	/* Is there more than one type of output? */
1997	return hweight16(intel_sdvo->caps.output_flags) > 1;
1998}
1999
2000static struct edid *
2001intel_sdvo_get_edid(struct drm_connector *connector)
2002{
2003	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2004	return drm_get_edid(connector, &sdvo->ddc);
2005}
2006
2007/* Mac mini hack -- use the same DDC as the analog connector */
2008static struct edid *
2009intel_sdvo_get_analog_edid(struct drm_connector *connector)
2010{
2011	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2012
2013	return drm_get_edid(connector,
2014			    intel_gmbus_get_adapter(dev_priv,
2015						    dev_priv->vbt.crt_ddc_pin));
2016}
2017
2018static enum drm_connector_status
2019intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2020{
2021	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2022	struct intel_sdvo_connector *intel_sdvo_connector =
2023		to_intel_sdvo_connector(connector);
2024	enum drm_connector_status status;
2025	struct edid *edid;
2026
2027	edid = intel_sdvo_get_edid(connector);
2028
2029	if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
2030		u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
2031
2032		/*
2033		 * Don't use the 1 as the argument of DDC bus switch to get
2034		 * the EDID. It is used for SDVO SPD ROM.
2035		 */
2036		for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
2037			intel_sdvo->ddc_bus = ddc;
2038			edid = intel_sdvo_get_edid(connector);
2039			if (edid)
2040				break;
2041		}
2042		/*
2043		 * If we found the EDID on the other bus,
2044		 * assume that is the correct DDC bus.
2045		 */
2046		if (edid == NULL)
2047			intel_sdvo->ddc_bus = saved_ddc;
2048	}
2049
2050	/*
2051	 * When there is no edid and no monitor is connected with VGA
2052	 * port, try to use the CRT ddc to read the EDID for DVI-connector.
2053	 */
2054	if (edid == NULL)
2055		edid = intel_sdvo_get_analog_edid(connector);
2056
2057	status = connector_status_unknown;
2058	if (edid != NULL) {
2059		/* DDC bus is shared, match EDID to connector type */
2060		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
2061			status = connector_status_connected;
2062			if (intel_sdvo_connector->is_hdmi) {
2063				intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
2064				intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
2065			}
2066		} else
2067			status = connector_status_disconnected;
2068		kfree(edid);
2069	}
2070
2071	return status;
2072}
2073
2074static bool
2075intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
2076				  struct edid *edid)
2077{
2078	bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
2079	bool connector_is_digital = !!IS_DIGITAL(sdvo);
2080
2081	DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
2082		      connector_is_digital, monitor_is_digital);
2083	return connector_is_digital == monitor_is_digital;
2084}
2085
2086static enum drm_connector_status
2087intel_sdvo_detect(struct drm_connector *connector, bool force)
2088{
2089	struct drm_i915_private *i915 = to_i915(connector->dev);
2090	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2091	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2092	enum drm_connector_status ret;
2093	u16 response;
2094
2095	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2096		      connector->base.id, connector->name);
2097
2098	if (!INTEL_DISPLAY_ENABLED(i915))
2099		return connector_status_disconnected;
2100
2101	if (!intel_sdvo_get_value(intel_sdvo,
2102				  SDVO_CMD_GET_ATTACHED_DISPLAYS,
2103				  &response, 2))
2104		return connector_status_unknown;
2105
2106	DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2107		      response & 0xff, response >> 8,
2108		      intel_sdvo_connector->output_flag);
2109
2110	if (response == 0)
2111		return connector_status_disconnected;
2112
2113	intel_sdvo->attached_output = response;
2114
2115	intel_sdvo->has_hdmi_monitor = false;
2116	intel_sdvo->has_hdmi_audio = false;
2117
2118	if ((intel_sdvo_connector->output_flag & response) == 0)
2119		ret = connector_status_disconnected;
2120	else if (IS_TMDS(intel_sdvo_connector))
2121		ret = intel_sdvo_tmds_sink_detect(connector);
2122	else {
2123		struct edid *edid;
2124
2125		/* if we have an edid check it matches the connection */
2126		edid = intel_sdvo_get_edid(connector);
2127		if (edid == NULL)
2128			edid = intel_sdvo_get_analog_edid(connector);
2129		if (edid != NULL) {
2130			if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
2131							      edid))
2132				ret = connector_status_connected;
2133			else
2134				ret = connector_status_disconnected;
2135
2136			kfree(edid);
2137		} else
2138			ret = connector_status_connected;
2139	}
2140
2141	return ret;
2142}
2143
2144static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2145{
2146	int num_modes = 0;
2147	struct edid *edid;
2148
2149	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2150		      connector->base.id, connector->name);
2151
2152	/* set the bus switch and get the modes */
2153	edid = intel_sdvo_get_edid(connector);
2154
2155	/*
2156	 * Mac mini hack.  On this device, the DVI-I connector shares one DDC
2157	 * link between analog and digital outputs. So, if the regular SDVO
2158	 * DDC fails, check to see if the analog output is disconnected, in
2159	 * which case we'll look there for the digital DDC data.
2160	 */
2161	if (!edid)
2162		edid = intel_sdvo_get_analog_edid(connector);
2163
2164	if (!edid)
2165		return 0;
2166
2167	if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2168					      edid))
2169		num_modes += intel_connector_update_modes(connector, edid);
2170
2171	kfree(edid);
2172
2173	return num_modes;
2174}
2175
2176/*
2177 * Set of SDVO TV modes.
2178 * Note!  This is in reply order (see loop in get_tv_modes).
2179 * XXX: all 60Hz refresh?
2180 */
2181static const struct drm_display_mode sdvo_tv_modes[] = {
2182	{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2183		   416, 0, 200, 201, 232, 233, 0,
2184		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2185	{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2186		   416, 0, 240, 241, 272, 273, 0,
2187		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2188	{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2189		   496, 0, 300, 301, 332, 333, 0,
2190		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2191	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2192		   736, 0, 350, 351, 382, 383, 0,
2193		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2194	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2195		   736, 0, 400, 401, 432, 433, 0,
2196		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2197	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2198		   736, 0, 480, 481, 512, 513, 0,
2199		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2200	{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2201		   800, 0, 480, 481, 512, 513, 0,
2202		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2203	{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2204		   800, 0, 576, 577, 608, 609, 0,
2205		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2206	{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2207		   816, 0, 350, 351, 382, 383, 0,
2208		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2209	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2210		   816, 0, 400, 401, 432, 433, 0,
2211		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2212	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2213		   816, 0, 480, 481, 512, 513, 0,
2214		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2215	{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2216		   816, 0, 540, 541, 572, 573, 0,
2217		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2218	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2219		   816, 0, 576, 577, 608, 609, 0,
2220		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2221	{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2222		   864, 0, 576, 577, 608, 609, 0,
2223		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2224	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2225		   896, 0, 600, 601, 632, 633, 0,
2226		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2227	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2228		   928, 0, 624, 625, 656, 657, 0,
2229		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2230	{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2231		   1016, 0, 766, 767, 798, 799, 0,
2232		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2233	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2234		   1120, 0, 768, 769, 800, 801, 0,
2235		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2236	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2237		   1376, 0, 1024, 1025, 1056, 1057, 0,
2238		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2239};
2240
2241static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
2242{
2243	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2244	const struct drm_connector_state *conn_state = connector->state;
2245	struct intel_sdvo_sdtv_resolution_request tv_res;
2246	u32 reply = 0, format_map = 0;
2247	int num_modes = 0;
2248	int i;
2249
2250	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2251		      connector->base.id, connector->name);
2252
2253	/*
2254	 * Read the list of supported input resolutions for the selected TV
2255	 * format.
2256	 */
2257	format_map = 1 << conn_state->tv.mode;
2258	memcpy(&tv_res, &format_map,
2259	       min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2260
2261	if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2262		return 0;
2263
2264	BUILD_BUG_ON(sizeof(tv_res) != 3);
2265	if (!intel_sdvo_write_cmd(intel_sdvo,
2266				  SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2267				  &tv_res, sizeof(tv_res)))
2268		return 0;
2269	if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2270		return 0;
2271
2272	for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) {
2273		if (reply & (1 << i)) {
2274			struct drm_display_mode *nmode;
2275			nmode = drm_mode_duplicate(connector->dev,
2276						   &sdvo_tv_modes[i]);
2277			if (nmode) {
2278				drm_mode_probed_add(connector, nmode);
2279				num_modes++;
2280			}
2281		}
2282	}
2283
2284	return num_modes;
2285}
2286
2287static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2288{
2289	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2290	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2291	struct drm_display_mode *newmode;
2292	int num_modes = 0;
2293
2294	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2295		    connector->base.id, connector->name);
2296
2297	/*
2298	 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2299	 * SDVO->LVDS transcoders can't cope with the EDID mode.
2300	 */
2301	if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2302		newmode = drm_mode_duplicate(connector->dev,
2303					     dev_priv->vbt.sdvo_lvds_vbt_mode);
2304		if (newmode != NULL) {
2305			/* Guarantee the mode is preferred */
2306			newmode->type = (DRM_MODE_TYPE_PREFERRED |
2307					 DRM_MODE_TYPE_DRIVER);
2308			drm_mode_probed_add(connector, newmode);
2309			num_modes++;
2310		}
2311	}
2312
2313	/*
2314	 * Attempt to get the mode list from DDC.
2315	 * Assume that the preferred modes are
2316	 * arranged in priority order.
2317	 */
2318	num_modes += intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2319
2320	return num_modes;
2321}
2322
2323static int intel_sdvo_get_modes(struct drm_connector *connector)
2324{
2325	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2326
2327	if (IS_TV(intel_sdvo_connector))
2328		return intel_sdvo_get_tv_modes(connector);
2329	else if (IS_LVDS(intel_sdvo_connector))
2330		return intel_sdvo_get_lvds_modes(connector);
2331	else
2332		return intel_sdvo_get_ddc_modes(connector);
2333}
2334
2335static int
2336intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2337					 const struct drm_connector_state *state,
2338					 struct drm_property *property,
2339					 u64 *val)
2340{
2341	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2342	const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2343
2344	if (property == intel_sdvo_connector->tv_format) {
2345		int i;
2346
2347		for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2348			if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2349				*val = i;
2350
2351				return 0;
2352			}
2353
2354		drm_WARN_ON(connector->dev, 1);
2355		*val = 0;
2356	} else if (property == intel_sdvo_connector->top ||
2357		   property == intel_sdvo_connector->bottom)
2358		*val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2359	else if (property == intel_sdvo_connector->left ||
2360		 property == intel_sdvo_connector->right)
2361		*val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2362	else if (property == intel_sdvo_connector->hpos)
2363		*val = sdvo_state->tv.hpos;
2364	else if (property == intel_sdvo_connector->vpos)
2365		*val = sdvo_state->tv.vpos;
2366	else if (property == intel_sdvo_connector->saturation)
2367		*val = state->tv.saturation;
2368	else if (property == intel_sdvo_connector->contrast)
2369		*val = state->tv.contrast;
2370	else if (property == intel_sdvo_connector->hue)
2371		*val = state->tv.hue;
2372	else if (property == intel_sdvo_connector->brightness)
2373		*val = state->tv.brightness;
2374	else if (property == intel_sdvo_connector->sharpness)
2375		*val = sdvo_state->tv.sharpness;
2376	else if (property == intel_sdvo_connector->flicker_filter)
2377		*val = sdvo_state->tv.flicker_filter;
2378	else if (property == intel_sdvo_connector->flicker_filter_2d)
2379		*val = sdvo_state->tv.flicker_filter_2d;
2380	else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2381		*val = sdvo_state->tv.flicker_filter_adaptive;
2382	else if (property == intel_sdvo_connector->tv_chroma_filter)
2383		*val = sdvo_state->tv.chroma_filter;
2384	else if (property == intel_sdvo_connector->tv_luma_filter)
2385		*val = sdvo_state->tv.luma_filter;
2386	else if (property == intel_sdvo_connector->dot_crawl)
2387		*val = sdvo_state->tv.dot_crawl;
2388	else
2389		return intel_digital_connector_atomic_get_property(connector, state, property, val);
2390
2391	return 0;
2392}
2393
2394static int
2395intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2396					 struct drm_connector_state *state,
2397					 struct drm_property *property,
2398					 u64 val)
2399{
2400	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2401	struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2402
2403	if (property == intel_sdvo_connector->tv_format) {
2404		state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2405
2406		if (state->crtc) {
2407			struct drm_crtc_state *crtc_state =
2408				drm_atomic_get_new_crtc_state(state->state, state->crtc);
2409
2410			crtc_state->connectors_changed = true;
2411		}
2412	} else if (property == intel_sdvo_connector->top ||
2413		   property == intel_sdvo_connector->bottom)
2414		/* Cannot set these independent from each other */
2415		sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2416	else if (property == intel_sdvo_connector->left ||
2417		 property == intel_sdvo_connector->right)
2418		/* Cannot set these independent from each other */
2419		sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2420	else if (property == intel_sdvo_connector->hpos)
2421		sdvo_state->tv.hpos = val;
2422	else if (property == intel_sdvo_connector->vpos)
2423		sdvo_state->tv.vpos = val;
2424	else if (property == intel_sdvo_connector->saturation)
2425		state->tv.saturation = val;
2426	else if (property == intel_sdvo_connector->contrast)
2427		state->tv.contrast = val;
2428	else if (property == intel_sdvo_connector->hue)
2429		state->tv.hue = val;
2430	else if (property == intel_sdvo_connector->brightness)
2431		state->tv.brightness = val;
2432	else if (property == intel_sdvo_connector->sharpness)
2433		sdvo_state->tv.sharpness = val;
2434	else if (property == intel_sdvo_connector->flicker_filter)
2435		sdvo_state->tv.flicker_filter = val;
2436	else if (property == intel_sdvo_connector->flicker_filter_2d)
2437		sdvo_state->tv.flicker_filter_2d = val;
2438	else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2439		sdvo_state->tv.flicker_filter_adaptive = val;
2440	else if (property == intel_sdvo_connector->tv_chroma_filter)
2441		sdvo_state->tv.chroma_filter = val;
2442	else if (property == intel_sdvo_connector->tv_luma_filter)
2443		sdvo_state->tv.luma_filter = val;
2444	else if (property == intel_sdvo_connector->dot_crawl)
2445		sdvo_state->tv.dot_crawl = val;
2446	else
2447		return intel_digital_connector_atomic_set_property(connector, state, property, val);
2448
2449	return 0;
2450}
2451
2452static int
2453intel_sdvo_connector_register(struct drm_connector *connector)
2454{
2455	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2456	int ret;
2457
2458	ret = intel_connector_register(connector);
2459	if (ret)
2460		return ret;
2461
2462	return sysfs_create_link(&connector->kdev->kobj,
2463				 &sdvo->ddc.dev.kobj,
2464				 sdvo->ddc.dev.kobj.name);
2465}
2466
2467static void
2468intel_sdvo_connector_unregister(struct drm_connector *connector)
2469{
2470	struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector));
2471
2472	sysfs_remove_link(&connector->kdev->kobj,
2473			  sdvo->ddc.dev.kobj.name);
2474	intel_connector_unregister(connector);
2475}
2476
2477static struct drm_connector_state *
2478intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2479{
2480	struct intel_sdvo_connector_state *state;
2481
2482	state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2483	if (!state)
2484		return NULL;
2485
2486	__drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2487	return &state->base.base;
2488}
2489
2490static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2491	.detect = intel_sdvo_detect,
2492	.fill_modes = drm_helper_probe_single_connector_modes,
2493	.atomic_get_property = intel_sdvo_connector_atomic_get_property,
2494	.atomic_set_property = intel_sdvo_connector_atomic_set_property,
2495	.late_register = intel_sdvo_connector_register,
2496	.early_unregister = intel_sdvo_connector_unregister,
2497	.destroy = intel_connector_destroy,
2498	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2499	.atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2500};
2501
2502static int intel_sdvo_atomic_check(struct drm_connector *conn,
2503				   struct drm_atomic_state *state)
2504{
2505	struct drm_connector_state *new_conn_state =
2506		drm_atomic_get_new_connector_state(state, conn);
2507	struct drm_connector_state *old_conn_state =
2508		drm_atomic_get_old_connector_state(state, conn);
2509	struct intel_sdvo_connector_state *old_state =
2510		to_intel_sdvo_connector_state(old_conn_state);
2511	struct intel_sdvo_connector_state *new_state =
2512		to_intel_sdvo_connector_state(new_conn_state);
2513
2514	if (new_conn_state->crtc &&
2515	    (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2516	     memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2517		struct drm_crtc_state *crtc_state =
2518			drm_atomic_get_new_crtc_state(state,
2519						      new_conn_state->crtc);
2520
2521		crtc_state->connectors_changed = true;
2522	}
2523
2524	return intel_digital_connector_atomic_check(conn, state);
2525}
2526
2527static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2528	.get_modes = intel_sdvo_get_modes,
2529	.mode_valid = intel_sdvo_mode_valid,
2530	.atomic_check = intel_sdvo_atomic_check,
2531};
2532
2533static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2534{
2535	struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2536
2537	i2c_del_adapter(&intel_sdvo->ddc);
2538	intel_encoder_destroy(encoder);
2539}
2540
2541static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2542	.destroy = intel_sdvo_enc_destroy,
2543};
2544
2545static void
2546intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2547{
2548	u16 mask = 0;
2549	unsigned int num_bits;
2550
2551	/*
2552	 * Make a mask of outputs less than or equal to our own priority in the
2553	 * list.
2554	 */
2555	switch (sdvo->controlled_output) {
2556	case SDVO_OUTPUT_LVDS1:
2557		mask |= SDVO_OUTPUT_LVDS1;
2558		fallthrough;
2559	case SDVO_OUTPUT_LVDS0:
2560		mask |= SDVO_OUTPUT_LVDS0;
2561		fallthrough;
2562	case SDVO_OUTPUT_TMDS1:
2563		mask |= SDVO_OUTPUT_TMDS1;
2564		fallthrough;
2565	case SDVO_OUTPUT_TMDS0:
2566		mask |= SDVO_OUTPUT_TMDS0;
2567		fallthrough;
2568	case SDVO_OUTPUT_RGB1:
2569		mask |= SDVO_OUTPUT_RGB1;
2570		fallthrough;
2571	case SDVO_OUTPUT_RGB0:
2572		mask |= SDVO_OUTPUT_RGB0;
2573		break;
2574	}
2575
2576	/* Count bits to find what number we are in the priority list. */
2577	mask &= sdvo->caps.output_flags;
2578	num_bits = hweight16(mask);
2579	/* If more than 3 outputs, default to DDC bus 3 for now. */
2580	if (num_bits > 3)
2581		num_bits = 3;
2582
2583	/* Corresponds to SDVO_CONTROL_BUS_DDCx */
2584	sdvo->ddc_bus = 1 << num_bits;
2585}
2586
2587/*
2588 * Choose the appropriate DDC bus for control bus switch command for this
2589 * SDVO output based on the controlled output.
2590 *
2591 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2592 * outputs, then LVDS outputs.
2593 */
2594static void
2595intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2596			  struct intel_sdvo *sdvo)
2597{
2598	struct sdvo_device_mapping *mapping;
2599
2600	if (sdvo->port == PORT_B)
2601		mapping = &dev_priv->vbt.sdvo_mappings[0];
2602	else
2603		mapping = &dev_priv->vbt.sdvo_mappings[1];
2604
2605	if (mapping->initialized)
2606		sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2607	else
2608		intel_sdvo_guess_ddc_bus(sdvo);
2609}
2610
2611static void
2612intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2613			  struct intel_sdvo *sdvo)
2614{
2615	struct sdvo_device_mapping *mapping;
2616	u8 pin;
2617
2618	if (sdvo->port == PORT_B)
2619		mapping = &dev_priv->vbt.sdvo_mappings[0];
2620	else
2621		mapping = &dev_priv->vbt.sdvo_mappings[1];
2622
2623	if (mapping->initialized &&
2624	    intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2625		pin = mapping->i2c_pin;
2626	else
2627		pin = GMBUS_PIN_DPB;
2628
2629	sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2630
2631	/*
2632	 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2633	 * our code totally fails once we start using gmbus. Hence fall back to
2634	 * bit banging for now.
2635	 */
2636	intel_gmbus_force_bit(sdvo->i2c, true);
2637}
2638
2639/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2640static void
2641intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2642{
2643	intel_gmbus_force_bit(sdvo->i2c, false);
2644}
2645
2646static bool
2647intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2648{
2649	return intel_sdvo_check_supp_encode(intel_sdvo);
2650}
2651
2652static u8
2653intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2654			  struct intel_sdvo *sdvo)
2655{
2656	struct sdvo_device_mapping *my_mapping, *other_mapping;
2657
2658	if (sdvo->port == PORT_B) {
2659		my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2660		other_mapping = &dev_priv->vbt.sdvo_mappings[1];
2661	} else {
2662		my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2663		other_mapping = &dev_priv->vbt.sdvo_mappings[0];
2664	}
2665
2666	/* If the BIOS described our SDVO device, take advantage of it. */
2667	if (my_mapping->slave_addr)
2668		return my_mapping->slave_addr;
2669
2670	/*
2671	 * If the BIOS only described a different SDVO device, use the
2672	 * address that it isn't using.
2673	 */
2674	if (other_mapping->slave_addr) {
2675		if (other_mapping->slave_addr == 0x70)
2676			return 0x72;
2677		else
2678			return 0x70;
2679	}
2680
2681	/*
2682	 * No SDVO device info is found for another DVO port,
2683	 * so use mapping assumption we had before BIOS parsing.
2684	 */
2685	if (sdvo->port == PORT_B)
2686		return 0x70;
2687	else
2688		return 0x72;
2689}
2690
2691static int
2692intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2693			  struct intel_sdvo *encoder)
2694{
2695	struct drm_connector *drm_connector;
2696	int ret;
2697
2698	drm_connector = &connector->base.base;
2699	ret = drm_connector_init(encoder->base.base.dev,
2700			   drm_connector,
2701			   &intel_sdvo_connector_funcs,
2702			   connector->base.base.connector_type);
2703	if (ret < 0)
2704		return ret;
2705
2706	drm_connector_helper_add(drm_connector,
2707				 &intel_sdvo_connector_helper_funcs);
2708
2709	connector->base.base.interlace_allowed = 1;
2710	connector->base.base.doublescan_allowed = 0;
2711	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
 
2712	connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2713
2714	intel_connector_attach_encoder(&connector->base, &encoder->base);
2715
2716	return 0;
2717}
2718
2719static void
2720intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2721			       struct intel_sdvo_connector *connector)
2722{
2723	intel_attach_force_audio_property(&connector->base.base);
2724	if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220)
2725		intel_attach_broadcast_rgb_property(&connector->base.base);
2726	intel_attach_aspect_ratio_property(&connector->base.base);
2727}
2728
2729static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2730{
2731	struct intel_sdvo_connector *sdvo_connector;
2732	struct intel_sdvo_connector_state *conn_state;
2733
2734	sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2735	if (!sdvo_connector)
2736		return NULL;
2737
2738	conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2739	if (!conn_state) {
2740		kfree(sdvo_connector);
2741		return NULL;
2742	}
2743
2744	__drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2745					    &conn_state->base.base);
2746
 
 
2747	return sdvo_connector;
2748}
2749
2750static bool
2751intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2752{
2753	struct drm_encoder *encoder = &intel_sdvo->base.base;
2754	struct drm_connector *connector;
2755	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2756	struct intel_connector *intel_connector;
2757	struct intel_sdvo_connector *intel_sdvo_connector;
2758
2759	DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2760
2761	intel_sdvo_connector = intel_sdvo_connector_alloc();
2762	if (!intel_sdvo_connector)
2763		return false;
2764
2765	if (device == 0) {
2766		intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2767		intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2768	} else if (device == 1) {
2769		intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2770		intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2771	}
2772
2773	intel_connector = &intel_sdvo_connector->base;
2774	connector = &intel_connector->base;
2775	if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2776		intel_sdvo_connector->output_flag) {
2777		intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2778		/*
2779		 * Some SDVO devices have one-shot hotplug interrupts.
2780		 * Ensure that they get re-enabled when an interrupt happens.
2781		 */
2782		intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2783		intel_encoder->hotplug = intel_sdvo_hotplug;
2784		intel_sdvo_enable_hotplug(intel_encoder);
2785	} else {
2786		intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2787	}
2788	encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2789	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2790
2791	if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2792		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2793		intel_sdvo_connector->is_hdmi = true;
2794	}
2795
2796	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2797		kfree(intel_sdvo_connector);
2798		return false;
2799	}
2800
2801	if (intel_sdvo_connector->is_hdmi)
2802		intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2803
2804	return true;
2805}
2806
2807static bool
2808intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2809{
2810	struct drm_encoder *encoder = &intel_sdvo->base.base;
2811	struct drm_connector *connector;
2812	struct intel_connector *intel_connector;
2813	struct intel_sdvo_connector *intel_sdvo_connector;
2814
2815	DRM_DEBUG_KMS("initialising TV type %d\n", type);
2816
2817	intel_sdvo_connector = intel_sdvo_connector_alloc();
2818	if (!intel_sdvo_connector)
2819		return false;
2820
2821	intel_connector = &intel_sdvo_connector->base;
2822	connector = &intel_connector->base;
2823	encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2824	connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2825
2826	intel_sdvo->controlled_output |= type;
2827	intel_sdvo_connector->output_flag = type;
2828
2829	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2830		kfree(intel_sdvo_connector);
2831		return false;
2832	}
2833
2834	if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2835		goto err;
2836
2837	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2838		goto err;
2839
2840	return true;
2841
2842err:
2843	intel_connector_destroy(connector);
2844	return false;
2845}
2846
2847static bool
2848intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2849{
2850	struct drm_encoder *encoder = &intel_sdvo->base.base;
2851	struct drm_connector *connector;
2852	struct intel_connector *intel_connector;
2853	struct intel_sdvo_connector *intel_sdvo_connector;
2854
2855	DRM_DEBUG_KMS("initialising analog device %d\n", device);
2856
2857	intel_sdvo_connector = intel_sdvo_connector_alloc();
2858	if (!intel_sdvo_connector)
2859		return false;
2860
2861	intel_connector = &intel_sdvo_connector->base;
2862	connector = &intel_connector->base;
2863	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2864	encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2865	connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2866
2867	if (device == 0) {
2868		intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2869		intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2870	} else if (device == 1) {
2871		intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2872		intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2873	}
2874
2875	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2876		kfree(intel_sdvo_connector);
2877		return false;
2878	}
2879
2880	return true;
2881}
2882
2883static bool
2884intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2885{
2886	struct drm_encoder *encoder = &intel_sdvo->base.base;
 
2887	struct drm_connector *connector;
2888	struct intel_connector *intel_connector;
2889	struct intel_sdvo_connector *intel_sdvo_connector;
2890	struct drm_display_mode *mode;
2891
2892	DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2893
2894	intel_sdvo_connector = intel_sdvo_connector_alloc();
2895	if (!intel_sdvo_connector)
2896		return false;
2897
2898	intel_connector = &intel_sdvo_connector->base;
2899	connector = &intel_connector->base;
2900	encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2901	connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2902
2903	if (device == 0) {
2904		intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2905		intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2906	} else if (device == 1) {
2907		intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2908		intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2909	}
2910
2911	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2912		kfree(intel_sdvo_connector);
2913		return false;
2914	}
2915
2916	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2917		goto err;
2918
2919	intel_sdvo_get_lvds_modes(connector);
2920
2921	list_for_each_entry(mode, &connector->probed_modes, head) {
2922		if (mode->type & DRM_MODE_TYPE_PREFERRED) {
2923			struct drm_display_mode *fixed_mode =
2924				drm_mode_duplicate(connector->dev, mode);
 
2925
2926			intel_panel_init(&intel_connector->panel,
2927					 fixed_mode, NULL);
2928			break;
2929		}
 
 
 
2930	}
2931
2932	if (!intel_connector->panel.fixed_mode)
 
 
2933		goto err;
2934
2935	return true;
2936
2937err:
2938	intel_connector_destroy(connector);
2939	return false;
2940}
2941
2942static bool
2943intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags)
2944{
 
 
2945	/* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
 
 
2946
2947	if (flags & SDVO_OUTPUT_TMDS0)
2948		if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2949			return false;
2950
2951	if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2952		if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2953			return false;
2954
2955	/* TV has no XXX1 function block */
2956	if (flags & SDVO_OUTPUT_SVID0)
2957		if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2958			return false;
2959
2960	if (flags & SDVO_OUTPUT_CVBS0)
2961		if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2962			return false;
 
 
 
 
 
 
 
 
 
 
2963
2964	if (flags & SDVO_OUTPUT_YPRPB0)
2965		if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2966			return false;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2967
2968	if (flags & SDVO_OUTPUT_RGB0)
2969		if (!intel_sdvo_analog_init(intel_sdvo, 0))
2970			return false;
2971
2972	if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2973		if (!intel_sdvo_analog_init(intel_sdvo, 1))
2974			return false;
 
 
2975
2976	if (flags & SDVO_OUTPUT_LVDS0)
2977		if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2978			return false;
2979
2980	if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2981		if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2982			return false;
2983
2984	if ((flags & SDVO_OUTPUT_MASK) == 0) {
2985		unsigned char bytes[2];
2986
2987		intel_sdvo->controlled_output = 0;
2988		memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2989		DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2990			      SDVO_NAME(intel_sdvo),
2991			      bytes[0], bytes[1]);
2992		return false;
2993	}
 
2994	intel_sdvo->base.pipe_mask = ~0;
2995
2996	return true;
2997}
2998
2999static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
3000{
3001	struct drm_device *dev = intel_sdvo->base.base.dev;
3002	struct drm_connector *connector, *tmp;
3003
3004	list_for_each_entry_safe(connector, tmp,
3005				 &dev->mode_config.connector_list, head) {
3006		if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
3007			drm_connector_unregister(connector);
3008			intel_connector_destroy(connector);
3009		}
3010	}
3011}
3012
3013static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
3014					  struct intel_sdvo_connector *intel_sdvo_connector,
3015					  int type)
3016{
3017	struct drm_device *dev = intel_sdvo->base.base.dev;
3018	struct intel_sdvo_tv_format format;
3019	u32 format_map, i;
3020
3021	if (!intel_sdvo_set_target_output(intel_sdvo, type))
3022		return false;
3023
3024	BUILD_BUG_ON(sizeof(format) != 6);
3025	if (!intel_sdvo_get_value(intel_sdvo,
3026				  SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
3027				  &format, sizeof(format)))
3028		return false;
3029
3030	memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
3031
3032	if (format_map == 0)
3033		return false;
3034
3035	intel_sdvo_connector->format_supported_num = 0;
3036	for (i = 0 ; i < TV_FORMAT_NUM; i++)
3037		if (format_map & (1 << i))
3038			intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
3039
3040
3041	intel_sdvo_connector->tv_format =
3042			drm_property_create(dev, DRM_MODE_PROP_ENUM,
3043					    "mode", intel_sdvo_connector->format_supported_num);
3044	if (!intel_sdvo_connector->tv_format)
3045		return false;
3046
3047	for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
3048		drm_property_add_enum(intel_sdvo_connector->tv_format, i,
3049				      tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
3050
3051	intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
3052	drm_object_attach_property(&intel_sdvo_connector->base.base.base,
3053				   intel_sdvo_connector->tv_format, 0);
3054	return true;
3055
3056}
3057
3058#define _ENHANCEMENT(state_assignment, name, NAME) do { \
3059	if (enhancements.name) { \
3060		if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
3061		    !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
3062			return false; \
3063		intel_sdvo_connector->name = \
3064			drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
3065		if (!intel_sdvo_connector->name) return false; \
3066		state_assignment = response; \
3067		drm_object_attach_property(&connector->base, \
3068					   intel_sdvo_connector->name, 0); \
3069		DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
3070			      data_value[0], data_value[1], response); \
3071	} \
3072} while (0)
3073
3074#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
3075
3076static bool
3077intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
3078				      struct intel_sdvo_connector *intel_sdvo_connector,
3079				      struct intel_sdvo_enhancements_reply enhancements)
3080{
3081	struct drm_device *dev = intel_sdvo->base.base.dev;
3082	struct drm_connector *connector = &intel_sdvo_connector->base.base;
3083	struct drm_connector_state *conn_state = connector->state;
3084	struct intel_sdvo_connector_state *sdvo_state =
3085		to_intel_sdvo_connector_state(conn_state);
3086	u16 response, data_value[2];
3087
3088	/* when horizontal overscan is supported, Add the left/right property */
3089	if (enhancements.overscan_h) {
3090		if (!intel_sdvo_get_value(intel_sdvo,
3091					  SDVO_CMD_GET_MAX_OVERSCAN_H,
3092					  &data_value, 4))
3093			return false;
3094
3095		if (!intel_sdvo_get_value(intel_sdvo,
3096					  SDVO_CMD_GET_OVERSCAN_H,
3097					  &response, 2))
3098			return false;
3099
3100		sdvo_state->tv.overscan_h = response;
3101
3102		intel_sdvo_connector->max_hscan = data_value[0];
3103		intel_sdvo_connector->left =
3104			drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
3105		if (!intel_sdvo_connector->left)
3106			return false;
3107
3108		drm_object_attach_property(&connector->base,
3109					   intel_sdvo_connector->left, 0);
3110
3111		intel_sdvo_connector->right =
3112			drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
3113		if (!intel_sdvo_connector->right)
3114			return false;
3115
3116		drm_object_attach_property(&connector->base,
3117					      intel_sdvo_connector->right, 0);
3118		DRM_DEBUG_KMS("h_overscan: max %d, "
3119			      "default %d, current %d\n",
3120			      data_value[0], data_value[1], response);
3121	}
3122
3123	if (enhancements.overscan_v) {
3124		if (!intel_sdvo_get_value(intel_sdvo,
3125					  SDVO_CMD_GET_MAX_OVERSCAN_V,
3126					  &data_value, 4))
3127			return false;
3128
3129		if (!intel_sdvo_get_value(intel_sdvo,
3130					  SDVO_CMD_GET_OVERSCAN_V,
3131					  &response, 2))
3132			return false;
3133
3134		sdvo_state->tv.overscan_v = response;
3135
3136		intel_sdvo_connector->max_vscan = data_value[0];
3137		intel_sdvo_connector->top =
3138			drm_property_create_range(dev, 0,
3139					    "top_margin", 0, data_value[0]);
3140		if (!intel_sdvo_connector->top)
3141			return false;
3142
3143		drm_object_attach_property(&connector->base,
3144					   intel_sdvo_connector->top, 0);
3145
3146		intel_sdvo_connector->bottom =
3147			drm_property_create_range(dev, 0,
3148					    "bottom_margin", 0, data_value[0]);
3149		if (!intel_sdvo_connector->bottom)
3150			return false;
3151
3152		drm_object_attach_property(&connector->base,
3153					      intel_sdvo_connector->bottom, 0);
3154		DRM_DEBUG_KMS("v_overscan: max %d, "
3155			      "default %d, current %d\n",
3156			      data_value[0], data_value[1], response);
3157	}
3158
3159	ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3160	ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3161	ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3162	ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3163	ENHANCEMENT(&conn_state->tv, hue, HUE);
3164	ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3165	ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3166	ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3167	ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3168	ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3169	_ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3170	_ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3171
3172	if (enhancements.dot_crawl) {
3173		if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3174			return false;
3175
3176		sdvo_state->tv.dot_crawl = response & 0x1;
3177		intel_sdvo_connector->dot_crawl =
3178			drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3179		if (!intel_sdvo_connector->dot_crawl)
3180			return false;
3181
3182		drm_object_attach_property(&connector->base,
3183					   intel_sdvo_connector->dot_crawl, 0);
3184		DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3185	}
3186
3187	return true;
3188}
3189
3190static bool
3191intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3192					struct intel_sdvo_connector *intel_sdvo_connector,
3193					struct intel_sdvo_enhancements_reply enhancements)
3194{
3195	struct drm_device *dev = intel_sdvo->base.base.dev;
3196	struct drm_connector *connector = &intel_sdvo_connector->base.base;
3197	u16 response, data_value[2];
3198
3199	ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3200
3201	return true;
3202}
3203#undef ENHANCEMENT
3204#undef _ENHANCEMENT
3205
3206static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3207					       struct intel_sdvo_connector *intel_sdvo_connector)
3208{
3209	union {
3210		struct intel_sdvo_enhancements_reply reply;
3211		u16 response;
3212	} enhancements;
3213
3214	BUILD_BUG_ON(sizeof(enhancements) != 2);
3215
3216	if (!intel_sdvo_get_value(intel_sdvo,
3217				  SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3218				  &enhancements, sizeof(enhancements)) ||
3219	    enhancements.response == 0) {
3220		DRM_DEBUG_KMS("No enhancement is supported\n");
3221		return true;
3222	}
3223
3224	if (IS_TV(intel_sdvo_connector))
3225		return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3226	else if (IS_LVDS(intel_sdvo_connector))
3227		return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3228	else
3229		return true;
3230}
3231
3232static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3233				     struct i2c_msg *msgs,
3234				     int num)
3235{
3236	struct intel_sdvo *sdvo = adapter->algo_data;
3237
3238	if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3239		return -EIO;
3240
3241	return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3242}
3243
3244static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3245{
3246	struct intel_sdvo *sdvo = adapter->algo_data;
3247	return sdvo->i2c->algo->functionality(sdvo->i2c);
3248}
3249
3250static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3251	.master_xfer	= intel_sdvo_ddc_proxy_xfer,
3252	.functionality	= intel_sdvo_ddc_proxy_func
3253};
3254
3255static void proxy_lock_bus(struct i2c_adapter *adapter,
3256			   unsigned int flags)
3257{
3258	struct intel_sdvo *sdvo = adapter->algo_data;
3259	sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3260}
3261
3262static int proxy_trylock_bus(struct i2c_adapter *adapter,
3263			     unsigned int flags)
3264{
3265	struct intel_sdvo *sdvo = adapter->algo_data;
3266	return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3267}
3268
3269static void proxy_unlock_bus(struct i2c_adapter *adapter,
3270			     unsigned int flags)
3271{
3272	struct intel_sdvo *sdvo = adapter->algo_data;
3273	sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3274}
3275
3276static const struct i2c_lock_operations proxy_lock_ops = {
3277	.lock_bus =    proxy_lock_bus,
3278	.trylock_bus = proxy_trylock_bus,
3279	.unlock_bus =  proxy_unlock_bus,
3280};
3281
3282static bool
3283intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3284			  struct drm_i915_private *dev_priv)
3285{
3286	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
3287
3288	sdvo->ddc.owner = THIS_MODULE;
3289	sdvo->ddc.class = I2C_CLASS_DDC;
3290	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3291	sdvo->ddc.dev.parent = &pdev->dev;
3292	sdvo->ddc.algo_data = sdvo;
3293	sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3294	sdvo->ddc.lock_ops = &proxy_lock_ops;
3295
3296	return i2c_add_adapter(&sdvo->ddc) == 0;
3297}
3298
3299static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3300				   enum port port)
3301{
3302	if (HAS_PCH_SPLIT(dev_priv))
3303		drm_WARN_ON(&dev_priv->drm, port != PORT_B);
3304	else
3305		drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C);
3306}
3307
3308bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3309		     i915_reg_t sdvo_reg, enum port port)
3310{
3311	struct intel_encoder *intel_encoder;
3312	struct intel_sdvo *intel_sdvo;
3313	int i;
3314
3315	assert_sdvo_port_valid(dev_priv, port);
3316
3317	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3318	if (!intel_sdvo)
3319		return false;
3320
3321	intel_sdvo->sdvo_reg = sdvo_reg;
3322	intel_sdvo->port = port;
3323	intel_sdvo->slave_addr =
3324		intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3325	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3326	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3327		goto err_i2c_bus;
3328
3329	/* encoder type will be decided later */
3330	intel_encoder = &intel_sdvo->base;
3331	intel_encoder->type = INTEL_OUTPUT_SDVO;
3332	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3333	intel_encoder->port = port;
3334	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3335			 &intel_sdvo_enc_funcs, 0,
3336			 "SDVO %c", port_name(port));
3337
3338	/* Read the regs to test if we can talk to the device */
3339	for (i = 0; i < 0x40; i++) {
3340		u8 byte;
3341
3342		if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3343			drm_dbg_kms(&dev_priv->drm,
3344				    "No SDVO device found on %s\n",
3345				    SDVO_NAME(intel_sdvo));
3346			goto err;
3347		}
3348	}
3349
3350	intel_encoder->compute_config = intel_sdvo_compute_config;
3351	if (HAS_PCH_SPLIT(dev_priv)) {
3352		intel_encoder->disable = pch_disable_sdvo;
3353		intel_encoder->post_disable = pch_post_disable_sdvo;
3354	} else {
3355		intel_encoder->disable = intel_disable_sdvo;
3356	}
3357	intel_encoder->pre_enable = intel_sdvo_pre_enable;
3358	intel_encoder->enable = intel_enable_sdvo;
3359	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3360	intel_encoder->get_config = intel_sdvo_get_config;
3361
3362	/* In default case sdvo lvds is false */
3363	if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3364		goto err;
3365
3366	intel_sdvo->colorimetry_cap =
3367		intel_sdvo_get_colorimetry_cap(intel_sdvo);
3368
3369	if (intel_sdvo_output_setup(intel_sdvo,
3370				    intel_sdvo->caps.output_flags) != true) {
3371		drm_dbg_kms(&dev_priv->drm,
3372			    "SDVO output failed to setup on %s\n",
3373			    SDVO_NAME(intel_sdvo));
3374		/* Output_setup can leave behind connectors! */
3375		goto err_output;
3376	}
3377
3378	/*
3379	 * Only enable the hotplug irq if we need it, to work around noisy
3380	 * hotplug lines.
3381	 */
3382	if (intel_sdvo->hotplug_active) {
3383		if (intel_sdvo->port == PORT_B)
3384			intel_encoder->hpd_pin = HPD_SDVO_B;
3385		else
3386			intel_encoder->hpd_pin = HPD_SDVO_C;
3387	}
3388
3389	/*
3390	 * Cloning SDVO with anything is often impossible, since the SDVO
3391	 * encoder can request a special input timing mode. And even if that's
3392	 * not the case we have evidence that cloning a plain unscaled mode with
3393	 * VGA doesn't really work. Furthermore the cloning flags are way too
3394	 * simplistic anyway to express such constraints, so just give up on
3395	 * cloning for SDVO encoders.
3396	 */
3397	intel_sdvo->base.cloneable = 0;
3398
3399	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3400
3401	/* Set the input timing to the screen. Assume always input 0. */
3402	if (!intel_sdvo_set_target_input(intel_sdvo))
3403		goto err_output;
3404
3405	if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3406						    &intel_sdvo->pixel_clock_min,
3407						    &intel_sdvo->pixel_clock_max))
3408		goto err_output;
3409
3410	drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
3411			"clock range %dMHz - %dMHz, "
3412			"input 1: %c, input 2: %c, "
3413			"output 1: %c, output 2: %c\n",
3414			SDVO_NAME(intel_sdvo),
3415			intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3416			intel_sdvo->caps.device_rev_id,
3417			intel_sdvo->pixel_clock_min / 1000,
3418			intel_sdvo->pixel_clock_max / 1000,
3419			(intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3420			(intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3421			/* check currently supported outputs */
3422			intel_sdvo->caps.output_flags &
3423			(SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
 
 
3424			intel_sdvo->caps.output_flags &
3425			(SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
 
3426	return true;
3427
3428err_output:
3429	intel_sdvo_output_cleanup(intel_sdvo);
3430
3431err:
3432	drm_encoder_cleanup(&intel_encoder->base);
3433	i2c_del_adapter(&intel_sdvo->ddc);
3434err_i2c_bus:
3435	intel_sdvo_unselect_i2c_bus(intel_sdvo);
3436	kfree(intel_sdvo);
3437
3438	return false;
3439}