1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2021 Intel Corporation
  4 */
  5
  6#include "gem/i915_gem_region.h"
  7#include "i915_drv.h"
  8#include "intel_atomic_plane.h"
  9#include "intel_display.h"
 10#include "intel_display_types.h"
 11#include "intel_fb.h"
 12#include "intel_plane_initial.h"
 13
 14static bool
 15intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
 16			      const struct intel_initial_plane_config *plane_config,
 17			      struct drm_framebuffer **fb,
 18			      struct i915_vma **vma)
 19{
 20	struct intel_crtc *crtc;
 21
 22	for_each_intel_crtc(&i915->drm, crtc) {
 23		struct intel_crtc_state *crtc_state =
 24			to_intel_crtc_state(crtc->base.state);
 25		struct intel_plane *plane =
 26			to_intel_plane(crtc->base.primary);
 27		struct intel_plane_state *plane_state =
 28			to_intel_plane_state(plane->base.state);
 29
 30		if (!crtc_state->uapi.active)
 31			continue;
 32
 33		if (!plane_state->ggtt_vma)
 34			continue;
 35
 36		if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
 37			*fb = plane_state->hw.fb;
 38			*vma = plane_state->ggtt_vma;
 39			return true;
 40		}
 41	}
 42
 43	return false;
 44}
 45
 46static struct i915_vma *
 47initial_plane_vma(struct drm_i915_private *i915,
 48		  struct intel_initial_plane_config *plane_config)
 49{
 50	struct intel_memory_region *mem;
 51	struct drm_i915_gem_object *obj;
 52	struct i915_vma *vma;
 53	resource_size_t phys_base;
 54	u32 base, size;
 55	u64 pinctl;
 56
 57	if (plane_config->size == 0)
 58		return NULL;
 59
 60	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
 61	if (IS_DGFX(i915)) {
 62		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
 63		gen8_pte_t pte;
 64
 65		gte += base / I915_GTT_PAGE_SIZE;
 66
 67		pte = ioread64(gte);
 68		if (!(pte & GEN12_GGTT_PTE_LM)) {
 69			drm_err(&i915->drm,
 70				"Initial plane programming missing PTE_LM bit\n");
 71			return NULL;
 72		}
 73
 74		phys_base = pte & I915_GTT_PAGE_MASK;
 75		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
 76
 77		/*
 78		 * We don't currently expect this to ever be placed in the
 79		 * stolen portion.
 80		 */
 81		if (phys_base >= resource_size(&mem->region)) {
 82			drm_err(&i915->drm,
 83				"Initial plane programming using invalid range, phys_base=%pa\n",
 84				&phys_base);
 85			return NULL;
 86		}
 87
 88		drm_dbg(&i915->drm,
 89			"Using phys_base=%pa, based on initial plane programming\n",
 90			&phys_base);
 91	} else {
 92		phys_base = base;
 93		mem = i915->mm.stolen_region;
 94	}
 95
 96	if (!mem)
 97		return NULL;
 98
 99	size = round_up(plane_config->base + plane_config->size,
100			mem->min_page_size);
101	size -= base;
102
103	/*
104	 * If the FB is too big, just don't use it since fbdev is not very
105	 * important and we should probably use that space with FBC or other
106	 * features.
107	 */
108	if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
109	    mem == i915->mm.stolen_region &&
110	    size * 2 > i915->stolen_usable_size)
111		return NULL;
112
113	obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);
114	if (IS_ERR(obj))
115		return NULL;
116
117	/*
118	 * Mark it WT ahead of time to avoid changing the
119	 * cache_level during fbdev initialization. The
120	 * unbind there would get stuck waiting for rcu.
121	 */
122	i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
123					    I915_CACHE_WT : I915_CACHE_NONE);
124
125	switch (plane_config->tiling) {
126	case I915_TILING_NONE:
127		break;
128	case I915_TILING_X:
129	case I915_TILING_Y:
130		obj->tiling_and_stride =
131			plane_config->fb->base.pitches[0] |
132			plane_config->tiling;
133		break;
134	default:
135		MISSING_CASE(plane_config->tiling);
136		goto err_obj;
137	}
138
139	vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
140	if (IS_ERR(vma))
141		goto err_obj;
142
143	pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base;
144	if (HAS_GMCH(i915))
145		pinctl |= PIN_MAPPABLE;
146	if (i915_vma_pin(vma, 0, 0, pinctl))
147		goto err_obj;
148
149	if (i915_gem_object_is_tiled(obj) &&
150	    !i915_vma_is_map_and_fenceable(vma))
151		goto err_obj;
152
153	return vma;
154
155err_obj:
156	i915_gem_object_put(obj);
157	return NULL;
158}
159
160static bool
161intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
162			      struct intel_initial_plane_config *plane_config)
163{
164	struct drm_device *dev = crtc->base.dev;
165	struct drm_i915_private *dev_priv = to_i915(dev);
166	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
167	struct drm_framebuffer *fb = &plane_config->fb->base;
168	struct i915_vma *vma;
169
170	switch (fb->modifier) {
171	case DRM_FORMAT_MOD_LINEAR:
172	case I915_FORMAT_MOD_X_TILED:
173	case I915_FORMAT_MOD_Y_TILED:
174	case I915_FORMAT_MOD_4_TILED:
175		break;
176	default:
177		drm_dbg(&dev_priv->drm,
178			"Unsupported modifier for initial FB: 0x%llx\n",
179			fb->modifier);
180		return false;
181	}
182
183	vma = initial_plane_vma(dev_priv, plane_config);
184	if (!vma)
185		return false;
186
187	mode_cmd.pixel_format = fb->format->format;
188	mode_cmd.width = fb->width;
189	mode_cmd.height = fb->height;
190	mode_cmd.pitches[0] = fb->pitches[0];
191	mode_cmd.modifier[0] = fb->modifier;
192	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
193
194	if (intel_framebuffer_init(to_intel_framebuffer(fb),
195				   vma->obj, &mode_cmd)) {
196		drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
197		goto err_vma;
198	}
199
200	plane_config->vma = vma;
201	return true;
202
203err_vma:
204	i915_vma_put(vma);
205	return false;
206}
207
208static void
209intel_find_initial_plane_obj(struct intel_crtc *crtc,
210			     struct intel_initial_plane_config *plane_config)
211{
212	struct drm_device *dev = crtc->base.dev;
213	struct drm_i915_private *dev_priv = to_i915(dev);
214	struct intel_plane *plane =
215		to_intel_plane(crtc->base.primary);
216	struct intel_plane_state *plane_state =
217		to_intel_plane_state(plane->base.state);
218	struct drm_framebuffer *fb;
219	struct i915_vma *vma;
220
221	/*
222	 * TODO:
223	 *   Disable planes if get_initial_plane_config() failed.
224	 *   Make sure things work if the surface base is not page aligned.
225	 */
226	if (!plane_config->fb)
227		return;
228
229	if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
230		fb = &plane_config->fb->base;
231		vma = plane_config->vma;
232		goto valid_fb;
233	}
234
235	/*
236	 * Failed to alloc the obj, check to see if we should share
237	 * an fb with another CRTC instead
238	 */
239	if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
240		goto valid_fb;
241
242	/*
243	 * We've failed to reconstruct the BIOS FB.  Current display state
244	 * indicates that the primary plane is visible, but has a NULL FB,
245	 * which will lead to problems later if we don't fix it up.  The
246	 * simplest solution is to just disable the primary plane now and
247	 * pretend the BIOS never had it enabled.
248	 */
249	intel_plane_disable_noatomic(crtc, plane);
250
251	return;
252
253valid_fb:
254	plane_state->uapi.rotation = plane_config->rotation;
255	intel_fb_fill_view(to_intel_framebuffer(fb),
256			   plane_state->uapi.rotation, &plane_state->view);
257
258	__i915_vma_pin(vma);
259	plane_state->ggtt_vma = i915_vma_get(vma);
260	if (intel_plane_uses_fence(plane_state) &&
261	    i915_vma_pin_fence(vma) == 0 && vma->fence)
262		plane_state->flags |= PLANE_HAS_FENCE;
263
264	plane_state->uapi.src_x = 0;
265	plane_state->uapi.src_y = 0;
266	plane_state->uapi.src_w = fb->width << 16;
267	plane_state->uapi.src_h = fb->height << 16;
268
269	plane_state->uapi.crtc_x = 0;
270	plane_state->uapi.crtc_y = 0;
271	plane_state->uapi.crtc_w = fb->width;
272	plane_state->uapi.crtc_h = fb->height;
273
274	if (plane_config->tiling)
275		dev_priv->preserve_bios_swizzle = true;
276
277	plane_state->uapi.fb = fb;
278	drm_framebuffer_get(fb);
279
280	plane_state->uapi.crtc = &crtc->base;
281	intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);
282
283	atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);
284}
285
286static void plane_config_fini(struct intel_initial_plane_config *plane_config)
287{
288	if (plane_config->fb) {
289		struct drm_framebuffer *fb = &plane_config->fb->base;
290
291		/* We may only have the stub and not a full framebuffer */
292		if (drm_framebuffer_read_refcount(fb))
293			drm_framebuffer_put(fb);
294		else
295			kfree(fb);
296	}
297
298	if (plane_config->vma)
299		i915_vma_put(plane_config->vma);
300}
301
302void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
303{
304	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
305	struct intel_initial_plane_config plane_config = {};
306
307	/*
308	 * Note that reserving the BIOS fb up front prevents us
309	 * from stuffing other stolen allocations like the ring
310	 * on top.  This prevents some ugliness at boot time, and
311	 * can even allow for smooth boot transitions if the BIOS
312	 * fb is large enough for the active pipe configuration.
313	 */
314	dev_priv->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
315
316	/*
317	 * If the fb is shared between multiple heads, we'll
318	 * just get the first one.
319	 */
320	intel_find_initial_plane_obj(crtc, &plane_config);
321
322	plane_config_fini(&plane_config);
323}