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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
37#include <drm/drm_hdcp.h>
38#include <drm/drm_scdc_helper.h>
39#include <drm/intel_lpe_audio.h>
40
41#include "i915_debugfs.h"
42#include "i915_drv.h"
43#include "intel_atomic.h"
44#include "intel_connector.h"
45#include "intel_ddi.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_dp.h"
49#include "intel_gmbus.h"
50#include "intel_hdcp.h"
51#include "intel_hdmi.h"
52#include "intel_lspcon.h"
53#include "intel_panel.h"
54
55static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
56{
57 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
58}
59
60static void
61assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
62{
63 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
64 struct drm_i915_private *dev_priv = to_i915(dev);
65 u32 enabled_bits;
66
67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
68
69 drm_WARN(dev,
70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
71 "HDMI port enabled, expecting disabled\n");
72}
73
74static void
75assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
76 enum transcoder cpu_transcoder)
77{
78 drm_WARN(&dev_priv->drm,
79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
80 TRANS_DDI_FUNC_ENABLE,
81 "HDMI transcoder function enabled, expecting disabled\n");
82}
83
84static u32 g4x_infoframe_index(unsigned int type)
85{
86 switch (type) {
87 case HDMI_PACKET_TYPE_GAMUT_METADATA:
88 return VIDEO_DIP_SELECT_GAMUT;
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_SELECT_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_SELECT_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_SELECT_VENDOR;
95 default:
96 MISSING_CASE(type);
97 return 0;
98 }
99}
100
101static u32 g4x_infoframe_enable(unsigned int type)
102{
103 switch (type) {
104 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
105 return VIDEO_DIP_ENABLE_GCP;
106 case HDMI_PACKET_TYPE_GAMUT_METADATA:
107 return VIDEO_DIP_ENABLE_GAMUT;
108 case DP_SDP_VSC:
109 return 0;
110 case HDMI_INFOFRAME_TYPE_AVI:
111 return VIDEO_DIP_ENABLE_AVI;
112 case HDMI_INFOFRAME_TYPE_SPD:
113 return VIDEO_DIP_ENABLE_SPD;
114 case HDMI_INFOFRAME_TYPE_VENDOR:
115 return VIDEO_DIP_ENABLE_VENDOR;
116 case HDMI_INFOFRAME_TYPE_DRM:
117 return 0;
118 default:
119 MISSING_CASE(type);
120 return 0;
121 }
122}
123
124static u32 hsw_infoframe_enable(unsigned int type)
125{
126 switch (type) {
127 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
128 return VIDEO_DIP_ENABLE_GCP_HSW;
129 case HDMI_PACKET_TYPE_GAMUT_METADATA:
130 return VIDEO_DIP_ENABLE_GMP_HSW;
131 case DP_SDP_VSC:
132 return VIDEO_DIP_ENABLE_VSC_HSW;
133 case DP_SDP_PPS:
134 return VDIP_ENABLE_PPS;
135 case HDMI_INFOFRAME_TYPE_AVI:
136 return VIDEO_DIP_ENABLE_AVI_HSW;
137 case HDMI_INFOFRAME_TYPE_SPD:
138 return VIDEO_DIP_ENABLE_SPD_HSW;
139 case HDMI_INFOFRAME_TYPE_VENDOR:
140 return VIDEO_DIP_ENABLE_VS_HSW;
141 case HDMI_INFOFRAME_TYPE_DRM:
142 return VIDEO_DIP_ENABLE_DRM_GLK;
143 default:
144 MISSING_CASE(type);
145 return 0;
146 }
147}
148
149static i915_reg_t
150hsw_dip_data_reg(struct drm_i915_private *dev_priv,
151 enum transcoder cpu_transcoder,
152 unsigned int type,
153 int i)
154{
155 switch (type) {
156 case HDMI_PACKET_TYPE_GAMUT_METADATA:
157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
158 case DP_SDP_VSC:
159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
160 case DP_SDP_PPS:
161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
162 case HDMI_INFOFRAME_TYPE_AVI:
163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
164 case HDMI_INFOFRAME_TYPE_SPD:
165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_VENDOR:
167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_DRM:
169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
170 default:
171 MISSING_CASE(type);
172 return INVALID_MMIO_REG;
173 }
174}
175
176static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
177 unsigned int type)
178{
179 switch (type) {
180 case DP_SDP_VSC:
181 return VIDEO_DIP_VSC_DATA_SIZE;
182 case DP_SDP_PPS:
183 return VIDEO_DIP_PPS_DATA_SIZE;
184 case HDMI_PACKET_TYPE_GAMUT_METADATA:
185 if (DISPLAY_VER(dev_priv) >= 11)
186 return VIDEO_DIP_GMP_DATA_SIZE;
187 else
188 return VIDEO_DIP_DATA_SIZE;
189 default:
190 return VIDEO_DIP_DATA_SIZE;
191 }
192}
193
194static void g4x_write_infoframe(struct intel_encoder *encoder,
195 const struct intel_crtc_state *crtc_state,
196 unsigned int type,
197 const void *frame, ssize_t len)
198{
199 const u32 *data = frame;
200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
202 int i;
203
204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
205 "Writing DIP with CTL reg disabled\n");
206
207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
208 val |= g4x_infoframe_index(type);
209
210 val &= ~g4x_infoframe_enable(type);
211
212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
213
214 for (i = 0; i < len; i += 4) {
215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
216 data++;
217 }
218 /* Write every possible data byte to force correct ECC calculation. */
219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
221
222 val |= g4x_infoframe_enable(type);
223 val &= ~VIDEO_DIP_FREQ_MASK;
224 val |= VIDEO_DIP_FREQ_VSYNC;
225
226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
228}
229
230static void g4x_read_infoframe(struct intel_encoder *encoder,
231 const struct intel_crtc_state *crtc_state,
232 unsigned int type,
233 void *frame, ssize_t len)
234{
235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
236 u32 val, *data = frame;
237 int i;
238
239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
240
241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
242 val |= g4x_infoframe_index(type);
243
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
245
246 for (i = 0; i < len; i += 4)
247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
248}
249
250static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
251 const struct intel_crtc_state *pipe_config)
252{
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
255
256 if ((val & VIDEO_DIP_ENABLE) == 0)
257 return 0;
258
259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
260 return 0;
261
262 return val & (VIDEO_DIP_ENABLE_AVI |
263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
264}
265
266static void ibx_write_infoframe(struct intel_encoder *encoder,
267 const struct intel_crtc_state *crtc_state,
268 unsigned int type,
269 const void *frame, ssize_t len)
270{
271 const u32 *data = frame;
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
274 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
275 u32 val = intel_de_read(dev_priv, reg);
276 int i;
277
278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
279 "Writing DIP with CTL reg disabled\n");
280
281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
282 val |= g4x_infoframe_index(type);
283
284 val &= ~g4x_infoframe_enable(type);
285
286 intel_de_write(dev_priv, reg, val);
287
288 for (i = 0; i < len; i += 4) {
289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
290 *data);
291 data++;
292 }
293 /* Write every possible data byte to force correct ECC calculation. */
294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
296
297 val |= g4x_infoframe_enable(type);
298 val &= ~VIDEO_DIP_FREQ_MASK;
299 val |= VIDEO_DIP_FREQ_VSYNC;
300
301 intel_de_write(dev_priv, reg, val);
302 intel_de_posting_read(dev_priv, reg);
303}
304
305static void ibx_read_infoframe(struct intel_encoder *encoder,
306 const struct intel_crtc_state *crtc_state,
307 unsigned int type,
308 void *frame, ssize_t len)
309{
310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
312 u32 val, *data = frame;
313 int i;
314
315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
316
317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
318 val |= g4x_infoframe_index(type);
319
320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
321
322 for (i = 0; i < len; i += 4)
323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
324}
325
326static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
327 const struct intel_crtc_state *pipe_config)
328{
329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
332 u32 val = intel_de_read(dev_priv, reg);
333
334 if ((val & VIDEO_DIP_ENABLE) == 0)
335 return 0;
336
337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
338 return 0;
339
340 return val & (VIDEO_DIP_ENABLE_AVI |
341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
343}
344
345static void cpt_write_infoframe(struct intel_encoder *encoder,
346 const struct intel_crtc_state *crtc_state,
347 unsigned int type,
348 const void *frame, ssize_t len)
349{
350 const u32 *data = frame;
351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
353 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
354 u32 val = intel_de_read(dev_priv, reg);
355 int i;
356
357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
358 "Writing DIP with CTL reg disabled\n");
359
360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
361 val |= g4x_infoframe_index(type);
362
363 /* The DIP control register spec says that we need to update the AVI
364 * infoframe without clearing its enable bit */
365 if (type != HDMI_INFOFRAME_TYPE_AVI)
366 val &= ~g4x_infoframe_enable(type);
367
368 intel_de_write(dev_priv, reg, val);
369
370 for (i = 0; i < len; i += 4) {
371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
372 *data);
373 data++;
374 }
375 /* Write every possible data byte to force correct ECC calculation. */
376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
378
379 val |= g4x_infoframe_enable(type);
380 val &= ~VIDEO_DIP_FREQ_MASK;
381 val |= VIDEO_DIP_FREQ_VSYNC;
382
383 intel_de_write(dev_priv, reg, val);
384 intel_de_posting_read(dev_priv, reg);
385}
386
387static void cpt_read_infoframe(struct intel_encoder *encoder,
388 const struct intel_crtc_state *crtc_state,
389 unsigned int type,
390 void *frame, ssize_t len)
391{
392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
394 u32 val, *data = frame;
395 int i;
396
397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
398
399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
400 val |= g4x_infoframe_index(type);
401
402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
403
404 for (i = 0; i < len; i += 4)
405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
406}
407
408static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
409 const struct intel_crtc_state *pipe_config)
410{
411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
414
415 if ((val & VIDEO_DIP_ENABLE) == 0)
416 return 0;
417
418 return val & (VIDEO_DIP_ENABLE_AVI |
419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
421}
422
423static void vlv_write_infoframe(struct intel_encoder *encoder,
424 const struct intel_crtc_state *crtc_state,
425 unsigned int type,
426 const void *frame, ssize_t len)
427{
428 const u32 *data = frame;
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
432 u32 val = intel_de_read(dev_priv, reg);
433 int i;
434
435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
436 "Writing DIP with CTL reg disabled\n");
437
438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
439 val |= g4x_infoframe_index(type);
440
441 val &= ~g4x_infoframe_enable(type);
442
443 intel_de_write(dev_priv, reg, val);
444
445 for (i = 0; i < len; i += 4) {
446 intel_de_write(dev_priv,
447 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
448 data++;
449 }
450 /* Write every possible data byte to force correct ECC calculation. */
451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
452 intel_de_write(dev_priv,
453 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
454
455 val |= g4x_infoframe_enable(type);
456 val &= ~VIDEO_DIP_FREQ_MASK;
457 val |= VIDEO_DIP_FREQ_VSYNC;
458
459 intel_de_write(dev_priv, reg, val);
460 intel_de_posting_read(dev_priv, reg);
461}
462
463static void vlv_read_infoframe(struct intel_encoder *encoder,
464 const struct intel_crtc_state *crtc_state,
465 unsigned int type,
466 void *frame, ssize_t len)
467{
468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
470 u32 val, *data = frame;
471 int i;
472
473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
474
475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
476 val |= g4x_infoframe_index(type);
477
478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
479
480 for (i = 0; i < len; i += 4)
481 *data++ = intel_de_read(dev_priv,
482 VLV_TVIDEO_DIP_DATA(crtc->pipe));
483}
484
485static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
486 const struct intel_crtc_state *pipe_config)
487{
488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
491
492 if ((val & VIDEO_DIP_ENABLE) == 0)
493 return 0;
494
495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
496 return 0;
497
498 return val & (VIDEO_DIP_ENABLE_AVI |
499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
501}
502
503void hsw_write_infoframe(struct intel_encoder *encoder,
504 const struct intel_crtc_state *crtc_state,
505 unsigned int type,
506 const void *frame, ssize_t len)
507{
508 const u32 *data = frame;
509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
512 int data_size;
513 int i;
514 u32 val = intel_de_read(dev_priv, ctl_reg);
515
516 data_size = hsw_dip_data_size(dev_priv, type);
517
518 drm_WARN_ON(&dev_priv->drm, len > data_size);
519
520 val &= ~hsw_infoframe_enable(type);
521 intel_de_write(dev_priv, ctl_reg, val);
522
523 for (i = 0; i < len; i += 4) {
524 intel_de_write(dev_priv,
525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
526 *data);
527 data++;
528 }
529 /* Write every possible data byte to force correct ECC calculation. */
530 for (; i < data_size; i += 4)
531 intel_de_write(dev_priv,
532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
533 0);
534
535 /* Wa_14013475917 */
536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
537 type == DP_SDP_VSC)
538 return;
539
540 val |= hsw_infoframe_enable(type);
541 intel_de_write(dev_priv, ctl_reg, val);
542 intel_de_posting_read(dev_priv, ctl_reg);
543}
544
545void hsw_read_infoframe(struct intel_encoder *encoder,
546 const struct intel_crtc_state *crtc_state,
547 unsigned int type, void *frame, ssize_t len)
548{
549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
551 u32 *data = frame;
552 int i;
553
554 for (i = 0; i < len; i += 4)
555 *data++ = intel_de_read(dev_priv,
556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
557}
558
559static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
560 const struct intel_crtc_state *pipe_config)
561{
562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 u32 val = intel_de_read(dev_priv,
564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
565 u32 mask;
566
567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
570
571 if (DISPLAY_VER(dev_priv) >= 10)
572 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
573
574 return val & mask;
575}
576
577static const u8 infoframe_type_to_idx[] = {
578 HDMI_PACKET_TYPE_GENERAL_CONTROL,
579 HDMI_PACKET_TYPE_GAMUT_METADATA,
580 DP_SDP_VSC,
581 HDMI_INFOFRAME_TYPE_AVI,
582 HDMI_INFOFRAME_TYPE_SPD,
583 HDMI_INFOFRAME_TYPE_VENDOR,
584 HDMI_INFOFRAME_TYPE_DRM,
585};
586
587u32 intel_hdmi_infoframe_enable(unsigned int type)
588{
589 int i;
590
591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
592 if (infoframe_type_to_idx[i] == type)
593 return BIT(i);
594 }
595
596 return 0;
597}
598
599u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
600 const struct intel_crtc_state *crtc_state)
601{
602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
604 u32 val, ret = 0;
605 int i;
606
607 val = dig_port->infoframes_enabled(encoder, crtc_state);
608
609 /* map from hardware bits to dip idx */
610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
611 unsigned int type = infoframe_type_to_idx[i];
612
613 if (HAS_DDI(dev_priv)) {
614 if (val & hsw_infoframe_enable(type))
615 ret |= BIT(i);
616 } else {
617 if (val & g4x_infoframe_enable(type))
618 ret |= BIT(i);
619 }
620 }
621
622 return ret;
623}
624
625/*
626 * The data we write to the DIP data buffer registers is 1 byte bigger than the
627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
629 * used for both technologies.
630 *
631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
632 * DW1: DB3 | DB2 | DB1 | DB0
633 * DW2: DB7 | DB6 | DB5 | DB4
634 * DW3: ...
635 *
636 * (HB is Header Byte, DB is Data Byte)
637 *
638 * The hdmi pack() functions don't know about that hardware specific hole so we
639 * trick them by giving an offset into the buffer and moving back the header
640 * bytes by one.
641 */
642static void intel_write_infoframe(struct intel_encoder *encoder,
643 const struct intel_crtc_state *crtc_state,
644 enum hdmi_infoframe_type type,
645 const union hdmi_infoframe *frame)
646{
647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
648 u8 buffer[VIDEO_DIP_DATA_SIZE];
649 ssize_t len;
650
651 if ((crtc_state->infoframes.enable &
652 intel_hdmi_infoframe_enable(type)) == 0)
653 return;
654
655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
656 return;
657
658 /* see comment above for the reason for this offset */
659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
660 if (drm_WARN_ON(encoder->base.dev, len < 0))
661 return;
662
663 /* Insert the 'hole' (see big comment above) at position 3 */
664 memmove(&buffer[0], &buffer[1], 3);
665 buffer[3] = 0;
666 len++;
667
668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
669}
670
671void intel_read_infoframe(struct intel_encoder *encoder,
672 const struct intel_crtc_state *crtc_state,
673 enum hdmi_infoframe_type type,
674 union hdmi_infoframe *frame)
675{
676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
677 u8 buffer[VIDEO_DIP_DATA_SIZE];
678 int ret;
679
680 if ((crtc_state->infoframes.enable &
681 intel_hdmi_infoframe_enable(type)) == 0)
682 return;
683
684 dig_port->read_infoframe(encoder, crtc_state,
685 type, buffer, sizeof(buffer));
686
687 /* Fill the 'hole' (see big comment above) at position 3 */
688 memmove(&buffer[1], &buffer[0], 3);
689
690 /* see comment above for the reason for this offset */
691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
692 if (ret) {
693 drm_dbg_kms(encoder->base.dev,
694 "Failed to unpack infoframe type 0x%02x\n", type);
695 return;
696 }
697
698 if (frame->any.type != type)
699 drm_dbg_kms(encoder->base.dev,
700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
701 frame->any.type, type);
702}
703
704static bool
705intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
706 struct intel_crtc_state *crtc_state,
707 struct drm_connector_state *conn_state)
708{
709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
710 const struct drm_display_mode *adjusted_mode =
711 &crtc_state->hw.adjusted_mode;
712 struct drm_connector *connector = conn_state->connector;
713 int ret;
714
715 if (!crtc_state->has_infoframe)
716 return true;
717
718 crtc_state->infoframes.enable |=
719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
720
721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
722 adjusted_mode);
723 if (ret)
724 return false;
725
726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
727 frame->colorspace = HDMI_COLORSPACE_YUV420;
728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
729 frame->colorspace = HDMI_COLORSPACE_YUV444;
730 else
731 frame->colorspace = HDMI_COLORSPACE_RGB;
732
733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
734
735 /* nonsense combination */
736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
738
739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
740 drm_hdmi_avi_infoframe_quant_range(frame, connector,
741 adjusted_mode,
742 crtc_state->limited_color_range ?
743 HDMI_QUANTIZATION_RANGE_LIMITED :
744 HDMI_QUANTIZATION_RANGE_FULL);
745 } else {
746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
748 }
749
750 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
751
752 /* TODO: handle pixel repetition for YCBCR420 outputs */
753
754 ret = hdmi_avi_infoframe_check(frame);
755 if (drm_WARN_ON(encoder->base.dev, ret))
756 return false;
757
758 return true;
759}
760
761static bool
762intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
763 struct intel_crtc_state *crtc_state,
764 struct drm_connector_state *conn_state)
765{
766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
767 int ret;
768
769 if (!crtc_state->has_infoframe)
770 return true;
771
772 crtc_state->infoframes.enable |=
773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
774
775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
776 if (drm_WARN_ON(encoder->base.dev, ret))
777 return false;
778
779 frame->sdi = HDMI_SPD_SDI_PC;
780
781 ret = hdmi_spd_infoframe_check(frame);
782 if (drm_WARN_ON(encoder->base.dev, ret))
783 return false;
784
785 return true;
786}
787
788static bool
789intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
790 struct intel_crtc_state *crtc_state,
791 struct drm_connector_state *conn_state)
792{
793 struct hdmi_vendor_infoframe *frame =
794 &crtc_state->infoframes.hdmi.vendor.hdmi;
795 const struct drm_display_info *info =
796 &conn_state->connector->display_info;
797 int ret;
798
799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
800 return true;
801
802 crtc_state->infoframes.enable |=
803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
804
805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
806 conn_state->connector,
807 &crtc_state->hw.adjusted_mode);
808 if (drm_WARN_ON(encoder->base.dev, ret))
809 return false;
810
811 ret = hdmi_vendor_infoframe_check(frame);
812 if (drm_WARN_ON(encoder->base.dev, ret))
813 return false;
814
815 return true;
816}
817
818static bool
819intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
820 struct intel_crtc_state *crtc_state,
821 struct drm_connector_state *conn_state)
822{
823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
825 int ret;
826
827 if (DISPLAY_VER(dev_priv) < 10)
828 return true;
829
830 if (!crtc_state->has_infoframe)
831 return true;
832
833 if (!conn_state->hdr_output_metadata)
834 return true;
835
836 crtc_state->infoframes.enable |=
837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
838
839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
840 if (ret < 0) {
841 drm_dbg_kms(&dev_priv->drm,
842 "couldn't set HDR metadata in infoframe\n");
843 return false;
844 }
845
846 ret = hdmi_drm_infoframe_check(frame);
847 if (drm_WARN_ON(&dev_priv->drm, ret))
848 return false;
849
850 return true;
851}
852
853static void g4x_set_infoframes(struct intel_encoder *encoder,
854 bool enable,
855 const struct intel_crtc_state *crtc_state,
856 const struct drm_connector_state *conn_state)
857{
858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
861 i915_reg_t reg = VIDEO_DIP_CTL;
862 u32 val = intel_de_read(dev_priv, reg);
863 u32 port = VIDEO_DIP_PORT(encoder->port);
864
865 assert_hdmi_port_disabled(intel_hdmi);
866
867 /* If the registers were not initialized yet, they might be zeroes,
868 * which means we're selecting the AVI DIP and we're setting its
869 * frequency to once. This seems to really confuse the HW and make
870 * things stop working (the register spec says the AVI always needs to
871 * be sent every VSync). So here we avoid writing to the register more
872 * than we need and also explicitly select the AVI DIP and explicitly
873 * set its frequency to every VSync. Avoiding to write it twice seems to
874 * be enough to solve the problem, but being defensive shouldn't hurt us
875 * either. */
876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
877
878 if (!enable) {
879 if (!(val & VIDEO_DIP_ENABLE))
880 return;
881 if (port != (val & VIDEO_DIP_PORT_MASK)) {
882 drm_dbg_kms(&dev_priv->drm,
883 "video DIP still enabled on port %c\n",
884 (val & VIDEO_DIP_PORT_MASK) >> 29);
885 return;
886 }
887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
889 intel_de_write(dev_priv, reg, val);
890 intel_de_posting_read(dev_priv, reg);
891 return;
892 }
893
894 if (port != (val & VIDEO_DIP_PORT_MASK)) {
895 if (val & VIDEO_DIP_ENABLE) {
896 drm_dbg_kms(&dev_priv->drm,
897 "video DIP already enabled on port %c\n",
898 (val & VIDEO_DIP_PORT_MASK) >> 29);
899 return;
900 }
901 val &= ~VIDEO_DIP_PORT_MASK;
902 val |= port;
903 }
904
905 val |= VIDEO_DIP_ENABLE;
906 val &= ~(VIDEO_DIP_ENABLE_AVI |
907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
908
909 intel_de_write(dev_priv, reg, val);
910 intel_de_posting_read(dev_priv, reg);
911
912 intel_write_infoframe(encoder, crtc_state,
913 HDMI_INFOFRAME_TYPE_AVI,
914 &crtc_state->infoframes.avi);
915 intel_write_infoframe(encoder, crtc_state,
916 HDMI_INFOFRAME_TYPE_SPD,
917 &crtc_state->infoframes.spd);
918 intel_write_infoframe(encoder, crtc_state,
919 HDMI_INFOFRAME_TYPE_VENDOR,
920 &crtc_state->infoframes.hdmi);
921}
922
923/*
924 * Determine if default_phase=1 can be indicated in the GCP infoframe.
925 *
926 * From HDMI specification 1.4a:
927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
931 * phase of 0
932 */
933static bool gcp_default_phase_possible(int pipe_bpp,
934 const struct drm_display_mode *mode)
935{
936 unsigned int pixels_per_group;
937
938 switch (pipe_bpp) {
939 case 30:
940 /* 4 pixels in 5 clocks */
941 pixels_per_group = 4;
942 break;
943 case 36:
944 /* 2 pixels in 3 clocks */
945 pixels_per_group = 2;
946 break;
947 case 48:
948 /* 1 pixel in 2 clocks */
949 pixels_per_group = 1;
950 break;
951 default:
952 /* phase information not relevant for 8bpc */
953 return false;
954 }
955
956 return mode->crtc_hdisplay % pixels_per_group == 0 &&
957 mode->crtc_htotal % pixels_per_group == 0 &&
958 mode->crtc_hblank_start % pixels_per_group == 0 &&
959 mode->crtc_hblank_end % pixels_per_group == 0 &&
960 mode->crtc_hsync_start % pixels_per_group == 0 &&
961 mode->crtc_hsync_end % pixels_per_group == 0 &&
962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
963 mode->crtc_htotal/2 % pixels_per_group == 0);
964}
965
966static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
967 const struct intel_crtc_state *crtc_state,
968 const struct drm_connector_state *conn_state)
969{
970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
972 i915_reg_t reg;
973
974 if ((crtc_state->infoframes.enable &
975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
976 return false;
977
978 if (HAS_DDI(dev_priv))
979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
982 else if (HAS_PCH_SPLIT(dev_priv))
983 reg = TVIDEO_DIP_GCP(crtc->pipe);
984 else
985 return false;
986
987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
988
989 return true;
990}
991
992void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
993 struct intel_crtc_state *crtc_state)
994{
995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
997 i915_reg_t reg;
998
999 if ((crtc_state->infoframes.enable &
1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1001 return;
1002
1003 if (HAS_DDI(dev_priv))
1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1007 else if (HAS_PCH_SPLIT(dev_priv))
1008 reg = TVIDEO_DIP_GCP(crtc->pipe);
1009 else
1010 return;
1011
1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1013}
1014
1015static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1016 struct intel_crtc_state *crtc_state,
1017 struct drm_connector_state *conn_state)
1018{
1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1020
1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1022 return;
1023
1024 crtc_state->infoframes.enable |=
1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1026
1027 /* Indicate color indication for deep color mode */
1028 if (crtc_state->pipe_bpp > 24)
1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1030
1031 /* Enable default_phase whenever the display mode is suitably aligned */
1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1033 &crtc_state->hw.adjusted_mode))
1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1035}
1036
1037static void ibx_set_infoframes(struct intel_encoder *encoder,
1038 bool enable,
1039 const struct intel_crtc_state *crtc_state,
1040 const struct drm_connector_state *conn_state)
1041{
1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1046 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1047 u32 val = intel_de_read(dev_priv, reg);
1048 u32 port = VIDEO_DIP_PORT(encoder->port);
1049
1050 assert_hdmi_port_disabled(intel_hdmi);
1051
1052 /* See the big comment in g4x_set_infoframes() */
1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1054
1055 if (!enable) {
1056 if (!(val & VIDEO_DIP_ENABLE))
1057 return;
1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1061 intel_de_write(dev_priv, reg, val);
1062 intel_de_posting_read(dev_priv, reg);
1063 return;
1064 }
1065
1066 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1068 "DIP already enabled on port %c\n",
1069 (val & VIDEO_DIP_PORT_MASK) >> 29);
1070 val &= ~VIDEO_DIP_PORT_MASK;
1071 val |= port;
1072 }
1073
1074 val |= VIDEO_DIP_ENABLE;
1075 val &= ~(VIDEO_DIP_ENABLE_AVI |
1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1078
1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1080 val |= VIDEO_DIP_ENABLE_GCP;
1081
1082 intel_de_write(dev_priv, reg, val);
1083 intel_de_posting_read(dev_priv, reg);
1084
1085 intel_write_infoframe(encoder, crtc_state,
1086 HDMI_INFOFRAME_TYPE_AVI,
1087 &crtc_state->infoframes.avi);
1088 intel_write_infoframe(encoder, crtc_state,
1089 HDMI_INFOFRAME_TYPE_SPD,
1090 &crtc_state->infoframes.spd);
1091 intel_write_infoframe(encoder, crtc_state,
1092 HDMI_INFOFRAME_TYPE_VENDOR,
1093 &crtc_state->infoframes.hdmi);
1094}
1095
1096static void cpt_set_infoframes(struct intel_encoder *encoder,
1097 bool enable,
1098 const struct intel_crtc_state *crtc_state,
1099 const struct drm_connector_state *conn_state)
1100{
1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1104 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1105 u32 val = intel_de_read(dev_priv, reg);
1106
1107 assert_hdmi_port_disabled(intel_hdmi);
1108
1109 /* See the big comment in g4x_set_infoframes() */
1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1111
1112 if (!enable) {
1113 if (!(val & VIDEO_DIP_ENABLE))
1114 return;
1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1118 intel_de_write(dev_priv, reg, val);
1119 intel_de_posting_read(dev_priv, reg);
1120 return;
1121 }
1122
1123 /* Set both together, unset both together: see the spec. */
1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1127
1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1129 val |= VIDEO_DIP_ENABLE_GCP;
1130
1131 intel_de_write(dev_priv, reg, val);
1132 intel_de_posting_read(dev_priv, reg);
1133
1134 intel_write_infoframe(encoder, crtc_state,
1135 HDMI_INFOFRAME_TYPE_AVI,
1136 &crtc_state->infoframes.avi);
1137 intel_write_infoframe(encoder, crtc_state,
1138 HDMI_INFOFRAME_TYPE_SPD,
1139 &crtc_state->infoframes.spd);
1140 intel_write_infoframe(encoder, crtc_state,
1141 HDMI_INFOFRAME_TYPE_VENDOR,
1142 &crtc_state->infoframes.hdmi);
1143}
1144
1145static void vlv_set_infoframes(struct intel_encoder *encoder,
1146 bool enable,
1147 const struct intel_crtc_state *crtc_state,
1148 const struct drm_connector_state *conn_state)
1149{
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1154 u32 val = intel_de_read(dev_priv, reg);
1155 u32 port = VIDEO_DIP_PORT(encoder->port);
1156
1157 assert_hdmi_port_disabled(intel_hdmi);
1158
1159 /* See the big comment in g4x_set_infoframes() */
1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1161
1162 if (!enable) {
1163 if (!(val & VIDEO_DIP_ENABLE))
1164 return;
1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1168 intel_de_write(dev_priv, reg, val);
1169 intel_de_posting_read(dev_priv, reg);
1170 return;
1171 }
1172
1173 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1175 "DIP already enabled on port %c\n",
1176 (val & VIDEO_DIP_PORT_MASK) >> 29);
1177 val &= ~VIDEO_DIP_PORT_MASK;
1178 val |= port;
1179 }
1180
1181 val |= VIDEO_DIP_ENABLE;
1182 val &= ~(VIDEO_DIP_ENABLE_AVI |
1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1185
1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1187 val |= VIDEO_DIP_ENABLE_GCP;
1188
1189 intel_de_write(dev_priv, reg, val);
1190 intel_de_posting_read(dev_priv, reg);
1191
1192 intel_write_infoframe(encoder, crtc_state,
1193 HDMI_INFOFRAME_TYPE_AVI,
1194 &crtc_state->infoframes.avi);
1195 intel_write_infoframe(encoder, crtc_state,
1196 HDMI_INFOFRAME_TYPE_SPD,
1197 &crtc_state->infoframes.spd);
1198 intel_write_infoframe(encoder, crtc_state,
1199 HDMI_INFOFRAME_TYPE_VENDOR,
1200 &crtc_state->infoframes.hdmi);
1201}
1202
1203static void hsw_set_infoframes(struct intel_encoder *encoder,
1204 bool enable,
1205 const struct intel_crtc_state *crtc_state,
1206 const struct drm_connector_state *conn_state)
1207{
1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1210 u32 val = intel_de_read(dev_priv, reg);
1211
1212 assert_hdmi_transcoder_func_disabled(dev_priv,
1213 crtc_state->cpu_transcoder);
1214
1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1218 VIDEO_DIP_ENABLE_DRM_GLK);
1219
1220 if (!enable) {
1221 intel_de_write(dev_priv, reg, val);
1222 intel_de_posting_read(dev_priv, reg);
1223 return;
1224 }
1225
1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1227 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1228
1229 intel_de_write(dev_priv, reg, val);
1230 intel_de_posting_read(dev_priv, reg);
1231
1232 intel_write_infoframe(encoder, crtc_state,
1233 HDMI_INFOFRAME_TYPE_AVI,
1234 &crtc_state->infoframes.avi);
1235 intel_write_infoframe(encoder, crtc_state,
1236 HDMI_INFOFRAME_TYPE_SPD,
1237 &crtc_state->infoframes.spd);
1238 intel_write_infoframe(encoder, crtc_state,
1239 HDMI_INFOFRAME_TYPE_VENDOR,
1240 &crtc_state->infoframes.hdmi);
1241 intel_write_infoframe(encoder, crtc_state,
1242 HDMI_INFOFRAME_TYPE_DRM,
1243 &crtc_state->infoframes.drm);
1244}
1245
1246void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1247{
1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1249 struct i2c_adapter *adapter =
1250 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1251
1252 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1253 return;
1254
1255 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1256 enable ? "Enabling" : "Disabling");
1257
1258 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1259}
1260
1261static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1262 unsigned int offset, void *buffer, size_t size)
1263{
1264 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1265 struct intel_hdmi *hdmi = &dig_port->hdmi;
1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1267 hdmi->ddc_bus);
1268 int ret;
1269 u8 start = offset & 0xff;
1270 struct i2c_msg msgs[] = {
1271 {
1272 .addr = DRM_HDCP_DDC_ADDR,
1273 .flags = 0,
1274 .len = 1,
1275 .buf = &start,
1276 },
1277 {
1278 .addr = DRM_HDCP_DDC_ADDR,
1279 .flags = I2C_M_RD,
1280 .len = size,
1281 .buf = buffer
1282 }
1283 };
1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1285 if (ret == ARRAY_SIZE(msgs))
1286 return 0;
1287 return ret >= 0 ? -EIO : ret;
1288}
1289
1290static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1291 unsigned int offset, void *buffer, size_t size)
1292{
1293 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1294 struct intel_hdmi *hdmi = &dig_port->hdmi;
1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1296 hdmi->ddc_bus);
1297 int ret;
1298 u8 *write_buf;
1299 struct i2c_msg msg;
1300
1301 write_buf = kzalloc(size + 1, GFP_KERNEL);
1302 if (!write_buf)
1303 return -ENOMEM;
1304
1305 write_buf[0] = offset & 0xff;
1306 memcpy(&write_buf[1], buffer, size);
1307
1308 msg.addr = DRM_HDCP_DDC_ADDR;
1309 msg.flags = 0,
1310 msg.len = size + 1,
1311 msg.buf = write_buf;
1312
1313 ret = i2c_transfer(adapter, &msg, 1);
1314 if (ret == 1)
1315 ret = 0;
1316 else if (ret >= 0)
1317 ret = -EIO;
1318
1319 kfree(write_buf);
1320 return ret;
1321}
1322
1323static
1324int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1325 u8 *an)
1326{
1327 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1328 struct intel_hdmi *hdmi = &dig_port->hdmi;
1329 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1330 hdmi->ddc_bus);
1331 int ret;
1332
1333 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1334 DRM_HDCP_AN_LEN);
1335 if (ret) {
1336 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1337 ret);
1338 return ret;
1339 }
1340
1341 ret = intel_gmbus_output_aksv(adapter);
1342 if (ret < 0) {
1343 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1344 return ret;
1345 }
1346 return 0;
1347}
1348
1349static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1350 u8 *bksv)
1351{
1352 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1353
1354 int ret;
1355 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1356 DRM_HDCP_KSV_LEN);
1357 if (ret)
1358 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1359 ret);
1360 return ret;
1361}
1362
1363static
1364int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1365 u8 *bstatus)
1366{
1367 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1368
1369 int ret;
1370 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1371 bstatus, DRM_HDCP_BSTATUS_LEN);
1372 if (ret)
1373 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1374 ret);
1375 return ret;
1376}
1377
1378static
1379int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1380 bool *repeater_present)
1381{
1382 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1383 int ret;
1384 u8 val;
1385
1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1387 if (ret) {
1388 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1389 ret);
1390 return ret;
1391 }
1392 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1393 return 0;
1394}
1395
1396static
1397int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1398 u8 *ri_prime)
1399{
1400 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1401
1402 int ret;
1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1404 ri_prime, DRM_HDCP_RI_LEN);
1405 if (ret)
1406 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1407 ret);
1408 return ret;
1409}
1410
1411static
1412int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1413 bool *ksv_ready)
1414{
1415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1416 int ret;
1417 u8 val;
1418
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1420 if (ret) {
1421 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1422 ret);
1423 return ret;
1424 }
1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1426 return 0;
1427}
1428
1429static
1430int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1431 int num_downstream, u8 *ksv_fifo)
1432{
1433 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1434 int ret;
1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1436 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1437 if (ret) {
1438 drm_dbg_kms(&i915->drm,
1439 "Read ksv fifo over DDC failed (%d)\n", ret);
1440 return ret;
1441 }
1442 return 0;
1443}
1444
1445static
1446int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1447 int i, u32 *part)
1448{
1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1450 int ret;
1451
1452 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1453 return -EINVAL;
1454
1455 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1456 part, DRM_HDCP_V_PRIME_PART_LEN);
1457 if (ret)
1458 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1459 i, ret);
1460 return ret;
1461}
1462
1463static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1464 enum transcoder cpu_transcoder)
1465{
1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1468 struct drm_crtc *crtc = connector->base.state->crtc;
1469 struct intel_crtc *intel_crtc = container_of(crtc,
1470 struct intel_crtc, base);
1471 u32 scanline;
1472 int ret;
1473
1474 for (;;) {
1475 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1476 if (scanline > 100 && scanline < 200)
1477 break;
1478 usleep_range(25, 50);
1479 }
1480
1481 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1482 false, TRANS_DDI_HDCP_SIGNALLING);
1483 if (ret) {
1484 drm_err(&dev_priv->drm,
1485 "Disable HDCP signalling failed (%d)\n", ret);
1486 return ret;
1487 }
1488
1489 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1490 true, TRANS_DDI_HDCP_SIGNALLING);
1491 if (ret) {
1492 drm_err(&dev_priv->drm,
1493 "Enable HDCP signalling failed (%d)\n", ret);
1494 return ret;
1495 }
1496
1497 return 0;
1498}
1499
1500static
1501int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1502 enum transcoder cpu_transcoder,
1503 bool enable)
1504{
1505 struct intel_hdmi *hdmi = &dig_port->hdmi;
1506 struct intel_connector *connector = hdmi->attached_connector;
1507 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1508 int ret;
1509
1510 if (!enable)
1511 usleep_range(6, 60); /* Bspec says >= 6us */
1512
1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1514 cpu_transcoder, enable,
1515 TRANS_DDI_HDCP_SIGNALLING);
1516 if (ret) {
1517 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1518 enable ? "Enable" : "Disable", ret);
1519 return ret;
1520 }
1521
1522 /*
1523 * WA: To fix incorrect positioning of the window of
1524 * opportunity and enc_en signalling in KABYLAKE.
1525 */
1526 if (IS_KABYLAKE(dev_priv) && enable)
1527 return kbl_repositioning_enc_en_signal(connector,
1528 cpu_transcoder);
1529
1530 return 0;
1531}
1532
1533static
1534bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1535 struct intel_connector *connector)
1536{
1537 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1538 enum port port = dig_port->base.port;
1539 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1540 int ret;
1541 union {
1542 u32 reg;
1543 u8 shim[DRM_HDCP_RI_LEN];
1544 } ri;
1545
1546 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1547 if (ret)
1548 return false;
1549
1550 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1551
1552 /* Wait for Ri prime match */
1553 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1554 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1556 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1557 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1558 port)));
1559 return false;
1560 }
1561 return true;
1562}
1563
1564static
1565bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1566 struct intel_connector *connector)
1567{
1568 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1569 int retry;
1570
1571 for (retry = 0; retry < 3; retry++)
1572 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1573 return true;
1574
1575 drm_err(&i915->drm, "Link check failed\n");
1576 return false;
1577}
1578
1579struct hdcp2_hdmi_msg_timeout {
1580 u8 msg_id;
1581 u16 timeout;
1582};
1583
1584static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1585 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1586 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1587 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1588 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1589 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1590};
1591
1592static
1593int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1594 u8 *rx_status)
1595{
1596 return intel_hdmi_hdcp_read(dig_port,
1597 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1598 rx_status,
1599 HDCP_2_2_HDMI_RXSTATUS_LEN);
1600}
1601
1602static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1603{
1604 int i;
1605
1606 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1607 if (is_paired)
1608 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1609 else
1610 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1611 }
1612
1613 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1614 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1615 return hdcp2_msg_timeout[i].timeout;
1616 }
1617
1618 return -EINVAL;
1619}
1620
1621static int
1622hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1623 u8 msg_id, bool *msg_ready,
1624 ssize_t *msg_sz)
1625{
1626 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1627 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1628 int ret;
1629
1630 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1631 if (ret < 0) {
1632 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1633 ret);
1634 return ret;
1635 }
1636
1637 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1638 rx_status[0]);
1639
1640 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1641 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1642 *msg_sz);
1643 else
1644 *msg_ready = *msg_sz;
1645
1646 return 0;
1647}
1648
1649static ssize_t
1650intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1651 u8 msg_id, bool paired)
1652{
1653 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1654 bool msg_ready = false;
1655 int timeout, ret;
1656 ssize_t msg_sz = 0;
1657
1658 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1659 if (timeout < 0)
1660 return timeout;
1661
1662 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1663 msg_id, &msg_ready,
1664 &msg_sz),
1665 !ret && msg_ready && msg_sz, timeout * 1000,
1666 1000, 5 * 1000);
1667 if (ret)
1668 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1669 msg_id, ret, timeout);
1670
1671 return ret ? ret : msg_sz;
1672}
1673
1674static
1675int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1676 void *buf, size_t size)
1677{
1678 unsigned int offset;
1679
1680 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1681 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1682}
1683
1684static
1685int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1686 u8 msg_id, void *buf, size_t size)
1687{
1688 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1689 struct intel_hdmi *hdmi = &dig_port->hdmi;
1690 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1691 unsigned int offset;
1692 ssize_t ret;
1693
1694 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1695 hdcp->is_paired);
1696 if (ret < 0)
1697 return ret;
1698
1699 /*
1700 * Available msg size should be equal to or lesser than the
1701 * available buffer.
1702 */
1703 if (ret > size) {
1704 drm_dbg_kms(&i915->drm,
1705 "msg_sz(%zd) is more than exp size(%zu)\n",
1706 ret, size);
1707 return -1;
1708 }
1709
1710 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1711 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1712 if (ret)
1713 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1714 msg_id, ret);
1715
1716 return ret;
1717}
1718
1719static
1720int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1721 struct intel_connector *connector)
1722{
1723 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1724 int ret;
1725
1726 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1727 if (ret)
1728 return ret;
1729
1730 /*
1731 * Re-auth request and Link Integrity Failures are represented by
1732 * same bit. i.e reauth_req.
1733 */
1734 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1735 ret = HDCP_REAUTH_REQUEST;
1736 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1737 ret = HDCP_TOPOLOGY_CHANGE;
1738
1739 return ret;
1740}
1741
1742static
1743int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1744 bool *capable)
1745{
1746 u8 hdcp2_version;
1747 int ret;
1748
1749 *capable = false;
1750 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1751 &hdcp2_version, sizeof(hdcp2_version));
1752 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1753 *capable = true;
1754
1755 return ret;
1756}
1757
1758static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1759 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1760 .read_bksv = intel_hdmi_hdcp_read_bksv,
1761 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1762 .repeater_present = intel_hdmi_hdcp_repeater_present,
1763 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1764 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1765 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1766 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1767 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1768 .check_link = intel_hdmi_hdcp_check_link,
1769 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1770 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1771 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1772 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1773 .protocol = HDCP_PROTOCOL_HDMI,
1774};
1775
1776static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1777{
1778 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1779 int max_tmds_clock, vbt_max_tmds_clock;
1780
1781 if (DISPLAY_VER(dev_priv) >= 10)
1782 max_tmds_clock = 594000;
1783 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1784 max_tmds_clock = 300000;
1785 else if (DISPLAY_VER(dev_priv) >= 5)
1786 max_tmds_clock = 225000;
1787 else
1788 max_tmds_clock = 165000;
1789
1790 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1791 if (vbt_max_tmds_clock)
1792 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1793
1794 return max_tmds_clock;
1795}
1796
1797static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1798 const struct drm_connector_state *conn_state)
1799{
1800 return hdmi->has_hdmi_sink &&
1801 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1802}
1803
1804static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1805 bool respect_downstream_limits,
1806 bool has_hdmi_sink)
1807{
1808 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1809 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1810
1811 if (respect_downstream_limits) {
1812 struct intel_connector *connector = hdmi->attached_connector;
1813 const struct drm_display_info *info = &connector->base.display_info;
1814
1815 if (hdmi->dp_dual_mode.max_tmds_clock)
1816 max_tmds_clock = min(max_tmds_clock,
1817 hdmi->dp_dual_mode.max_tmds_clock);
1818
1819 if (info->max_tmds_clock)
1820 max_tmds_clock = min(max_tmds_clock,
1821 info->max_tmds_clock);
1822 else if (!has_hdmi_sink)
1823 max_tmds_clock = min(max_tmds_clock, 165000);
1824 }
1825
1826 return max_tmds_clock;
1827}
1828
1829static enum drm_mode_status
1830hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1831 int clock, bool respect_downstream_limits,
1832 bool has_hdmi_sink)
1833{
1834 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1835
1836 if (clock < 25000)
1837 return MODE_CLOCK_LOW;
1838 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1839 has_hdmi_sink))
1840 return MODE_CLOCK_HIGH;
1841
1842 /* GLK DPLL can't generate 446-480 MHz */
1843 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1844 return MODE_CLOCK_RANGE;
1845
1846 /* BXT/GLK DPLL can't generate 223-240 MHz */
1847 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1848 clock > 223333 && clock < 240000)
1849 return MODE_CLOCK_RANGE;
1850
1851 /* CHV DPLL can't generate 216-240 MHz */
1852 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1853 return MODE_CLOCK_RANGE;
1854
1855 return MODE_OK;
1856}
1857
1858static int intel_hdmi_port_clock(int clock, int bpc)
1859{
1860 /*
1861 * Need to adjust the port link by:
1862 * 1.5x for 12bpc
1863 * 1.25x for 10bpc
1864 */
1865 return clock * bpc / 8;
1866}
1867
1868static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
1869 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1870{
1871 struct drm_i915_private *i915 = to_i915(connector->dev);
1872 const struct drm_display_info *info = &connector->display_info;
1873 const struct drm_hdmi_info *hdmi = &info->hdmi;
1874
1875 switch (bpc) {
1876 case 12:
1877 if (HAS_GMCH(i915))
1878 return false;
1879
1880 if (!has_hdmi_sink)
1881 return false;
1882
1883 if (ycbcr420_output)
1884 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1885 else
1886 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36;
1887 case 10:
1888 if (DISPLAY_VER(i915) < 11)
1889 return false;
1890
1891 if (!has_hdmi_sink)
1892 return false;
1893
1894 if (ycbcr420_output)
1895 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1896 else
1897 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30;
1898 case 8:
1899 return true;
1900 default:
1901 MISSING_CASE(bpc);
1902 return false;
1903 }
1904}
1905
1906static enum drm_mode_status
1907intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1908 bool has_hdmi_sink, bool ycbcr420_output)
1909{
1910 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1911 enum drm_mode_status status;
1912
1913 if (ycbcr420_output)
1914 clock /= 2;
1915
1916 /* check if we can do 8bpc */
1917 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
1918 true, has_hdmi_sink);
1919
1920 /* if we can't do 8bpc we may still be able to do 12bpc */
1921 if (status != MODE_OK &&
1922 intel_hdmi_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
1923 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
1924 true, has_hdmi_sink);
1925
1926 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1927 if (status != MODE_OK &&
1928 intel_hdmi_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
1929 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
1930 true, has_hdmi_sink);
1931
1932 return status;
1933}
1934
1935static enum drm_mode_status
1936intel_hdmi_mode_valid(struct drm_connector *connector,
1937 struct drm_display_mode *mode)
1938{
1939 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1940 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1941 struct drm_i915_private *dev_priv = to_i915(dev);
1942 enum drm_mode_status status;
1943 int clock = mode->clock;
1944 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1945 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1946 bool ycbcr_420_only;
1947
1948 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1949 return MODE_NO_DBLESCAN;
1950
1951 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1952 clock *= 2;
1953
1954 if (clock > max_dotclk)
1955 return MODE_CLOCK_HIGH;
1956
1957 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1958 if (!has_hdmi_sink)
1959 return MODE_CLOCK_LOW;
1960 clock *= 2;
1961 }
1962
1963 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
1964
1965 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
1966 if (status != MODE_OK) {
1967 if (ycbcr_420_only ||
1968 !connector->ycbcr_420_allowed ||
1969 !drm_mode_is_420_also(&connector->display_info, mode))
1970 return status;
1971
1972 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
1973 if (status != MODE_OK)
1974 return status;
1975 }
1976
1977 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
1978}
1979
1980bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1981 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1982{
1983 struct drm_atomic_state *state = crtc_state->uapi.state;
1984 struct drm_connector_state *connector_state;
1985 struct drm_connector *connector;
1986 int i;
1987
1988 if (crtc_state->pipe_bpp < bpc * 3)
1989 return false;
1990
1991 for_each_new_connector_in_state(state, connector, connector_state, i) {
1992 if (connector_state->crtc != crtc_state->uapi.crtc)
1993 continue;
1994
1995 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1996 return false;
1997 }
1998
1999 return true;
2000}
2001
2002static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2003 int bpc)
2004{
2005 struct drm_i915_private *dev_priv =
2006 to_i915(crtc_state->uapi.crtc->dev);
2007 const struct drm_display_mode *adjusted_mode =
2008 &crtc_state->hw.adjusted_mode;
2009
2010 /*
2011 * HDMI deep color affects the clocks, so it's only possible
2012 * when not cloning with other encoder types.
2013 */
2014 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2015 return false;
2016
2017 /* Display Wa_1405510057:icl,ehl */
2018 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2019 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2020 (adjusted_mode->crtc_hblank_end -
2021 adjusted_mode->crtc_hblank_start) % 8 == 2)
2022 return false;
2023
2024 return intel_hdmi_deep_color_possible(crtc_state, bpc,
2025 crtc_state->has_hdmi_sink,
2026 crtc_state->output_format ==
2027 INTEL_OUTPUT_FORMAT_YCBCR420);
2028}
2029
2030static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2031 struct intel_crtc_state *crtc_state,
2032 int clock)
2033{
2034 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2035 int bpc;
2036
2037 for (bpc = 12; bpc >= 10; bpc -= 2) {
2038 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2039 hdmi_port_clock_valid(intel_hdmi,
2040 intel_hdmi_port_clock(clock, bpc),
2041 true, crtc_state->has_hdmi_sink) == MODE_OK)
2042 return bpc;
2043 }
2044
2045 return 8;
2046}
2047
2048static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2049 struct intel_crtc_state *crtc_state)
2050{
2051 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2052 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2053 const struct drm_display_mode *adjusted_mode =
2054 &crtc_state->hw.adjusted_mode;
2055 int bpc, clock = adjusted_mode->crtc_clock;
2056
2057 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2058 clock *= 2;
2059
2060 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2061 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2062 clock /= 2;
2063
2064 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2065
2066 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2067
2068 /*
2069 * pipe_bpp could already be below 8bpc due to
2070 * FDI bandwidth constraints. We shouldn't bump it
2071 * back up to 8bpc in that case.
2072 */
2073 if (crtc_state->pipe_bpp > bpc * 3)
2074 crtc_state->pipe_bpp = bpc * 3;
2075
2076 drm_dbg_kms(&i915->drm,
2077 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2078 bpc, crtc_state->pipe_bpp);
2079
2080 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2081 false, crtc_state->has_hdmi_sink) != MODE_OK) {
2082 drm_dbg_kms(&i915->drm,
2083 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2084 crtc_state->port_clock);
2085 return -EINVAL;
2086 }
2087
2088 return 0;
2089}
2090
2091bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2092 const struct drm_connector_state *conn_state)
2093{
2094 const struct intel_digital_connector_state *intel_conn_state =
2095 to_intel_digital_connector_state(conn_state);
2096 const struct drm_display_mode *adjusted_mode =
2097 &crtc_state->hw.adjusted_mode;
2098
2099 /*
2100 * Our YCbCr output is always limited range.
2101 * crtc_state->limited_color_range only applies to RGB,
2102 * and it must never be set for YCbCr or we risk setting
2103 * some conflicting bits in PIPECONF which will mess up
2104 * the colors on the monitor.
2105 */
2106 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2107 return false;
2108
2109 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2110 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2111 return crtc_state->has_hdmi_sink &&
2112 drm_default_rgb_quant_range(adjusted_mode) ==
2113 HDMI_QUANTIZATION_RANGE_LIMITED;
2114 } else {
2115 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2116 }
2117}
2118
2119static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2120 const struct intel_crtc_state *crtc_state,
2121 const struct drm_connector_state *conn_state)
2122{
2123 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2124 const struct intel_digital_connector_state *intel_conn_state =
2125 to_intel_digital_connector_state(conn_state);
2126
2127 if (!crtc_state->has_hdmi_sink)
2128 return false;
2129
2130 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2131 return intel_hdmi->has_audio;
2132 else
2133 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2134}
2135
2136static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2137 struct intel_crtc_state *crtc_state,
2138 const struct drm_connector_state *conn_state)
2139{
2140 struct drm_connector *connector = conn_state->connector;
2141 struct drm_i915_private *i915 = to_i915(connector->dev);
2142 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2143 int ret;
2144 bool ycbcr_420_only;
2145
2146 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
2147 if (connector->ycbcr_420_allowed && ycbcr_420_only) {
2148 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2149 } else {
2150 if (!connector->ycbcr_420_allowed && ycbcr_420_only)
2151 drm_dbg_kms(&i915->drm,
2152 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2153 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2154 }
2155
2156 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2157 if (ret) {
2158 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
2159 connector->ycbcr_420_allowed &&
2160 drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
2161 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2162 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2163 }
2164 }
2165
2166 return ret;
2167}
2168
2169int intel_hdmi_compute_config(struct intel_encoder *encoder,
2170 struct intel_crtc_state *pipe_config,
2171 struct drm_connector_state *conn_state)
2172{
2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2175 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2176 struct drm_connector *connector = conn_state->connector;
2177 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2178 int ret;
2179
2180 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2181 return -EINVAL;
2182
2183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2184 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2185 conn_state);
2186
2187 if (pipe_config->has_hdmi_sink)
2188 pipe_config->has_infoframe = true;
2189
2190 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2191 pipe_config->pixel_multiplier = 2;
2192
2193 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2194 pipe_config->has_pch_encoder = true;
2195
2196 pipe_config->has_audio =
2197 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2198
2199 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
2200 if (ret)
2201 return ret;
2202
2203 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2204 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2205 if (ret)
2206 return ret;
2207 }
2208
2209 pipe_config->limited_color_range =
2210 intel_hdmi_limited_color_range(pipe_config, conn_state);
2211
2212 if (conn_state->picture_aspect_ratio)
2213 adjusted_mode->picture_aspect_ratio =
2214 conn_state->picture_aspect_ratio;
2215
2216 pipe_config->lane_count = 4;
2217
2218 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2219 if (scdc->scrambling.low_rates)
2220 pipe_config->hdmi_scrambling = true;
2221
2222 if (pipe_config->port_clock > 340000) {
2223 pipe_config->hdmi_scrambling = true;
2224 pipe_config->hdmi_high_tmds_clock_ratio = true;
2225 }
2226 }
2227
2228 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2229 conn_state);
2230
2231 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2232 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2233 return -EINVAL;
2234 }
2235
2236 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2237 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2238 return -EINVAL;
2239 }
2240
2241 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2242 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2243 return -EINVAL;
2244 }
2245
2246 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2247 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2248 return -EINVAL;
2249 }
2250
2251 return 0;
2252}
2253
2254static void
2255intel_hdmi_unset_edid(struct drm_connector *connector)
2256{
2257 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2258
2259 intel_hdmi->has_hdmi_sink = false;
2260 intel_hdmi->has_audio = false;
2261
2262 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2263 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2264
2265 kfree(to_intel_connector(connector)->detect_edid);
2266 to_intel_connector(connector)->detect_edid = NULL;
2267}
2268
2269static void
2270intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2271{
2272 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2273 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2274 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2275 struct i2c_adapter *adapter =
2276 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2277 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2278
2279 /*
2280 * Type 1 DVI adaptors are not required to implement any
2281 * registers, so we can't always detect their presence.
2282 * Ideally we should be able to check the state of the
2283 * CONFIG1 pin, but no such luck on our hardware.
2284 *
2285 * The only method left to us is to check the VBT to see
2286 * if the port is a dual mode capable DP port. But let's
2287 * only do that when we sucesfully read the EDID, to avoid
2288 * confusing log messages about DP dual mode adaptors when
2289 * there's nothing connected to the port.
2290 */
2291 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2292 /* An overridden EDID imply that we want this port for testing.
2293 * Make sure not to set limits for that port.
2294 */
2295 if (has_edid && !connector->override_edid &&
2296 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2297 drm_dbg_kms(&dev_priv->drm,
2298 "Assuming DP dual mode adaptor presence based on VBT\n");
2299 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2300 } else {
2301 type = DRM_DP_DUAL_MODE_NONE;
2302 }
2303 }
2304
2305 if (type == DRM_DP_DUAL_MODE_NONE)
2306 return;
2307
2308 hdmi->dp_dual_mode.type = type;
2309 hdmi->dp_dual_mode.max_tmds_clock =
2310 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2311
2312 drm_dbg_kms(&dev_priv->drm,
2313 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2314 drm_dp_get_dual_mode_type_name(type),
2315 hdmi->dp_dual_mode.max_tmds_clock);
2316}
2317
2318static bool
2319intel_hdmi_set_edid(struct drm_connector *connector)
2320{
2321 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2322 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2323 intel_wakeref_t wakeref;
2324 struct edid *edid;
2325 bool connected = false;
2326 struct i2c_adapter *i2c;
2327
2328 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2329
2330 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2331
2332 edid = drm_get_edid(connector, i2c);
2333
2334 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2335 drm_dbg_kms(&dev_priv->drm,
2336 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2337 intel_gmbus_force_bit(i2c, true);
2338 edid = drm_get_edid(connector, i2c);
2339 intel_gmbus_force_bit(i2c, false);
2340 }
2341
2342 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2343
2344 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2345
2346 to_intel_connector(connector)->detect_edid = edid;
2347 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2348 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2349 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2350
2351 connected = true;
2352 }
2353
2354 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2355
2356 return connected;
2357}
2358
2359static enum drm_connector_status
2360intel_hdmi_detect(struct drm_connector *connector, bool force)
2361{
2362 enum drm_connector_status status = connector_status_disconnected;
2363 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2364 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2365 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2366 intel_wakeref_t wakeref;
2367
2368 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2369 connector->base.id, connector->name);
2370
2371 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2372 return connector_status_disconnected;
2373
2374 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2375
2376 if (DISPLAY_VER(dev_priv) >= 11 &&
2377 !intel_digital_port_connected(encoder))
2378 goto out;
2379
2380 intel_hdmi_unset_edid(connector);
2381
2382 if (intel_hdmi_set_edid(connector))
2383 status = connector_status_connected;
2384
2385out:
2386 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2387
2388 if (status != connector_status_connected)
2389 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2390
2391 /*
2392 * Make sure the refs for power wells enabled during detect are
2393 * dropped to avoid a new detect cycle triggered by HPD polling.
2394 */
2395 intel_display_power_flush_work(dev_priv);
2396
2397 return status;
2398}
2399
2400static void
2401intel_hdmi_force(struct drm_connector *connector)
2402{
2403 struct drm_i915_private *i915 = to_i915(connector->dev);
2404
2405 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2406 connector->base.id, connector->name);
2407
2408 intel_hdmi_unset_edid(connector);
2409
2410 if (connector->status != connector_status_connected)
2411 return;
2412
2413 intel_hdmi_set_edid(connector);
2414}
2415
2416static int intel_hdmi_get_modes(struct drm_connector *connector)
2417{
2418 struct edid *edid;
2419
2420 edid = to_intel_connector(connector)->detect_edid;
2421 if (edid == NULL)
2422 return 0;
2423
2424 return intel_connector_update_modes(connector, edid);
2425}
2426
2427static struct i2c_adapter *
2428intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2429{
2430 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2431 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2432
2433 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2434}
2435
2436static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2437{
2438 struct drm_i915_private *i915 = to_i915(connector->dev);
2439 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2440 struct kobject *i2c_kobj = &adapter->dev.kobj;
2441 struct kobject *connector_kobj = &connector->kdev->kobj;
2442 int ret;
2443
2444 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2445 if (ret)
2446 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2447}
2448
2449static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2450{
2451 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2452 struct kobject *i2c_kobj = &adapter->dev.kobj;
2453 struct kobject *connector_kobj = &connector->kdev->kobj;
2454
2455 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2456}
2457
2458static int
2459intel_hdmi_connector_register(struct drm_connector *connector)
2460{
2461 int ret;
2462
2463 ret = intel_connector_register(connector);
2464 if (ret)
2465 return ret;
2466
2467 intel_hdmi_create_i2c_symlink(connector);
2468
2469 return ret;
2470}
2471
2472static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2473{
2474 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2475
2476 cec_notifier_conn_unregister(n);
2477
2478 intel_hdmi_remove_i2c_symlink(connector);
2479 intel_connector_unregister(connector);
2480}
2481
2482static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2483 .detect = intel_hdmi_detect,
2484 .force = intel_hdmi_force,
2485 .fill_modes = drm_helper_probe_single_connector_modes,
2486 .atomic_get_property = intel_digital_connector_atomic_get_property,
2487 .atomic_set_property = intel_digital_connector_atomic_set_property,
2488 .late_register = intel_hdmi_connector_register,
2489 .early_unregister = intel_hdmi_connector_unregister,
2490 .destroy = intel_connector_destroy,
2491 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2492 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2493};
2494
2495static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2496 .get_modes = intel_hdmi_get_modes,
2497 .mode_valid = intel_hdmi_mode_valid,
2498 .atomic_check = intel_digital_connector_atomic_check,
2499};
2500
2501static void
2502intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2503{
2504 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2505
2506 intel_attach_force_audio_property(connector);
2507 intel_attach_broadcast_rgb_property(connector);
2508 intel_attach_aspect_ratio_property(connector);
2509
2510 intel_attach_hdmi_colorspace_property(connector);
2511 drm_connector_attach_content_type_property(connector);
2512
2513 if (DISPLAY_VER(dev_priv) >= 10)
2514 drm_connector_attach_hdr_output_metadata_property(connector);
2515
2516 if (!HAS_GMCH(dev_priv))
2517 drm_connector_attach_max_bpc_property(connector, 8, 12);
2518}
2519
2520/*
2521 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2522 * @encoder: intel_encoder
2523 * @connector: drm_connector
2524 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2525 * or reset the high tmds clock ratio for scrambling
2526 * @scrambling: bool to Indicate if the function needs to set or reset
2527 * sink scrambling
2528 *
2529 * This function handles scrambling on HDMI 2.0 capable sinks.
2530 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2531 * it enables scrambling. This should be called before enabling the HDMI
2532 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2533 * detect a scrambled clock within 100 ms.
2534 *
2535 * Returns:
2536 * True on success, false on failure.
2537 */
2538bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2539 struct drm_connector *connector,
2540 bool high_tmds_clock_ratio,
2541 bool scrambling)
2542{
2543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2545 struct drm_scrambling *sink_scrambling =
2546 &connector->display_info.hdmi.scdc.scrambling;
2547 struct i2c_adapter *adapter =
2548 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2549
2550 if (!sink_scrambling->supported)
2551 return true;
2552
2553 drm_dbg_kms(&dev_priv->drm,
2554 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2555 connector->base.id, connector->name,
2556 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2557
2558 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2559 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2560 high_tmds_clock_ratio) &&
2561 drm_scdc_set_scrambling(adapter, scrambling);
2562}
2563
2564static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2565{
2566 u8 ddc_pin;
2567
2568 switch (port) {
2569 case PORT_B:
2570 ddc_pin = GMBUS_PIN_DPB;
2571 break;
2572 case PORT_C:
2573 ddc_pin = GMBUS_PIN_DPC;
2574 break;
2575 case PORT_D:
2576 ddc_pin = GMBUS_PIN_DPD_CHV;
2577 break;
2578 default:
2579 MISSING_CASE(port);
2580 ddc_pin = GMBUS_PIN_DPB;
2581 break;
2582 }
2583 return ddc_pin;
2584}
2585
2586static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2587{
2588 u8 ddc_pin;
2589
2590 switch (port) {
2591 case PORT_B:
2592 ddc_pin = GMBUS_PIN_1_BXT;
2593 break;
2594 case PORT_C:
2595 ddc_pin = GMBUS_PIN_2_BXT;
2596 break;
2597 default:
2598 MISSING_CASE(port);
2599 ddc_pin = GMBUS_PIN_1_BXT;
2600 break;
2601 }
2602 return ddc_pin;
2603}
2604
2605static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2606 enum port port)
2607{
2608 u8 ddc_pin;
2609
2610 switch (port) {
2611 case PORT_B:
2612 ddc_pin = GMBUS_PIN_1_BXT;
2613 break;
2614 case PORT_C:
2615 ddc_pin = GMBUS_PIN_2_BXT;
2616 break;
2617 case PORT_D:
2618 ddc_pin = GMBUS_PIN_4_CNP;
2619 break;
2620 case PORT_F:
2621 ddc_pin = GMBUS_PIN_3_BXT;
2622 break;
2623 default:
2624 MISSING_CASE(port);
2625 ddc_pin = GMBUS_PIN_1_BXT;
2626 break;
2627 }
2628 return ddc_pin;
2629}
2630
2631static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2632{
2633 enum phy phy = intel_port_to_phy(dev_priv, port);
2634
2635 if (intel_phy_is_combo(dev_priv, phy))
2636 return GMBUS_PIN_1_BXT + port;
2637 else if (intel_phy_is_tc(dev_priv, phy))
2638 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2639
2640 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2641 return GMBUS_PIN_2_BXT;
2642}
2643
2644static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2645{
2646 enum phy phy = intel_port_to_phy(dev_priv, port);
2647 u8 ddc_pin;
2648
2649 switch (phy) {
2650 case PHY_A:
2651 ddc_pin = GMBUS_PIN_1_BXT;
2652 break;
2653 case PHY_B:
2654 ddc_pin = GMBUS_PIN_2_BXT;
2655 break;
2656 case PHY_C:
2657 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2658 break;
2659 default:
2660 MISSING_CASE(phy);
2661 ddc_pin = GMBUS_PIN_1_BXT;
2662 break;
2663 }
2664 return ddc_pin;
2665}
2666
2667static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2668{
2669 enum phy phy = intel_port_to_phy(dev_priv, port);
2670
2671 WARN_ON(port == PORT_C);
2672
2673 /*
2674 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2675 * final two outputs use type-c pins, even though they're actually
2676 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2677 * all outputs.
2678 */
2679 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2680 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2681
2682 return GMBUS_PIN_1_BXT + phy;
2683}
2684
2685static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2686{
2687 enum phy phy = intel_port_to_phy(i915, port);
2688
2689 drm_WARN_ON(&i915->drm, port == PORT_A);
2690
2691 /*
2692 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2693 * final two outputs use type-c pins, even though they're actually
2694 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2695 * all outputs.
2696 */
2697 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2698 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2699
2700 return GMBUS_PIN_1_BXT + phy;
2701}
2702
2703static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2704{
2705 return intel_port_to_phy(dev_priv, port) + 1;
2706}
2707
2708static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2709{
2710 enum phy phy = intel_port_to_phy(dev_priv, port);
2711
2712 WARN_ON(port == PORT_B || port == PORT_C);
2713
2714 /*
2715 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2716 * except first combo output.
2717 */
2718 if (phy == PHY_A)
2719 return GMBUS_PIN_1_BXT;
2720
2721 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2722}
2723
2724static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2725 enum port port)
2726{
2727 u8 ddc_pin;
2728
2729 switch (port) {
2730 case PORT_B:
2731 ddc_pin = GMBUS_PIN_DPB;
2732 break;
2733 case PORT_C:
2734 ddc_pin = GMBUS_PIN_DPC;
2735 break;
2736 case PORT_D:
2737 ddc_pin = GMBUS_PIN_DPD;
2738 break;
2739 default:
2740 MISSING_CASE(port);
2741 ddc_pin = GMBUS_PIN_DPB;
2742 break;
2743 }
2744 return ddc_pin;
2745}
2746
2747static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2748{
2749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750 enum port port = encoder->port;
2751 u8 ddc_pin;
2752
2753 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2754 if (ddc_pin) {
2755 drm_dbg_kms(&dev_priv->drm,
2756 "Using DDC pin 0x%x for port %c (VBT)\n",
2757 ddc_pin, port_name(port));
2758 return ddc_pin;
2759 }
2760
2761 if (IS_ALDERLAKE_S(dev_priv))
2762 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2763 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2764 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2765 else if (IS_ROCKETLAKE(dev_priv))
2766 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2767 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2768 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2769 else if (HAS_PCH_MCC(dev_priv))
2770 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2771 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2772 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2773 else if (HAS_PCH_CNP(dev_priv))
2774 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2775 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2776 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2777 else if (IS_CHERRYVIEW(dev_priv))
2778 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2779 else
2780 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2781
2782 drm_dbg_kms(&dev_priv->drm,
2783 "Using DDC pin 0x%x for port %c (platform default)\n",
2784 ddc_pin, port_name(port));
2785
2786 return ddc_pin;
2787}
2788
2789void intel_infoframe_init(struct intel_digital_port *dig_port)
2790{
2791 struct drm_i915_private *dev_priv =
2792 to_i915(dig_port->base.base.dev);
2793
2794 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2795 dig_port->write_infoframe = vlv_write_infoframe;
2796 dig_port->read_infoframe = vlv_read_infoframe;
2797 dig_port->set_infoframes = vlv_set_infoframes;
2798 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2799 } else if (IS_G4X(dev_priv)) {
2800 dig_port->write_infoframe = g4x_write_infoframe;
2801 dig_port->read_infoframe = g4x_read_infoframe;
2802 dig_port->set_infoframes = g4x_set_infoframes;
2803 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2804 } else if (HAS_DDI(dev_priv)) {
2805 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2806 dig_port->write_infoframe = lspcon_write_infoframe;
2807 dig_port->read_infoframe = lspcon_read_infoframe;
2808 dig_port->set_infoframes = lspcon_set_infoframes;
2809 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2810 } else {
2811 dig_port->write_infoframe = hsw_write_infoframe;
2812 dig_port->read_infoframe = hsw_read_infoframe;
2813 dig_port->set_infoframes = hsw_set_infoframes;
2814 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2815 }
2816 } else if (HAS_PCH_IBX(dev_priv)) {
2817 dig_port->write_infoframe = ibx_write_infoframe;
2818 dig_port->read_infoframe = ibx_read_infoframe;
2819 dig_port->set_infoframes = ibx_set_infoframes;
2820 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2821 } else {
2822 dig_port->write_infoframe = cpt_write_infoframe;
2823 dig_port->read_infoframe = cpt_read_infoframe;
2824 dig_port->set_infoframes = cpt_set_infoframes;
2825 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2826 }
2827}
2828
2829void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2830 struct intel_connector *intel_connector)
2831{
2832 struct drm_connector *connector = &intel_connector->base;
2833 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2834 struct intel_encoder *intel_encoder = &dig_port->base;
2835 struct drm_device *dev = intel_encoder->base.dev;
2836 struct drm_i915_private *dev_priv = to_i915(dev);
2837 struct i2c_adapter *ddc;
2838 enum port port = intel_encoder->port;
2839 struct cec_connector_info conn_info;
2840
2841 drm_dbg_kms(&dev_priv->drm,
2842 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2843 intel_encoder->base.base.id, intel_encoder->base.name);
2844
2845 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2846 return;
2847
2848 if (drm_WARN(dev, dig_port->max_lanes < 4,
2849 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2850 dig_port->max_lanes, intel_encoder->base.base.id,
2851 intel_encoder->base.name))
2852 return;
2853
2854 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2855 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2856
2857 drm_connector_init_with_ddc(dev, connector,
2858 &intel_hdmi_connector_funcs,
2859 DRM_MODE_CONNECTOR_HDMIA,
2860 ddc);
2861 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2862
2863 connector->interlace_allowed = 1;
2864 connector->doublescan_allowed = 0;
2865 connector->stereo_allowed = 1;
2866
2867 if (DISPLAY_VER(dev_priv) >= 10)
2868 connector->ycbcr_420_allowed = true;
2869
2870 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2871
2872 if (HAS_DDI(dev_priv))
2873 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2874 else
2875 intel_connector->get_hw_state = intel_connector_get_hw_state;
2876
2877 intel_hdmi_add_properties(intel_hdmi, connector);
2878
2879 intel_connector_attach_encoder(intel_connector, intel_encoder);
2880 intel_hdmi->attached_connector = intel_connector;
2881
2882 if (is_hdcp_supported(dev_priv, port)) {
2883 int ret = intel_hdcp_init(intel_connector, dig_port,
2884 &intel_hdmi_hdcp_shim);
2885 if (ret)
2886 drm_dbg_kms(&dev_priv->drm,
2887 "HDCP init failed, skipping.\n");
2888 }
2889
2890 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2891 * 0xd. Failure to do so will result in spurious interrupts being
2892 * generated on the port when a cable is not attached.
2893 */
2894 if (IS_G45(dev_priv)) {
2895 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2896 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2897 (temp & ~0xf) | 0xd);
2898 }
2899
2900 cec_fill_conn_info_from_drm(&conn_info, connector);
2901
2902 intel_hdmi->cec_notifier =
2903 cec_notifier_conn_register(dev->dev, port_identifier(port),
2904 &conn_info);
2905 if (!intel_hdmi->cec_notifier)
2906 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2907}
2908
2909/*
2910 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2911 * @vactive: Vactive of a display mode
2912 *
2913 * @return: appropriate dsc slice height for a given mode.
2914 */
2915int intel_hdmi_dsc_get_slice_height(int vactive)
2916{
2917 int slice_height;
2918
2919 /*
2920 * Slice Height determination : HDMI2.1 Section 7.7.5.2
2921 * Select smallest slice height >=96, that results in a valid PPS and
2922 * requires minimum padding lines required for final slice.
2923 *
2924 * Assumption : Vactive is even.
2925 */
2926 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
2927 if (vactive % slice_height == 0)
2928 return slice_height;
2929
2930 return 0;
2931}
2932
2933/*
2934 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
2935 * and dsc decoder capabilities
2936 *
2937 * @crtc_state: intel crtc_state
2938 * @src_max_slices: maximum slices supported by the DSC encoder
2939 * @src_max_slice_width: maximum slice width supported by DSC encoder
2940 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
2941 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
2942 *
2943 * @return: num of dsc slices that can be supported by the dsc encoder
2944 * and decoder.
2945 */
2946int
2947intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
2948 int src_max_slices, int src_max_slice_width,
2949 int hdmi_max_slices, int hdmi_throughput)
2950{
2951/* Pixel rates in KPixels/sec */
2952#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
2953/*
2954 * Rates at which the source and sink are required to process pixels in each
2955 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
2956 */
2957#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
2958#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
2959
2960/* Spec limits the slice width to 2720 pixels */
2961#define MAX_HDMI_SLICE_WIDTH 2720
2962 int kslice_adjust;
2963 int adjusted_clk_khz;
2964 int min_slices;
2965 int target_slices;
2966 int max_throughput; /* max clock freq. in khz per slice */
2967 int max_slice_width;
2968 int slice_width;
2969 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
2970
2971 if (!hdmi_throughput)
2972 return 0;
2973
2974 /*
2975 * Slice Width determination : HDMI2.1 Section 7.7.5.1
2976 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
2977 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
2978 * dividing adjusted clock value by 10.
2979 */
2980 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
2981 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2982 kslice_adjust = 10;
2983 else
2984 kslice_adjust = 5;
2985
2986 /*
2987 * As per spec, the rate at which the source and the sink process
2988 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
2989 * This depends upon the pixel clock rate and output formats
2990 * (kslice adjust).
2991 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
2992 * at max 340MHz, otherwise they can be processed at max 400MHz.
2993 */
2994
2995 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
2996
2997 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
2998 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
2999 else
3000 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3001
3002 /*
3003 * Taking into account the sink's capability for maximum
3004 * clock per slice (in MHz) as read from HF-VSDB.
3005 */
3006 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3007
3008 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3009 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3010
3011 /*
3012 * Keep on increasing the num of slices/line, starting from min_slices
3013 * per line till we get such a number, for which the slice_width is
3014 * just less than max_slice_width. The slices/line selected should be
3015 * less than or equal to the max horizontal slices that the combination
3016 * of PCON encoder and HDMI decoder can support.
3017 */
3018 slice_width = max_slice_width;
3019
3020 do {
3021 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3022 target_slices = 1;
3023 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3024 target_slices = 2;
3025 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3026 target_slices = 4;
3027 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3028 target_slices = 8;
3029 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3030 target_slices = 12;
3031 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3032 target_slices = 16;
3033 else
3034 return 0;
3035
3036 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3037 if (slice_width >= max_slice_width)
3038 min_slices = target_slices + 1;
3039 } while (slice_width >= max_slice_width);
3040
3041 return target_slices;
3042}
3043
3044/*
3045 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3046 * source and sink capabilities.
3047 *
3048 * @src_fraction_bpp: fractional bpp supported by the source
3049 * @slice_width: dsc slice width supported by the source and sink
3050 * @num_slices: num of slices supported by the source and sink
3051 * @output_format: video output format
3052 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3053 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3054 *
3055 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3056 */
3057int
3058intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3059 int output_format, bool hdmi_all_bpp,
3060 int hdmi_max_chunk_bytes)
3061{
3062 int max_dsc_bpp, min_dsc_bpp;
3063 int target_bytes;
3064 bool bpp_found = false;
3065 int bpp_decrement_x16;
3066 int bpp_target;
3067 int bpp_target_x16;
3068
3069 /*
3070 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3071 * Start with the max bpp and keep on decrementing with
3072 * fractional bpp, if supported by PCON DSC encoder
3073 *
3074 * for each bpp we check if no of bytes can be supported by HDMI sink
3075 */
3076
3077 /* Assuming: bpc as 8*/
3078 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3079 min_dsc_bpp = 6;
3080 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3081 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3082 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3083 min_dsc_bpp = 8;
3084 max_dsc_bpp = 3 * 8; /* 3*bpc */
3085 } else {
3086 /* Assuming 4:2:2 encoding */
3087 min_dsc_bpp = 7;
3088 max_dsc_bpp = 2 * 8; /* 2*bpc */
3089 }
3090
3091 /*
3092 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3093 * Section 7.7.34 : Source shall not enable compressed Video
3094 * Transport with bpp_target settings above 12 bpp unless
3095 * DSC_all_bpp is set to 1.
3096 */
3097 if (!hdmi_all_bpp)
3098 max_dsc_bpp = min(max_dsc_bpp, 12);
3099
3100 /*
3101 * The Sink has a limit of compressed data in bytes for a scanline,
3102 * as described in max_chunk_bytes field in HFVSDB block of edid.
3103 * The no. of bytes depend on the target bits per pixel that the
3104 * source configures. So we start with the max_bpp and calculate
3105 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3106 * till we get the target_chunk_bytes just less than what the sink's
3107 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3108 *
3109 * The decrement is according to the fractional support from PCON DSC
3110 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3111 *
3112 * bpp_target_x16 = bpp_target * 16
3113 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3114 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3115 */
3116
3117 bpp_target = max_dsc_bpp;
3118
3119 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3120 if (!src_fractional_bpp)
3121 src_fractional_bpp = 1;
3122 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3123 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3124
3125 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3126 int bpp;
3127
3128 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3129 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3130 if (target_bytes <= hdmi_max_chunk_bytes) {
3131 bpp_found = true;
3132 break;
3133 }
3134 bpp_target_x16 -= bpp_decrement_x16;
3135 }
3136 if (bpp_found)
3137 return bpp_target_x16;
3138
3139 return 0;
3140}
1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <drm/display/drm_hdcp_helper.h>
36#include <drm/display/drm_hdmi_helper.h>
37#include <drm/display/drm_scdc_helper.h>
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_crtc.h>
40#include <drm/drm_edid.h>
41#include <drm/intel_lpe_audio.h>
42
43#include "i915_debugfs.h"
44#include "i915_drv.h"
45#include "i915_reg.h"
46#include "intel_atomic.h"
47#include "intel_connector.h"
48#include "intel_ddi.h"
49#include "intel_de.h"
50#include "intel_display_types.h"
51#include "intel_dp.h"
52#include "intel_gmbus.h"
53#include "intel_hdcp.h"
54#include "intel_hdcp_regs.h"
55#include "intel_hdmi.h"
56#include "intel_lspcon.h"
57#include "intel_panel.h"
58#include "intel_snps_phy.h"
59
60static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
61{
62 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
63}
64
65static void
66assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
67{
68 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
69 u32 enabled_bits;
70
71 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
72
73 drm_WARN(&dev_priv->drm,
74 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
75 "HDMI port enabled, expecting disabled\n");
76}
77
78static void
79assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
80 enum transcoder cpu_transcoder)
81{
82 drm_WARN(&dev_priv->drm,
83 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
84 TRANS_DDI_FUNC_ENABLE,
85 "HDMI transcoder function enabled, expecting disabled\n");
86}
87
88static u32 g4x_infoframe_index(unsigned int type)
89{
90 switch (type) {
91 case HDMI_PACKET_TYPE_GAMUT_METADATA:
92 return VIDEO_DIP_SELECT_GAMUT;
93 case HDMI_INFOFRAME_TYPE_AVI:
94 return VIDEO_DIP_SELECT_AVI;
95 case HDMI_INFOFRAME_TYPE_SPD:
96 return VIDEO_DIP_SELECT_SPD;
97 case HDMI_INFOFRAME_TYPE_VENDOR:
98 return VIDEO_DIP_SELECT_VENDOR;
99 default:
100 MISSING_CASE(type);
101 return 0;
102 }
103}
104
105static u32 g4x_infoframe_enable(unsigned int type)
106{
107 switch (type) {
108 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
109 return VIDEO_DIP_ENABLE_GCP;
110 case HDMI_PACKET_TYPE_GAMUT_METADATA:
111 return VIDEO_DIP_ENABLE_GAMUT;
112 case DP_SDP_VSC:
113 return 0;
114 case HDMI_INFOFRAME_TYPE_AVI:
115 return VIDEO_DIP_ENABLE_AVI;
116 case HDMI_INFOFRAME_TYPE_SPD:
117 return VIDEO_DIP_ENABLE_SPD;
118 case HDMI_INFOFRAME_TYPE_VENDOR:
119 return VIDEO_DIP_ENABLE_VENDOR;
120 case HDMI_INFOFRAME_TYPE_DRM:
121 return 0;
122 default:
123 MISSING_CASE(type);
124 return 0;
125 }
126}
127
128static u32 hsw_infoframe_enable(unsigned int type)
129{
130 switch (type) {
131 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
132 return VIDEO_DIP_ENABLE_GCP_HSW;
133 case HDMI_PACKET_TYPE_GAMUT_METADATA:
134 return VIDEO_DIP_ENABLE_GMP_HSW;
135 case DP_SDP_VSC:
136 return VIDEO_DIP_ENABLE_VSC_HSW;
137 case DP_SDP_PPS:
138 return VDIP_ENABLE_PPS;
139 case HDMI_INFOFRAME_TYPE_AVI:
140 return VIDEO_DIP_ENABLE_AVI_HSW;
141 case HDMI_INFOFRAME_TYPE_SPD:
142 return VIDEO_DIP_ENABLE_SPD_HSW;
143 case HDMI_INFOFRAME_TYPE_VENDOR:
144 return VIDEO_DIP_ENABLE_VS_HSW;
145 case HDMI_INFOFRAME_TYPE_DRM:
146 return VIDEO_DIP_ENABLE_DRM_GLK;
147 default:
148 MISSING_CASE(type);
149 return 0;
150 }
151}
152
153static i915_reg_t
154hsw_dip_data_reg(struct drm_i915_private *dev_priv,
155 enum transcoder cpu_transcoder,
156 unsigned int type,
157 int i)
158{
159 switch (type) {
160 case HDMI_PACKET_TYPE_GAMUT_METADATA:
161 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
162 case DP_SDP_VSC:
163 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
164 case DP_SDP_PPS:
165 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_AVI:
167 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_SPD:
169 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
170 case HDMI_INFOFRAME_TYPE_VENDOR:
171 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
172 case HDMI_INFOFRAME_TYPE_DRM:
173 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
174 default:
175 MISSING_CASE(type);
176 return INVALID_MMIO_REG;
177 }
178}
179
180static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
181 unsigned int type)
182{
183 switch (type) {
184 case DP_SDP_VSC:
185 return VIDEO_DIP_VSC_DATA_SIZE;
186 case DP_SDP_PPS:
187 return VIDEO_DIP_PPS_DATA_SIZE;
188 case HDMI_PACKET_TYPE_GAMUT_METADATA:
189 if (DISPLAY_VER(dev_priv) >= 11)
190 return VIDEO_DIP_GMP_DATA_SIZE;
191 else
192 return VIDEO_DIP_DATA_SIZE;
193 default:
194 return VIDEO_DIP_DATA_SIZE;
195 }
196}
197
198static void g4x_write_infoframe(struct intel_encoder *encoder,
199 const struct intel_crtc_state *crtc_state,
200 unsigned int type,
201 const void *frame, ssize_t len)
202{
203 const u32 *data = frame;
204 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
205 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
206 int i;
207
208 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
209 "Writing DIP with CTL reg disabled\n");
210
211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
212 val |= g4x_infoframe_index(type);
213
214 val &= ~g4x_infoframe_enable(type);
215
216 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
217
218 for (i = 0; i < len; i += 4) {
219 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
220 data++;
221 }
222 /* Write every possible data byte to force correct ECC calculation. */
223 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
224 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
225
226 val |= g4x_infoframe_enable(type);
227 val &= ~VIDEO_DIP_FREQ_MASK;
228 val |= VIDEO_DIP_FREQ_VSYNC;
229
230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
231 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
232}
233
234static void g4x_read_infoframe(struct intel_encoder *encoder,
235 const struct intel_crtc_state *crtc_state,
236 unsigned int type,
237 void *frame, ssize_t len)
238{
239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
240 u32 val, *data = frame;
241 int i;
242
243 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
244
245 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
246 val |= g4x_infoframe_index(type);
247
248 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
249
250 for (i = 0; i < len; i += 4)
251 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
252}
253
254static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
255 const struct intel_crtc_state *pipe_config)
256{
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
258 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
259
260 if ((val & VIDEO_DIP_ENABLE) == 0)
261 return 0;
262
263 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
264 return 0;
265
266 return val & (VIDEO_DIP_ENABLE_AVI |
267 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
268}
269
270static void ibx_write_infoframe(struct intel_encoder *encoder,
271 const struct intel_crtc_state *crtc_state,
272 unsigned int type,
273 const void *frame, ssize_t len)
274{
275 const u32 *data = frame;
276 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
278 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
279 u32 val = intel_de_read(dev_priv, reg);
280 int i;
281
282 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
283 "Writing DIP with CTL reg disabled\n");
284
285 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
286 val |= g4x_infoframe_index(type);
287
288 val &= ~g4x_infoframe_enable(type);
289
290 intel_de_write(dev_priv, reg, val);
291
292 for (i = 0; i < len; i += 4) {
293 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
294 *data);
295 data++;
296 }
297 /* Write every possible data byte to force correct ECC calculation. */
298 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
299 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
300
301 val |= g4x_infoframe_enable(type);
302 val &= ~VIDEO_DIP_FREQ_MASK;
303 val |= VIDEO_DIP_FREQ_VSYNC;
304
305 intel_de_write(dev_priv, reg, val);
306 intel_de_posting_read(dev_priv, reg);
307}
308
309static void ibx_read_infoframe(struct intel_encoder *encoder,
310 const struct intel_crtc_state *crtc_state,
311 unsigned int type,
312 void *frame, ssize_t len)
313{
314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
316 u32 val, *data = frame;
317 int i;
318
319 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
320
321 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
322 val |= g4x_infoframe_index(type);
323
324 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
325
326 for (i = 0; i < len; i += 4)
327 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
328}
329
330static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
331 const struct intel_crtc_state *pipe_config)
332{
333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
334 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
335 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
336 u32 val = intel_de_read(dev_priv, reg);
337
338 if ((val & VIDEO_DIP_ENABLE) == 0)
339 return 0;
340
341 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
342 return 0;
343
344 return val & (VIDEO_DIP_ENABLE_AVI |
345 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
346 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
347}
348
349static void cpt_write_infoframe(struct intel_encoder *encoder,
350 const struct intel_crtc_state *crtc_state,
351 unsigned int type,
352 const void *frame, ssize_t len)
353{
354 const u32 *data = frame;
355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
356 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
357 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
358 u32 val = intel_de_read(dev_priv, reg);
359 int i;
360
361 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
362 "Writing DIP with CTL reg disabled\n");
363
364 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
365 val |= g4x_infoframe_index(type);
366
367 /* The DIP control register spec says that we need to update the AVI
368 * infoframe without clearing its enable bit */
369 if (type != HDMI_INFOFRAME_TYPE_AVI)
370 val &= ~g4x_infoframe_enable(type);
371
372 intel_de_write(dev_priv, reg, val);
373
374 for (i = 0; i < len; i += 4) {
375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
376 *data);
377 data++;
378 }
379 /* Write every possible data byte to force correct ECC calculation. */
380 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
381 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
382
383 val |= g4x_infoframe_enable(type);
384 val &= ~VIDEO_DIP_FREQ_MASK;
385 val |= VIDEO_DIP_FREQ_VSYNC;
386
387 intel_de_write(dev_priv, reg, val);
388 intel_de_posting_read(dev_priv, reg);
389}
390
391static void cpt_read_infoframe(struct intel_encoder *encoder,
392 const struct intel_crtc_state *crtc_state,
393 unsigned int type,
394 void *frame, ssize_t len)
395{
396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
397 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
398 u32 val, *data = frame;
399 int i;
400
401 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
402
403 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
404 val |= g4x_infoframe_index(type);
405
406 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
407
408 for (i = 0; i < len; i += 4)
409 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
410}
411
412static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
413 const struct intel_crtc_state *pipe_config)
414{
415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
417 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
418
419 if ((val & VIDEO_DIP_ENABLE) == 0)
420 return 0;
421
422 return val & (VIDEO_DIP_ENABLE_AVI |
423 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
424 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
425}
426
427static void vlv_write_infoframe(struct intel_encoder *encoder,
428 const struct intel_crtc_state *crtc_state,
429 unsigned int type,
430 const void *frame, ssize_t len)
431{
432 const u32 *data = frame;
433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
436 u32 val = intel_de_read(dev_priv, reg);
437 int i;
438
439 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
440 "Writing DIP with CTL reg disabled\n");
441
442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
443 val |= g4x_infoframe_index(type);
444
445 val &= ~g4x_infoframe_enable(type);
446
447 intel_de_write(dev_priv, reg, val);
448
449 for (i = 0; i < len; i += 4) {
450 intel_de_write(dev_priv,
451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
452 data++;
453 }
454 /* Write every possible data byte to force correct ECC calculation. */
455 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
456 intel_de_write(dev_priv,
457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
458
459 val |= g4x_infoframe_enable(type);
460 val &= ~VIDEO_DIP_FREQ_MASK;
461 val |= VIDEO_DIP_FREQ_VSYNC;
462
463 intel_de_write(dev_priv, reg, val);
464 intel_de_posting_read(dev_priv, reg);
465}
466
467static void vlv_read_infoframe(struct intel_encoder *encoder,
468 const struct intel_crtc_state *crtc_state,
469 unsigned int type,
470 void *frame, ssize_t len)
471{
472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
474 u32 val, *data = frame;
475 int i;
476
477 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
478
479 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
480 val |= g4x_infoframe_index(type);
481
482 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
483
484 for (i = 0; i < len; i += 4)
485 *data++ = intel_de_read(dev_priv,
486 VLV_TVIDEO_DIP_DATA(crtc->pipe));
487}
488
489static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
490 const struct intel_crtc_state *pipe_config)
491{
492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
493 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
494 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
495
496 if ((val & VIDEO_DIP_ENABLE) == 0)
497 return 0;
498
499 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
500 return 0;
501
502 return val & (VIDEO_DIP_ENABLE_AVI |
503 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
504 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
505}
506
507void hsw_write_infoframe(struct intel_encoder *encoder,
508 const struct intel_crtc_state *crtc_state,
509 unsigned int type,
510 const void *frame, ssize_t len)
511{
512 const u32 *data = frame;
513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
514 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
515 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
516 int data_size;
517 int i;
518 u32 val = intel_de_read(dev_priv, ctl_reg);
519
520 data_size = hsw_dip_data_size(dev_priv, type);
521
522 drm_WARN_ON(&dev_priv->drm, len > data_size);
523
524 val &= ~hsw_infoframe_enable(type);
525 intel_de_write(dev_priv, ctl_reg, val);
526
527 for (i = 0; i < len; i += 4) {
528 intel_de_write(dev_priv,
529 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
530 *data);
531 data++;
532 }
533 /* Write every possible data byte to force correct ECC calculation. */
534 for (; i < data_size; i += 4)
535 intel_de_write(dev_priv,
536 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
537 0);
538
539 /* Wa_14013475917 */
540 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
541 type == DP_SDP_VSC)
542 return;
543
544 val |= hsw_infoframe_enable(type);
545 intel_de_write(dev_priv, ctl_reg, val);
546 intel_de_posting_read(dev_priv, ctl_reg);
547}
548
549void hsw_read_infoframe(struct intel_encoder *encoder,
550 const struct intel_crtc_state *crtc_state,
551 unsigned int type, void *frame, ssize_t len)
552{
553 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
554 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
555 u32 *data = frame;
556 int i;
557
558 for (i = 0; i < len; i += 4)
559 *data++ = intel_de_read(dev_priv,
560 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
561}
562
563static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
564 const struct intel_crtc_state *pipe_config)
565{
566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
567 u32 val = intel_de_read(dev_priv,
568 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
569 u32 mask;
570
571 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
572 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
573 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
574
575 if (DISPLAY_VER(dev_priv) >= 10)
576 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
577
578 return val & mask;
579}
580
581static const u8 infoframe_type_to_idx[] = {
582 HDMI_PACKET_TYPE_GENERAL_CONTROL,
583 HDMI_PACKET_TYPE_GAMUT_METADATA,
584 DP_SDP_VSC,
585 HDMI_INFOFRAME_TYPE_AVI,
586 HDMI_INFOFRAME_TYPE_SPD,
587 HDMI_INFOFRAME_TYPE_VENDOR,
588 HDMI_INFOFRAME_TYPE_DRM,
589};
590
591u32 intel_hdmi_infoframe_enable(unsigned int type)
592{
593 int i;
594
595 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
596 if (infoframe_type_to_idx[i] == type)
597 return BIT(i);
598 }
599
600 return 0;
601}
602
603u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
604 const struct intel_crtc_state *crtc_state)
605{
606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
607 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
608 u32 val, ret = 0;
609 int i;
610
611 val = dig_port->infoframes_enabled(encoder, crtc_state);
612
613 /* map from hardware bits to dip idx */
614 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
615 unsigned int type = infoframe_type_to_idx[i];
616
617 if (HAS_DDI(dev_priv)) {
618 if (val & hsw_infoframe_enable(type))
619 ret |= BIT(i);
620 } else {
621 if (val & g4x_infoframe_enable(type))
622 ret |= BIT(i);
623 }
624 }
625
626 return ret;
627}
628
629/*
630 * The data we write to the DIP data buffer registers is 1 byte bigger than the
631 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
632 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
633 * used for both technologies.
634 *
635 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
636 * DW1: DB3 | DB2 | DB1 | DB0
637 * DW2: DB7 | DB6 | DB5 | DB4
638 * DW3: ...
639 *
640 * (HB is Header Byte, DB is Data Byte)
641 *
642 * The hdmi pack() functions don't know about that hardware specific hole so we
643 * trick them by giving an offset into the buffer and moving back the header
644 * bytes by one.
645 */
646static void intel_write_infoframe(struct intel_encoder *encoder,
647 const struct intel_crtc_state *crtc_state,
648 enum hdmi_infoframe_type type,
649 const union hdmi_infoframe *frame)
650{
651 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
652 u8 buffer[VIDEO_DIP_DATA_SIZE];
653 ssize_t len;
654
655 if ((crtc_state->infoframes.enable &
656 intel_hdmi_infoframe_enable(type)) == 0)
657 return;
658
659 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
660 return;
661
662 /* see comment above for the reason for this offset */
663 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
664 if (drm_WARN_ON(encoder->base.dev, len < 0))
665 return;
666
667 /* Insert the 'hole' (see big comment above) at position 3 */
668 memmove(&buffer[0], &buffer[1], 3);
669 buffer[3] = 0;
670 len++;
671
672 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
673}
674
675void intel_read_infoframe(struct intel_encoder *encoder,
676 const struct intel_crtc_state *crtc_state,
677 enum hdmi_infoframe_type type,
678 union hdmi_infoframe *frame)
679{
680 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
681 u8 buffer[VIDEO_DIP_DATA_SIZE];
682 int ret;
683
684 if ((crtc_state->infoframes.enable &
685 intel_hdmi_infoframe_enable(type)) == 0)
686 return;
687
688 dig_port->read_infoframe(encoder, crtc_state,
689 type, buffer, sizeof(buffer));
690
691 /* Fill the 'hole' (see big comment above) at position 3 */
692 memmove(&buffer[1], &buffer[0], 3);
693
694 /* see comment above for the reason for this offset */
695 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
696 if (ret) {
697 drm_dbg_kms(encoder->base.dev,
698 "Failed to unpack infoframe type 0x%02x\n", type);
699 return;
700 }
701
702 if (frame->any.type != type)
703 drm_dbg_kms(encoder->base.dev,
704 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
705 frame->any.type, type);
706}
707
708static bool
709intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
710 struct intel_crtc_state *crtc_state,
711 struct drm_connector_state *conn_state)
712{
713 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
714 const struct drm_display_mode *adjusted_mode =
715 &crtc_state->hw.adjusted_mode;
716 struct drm_connector *connector = conn_state->connector;
717 int ret;
718
719 if (!crtc_state->has_infoframe)
720 return true;
721
722 crtc_state->infoframes.enable |=
723 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
724
725 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
726 adjusted_mode);
727 if (ret)
728 return false;
729
730 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
731 frame->colorspace = HDMI_COLORSPACE_YUV420;
732 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
733 frame->colorspace = HDMI_COLORSPACE_YUV444;
734 else
735 frame->colorspace = HDMI_COLORSPACE_RGB;
736
737 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
738
739 /* nonsense combination */
740 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
742
743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
744 drm_hdmi_avi_infoframe_quant_range(frame, connector,
745 adjusted_mode,
746 crtc_state->limited_color_range ?
747 HDMI_QUANTIZATION_RANGE_LIMITED :
748 HDMI_QUANTIZATION_RANGE_FULL);
749 } else {
750 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
751 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
752 }
753
754 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
755
756 /* TODO: handle pixel repetition for YCBCR420 outputs */
757
758 ret = hdmi_avi_infoframe_check(frame);
759 if (drm_WARN_ON(encoder->base.dev, ret))
760 return false;
761
762 return true;
763}
764
765static bool
766intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
767 struct intel_crtc_state *crtc_state,
768 struct drm_connector_state *conn_state)
769{
770 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
771 int ret;
772
773 if (!crtc_state->has_infoframe)
774 return true;
775
776 crtc_state->infoframes.enable |=
777 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
778
779 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
780 if (drm_WARN_ON(encoder->base.dev, ret))
781 return false;
782
783 frame->sdi = HDMI_SPD_SDI_PC;
784
785 ret = hdmi_spd_infoframe_check(frame);
786 if (drm_WARN_ON(encoder->base.dev, ret))
787 return false;
788
789 return true;
790}
791
792static bool
793intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
794 struct intel_crtc_state *crtc_state,
795 struct drm_connector_state *conn_state)
796{
797 struct hdmi_vendor_infoframe *frame =
798 &crtc_state->infoframes.hdmi.vendor.hdmi;
799 const struct drm_display_info *info =
800 &conn_state->connector->display_info;
801 int ret;
802
803 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
804 return true;
805
806 crtc_state->infoframes.enable |=
807 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
808
809 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
810 conn_state->connector,
811 &crtc_state->hw.adjusted_mode);
812 if (drm_WARN_ON(encoder->base.dev, ret))
813 return false;
814
815 ret = hdmi_vendor_infoframe_check(frame);
816 if (drm_WARN_ON(encoder->base.dev, ret))
817 return false;
818
819 return true;
820}
821
822static bool
823intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
824 struct intel_crtc_state *crtc_state,
825 struct drm_connector_state *conn_state)
826{
827 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
829 int ret;
830
831 if (DISPLAY_VER(dev_priv) < 10)
832 return true;
833
834 if (!crtc_state->has_infoframe)
835 return true;
836
837 if (!conn_state->hdr_output_metadata)
838 return true;
839
840 crtc_state->infoframes.enable |=
841 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
842
843 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
844 if (ret < 0) {
845 drm_dbg_kms(&dev_priv->drm,
846 "couldn't set HDR metadata in infoframe\n");
847 return false;
848 }
849
850 ret = hdmi_drm_infoframe_check(frame);
851 if (drm_WARN_ON(&dev_priv->drm, ret))
852 return false;
853
854 return true;
855}
856
857static void g4x_set_infoframes(struct intel_encoder *encoder,
858 bool enable,
859 const struct intel_crtc_state *crtc_state,
860 const struct drm_connector_state *conn_state)
861{
862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
863 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
864 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
865 i915_reg_t reg = VIDEO_DIP_CTL;
866 u32 val = intel_de_read(dev_priv, reg);
867 u32 port = VIDEO_DIP_PORT(encoder->port);
868
869 assert_hdmi_port_disabled(intel_hdmi);
870
871 /* If the registers were not initialized yet, they might be zeroes,
872 * which means we're selecting the AVI DIP and we're setting its
873 * frequency to once. This seems to really confuse the HW and make
874 * things stop working (the register spec says the AVI always needs to
875 * be sent every VSync). So here we avoid writing to the register more
876 * than we need and also explicitly select the AVI DIP and explicitly
877 * set its frequency to every VSync. Avoiding to write it twice seems to
878 * be enough to solve the problem, but being defensive shouldn't hurt us
879 * either. */
880 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
881
882 if (!enable) {
883 if (!(val & VIDEO_DIP_ENABLE))
884 return;
885 if (port != (val & VIDEO_DIP_PORT_MASK)) {
886 drm_dbg_kms(&dev_priv->drm,
887 "video DIP still enabled on port %c\n",
888 (val & VIDEO_DIP_PORT_MASK) >> 29);
889 return;
890 }
891 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
892 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
893 intel_de_write(dev_priv, reg, val);
894 intel_de_posting_read(dev_priv, reg);
895 return;
896 }
897
898 if (port != (val & VIDEO_DIP_PORT_MASK)) {
899 if (val & VIDEO_DIP_ENABLE) {
900 drm_dbg_kms(&dev_priv->drm,
901 "video DIP already enabled on port %c\n",
902 (val & VIDEO_DIP_PORT_MASK) >> 29);
903 return;
904 }
905 val &= ~VIDEO_DIP_PORT_MASK;
906 val |= port;
907 }
908
909 val |= VIDEO_DIP_ENABLE;
910 val &= ~(VIDEO_DIP_ENABLE_AVI |
911 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
912
913 intel_de_write(dev_priv, reg, val);
914 intel_de_posting_read(dev_priv, reg);
915
916 intel_write_infoframe(encoder, crtc_state,
917 HDMI_INFOFRAME_TYPE_AVI,
918 &crtc_state->infoframes.avi);
919 intel_write_infoframe(encoder, crtc_state,
920 HDMI_INFOFRAME_TYPE_SPD,
921 &crtc_state->infoframes.spd);
922 intel_write_infoframe(encoder, crtc_state,
923 HDMI_INFOFRAME_TYPE_VENDOR,
924 &crtc_state->infoframes.hdmi);
925}
926
927/*
928 * Determine if default_phase=1 can be indicated in the GCP infoframe.
929 *
930 * From HDMI specification 1.4a:
931 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
932 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
933 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
934 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
935 * phase of 0
936 */
937static bool gcp_default_phase_possible(int pipe_bpp,
938 const struct drm_display_mode *mode)
939{
940 unsigned int pixels_per_group;
941
942 switch (pipe_bpp) {
943 case 30:
944 /* 4 pixels in 5 clocks */
945 pixels_per_group = 4;
946 break;
947 case 36:
948 /* 2 pixels in 3 clocks */
949 pixels_per_group = 2;
950 break;
951 case 48:
952 /* 1 pixel in 2 clocks */
953 pixels_per_group = 1;
954 break;
955 default:
956 /* phase information not relevant for 8bpc */
957 return false;
958 }
959
960 return mode->crtc_hdisplay % pixels_per_group == 0 &&
961 mode->crtc_htotal % pixels_per_group == 0 &&
962 mode->crtc_hblank_start % pixels_per_group == 0 &&
963 mode->crtc_hblank_end % pixels_per_group == 0 &&
964 mode->crtc_hsync_start % pixels_per_group == 0 &&
965 mode->crtc_hsync_end % pixels_per_group == 0 &&
966 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
967 mode->crtc_htotal/2 % pixels_per_group == 0);
968}
969
970static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
971 const struct intel_crtc_state *crtc_state,
972 const struct drm_connector_state *conn_state)
973{
974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
975 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
976 i915_reg_t reg;
977
978 if ((crtc_state->infoframes.enable &
979 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
980 return false;
981
982 if (HAS_DDI(dev_priv))
983 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
984 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
985 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
986 else if (HAS_PCH_SPLIT(dev_priv))
987 reg = TVIDEO_DIP_GCP(crtc->pipe);
988 else
989 return false;
990
991 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
992
993 return true;
994}
995
996void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
997 struct intel_crtc_state *crtc_state)
998{
999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1001 i915_reg_t reg;
1002
1003 if ((crtc_state->infoframes.enable &
1004 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1005 return;
1006
1007 if (HAS_DDI(dev_priv))
1008 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1009 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1010 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1011 else if (HAS_PCH_SPLIT(dev_priv))
1012 reg = TVIDEO_DIP_GCP(crtc->pipe);
1013 else
1014 return;
1015
1016 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1017}
1018
1019static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1020 struct intel_crtc_state *crtc_state,
1021 struct drm_connector_state *conn_state)
1022{
1023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1024
1025 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1026 return;
1027
1028 crtc_state->infoframes.enable |=
1029 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1030
1031 /* Indicate color indication for deep color mode */
1032 if (crtc_state->pipe_bpp > 24)
1033 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1034
1035 /* Enable default_phase whenever the display mode is suitably aligned */
1036 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1037 &crtc_state->hw.adjusted_mode))
1038 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1039}
1040
1041static void ibx_set_infoframes(struct intel_encoder *encoder,
1042 bool enable,
1043 const struct intel_crtc_state *crtc_state,
1044 const struct drm_connector_state *conn_state)
1045{
1046 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1047 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1048 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1049 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1050 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1051 u32 val = intel_de_read(dev_priv, reg);
1052 u32 port = VIDEO_DIP_PORT(encoder->port);
1053
1054 assert_hdmi_port_disabled(intel_hdmi);
1055
1056 /* See the big comment in g4x_set_infoframes() */
1057 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1058
1059 if (!enable) {
1060 if (!(val & VIDEO_DIP_ENABLE))
1061 return;
1062 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1063 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1064 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1065 intel_de_write(dev_priv, reg, val);
1066 intel_de_posting_read(dev_priv, reg);
1067 return;
1068 }
1069
1070 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1071 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1072 "DIP already enabled on port %c\n",
1073 (val & VIDEO_DIP_PORT_MASK) >> 29);
1074 val &= ~VIDEO_DIP_PORT_MASK;
1075 val |= port;
1076 }
1077
1078 val |= VIDEO_DIP_ENABLE;
1079 val &= ~(VIDEO_DIP_ENABLE_AVI |
1080 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1081 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1082
1083 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1084 val |= VIDEO_DIP_ENABLE_GCP;
1085
1086 intel_de_write(dev_priv, reg, val);
1087 intel_de_posting_read(dev_priv, reg);
1088
1089 intel_write_infoframe(encoder, crtc_state,
1090 HDMI_INFOFRAME_TYPE_AVI,
1091 &crtc_state->infoframes.avi);
1092 intel_write_infoframe(encoder, crtc_state,
1093 HDMI_INFOFRAME_TYPE_SPD,
1094 &crtc_state->infoframes.spd);
1095 intel_write_infoframe(encoder, crtc_state,
1096 HDMI_INFOFRAME_TYPE_VENDOR,
1097 &crtc_state->infoframes.hdmi);
1098}
1099
1100static void cpt_set_infoframes(struct intel_encoder *encoder,
1101 bool enable,
1102 const struct intel_crtc_state *crtc_state,
1103 const struct drm_connector_state *conn_state)
1104{
1105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1106 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1107 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1108 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1109 u32 val = intel_de_read(dev_priv, reg);
1110
1111 assert_hdmi_port_disabled(intel_hdmi);
1112
1113 /* See the big comment in g4x_set_infoframes() */
1114 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1115
1116 if (!enable) {
1117 if (!(val & VIDEO_DIP_ENABLE))
1118 return;
1119 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1120 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1121 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1122 intel_de_write(dev_priv, reg, val);
1123 intel_de_posting_read(dev_priv, reg);
1124 return;
1125 }
1126
1127 /* Set both together, unset both together: see the spec. */
1128 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1129 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1130 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1131
1132 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1133 val |= VIDEO_DIP_ENABLE_GCP;
1134
1135 intel_de_write(dev_priv, reg, val);
1136 intel_de_posting_read(dev_priv, reg);
1137
1138 intel_write_infoframe(encoder, crtc_state,
1139 HDMI_INFOFRAME_TYPE_AVI,
1140 &crtc_state->infoframes.avi);
1141 intel_write_infoframe(encoder, crtc_state,
1142 HDMI_INFOFRAME_TYPE_SPD,
1143 &crtc_state->infoframes.spd);
1144 intel_write_infoframe(encoder, crtc_state,
1145 HDMI_INFOFRAME_TYPE_VENDOR,
1146 &crtc_state->infoframes.hdmi);
1147}
1148
1149static void vlv_set_infoframes(struct intel_encoder *encoder,
1150 bool enable,
1151 const struct intel_crtc_state *crtc_state,
1152 const struct drm_connector_state *conn_state)
1153{
1154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1156 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1157 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1158 u32 val = intel_de_read(dev_priv, reg);
1159 u32 port = VIDEO_DIP_PORT(encoder->port);
1160
1161 assert_hdmi_port_disabled(intel_hdmi);
1162
1163 /* See the big comment in g4x_set_infoframes() */
1164 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1165
1166 if (!enable) {
1167 if (!(val & VIDEO_DIP_ENABLE))
1168 return;
1169 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1170 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1171 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1172 intel_de_write(dev_priv, reg, val);
1173 intel_de_posting_read(dev_priv, reg);
1174 return;
1175 }
1176
1177 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1178 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1179 "DIP already enabled on port %c\n",
1180 (val & VIDEO_DIP_PORT_MASK) >> 29);
1181 val &= ~VIDEO_DIP_PORT_MASK;
1182 val |= port;
1183 }
1184
1185 val |= VIDEO_DIP_ENABLE;
1186 val &= ~(VIDEO_DIP_ENABLE_AVI |
1187 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1188 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1189
1190 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1191 val |= VIDEO_DIP_ENABLE_GCP;
1192
1193 intel_de_write(dev_priv, reg, val);
1194 intel_de_posting_read(dev_priv, reg);
1195
1196 intel_write_infoframe(encoder, crtc_state,
1197 HDMI_INFOFRAME_TYPE_AVI,
1198 &crtc_state->infoframes.avi);
1199 intel_write_infoframe(encoder, crtc_state,
1200 HDMI_INFOFRAME_TYPE_SPD,
1201 &crtc_state->infoframes.spd);
1202 intel_write_infoframe(encoder, crtc_state,
1203 HDMI_INFOFRAME_TYPE_VENDOR,
1204 &crtc_state->infoframes.hdmi);
1205}
1206
1207static void hsw_set_infoframes(struct intel_encoder *encoder,
1208 bool enable,
1209 const struct intel_crtc_state *crtc_state,
1210 const struct drm_connector_state *conn_state)
1211{
1212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1213 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1214 u32 val = intel_de_read(dev_priv, reg);
1215
1216 assert_hdmi_transcoder_func_disabled(dev_priv,
1217 crtc_state->cpu_transcoder);
1218
1219 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1220 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1221 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1222 VIDEO_DIP_ENABLE_DRM_GLK);
1223
1224 if (!enable) {
1225 intel_de_write(dev_priv, reg, val);
1226 intel_de_posting_read(dev_priv, reg);
1227 return;
1228 }
1229
1230 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1231 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1232
1233 intel_de_write(dev_priv, reg, val);
1234 intel_de_posting_read(dev_priv, reg);
1235
1236 intel_write_infoframe(encoder, crtc_state,
1237 HDMI_INFOFRAME_TYPE_AVI,
1238 &crtc_state->infoframes.avi);
1239 intel_write_infoframe(encoder, crtc_state,
1240 HDMI_INFOFRAME_TYPE_SPD,
1241 &crtc_state->infoframes.spd);
1242 intel_write_infoframe(encoder, crtc_state,
1243 HDMI_INFOFRAME_TYPE_VENDOR,
1244 &crtc_state->infoframes.hdmi);
1245 intel_write_infoframe(encoder, crtc_state,
1246 HDMI_INFOFRAME_TYPE_DRM,
1247 &crtc_state->infoframes.drm);
1248}
1249
1250void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1251{
1252 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1253 struct i2c_adapter *adapter;
1254
1255 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1256 return;
1257
1258 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1259
1260 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1261 enable ? "Enabling" : "Disabling");
1262
1263 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1264}
1265
1266static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1267 unsigned int offset, void *buffer, size_t size)
1268{
1269 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1270 struct intel_hdmi *hdmi = &dig_port->hdmi;
1271 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1272 hdmi->ddc_bus);
1273 int ret;
1274 u8 start = offset & 0xff;
1275 struct i2c_msg msgs[] = {
1276 {
1277 .addr = DRM_HDCP_DDC_ADDR,
1278 .flags = 0,
1279 .len = 1,
1280 .buf = &start,
1281 },
1282 {
1283 .addr = DRM_HDCP_DDC_ADDR,
1284 .flags = I2C_M_RD,
1285 .len = size,
1286 .buf = buffer
1287 }
1288 };
1289 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1290 if (ret == ARRAY_SIZE(msgs))
1291 return 0;
1292 return ret >= 0 ? -EIO : ret;
1293}
1294
1295static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1296 unsigned int offset, void *buffer, size_t size)
1297{
1298 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1299 struct intel_hdmi *hdmi = &dig_port->hdmi;
1300 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1301 hdmi->ddc_bus);
1302 int ret;
1303 u8 *write_buf;
1304 struct i2c_msg msg;
1305
1306 write_buf = kzalloc(size + 1, GFP_KERNEL);
1307 if (!write_buf)
1308 return -ENOMEM;
1309
1310 write_buf[0] = offset & 0xff;
1311 memcpy(&write_buf[1], buffer, size);
1312
1313 msg.addr = DRM_HDCP_DDC_ADDR;
1314 msg.flags = 0,
1315 msg.len = size + 1,
1316 msg.buf = write_buf;
1317
1318 ret = i2c_transfer(adapter, &msg, 1);
1319 if (ret == 1)
1320 ret = 0;
1321 else if (ret >= 0)
1322 ret = -EIO;
1323
1324 kfree(write_buf);
1325 return ret;
1326}
1327
1328static
1329int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1330 u8 *an)
1331{
1332 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1333 struct intel_hdmi *hdmi = &dig_port->hdmi;
1334 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1335 hdmi->ddc_bus);
1336 int ret;
1337
1338 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1339 DRM_HDCP_AN_LEN);
1340 if (ret) {
1341 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1342 ret);
1343 return ret;
1344 }
1345
1346 ret = intel_gmbus_output_aksv(adapter);
1347 if (ret < 0) {
1348 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1349 return ret;
1350 }
1351 return 0;
1352}
1353
1354static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1355 u8 *bksv)
1356{
1357 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1358
1359 int ret;
1360 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1361 DRM_HDCP_KSV_LEN);
1362 if (ret)
1363 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1364 ret);
1365 return ret;
1366}
1367
1368static
1369int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1370 u8 *bstatus)
1371{
1372 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1373
1374 int ret;
1375 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1376 bstatus, DRM_HDCP_BSTATUS_LEN);
1377 if (ret)
1378 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1379 ret);
1380 return ret;
1381}
1382
1383static
1384int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1385 bool *repeater_present)
1386{
1387 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1388 int ret;
1389 u8 val;
1390
1391 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1392 if (ret) {
1393 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1394 ret);
1395 return ret;
1396 }
1397 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1398 return 0;
1399}
1400
1401static
1402int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1403 u8 *ri_prime)
1404{
1405 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1406
1407 int ret;
1408 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1409 ri_prime, DRM_HDCP_RI_LEN);
1410 if (ret)
1411 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1412 ret);
1413 return ret;
1414}
1415
1416static
1417int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1418 bool *ksv_ready)
1419{
1420 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1421 int ret;
1422 u8 val;
1423
1424 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1425 if (ret) {
1426 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1427 ret);
1428 return ret;
1429 }
1430 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1431 return 0;
1432}
1433
1434static
1435int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1436 int num_downstream, u8 *ksv_fifo)
1437{
1438 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1439 int ret;
1440 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1441 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1442 if (ret) {
1443 drm_dbg_kms(&i915->drm,
1444 "Read ksv fifo over DDC failed (%d)\n", ret);
1445 return ret;
1446 }
1447 return 0;
1448}
1449
1450static
1451int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1452 int i, u32 *part)
1453{
1454 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1455 int ret;
1456
1457 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1458 return -EINVAL;
1459
1460 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1461 part, DRM_HDCP_V_PRIME_PART_LEN);
1462 if (ret)
1463 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1464 i, ret);
1465 return ret;
1466}
1467
1468static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1469 enum transcoder cpu_transcoder)
1470{
1471 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1473 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1474 u32 scanline;
1475 int ret;
1476
1477 for (;;) {
1478 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1479 if (scanline > 100 && scanline < 200)
1480 break;
1481 usleep_range(25, 50);
1482 }
1483
1484 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1485 false, TRANS_DDI_HDCP_SIGNALLING);
1486 if (ret) {
1487 drm_err(&dev_priv->drm,
1488 "Disable HDCP signalling failed (%d)\n", ret);
1489 return ret;
1490 }
1491
1492 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1493 true, TRANS_DDI_HDCP_SIGNALLING);
1494 if (ret) {
1495 drm_err(&dev_priv->drm,
1496 "Enable HDCP signalling failed (%d)\n", ret);
1497 return ret;
1498 }
1499
1500 return 0;
1501}
1502
1503static
1504int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1505 enum transcoder cpu_transcoder,
1506 bool enable)
1507{
1508 struct intel_hdmi *hdmi = &dig_port->hdmi;
1509 struct intel_connector *connector = hdmi->attached_connector;
1510 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1511 int ret;
1512
1513 if (!enable)
1514 usleep_range(6, 60); /* Bspec says >= 6us */
1515
1516 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1517 cpu_transcoder, enable,
1518 TRANS_DDI_HDCP_SIGNALLING);
1519 if (ret) {
1520 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1521 enable ? "Enable" : "Disable", ret);
1522 return ret;
1523 }
1524
1525 /*
1526 * WA: To fix incorrect positioning of the window of
1527 * opportunity and enc_en signalling in KABYLAKE.
1528 */
1529 if (IS_KABYLAKE(dev_priv) && enable)
1530 return kbl_repositioning_enc_en_signal(connector,
1531 cpu_transcoder);
1532
1533 return 0;
1534}
1535
1536static
1537bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1538 struct intel_connector *connector)
1539{
1540 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1541 enum port port = dig_port->base.port;
1542 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1543 int ret;
1544 union {
1545 u32 reg;
1546 u8 shim[DRM_HDCP_RI_LEN];
1547 } ri;
1548
1549 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1550 if (ret)
1551 return false;
1552
1553 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1554
1555 /* Wait for Ri prime match */
1556 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1557 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1558 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1559 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1560 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1561 port)));
1562 return false;
1563 }
1564 return true;
1565}
1566
1567static
1568bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1569 struct intel_connector *connector)
1570{
1571 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1572 int retry;
1573
1574 for (retry = 0; retry < 3; retry++)
1575 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1576 return true;
1577
1578 drm_err(&i915->drm, "Link check failed\n");
1579 return false;
1580}
1581
1582struct hdcp2_hdmi_msg_timeout {
1583 u8 msg_id;
1584 u16 timeout;
1585};
1586
1587static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1588 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1589 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1590 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1591 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1592 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1593};
1594
1595static
1596int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1597 u8 *rx_status)
1598{
1599 return intel_hdmi_hdcp_read(dig_port,
1600 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1601 rx_status,
1602 HDCP_2_2_HDMI_RXSTATUS_LEN);
1603}
1604
1605static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1606{
1607 int i;
1608
1609 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1610 if (is_paired)
1611 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1612 else
1613 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1614 }
1615
1616 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1617 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1618 return hdcp2_msg_timeout[i].timeout;
1619 }
1620
1621 return -EINVAL;
1622}
1623
1624static int
1625hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1626 u8 msg_id, bool *msg_ready,
1627 ssize_t *msg_sz)
1628{
1629 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1630 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1631 int ret;
1632
1633 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1634 if (ret < 0) {
1635 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1636 ret);
1637 return ret;
1638 }
1639
1640 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1641 rx_status[0]);
1642
1643 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1644 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1645 *msg_sz);
1646 else
1647 *msg_ready = *msg_sz;
1648
1649 return 0;
1650}
1651
1652static ssize_t
1653intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1654 u8 msg_id, bool paired)
1655{
1656 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1657 bool msg_ready = false;
1658 int timeout, ret;
1659 ssize_t msg_sz = 0;
1660
1661 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1662 if (timeout < 0)
1663 return timeout;
1664
1665 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1666 msg_id, &msg_ready,
1667 &msg_sz),
1668 !ret && msg_ready && msg_sz, timeout * 1000,
1669 1000, 5 * 1000);
1670 if (ret)
1671 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1672 msg_id, ret, timeout);
1673
1674 return ret ? ret : msg_sz;
1675}
1676
1677static
1678int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1679 void *buf, size_t size)
1680{
1681 unsigned int offset;
1682
1683 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1684 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1685}
1686
1687static
1688int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1689 u8 msg_id, void *buf, size_t size)
1690{
1691 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1692 struct intel_hdmi *hdmi = &dig_port->hdmi;
1693 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1694 unsigned int offset;
1695 ssize_t ret;
1696
1697 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1698 hdcp->is_paired);
1699 if (ret < 0)
1700 return ret;
1701
1702 /*
1703 * Available msg size should be equal to or lesser than the
1704 * available buffer.
1705 */
1706 if (ret > size) {
1707 drm_dbg_kms(&i915->drm,
1708 "msg_sz(%zd) is more than exp size(%zu)\n",
1709 ret, size);
1710 return -EINVAL;
1711 }
1712
1713 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1714 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1715 if (ret)
1716 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1717 msg_id, ret);
1718
1719 return ret;
1720}
1721
1722static
1723int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1724 struct intel_connector *connector)
1725{
1726 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1727 int ret;
1728
1729 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1730 if (ret)
1731 return ret;
1732
1733 /*
1734 * Re-auth request and Link Integrity Failures are represented by
1735 * same bit. i.e reauth_req.
1736 */
1737 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1738 ret = HDCP_REAUTH_REQUEST;
1739 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1740 ret = HDCP_TOPOLOGY_CHANGE;
1741
1742 return ret;
1743}
1744
1745static
1746int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1747 bool *capable)
1748{
1749 u8 hdcp2_version;
1750 int ret;
1751
1752 *capable = false;
1753 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1754 &hdcp2_version, sizeof(hdcp2_version));
1755 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1756 *capable = true;
1757
1758 return ret;
1759}
1760
1761static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1762 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1763 .read_bksv = intel_hdmi_hdcp_read_bksv,
1764 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1765 .repeater_present = intel_hdmi_hdcp_repeater_present,
1766 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1767 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1768 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1769 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1770 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1771 .check_link = intel_hdmi_hdcp_check_link,
1772 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1773 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1774 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1775 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1776 .protocol = HDCP_PROTOCOL_HDMI,
1777};
1778
1779static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1780{
1781 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1782 int max_tmds_clock, vbt_max_tmds_clock;
1783
1784 if (DISPLAY_VER(dev_priv) >= 10)
1785 max_tmds_clock = 594000;
1786 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1787 max_tmds_clock = 300000;
1788 else if (DISPLAY_VER(dev_priv) >= 5)
1789 max_tmds_clock = 225000;
1790 else
1791 max_tmds_clock = 165000;
1792
1793 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1794 if (vbt_max_tmds_clock)
1795 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1796
1797 return max_tmds_clock;
1798}
1799
1800static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1801 const struct drm_connector_state *conn_state)
1802{
1803 return hdmi->has_hdmi_sink &&
1804 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1805}
1806
1807static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1808{
1809 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1810}
1811
1812static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1813 bool respect_downstream_limits,
1814 bool has_hdmi_sink)
1815{
1816 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1817 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1818
1819 if (respect_downstream_limits) {
1820 struct intel_connector *connector = hdmi->attached_connector;
1821 const struct drm_display_info *info = &connector->base.display_info;
1822
1823 if (hdmi->dp_dual_mode.max_tmds_clock)
1824 max_tmds_clock = min(max_tmds_clock,
1825 hdmi->dp_dual_mode.max_tmds_clock);
1826
1827 if (info->max_tmds_clock)
1828 max_tmds_clock = min(max_tmds_clock,
1829 info->max_tmds_clock);
1830 else if (!has_hdmi_sink)
1831 max_tmds_clock = min(max_tmds_clock, 165000);
1832 }
1833
1834 return max_tmds_clock;
1835}
1836
1837static enum drm_mode_status
1838hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1839 int clock, bool respect_downstream_limits,
1840 bool has_hdmi_sink)
1841{
1842 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1843 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1844
1845 if (clock < 25000)
1846 return MODE_CLOCK_LOW;
1847 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1848 has_hdmi_sink))
1849 return MODE_CLOCK_HIGH;
1850
1851 /* GLK DPLL can't generate 446-480 MHz */
1852 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1853 return MODE_CLOCK_RANGE;
1854
1855 /* BXT/GLK DPLL can't generate 223-240 MHz */
1856 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1857 clock > 223333 && clock < 240000)
1858 return MODE_CLOCK_RANGE;
1859
1860 /* CHV DPLL can't generate 216-240 MHz */
1861 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1862 return MODE_CLOCK_RANGE;
1863
1864 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1865 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1866 return MODE_CLOCK_RANGE;
1867
1868 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1869 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1870 return MODE_CLOCK_RANGE;
1871
1872 /*
1873 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1874 * set of link rates.
1875 *
1876 * FIXME: We will hopefully get an algorithmic way of programming
1877 * the MPLLB for HDMI in the future.
1878 */
1879 if (IS_DG2(dev_priv))
1880 return intel_snps_phy_check_hdmi_link_rate(clock);
1881
1882 return MODE_OK;
1883}
1884
1885int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1886{
1887 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1888 if (ycbcr420_output)
1889 clock /= 2;
1890
1891 /*
1892 * Need to adjust the port link by:
1893 * 1.5x for 12bpc
1894 * 1.25x for 10bpc
1895 */
1896 return DIV_ROUND_CLOSEST(clock * bpc, 8);
1897}
1898
1899static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1900{
1901 switch (bpc) {
1902 case 12:
1903 return !HAS_GMCH(i915);
1904 case 10:
1905 return DISPLAY_VER(i915) >= 11;
1906 case 8:
1907 return true;
1908 default:
1909 MISSING_CASE(bpc);
1910 return false;
1911 }
1912}
1913
1914static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1915 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1916{
1917 const struct drm_display_info *info = &connector->display_info;
1918 const struct drm_hdmi_info *hdmi = &info->hdmi;
1919
1920 switch (bpc) {
1921 case 12:
1922 if (!has_hdmi_sink)
1923 return false;
1924
1925 if (ycbcr420_output)
1926 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1927 else
1928 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1929 case 10:
1930 if (!has_hdmi_sink)
1931 return false;
1932
1933 if (ycbcr420_output)
1934 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1935 else
1936 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1937 case 8:
1938 return true;
1939 default:
1940 MISSING_CASE(bpc);
1941 return false;
1942 }
1943}
1944
1945static enum drm_mode_status
1946intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1947 bool has_hdmi_sink, bool ycbcr420_output)
1948{
1949 struct drm_i915_private *i915 = to_i915(connector->dev);
1950 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1951 enum drm_mode_status status = MODE_OK;
1952 int bpc;
1953
1954 /*
1955 * Try all color depths since valid port clock range
1956 * can have holes. Any mode that can be used with at
1957 * least one color depth is accepted.
1958 */
1959 for (bpc = 12; bpc >= 8; bpc -= 2) {
1960 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1961
1962 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1963 continue;
1964
1965 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1966 continue;
1967
1968 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1969 if (status == MODE_OK)
1970 return MODE_OK;
1971 }
1972
1973 /* can never happen */
1974 drm_WARN_ON(&i915->drm, status == MODE_OK);
1975
1976 return status;
1977}
1978
1979static enum drm_mode_status
1980intel_hdmi_mode_valid(struct drm_connector *connector,
1981 struct drm_display_mode *mode)
1982{
1983 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1984 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1985 enum drm_mode_status status;
1986 int clock = mode->clock;
1987 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1988 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1989 bool ycbcr_420_only;
1990
1991 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1992 return MODE_NO_DBLESCAN;
1993
1994 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1995 clock *= 2;
1996
1997 if (clock > max_dotclk)
1998 return MODE_CLOCK_HIGH;
1999
2000 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2001 if (!has_hdmi_sink)
2002 return MODE_CLOCK_LOW;
2003 clock *= 2;
2004 }
2005
2006 /*
2007 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2008 * enumerated only if FRL is supported. Current platforms do not support
2009 * FRL so prune the higher resolution modes that require doctclock more
2010 * than 600MHz.
2011 */
2012 if (clock > 600000)
2013 return MODE_CLOCK_HIGH;
2014
2015 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2016
2017 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2018 if (status != MODE_OK) {
2019 if (ycbcr_420_only ||
2020 !connector->ycbcr_420_allowed ||
2021 !drm_mode_is_420_also(&connector->display_info, mode))
2022 return status;
2023
2024 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2025 if (status != MODE_OK)
2026 return status;
2027 }
2028
2029 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2030}
2031
2032bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2033 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2034{
2035 struct drm_atomic_state *state = crtc_state->uapi.state;
2036 struct drm_connector_state *connector_state;
2037 struct drm_connector *connector;
2038 int i;
2039
2040 for_each_new_connector_in_state(state, connector, connector_state, i) {
2041 if (connector_state->crtc != crtc_state->uapi.crtc)
2042 continue;
2043
2044 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2045 return false;
2046 }
2047
2048 return true;
2049}
2050
2051static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2052{
2053 struct drm_i915_private *dev_priv =
2054 to_i915(crtc_state->uapi.crtc->dev);
2055 const struct drm_display_mode *adjusted_mode =
2056 &crtc_state->hw.adjusted_mode;
2057
2058 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2059 return false;
2060
2061 /* Display Wa_1405510057:icl,ehl */
2062 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2063 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2064 (adjusted_mode->crtc_hblank_end -
2065 adjusted_mode->crtc_hblank_start) % 8 == 2)
2066 return false;
2067
2068 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2069 intel_hdmi_is_ycbcr420(crtc_state));
2070}
2071
2072static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2073 struct intel_crtc_state *crtc_state,
2074 int clock, bool respect_downstream_limits)
2075{
2076 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2077 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2078 int bpc;
2079
2080 /*
2081 * pipe_bpp could already be below 8bpc due to FDI
2082 * bandwidth constraints. HDMI minimum is 8bpc however.
2083 */
2084 bpc = max(crtc_state->pipe_bpp / 3, 8);
2085
2086 /*
2087 * We will never exceed downstream TMDS clock limits while
2088 * attempting deep color. If the user insists on forcing an
2089 * out of spec mode they will have to be satisfied with 8bpc.
2090 */
2091 if (!respect_downstream_limits)
2092 bpc = 8;
2093
2094 for (; bpc >= 8; bpc -= 2) {
2095 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2096
2097 if (hdmi_bpc_possible(crtc_state, bpc) &&
2098 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2099 respect_downstream_limits,
2100 crtc_state->has_hdmi_sink) == MODE_OK)
2101 return bpc;
2102 }
2103
2104 return -EINVAL;
2105}
2106
2107static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2108 struct intel_crtc_state *crtc_state,
2109 bool respect_downstream_limits)
2110{
2111 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2112 const struct drm_display_mode *adjusted_mode =
2113 &crtc_state->hw.adjusted_mode;
2114 int bpc, clock = adjusted_mode->crtc_clock;
2115
2116 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2117 clock *= 2;
2118
2119 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2120 respect_downstream_limits);
2121 if (bpc < 0)
2122 return bpc;
2123
2124 crtc_state->port_clock =
2125 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2126
2127 /*
2128 * pipe_bpp could already be below 8bpc due to
2129 * FDI bandwidth constraints. We shouldn't bump it
2130 * back up to the HDMI minimum 8bpc in that case.
2131 */
2132 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2133
2134 drm_dbg_kms(&i915->drm,
2135 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2136 bpc, crtc_state->pipe_bpp);
2137
2138 return 0;
2139}
2140
2141bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2142 const struct drm_connector_state *conn_state)
2143{
2144 const struct intel_digital_connector_state *intel_conn_state =
2145 to_intel_digital_connector_state(conn_state);
2146 const struct drm_display_mode *adjusted_mode =
2147 &crtc_state->hw.adjusted_mode;
2148
2149 /*
2150 * Our YCbCr output is always limited range.
2151 * crtc_state->limited_color_range only applies to RGB,
2152 * and it must never be set for YCbCr or we risk setting
2153 * some conflicting bits in PIPECONF which will mess up
2154 * the colors on the monitor.
2155 */
2156 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2157 return false;
2158
2159 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2160 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2161 return crtc_state->has_hdmi_sink &&
2162 drm_default_rgb_quant_range(adjusted_mode) ==
2163 HDMI_QUANTIZATION_RANGE_LIMITED;
2164 } else {
2165 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2166 }
2167}
2168
2169static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2170 const struct intel_crtc_state *crtc_state,
2171 const struct drm_connector_state *conn_state)
2172{
2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2174 const struct intel_digital_connector_state *intel_conn_state =
2175 to_intel_digital_connector_state(conn_state);
2176
2177 if (!crtc_state->has_hdmi_sink)
2178 return false;
2179
2180 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2181 return intel_hdmi->has_audio;
2182 else
2183 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2184}
2185
2186static enum intel_output_format
2187intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
2188 struct intel_connector *connector,
2189 bool ycbcr_420_output)
2190{
2191 if (!crtc_state->has_hdmi_sink)
2192 return INTEL_OUTPUT_FORMAT_RGB;
2193
2194 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2195 return INTEL_OUTPUT_FORMAT_YCBCR420;
2196 else
2197 return INTEL_OUTPUT_FORMAT_RGB;
2198}
2199
2200static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2201 struct intel_crtc_state *crtc_state,
2202 const struct drm_connector_state *conn_state,
2203 bool respect_downstream_limits)
2204{
2205 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2206 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2207 const struct drm_display_info *info = &connector->base.display_info;
2208 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2209 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2210 int ret;
2211
2212 crtc_state->output_format =
2213 intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
2214
2215 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2216 drm_dbg_kms(&i915->drm,
2217 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2218 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2219 }
2220
2221 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2222 if (ret) {
2223 if (intel_hdmi_is_ycbcr420(crtc_state) ||
2224 !connector->base.ycbcr_420_allowed ||
2225 !drm_mode_is_420_also(info, adjusted_mode))
2226 return ret;
2227
2228 crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
2229 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2230 }
2231
2232 return ret;
2233}
2234
2235static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2236{
2237 return crtc_state->uapi.encoder_mask &&
2238 !is_power_of_2(crtc_state->uapi.encoder_mask);
2239}
2240
2241int intel_hdmi_compute_config(struct intel_encoder *encoder,
2242 struct intel_crtc_state *pipe_config,
2243 struct drm_connector_state *conn_state)
2244{
2245 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2246 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2247 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2248 struct drm_connector *connector = conn_state->connector;
2249 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2250 int ret;
2251
2252 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2253 return -EINVAL;
2254
2255 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2256 pipe_config->has_hdmi_sink =
2257 intel_has_hdmi_sink(intel_hdmi, conn_state) &&
2258 !intel_hdmi_is_cloned(pipe_config);
2259
2260 if (pipe_config->has_hdmi_sink)
2261 pipe_config->has_infoframe = true;
2262
2263 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2264 pipe_config->pixel_multiplier = 2;
2265
2266 pipe_config->has_audio =
2267 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2268
2269 /*
2270 * Try to respect downstream TMDS clock limits first, if
2271 * that fails assume the user might know something we don't.
2272 */
2273 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2274 if (ret)
2275 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2276 if (ret) {
2277 drm_dbg_kms(&dev_priv->drm,
2278 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2279 pipe_config->hw.adjusted_mode.crtc_clock);
2280 return ret;
2281 }
2282
2283 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2284 ret = intel_panel_fitting(pipe_config, conn_state);
2285 if (ret)
2286 return ret;
2287 }
2288
2289 pipe_config->limited_color_range =
2290 intel_hdmi_limited_color_range(pipe_config, conn_state);
2291
2292 if (conn_state->picture_aspect_ratio)
2293 adjusted_mode->picture_aspect_ratio =
2294 conn_state->picture_aspect_ratio;
2295
2296 pipe_config->lane_count = 4;
2297
2298 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2299 if (scdc->scrambling.low_rates)
2300 pipe_config->hdmi_scrambling = true;
2301
2302 if (pipe_config->port_clock > 340000) {
2303 pipe_config->hdmi_scrambling = true;
2304 pipe_config->hdmi_high_tmds_clock_ratio = true;
2305 }
2306 }
2307
2308 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2309 conn_state);
2310
2311 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2312 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2313 return -EINVAL;
2314 }
2315
2316 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2317 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2318 return -EINVAL;
2319 }
2320
2321 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2322 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2323 return -EINVAL;
2324 }
2325
2326 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2327 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2328 return -EINVAL;
2329 }
2330
2331 return 0;
2332}
2333
2334void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2335{
2336 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2337
2338 /*
2339 * Give a hand to buggy BIOSen which forget to turn
2340 * the TMDS output buffers back on after a reboot.
2341 */
2342 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2343}
2344
2345static void
2346intel_hdmi_unset_edid(struct drm_connector *connector)
2347{
2348 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2349
2350 intel_hdmi->has_hdmi_sink = false;
2351 intel_hdmi->has_audio = false;
2352
2353 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2354 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2355
2356 kfree(to_intel_connector(connector)->detect_edid);
2357 to_intel_connector(connector)->detect_edid = NULL;
2358}
2359
2360static void
2361intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2362{
2363 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2364 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2365 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2366 struct i2c_adapter *adapter =
2367 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2368 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2369
2370 /*
2371 * Type 1 DVI adaptors are not required to implement any
2372 * registers, so we can't always detect their presence.
2373 * Ideally we should be able to check the state of the
2374 * CONFIG1 pin, but no such luck on our hardware.
2375 *
2376 * The only method left to us is to check the VBT to see
2377 * if the port is a dual mode capable DP port.
2378 */
2379 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2380 if (!connector->force &&
2381 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2382 drm_dbg_kms(&dev_priv->drm,
2383 "Assuming DP dual mode adaptor presence based on VBT\n");
2384 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2385 } else {
2386 type = DRM_DP_DUAL_MODE_NONE;
2387 }
2388 }
2389
2390 if (type == DRM_DP_DUAL_MODE_NONE)
2391 return;
2392
2393 hdmi->dp_dual_mode.type = type;
2394 hdmi->dp_dual_mode.max_tmds_clock =
2395 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2396
2397 drm_dbg_kms(&dev_priv->drm,
2398 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2399 drm_dp_get_dual_mode_type_name(type),
2400 hdmi->dp_dual_mode.max_tmds_clock);
2401
2402 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2403 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2404 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2405 drm_dbg_kms(&dev_priv->drm,
2406 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2407 hdmi->dp_dual_mode.max_tmds_clock = 0;
2408 }
2409}
2410
2411static bool
2412intel_hdmi_set_edid(struct drm_connector *connector)
2413{
2414 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2415 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2416 intel_wakeref_t wakeref;
2417 struct edid *edid;
2418 bool connected = false;
2419 struct i2c_adapter *i2c;
2420
2421 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2422
2423 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2424
2425 edid = drm_get_edid(connector, i2c);
2426
2427 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2428 drm_dbg_kms(&dev_priv->drm,
2429 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2430 intel_gmbus_force_bit(i2c, true);
2431 edid = drm_get_edid(connector, i2c);
2432 intel_gmbus_force_bit(i2c, false);
2433 }
2434
2435 to_intel_connector(connector)->detect_edid = edid;
2436 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2437 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2438 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2439
2440 intel_hdmi_dp_dual_mode_detect(connector);
2441
2442 connected = true;
2443 }
2444
2445 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2446
2447 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2448
2449 return connected;
2450}
2451
2452static enum drm_connector_status
2453intel_hdmi_detect(struct drm_connector *connector, bool force)
2454{
2455 enum drm_connector_status status = connector_status_disconnected;
2456 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2457 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2458 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2459 intel_wakeref_t wakeref;
2460
2461 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2462 connector->base.id, connector->name);
2463
2464 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2465 return connector_status_disconnected;
2466
2467 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2468
2469 if (DISPLAY_VER(dev_priv) >= 11 &&
2470 !intel_digital_port_connected(encoder))
2471 goto out;
2472
2473 intel_hdmi_unset_edid(connector);
2474
2475 if (intel_hdmi_set_edid(connector))
2476 status = connector_status_connected;
2477
2478out:
2479 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2480
2481 if (status != connector_status_connected)
2482 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2483
2484 /*
2485 * Make sure the refs for power wells enabled during detect are
2486 * dropped to avoid a new detect cycle triggered by HPD polling.
2487 */
2488 intel_display_power_flush_work(dev_priv);
2489
2490 return status;
2491}
2492
2493static void
2494intel_hdmi_force(struct drm_connector *connector)
2495{
2496 struct drm_i915_private *i915 = to_i915(connector->dev);
2497
2498 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2499 connector->base.id, connector->name);
2500
2501 intel_hdmi_unset_edid(connector);
2502
2503 if (connector->status != connector_status_connected)
2504 return;
2505
2506 intel_hdmi_set_edid(connector);
2507}
2508
2509static int intel_hdmi_get_modes(struct drm_connector *connector)
2510{
2511 struct edid *edid;
2512
2513 edid = to_intel_connector(connector)->detect_edid;
2514 if (edid == NULL)
2515 return 0;
2516
2517 return intel_connector_update_modes(connector, edid);
2518}
2519
2520static struct i2c_adapter *
2521intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2522{
2523 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2524 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2525
2526 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2527}
2528
2529static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2530{
2531 struct drm_i915_private *i915 = to_i915(connector->dev);
2532 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2533 struct kobject *i2c_kobj = &adapter->dev.kobj;
2534 struct kobject *connector_kobj = &connector->kdev->kobj;
2535 int ret;
2536
2537 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2538 if (ret)
2539 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2540}
2541
2542static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2543{
2544 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2545 struct kobject *i2c_kobj = &adapter->dev.kobj;
2546 struct kobject *connector_kobj = &connector->kdev->kobj;
2547
2548 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2549}
2550
2551static int
2552intel_hdmi_connector_register(struct drm_connector *connector)
2553{
2554 int ret;
2555
2556 ret = intel_connector_register(connector);
2557 if (ret)
2558 return ret;
2559
2560 intel_hdmi_create_i2c_symlink(connector);
2561
2562 return ret;
2563}
2564
2565static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2566{
2567 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2568
2569 cec_notifier_conn_unregister(n);
2570
2571 intel_hdmi_remove_i2c_symlink(connector);
2572 intel_connector_unregister(connector);
2573}
2574
2575static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2576 .detect = intel_hdmi_detect,
2577 .force = intel_hdmi_force,
2578 .fill_modes = drm_helper_probe_single_connector_modes,
2579 .atomic_get_property = intel_digital_connector_atomic_get_property,
2580 .atomic_set_property = intel_digital_connector_atomic_set_property,
2581 .late_register = intel_hdmi_connector_register,
2582 .early_unregister = intel_hdmi_connector_unregister,
2583 .destroy = intel_connector_destroy,
2584 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2585 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2586};
2587
2588static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2589 .get_modes = intel_hdmi_get_modes,
2590 .mode_valid = intel_hdmi_mode_valid,
2591 .atomic_check = intel_digital_connector_atomic_check,
2592};
2593
2594static void
2595intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2596{
2597 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2598
2599 intel_attach_force_audio_property(connector);
2600 intel_attach_broadcast_rgb_property(connector);
2601 intel_attach_aspect_ratio_property(connector);
2602
2603 intel_attach_hdmi_colorspace_property(connector);
2604 drm_connector_attach_content_type_property(connector);
2605
2606 if (DISPLAY_VER(dev_priv) >= 10)
2607 drm_connector_attach_hdr_output_metadata_property(connector);
2608
2609 if (!HAS_GMCH(dev_priv))
2610 drm_connector_attach_max_bpc_property(connector, 8, 12);
2611}
2612
2613/*
2614 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2615 * @encoder: intel_encoder
2616 * @connector: drm_connector
2617 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2618 * or reset the high tmds clock ratio for scrambling
2619 * @scrambling: bool to Indicate if the function needs to set or reset
2620 * sink scrambling
2621 *
2622 * This function handles scrambling on HDMI 2.0 capable sinks.
2623 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2624 * it enables scrambling. This should be called before enabling the HDMI
2625 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2626 * detect a scrambled clock within 100 ms.
2627 *
2628 * Returns:
2629 * True on success, false on failure.
2630 */
2631bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2632 struct drm_connector *connector,
2633 bool high_tmds_clock_ratio,
2634 bool scrambling)
2635{
2636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2637 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2638 struct drm_scrambling *sink_scrambling =
2639 &connector->display_info.hdmi.scdc.scrambling;
2640 struct i2c_adapter *adapter =
2641 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2642
2643 if (!sink_scrambling->supported)
2644 return true;
2645
2646 drm_dbg_kms(&dev_priv->drm,
2647 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2648 connector->base.id, connector->name,
2649 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2650
2651 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2652 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2653 high_tmds_clock_ratio) &&
2654 drm_scdc_set_scrambling(adapter, scrambling);
2655}
2656
2657static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2658{
2659 u8 ddc_pin;
2660
2661 switch (port) {
2662 case PORT_B:
2663 ddc_pin = GMBUS_PIN_DPB;
2664 break;
2665 case PORT_C:
2666 ddc_pin = GMBUS_PIN_DPC;
2667 break;
2668 case PORT_D:
2669 ddc_pin = GMBUS_PIN_DPD_CHV;
2670 break;
2671 default:
2672 MISSING_CASE(port);
2673 ddc_pin = GMBUS_PIN_DPB;
2674 break;
2675 }
2676 return ddc_pin;
2677}
2678
2679static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2680{
2681 u8 ddc_pin;
2682
2683 switch (port) {
2684 case PORT_B:
2685 ddc_pin = GMBUS_PIN_1_BXT;
2686 break;
2687 case PORT_C:
2688 ddc_pin = GMBUS_PIN_2_BXT;
2689 break;
2690 default:
2691 MISSING_CASE(port);
2692 ddc_pin = GMBUS_PIN_1_BXT;
2693 break;
2694 }
2695 return ddc_pin;
2696}
2697
2698static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2699 enum port port)
2700{
2701 u8 ddc_pin;
2702
2703 switch (port) {
2704 case PORT_B:
2705 ddc_pin = GMBUS_PIN_1_BXT;
2706 break;
2707 case PORT_C:
2708 ddc_pin = GMBUS_PIN_2_BXT;
2709 break;
2710 case PORT_D:
2711 ddc_pin = GMBUS_PIN_4_CNP;
2712 break;
2713 case PORT_F:
2714 ddc_pin = GMBUS_PIN_3_BXT;
2715 break;
2716 default:
2717 MISSING_CASE(port);
2718 ddc_pin = GMBUS_PIN_1_BXT;
2719 break;
2720 }
2721 return ddc_pin;
2722}
2723
2724static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2725{
2726 enum phy phy = intel_port_to_phy(dev_priv, port);
2727
2728 if (intel_phy_is_combo(dev_priv, phy))
2729 return GMBUS_PIN_1_BXT + port;
2730 else if (intel_phy_is_tc(dev_priv, phy))
2731 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2732
2733 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2734 return GMBUS_PIN_2_BXT;
2735}
2736
2737static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2738{
2739 enum phy phy = intel_port_to_phy(dev_priv, port);
2740 u8 ddc_pin;
2741
2742 switch (phy) {
2743 case PHY_A:
2744 ddc_pin = GMBUS_PIN_1_BXT;
2745 break;
2746 case PHY_B:
2747 ddc_pin = GMBUS_PIN_2_BXT;
2748 break;
2749 case PHY_C:
2750 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2751 break;
2752 default:
2753 MISSING_CASE(phy);
2754 ddc_pin = GMBUS_PIN_1_BXT;
2755 break;
2756 }
2757 return ddc_pin;
2758}
2759
2760static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2761{
2762 enum phy phy = intel_port_to_phy(dev_priv, port);
2763
2764 WARN_ON(port == PORT_C);
2765
2766 /*
2767 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2768 * final two outputs use type-c pins, even though they're actually
2769 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2770 * all outputs.
2771 */
2772 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2773 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2774
2775 return GMBUS_PIN_1_BXT + phy;
2776}
2777
2778static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2779{
2780 enum phy phy = intel_port_to_phy(i915, port);
2781
2782 drm_WARN_ON(&i915->drm, port == PORT_A);
2783
2784 /*
2785 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2786 * final two outputs use type-c pins, even though they're actually
2787 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2788 * all outputs.
2789 */
2790 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2791 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2792
2793 return GMBUS_PIN_1_BXT + phy;
2794}
2795
2796static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2797{
2798 return intel_port_to_phy(dev_priv, port) + 1;
2799}
2800
2801static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2802{
2803 enum phy phy = intel_port_to_phy(dev_priv, port);
2804
2805 WARN_ON(port == PORT_B || port == PORT_C);
2806
2807 /*
2808 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2809 * except first combo output.
2810 */
2811 if (phy == PHY_A)
2812 return GMBUS_PIN_1_BXT;
2813
2814 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2815}
2816
2817static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2818 enum port port)
2819{
2820 u8 ddc_pin;
2821
2822 switch (port) {
2823 case PORT_B:
2824 ddc_pin = GMBUS_PIN_DPB;
2825 break;
2826 case PORT_C:
2827 ddc_pin = GMBUS_PIN_DPC;
2828 break;
2829 case PORT_D:
2830 ddc_pin = GMBUS_PIN_DPD;
2831 break;
2832 default:
2833 MISSING_CASE(port);
2834 ddc_pin = GMBUS_PIN_DPB;
2835 break;
2836 }
2837 return ddc_pin;
2838}
2839
2840static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2841{
2842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2843 enum port port = encoder->port;
2844 u8 ddc_pin;
2845
2846 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2847 if (ddc_pin) {
2848 drm_dbg_kms(&dev_priv->drm,
2849 "Using DDC pin 0x%x for port %c (VBT)\n",
2850 ddc_pin, port_name(port));
2851 return ddc_pin;
2852 }
2853
2854 if (IS_ALDERLAKE_S(dev_priv))
2855 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2856 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2857 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2858 else if (IS_ROCKETLAKE(dev_priv))
2859 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2860 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2861 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2862 else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2863 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2864 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2865 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2866 else if (HAS_PCH_CNP(dev_priv))
2867 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2868 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2869 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2870 else if (IS_CHERRYVIEW(dev_priv))
2871 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2872 else
2873 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2874
2875 drm_dbg_kms(&dev_priv->drm,
2876 "Using DDC pin 0x%x for port %c (platform default)\n",
2877 ddc_pin, port_name(port));
2878
2879 return ddc_pin;
2880}
2881
2882void intel_infoframe_init(struct intel_digital_port *dig_port)
2883{
2884 struct drm_i915_private *dev_priv =
2885 to_i915(dig_port->base.base.dev);
2886
2887 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2888 dig_port->write_infoframe = vlv_write_infoframe;
2889 dig_port->read_infoframe = vlv_read_infoframe;
2890 dig_port->set_infoframes = vlv_set_infoframes;
2891 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2892 } else if (IS_G4X(dev_priv)) {
2893 dig_port->write_infoframe = g4x_write_infoframe;
2894 dig_port->read_infoframe = g4x_read_infoframe;
2895 dig_port->set_infoframes = g4x_set_infoframes;
2896 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2897 } else if (HAS_DDI(dev_priv)) {
2898 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2899 dig_port->write_infoframe = lspcon_write_infoframe;
2900 dig_port->read_infoframe = lspcon_read_infoframe;
2901 dig_port->set_infoframes = lspcon_set_infoframes;
2902 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2903 } else {
2904 dig_port->write_infoframe = hsw_write_infoframe;
2905 dig_port->read_infoframe = hsw_read_infoframe;
2906 dig_port->set_infoframes = hsw_set_infoframes;
2907 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2908 }
2909 } else if (HAS_PCH_IBX(dev_priv)) {
2910 dig_port->write_infoframe = ibx_write_infoframe;
2911 dig_port->read_infoframe = ibx_read_infoframe;
2912 dig_port->set_infoframes = ibx_set_infoframes;
2913 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2914 } else {
2915 dig_port->write_infoframe = cpt_write_infoframe;
2916 dig_port->read_infoframe = cpt_read_infoframe;
2917 dig_port->set_infoframes = cpt_set_infoframes;
2918 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2919 }
2920}
2921
2922void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2923 struct intel_connector *intel_connector)
2924{
2925 struct drm_connector *connector = &intel_connector->base;
2926 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2927 struct intel_encoder *intel_encoder = &dig_port->base;
2928 struct drm_device *dev = intel_encoder->base.dev;
2929 struct drm_i915_private *dev_priv = to_i915(dev);
2930 struct i2c_adapter *ddc;
2931 enum port port = intel_encoder->port;
2932 struct cec_connector_info conn_info;
2933
2934 drm_dbg_kms(&dev_priv->drm,
2935 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2936 intel_encoder->base.base.id, intel_encoder->base.name);
2937
2938 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2939 return;
2940
2941 if (drm_WARN(dev, dig_port->max_lanes < 4,
2942 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2943 dig_port->max_lanes, intel_encoder->base.base.id,
2944 intel_encoder->base.name))
2945 return;
2946
2947 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2948 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2949
2950 drm_connector_init_with_ddc(dev, connector,
2951 &intel_hdmi_connector_funcs,
2952 DRM_MODE_CONNECTOR_HDMIA,
2953 ddc);
2954 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2955
2956 connector->interlace_allowed = true;
2957 connector->stereo_allowed = true;
2958
2959 if (DISPLAY_VER(dev_priv) >= 10)
2960 connector->ycbcr_420_allowed = true;
2961
2962 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2963
2964 if (HAS_DDI(dev_priv))
2965 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2966 else
2967 intel_connector->get_hw_state = intel_connector_get_hw_state;
2968
2969 intel_hdmi_add_properties(intel_hdmi, connector);
2970
2971 intel_connector_attach_encoder(intel_connector, intel_encoder);
2972 intel_hdmi->attached_connector = intel_connector;
2973
2974 if (is_hdcp_supported(dev_priv, port)) {
2975 int ret = intel_hdcp_init(intel_connector, dig_port,
2976 &intel_hdmi_hdcp_shim);
2977 if (ret)
2978 drm_dbg_kms(&dev_priv->drm,
2979 "HDCP init failed, skipping.\n");
2980 }
2981
2982 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2983 * 0xd. Failure to do so will result in spurious interrupts being
2984 * generated on the port when a cable is not attached.
2985 */
2986 if (IS_G45(dev_priv)) {
2987 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2988 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2989 (temp & ~0xf) | 0xd);
2990 }
2991
2992 cec_fill_conn_info_from_drm(&conn_info, connector);
2993
2994 intel_hdmi->cec_notifier =
2995 cec_notifier_conn_register(dev->dev, port_identifier(port),
2996 &conn_info);
2997 if (!intel_hdmi->cec_notifier)
2998 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2999}
3000
3001/*
3002 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3003 * @vactive: Vactive of a display mode
3004 *
3005 * @return: appropriate dsc slice height for a given mode.
3006 */
3007int intel_hdmi_dsc_get_slice_height(int vactive)
3008{
3009 int slice_height;
3010
3011 /*
3012 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3013 * Select smallest slice height >=96, that results in a valid PPS and
3014 * requires minimum padding lines required for final slice.
3015 *
3016 * Assumption : Vactive is even.
3017 */
3018 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3019 if (vactive % slice_height == 0)
3020 return slice_height;
3021
3022 return 0;
3023}
3024
3025/*
3026 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3027 * and dsc decoder capabilities
3028 *
3029 * @crtc_state: intel crtc_state
3030 * @src_max_slices: maximum slices supported by the DSC encoder
3031 * @src_max_slice_width: maximum slice width supported by DSC encoder
3032 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3033 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3034 *
3035 * @return: num of dsc slices that can be supported by the dsc encoder
3036 * and decoder.
3037 */
3038int
3039intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3040 int src_max_slices, int src_max_slice_width,
3041 int hdmi_max_slices, int hdmi_throughput)
3042{
3043/* Pixel rates in KPixels/sec */
3044#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3045/*
3046 * Rates at which the source and sink are required to process pixels in each
3047 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3048 */
3049#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3050#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3051
3052/* Spec limits the slice width to 2720 pixels */
3053#define MAX_HDMI_SLICE_WIDTH 2720
3054 int kslice_adjust;
3055 int adjusted_clk_khz;
3056 int min_slices;
3057 int target_slices;
3058 int max_throughput; /* max clock freq. in khz per slice */
3059 int max_slice_width;
3060 int slice_width;
3061 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3062
3063 if (!hdmi_throughput)
3064 return 0;
3065
3066 /*
3067 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3068 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3069 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3070 * dividing adjusted clock value by 10.
3071 */
3072 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3073 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3074 kslice_adjust = 10;
3075 else
3076 kslice_adjust = 5;
3077
3078 /*
3079 * As per spec, the rate at which the source and the sink process
3080 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3081 * This depends upon the pixel clock rate and output formats
3082 * (kslice adjust).
3083 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3084 * at max 340MHz, otherwise they can be processed at max 400MHz.
3085 */
3086
3087 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3088
3089 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3090 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3091 else
3092 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3093
3094 /*
3095 * Taking into account the sink's capability for maximum
3096 * clock per slice (in MHz) as read from HF-VSDB.
3097 */
3098 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3099
3100 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3101 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3102
3103 /*
3104 * Keep on increasing the num of slices/line, starting from min_slices
3105 * per line till we get such a number, for which the slice_width is
3106 * just less than max_slice_width. The slices/line selected should be
3107 * less than or equal to the max horizontal slices that the combination
3108 * of PCON encoder and HDMI decoder can support.
3109 */
3110 slice_width = max_slice_width;
3111
3112 do {
3113 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3114 target_slices = 1;
3115 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3116 target_slices = 2;
3117 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3118 target_slices = 4;
3119 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3120 target_slices = 8;
3121 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3122 target_slices = 12;
3123 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3124 target_slices = 16;
3125 else
3126 return 0;
3127
3128 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3129 if (slice_width >= max_slice_width)
3130 min_slices = target_slices + 1;
3131 } while (slice_width >= max_slice_width);
3132
3133 return target_slices;
3134}
3135
3136/*
3137 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3138 * source and sink capabilities.
3139 *
3140 * @src_fraction_bpp: fractional bpp supported by the source
3141 * @slice_width: dsc slice width supported by the source and sink
3142 * @num_slices: num of slices supported by the source and sink
3143 * @output_format: video output format
3144 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3145 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3146 *
3147 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3148 */
3149int
3150intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3151 int output_format, bool hdmi_all_bpp,
3152 int hdmi_max_chunk_bytes)
3153{
3154 int max_dsc_bpp, min_dsc_bpp;
3155 int target_bytes;
3156 bool bpp_found = false;
3157 int bpp_decrement_x16;
3158 int bpp_target;
3159 int bpp_target_x16;
3160
3161 /*
3162 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3163 * Start with the max bpp and keep on decrementing with
3164 * fractional bpp, if supported by PCON DSC encoder
3165 *
3166 * for each bpp we check if no of bytes can be supported by HDMI sink
3167 */
3168
3169 /* Assuming: bpc as 8*/
3170 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3171 min_dsc_bpp = 6;
3172 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3173 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3174 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3175 min_dsc_bpp = 8;
3176 max_dsc_bpp = 3 * 8; /* 3*bpc */
3177 } else {
3178 /* Assuming 4:2:2 encoding */
3179 min_dsc_bpp = 7;
3180 max_dsc_bpp = 2 * 8; /* 2*bpc */
3181 }
3182
3183 /*
3184 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3185 * Section 7.7.34 : Source shall not enable compressed Video
3186 * Transport with bpp_target settings above 12 bpp unless
3187 * DSC_all_bpp is set to 1.
3188 */
3189 if (!hdmi_all_bpp)
3190 max_dsc_bpp = min(max_dsc_bpp, 12);
3191
3192 /*
3193 * The Sink has a limit of compressed data in bytes for a scanline,
3194 * as described in max_chunk_bytes field in HFVSDB block of edid.
3195 * The no. of bytes depend on the target bits per pixel that the
3196 * source configures. So we start with the max_bpp and calculate
3197 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3198 * till we get the target_chunk_bytes just less than what the sink's
3199 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3200 *
3201 * The decrement is according to the fractional support from PCON DSC
3202 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3203 *
3204 * bpp_target_x16 = bpp_target * 16
3205 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3206 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3207 */
3208
3209 bpp_target = max_dsc_bpp;
3210
3211 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3212 if (!src_fractional_bpp)
3213 src_fractional_bpp = 1;
3214 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3215 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3216
3217 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3218 int bpp;
3219
3220 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3221 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3222 if (target_bytes <= hdmi_max_chunk_bytes) {
3223 bpp_found = true;
3224 break;
3225 }
3226 bpp_target_x16 -= bpp_decrement_x16;
3227 }
3228 if (bpp_found)
3229 return bpp_target_x16;
3230
3231 return 0;
3232}