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1/*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29
30enum link_m_n_set;
31enum drm_scaling_filter;
32struct dpll;
33struct drm_connector;
34struct drm_device;
35struct drm_display_mode;
36struct drm_encoder;
37struct drm_file;
38struct drm_format_info;
39struct drm_framebuffer;
40struct drm_i915_gem_object;
41struct drm_i915_private;
42struct drm_mode_fb_cmd2;
43struct drm_modeset_acquire_ctx;
44struct drm_plane;
45struct drm_plane_state;
46struct i915_address_space;
47struct i915_ggtt_view;
48struct intel_atomic_state;
49struct intel_crtc;
50struct intel_crtc_state;
51struct intel_digital_port;
52struct intel_dp;
53struct intel_encoder;
54struct intel_initial_plane_config;
55struct intel_load_detect_pipe;
56struct intel_plane;
57struct intel_plane_state;
58struct intel_remapped_info;
59struct intel_rotation_info;
60
61enum i915_gpio {
62 GPIOA,
63 GPIOB,
64 GPIOC,
65 GPIOD,
66 GPIOE,
67 GPIOF,
68 GPIOG,
69 GPIOH,
70 __GPIOI_UNUSED,
71 GPIOJ,
72 GPIOK,
73 GPIOL,
74 GPIOM,
75 GPION,
76 GPIOO,
77};
78
79/*
80 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
81 * rest have consecutive values and match the enum values of transcoders
82 * with a 1:1 transcoder -> pipe mapping.
83 */
84enum pipe {
85 INVALID_PIPE = -1,
86
87 PIPE_A = 0,
88 PIPE_B,
89 PIPE_C,
90 PIPE_D,
91 _PIPE_EDP,
92
93 I915_MAX_PIPES = _PIPE_EDP
94};
95
96#define pipe_name(p) ((p) + 'A')
97
98enum transcoder {
99 INVALID_TRANSCODER = -1,
100 /*
101 * The following transcoders have a 1:1 transcoder -> pipe mapping,
102 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
103 * rest have consecutive values and match the enum values of the pipes
104 * they map to.
105 */
106 TRANSCODER_A = PIPE_A,
107 TRANSCODER_B = PIPE_B,
108 TRANSCODER_C = PIPE_C,
109 TRANSCODER_D = PIPE_D,
110
111 /*
112 * The following transcoders can map to any pipe, their enum value
113 * doesn't need to stay fixed.
114 */
115 TRANSCODER_EDP,
116 TRANSCODER_DSI_0,
117 TRANSCODER_DSI_1,
118 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
119 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
120
121 I915_MAX_TRANSCODERS
122};
123
124static inline const char *transcoder_name(enum transcoder transcoder)
125{
126 switch (transcoder) {
127 case TRANSCODER_A:
128 return "A";
129 case TRANSCODER_B:
130 return "B";
131 case TRANSCODER_C:
132 return "C";
133 case TRANSCODER_D:
134 return "D";
135 case TRANSCODER_EDP:
136 return "EDP";
137 case TRANSCODER_DSI_A:
138 return "DSI A";
139 case TRANSCODER_DSI_C:
140 return "DSI C";
141 default:
142 return "<invalid>";
143 }
144}
145
146static inline bool transcoder_is_dsi(enum transcoder transcoder)
147{
148 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
149}
150
151/*
152 * Global legacy plane identifier. Valid only for primary/sprite
153 * planes on pre-g4x, and only for primary planes on g4x-bdw.
154 */
155enum i9xx_plane_id {
156 PLANE_A,
157 PLANE_B,
158 PLANE_C,
159};
160
161#define plane_name(p) ((p) + 'A')
162#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
163
164/*
165 * Per-pipe plane identifier.
166 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
167 * number of planes per CRTC. Not all platforms really have this many planes,
168 * which means some arrays of size I915_MAX_PLANES may have unused entries
169 * between the topmost sprite plane and the cursor plane.
170 *
171 * This is expected to be passed to various register macros
172 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
173 */
174enum plane_id {
175 PLANE_PRIMARY,
176 PLANE_SPRITE0,
177 PLANE_SPRITE1,
178 PLANE_SPRITE2,
179 PLANE_SPRITE3,
180 PLANE_SPRITE4,
181 PLANE_SPRITE5,
182 PLANE_CURSOR,
183
184 I915_MAX_PLANES,
185};
186
187#define for_each_plane_id_on_crtc(__crtc, __p) \
188 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
189 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
190
191#define for_each_dbuf_slice(__dev_priv, __slice) \
192 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
193 for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
194
195#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
196 for_each_dbuf_slice((__dev_priv), (__slice)) \
197 for_each_if((__mask) & BIT(__slice))
198
199enum port {
200 PORT_NONE = -1,
201
202 PORT_A = 0,
203 PORT_B,
204 PORT_C,
205 PORT_D,
206 PORT_E,
207 PORT_F,
208 PORT_G,
209 PORT_H,
210 PORT_I,
211
212 /* tgl+ */
213 PORT_TC1 = PORT_D,
214 PORT_TC2,
215 PORT_TC3,
216 PORT_TC4,
217 PORT_TC5,
218 PORT_TC6,
219
220 /* XE_LPD repositions D/E offsets and bitfields */
221 PORT_D_XELPD = PORT_TC5,
222 PORT_E_XELPD,
223
224 I915_MAX_PORTS
225};
226
227#define port_name(p) ((p) + 'A')
228
229/*
230 * Ports identifier referenced from other drivers.
231 * Expected to remain stable over time
232 */
233static inline const char *port_identifier(enum port port)
234{
235 switch (port) {
236 case PORT_A:
237 return "Port A";
238 case PORT_B:
239 return "Port B";
240 case PORT_C:
241 return "Port C";
242 case PORT_D:
243 return "Port D";
244 case PORT_E:
245 return "Port E";
246 case PORT_F:
247 return "Port F";
248 case PORT_G:
249 return "Port G";
250 case PORT_H:
251 return "Port H";
252 case PORT_I:
253 return "Port I";
254 default:
255 return "<invalid>";
256 }
257}
258
259enum tc_port {
260 TC_PORT_NONE = -1,
261
262 TC_PORT_1 = 0,
263 TC_PORT_2,
264 TC_PORT_3,
265 TC_PORT_4,
266 TC_PORT_5,
267 TC_PORT_6,
268
269 I915_MAX_TC_PORTS
270};
271
272enum tc_port_mode {
273 TC_PORT_TBT_ALT,
274 TC_PORT_DP_ALT,
275 TC_PORT_LEGACY,
276};
277
278enum dpio_channel {
279 DPIO_CH0,
280 DPIO_CH1
281};
282
283enum dpio_phy {
284 DPIO_PHY0,
285 DPIO_PHY1,
286 DPIO_PHY2,
287};
288
289enum aux_ch {
290 AUX_CH_A,
291 AUX_CH_B,
292 AUX_CH_C,
293 AUX_CH_D,
294 AUX_CH_E, /* ICL+ */
295 AUX_CH_F,
296 AUX_CH_G,
297 AUX_CH_H,
298 AUX_CH_I,
299
300 /* tgl+ */
301 AUX_CH_USBC1 = AUX_CH_D,
302 AUX_CH_USBC2,
303 AUX_CH_USBC3,
304 AUX_CH_USBC4,
305 AUX_CH_USBC5,
306 AUX_CH_USBC6,
307
308 /* XE_LPD repositions D/E offsets and bitfields */
309 AUX_CH_D_XELPD = AUX_CH_USBC5,
310 AUX_CH_E_XELPD,
311};
312
313#define aux_ch_name(a) ((a) + 'A')
314
315/* Used by dp and fdi links */
316struct intel_link_m_n {
317 u32 tu;
318 u32 gmch_m;
319 u32 gmch_n;
320 u32 link_m;
321 u32 link_n;
322};
323
324enum phy {
325 PHY_NONE = -1,
326
327 PHY_A = 0,
328 PHY_B,
329 PHY_C,
330 PHY_D,
331 PHY_E,
332 PHY_F,
333 PHY_G,
334 PHY_H,
335 PHY_I,
336
337 I915_MAX_PHYS
338};
339
340#define phy_name(a) ((a) + 'A')
341
342enum phy_fia {
343 FIA1,
344 FIA2,
345 FIA3,
346};
347
348#define for_each_pipe(__dev_priv, __p) \
349 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
350 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
351
352#define for_each_pipe_masked(__dev_priv, __p, __mask) \
353 for_each_pipe(__dev_priv, __p) \
354 for_each_if((__mask) & BIT(__p))
355
356#define for_each_cpu_transcoder(__dev_priv, __t) \
357 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
358 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
359
360#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
361 for_each_cpu_transcoder(__dev_priv, __t) \
362 for_each_if ((__mask) & BIT(__t))
363
364#define for_each_sprite(__dev_priv, __p, __s) \
365 for ((__s) = 0; \
366 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
367 (__s)++)
368
369#define for_each_port(__port) \
370 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
371
372#define for_each_port_masked(__port, __ports_mask) \
373 for_each_port(__port) \
374 for_each_if((__ports_mask) & BIT(__port))
375
376#define for_each_phy_masked(__phy, __phys_mask) \
377 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
378 for_each_if((__phys_mask) & BIT(__phy))
379
380#define for_each_crtc(dev, crtc) \
381 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
382
383#define for_each_intel_plane(dev, intel_plane) \
384 list_for_each_entry(intel_plane, \
385 &(dev)->mode_config.plane_list, \
386 base.head)
387
388#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
389 list_for_each_entry(intel_plane, \
390 &(dev)->mode_config.plane_list, \
391 base.head) \
392 for_each_if((plane_mask) & \
393 drm_plane_mask(&intel_plane->base))
394
395#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
396 list_for_each_entry(intel_plane, \
397 &(dev)->mode_config.plane_list, \
398 base.head) \
399 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
400
401#define for_each_intel_crtc(dev, intel_crtc) \
402 list_for_each_entry(intel_crtc, \
403 &(dev)->mode_config.crtc_list, \
404 base.head)
405
406#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
407 list_for_each_entry(intel_crtc, \
408 &(dev)->mode_config.crtc_list, \
409 base.head) \
410 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
411
412#define for_each_intel_encoder(dev, intel_encoder) \
413 list_for_each_entry(intel_encoder, \
414 &(dev)->mode_config.encoder_list, \
415 base.head)
416
417#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
418 list_for_each_entry(intel_encoder, \
419 &(dev)->mode_config.encoder_list, \
420 base.head) \
421 for_each_if((encoder_mask) & \
422 drm_encoder_mask(&intel_encoder->base))
423
424#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
425 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
426 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
427 intel_encoder_can_psr(intel_encoder))
428
429#define for_each_intel_dp(dev, intel_encoder) \
430 for_each_intel_encoder(dev, intel_encoder) \
431 for_each_if(intel_encoder_is_dp(intel_encoder))
432
433#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
434 for_each_intel_encoder((dev), (intel_encoder)) \
435 for_each_if(intel_encoder_can_psr(intel_encoder))
436
437#define for_each_intel_connector_iter(intel_connector, iter) \
438 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
439
440#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
441 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
442 for_each_if((intel_encoder)->base.crtc == (__crtc))
443
444#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
445 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
446 for_each_if((intel_connector)->base.encoder == (__encoder))
447
448#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
449 for ((__i) = 0; \
450 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
451 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
452 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
453 (__i)++) \
454 for_each_if(plane)
455
456#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
457 for ((__i) = 0; \
458 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
459 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
460 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
461 (__i)++) \
462 for_each_if(plane)
463
464#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
465 for ((__i) = 0; \
466 (__i) < (__state)->base.dev->mode_config.num_crtc && \
467 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
468 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
469 (__i)++) \
470 for_each_if(crtc)
471
472#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
473 for ((__i) = 0; \
474 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
475 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
476 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
477 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
478 (__i)++) \
479 for_each_if(plane)
480
481#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
482 for ((__i) = 0; \
483 (__i) < (__state)->base.dev->mode_config.num_crtc && \
484 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
485 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
486 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
487 (__i)++) \
488 for_each_if(crtc)
489
490#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
491 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
492 (__i) >= 0 && \
493 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
494 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
495 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
496 (__i)--) \
497 for_each_if(crtc)
498
499#define intel_atomic_crtc_state_for_each_plane_state( \
500 plane, plane_state, \
501 crtc_state) \
502 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
503 ((crtc_state)->uapi.plane_mask)) \
504 for_each_if ((plane_state = \
505 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
506
507#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
508 for ((__i) = 0; \
509 (__i) < (__state)->base.num_connector; \
510 (__i)++) \
511 for_each_if ((__state)->base.connectors[__i].ptr && \
512 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
513 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
514
515int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
516 struct intel_crtc *crtc);
517u8 intel_calc_active_pipes(struct intel_atomic_state *state,
518 u8 active_pipes);
519void intel_link_compute_m_n(u16 bpp, int nlanes,
520 int pixel_clock, int link_clock,
521 struct intel_link_m_n *m_n,
522 bool constant_n, bool fec_enable);
523void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
524u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
525 u32 pixel_format, u64 modifier);
526enum drm_mode_status
527intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
528 const struct drm_display_mode *mode,
529 bool bigjoiner);
530enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
531bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
532
533void intel_plane_destroy(struct drm_plane *plane);
534void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state);
535void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
536void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
537void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
538enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
539int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
540int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
541 const char *name, u32 reg, int ref_freq);
542int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
543 const char *name, u32 reg);
544void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
545void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
546void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
547void intel_init_display_hooks(struct drm_i915_private *dev_priv);
548unsigned int intel_fb_xy_to_linear(int x, int y,
549 const struct intel_plane_state *state,
550 int plane);
551unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
552 int color_plane, unsigned int height);
553void intel_add_fb_offsets(int *x, int *y,
554 const struct intel_plane_state *state, int plane);
555unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
556unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
557bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
558int intel_display_suspend(struct drm_device *dev);
559void intel_encoder_destroy(struct drm_encoder *encoder);
560struct drm_display_mode *
561intel_encoder_current_mode(struct intel_encoder *encoder);
562bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
563bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
564enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
565 enum port port);
566int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
567 struct drm_file *file_priv);
568
569int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
570void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
571 struct intel_digital_port *dig_port,
572 unsigned int expected_mask);
573int intel_get_load_detect_pipe(struct drm_connector *connector,
574 struct intel_load_detect_pipe *old,
575 struct drm_modeset_acquire_ctx *ctx);
576void intel_release_load_detect_pipe(struct drm_connector *connector,
577 struct intel_load_detect_pipe *old,
578 struct drm_modeset_acquire_ctx *ctx);
579struct i915_vma *
580intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, bool phys_cursor,
581 const struct i915_ggtt_view *view,
582 bool uses_fence,
583 unsigned long *out_flags);
584void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
585struct drm_framebuffer *
586intel_framebuffer_create(struct drm_i915_gem_object *obj,
587 struct drm_mode_fb_cmd2 *mode_cmd);
588int intel_prepare_plane_fb(struct drm_plane *plane,
589 struct drm_plane_state *new_state);
590void intel_cleanup_plane_fb(struct drm_plane *plane,
591 struct drm_plane_state *old_state);
592
593void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
594 enum pipe pipe);
595
596int lpt_get_iclkip(struct drm_i915_private *dev_priv);
597bool intel_fuzzy_clock_check(int clock1, int clock2);
598
599void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
600void intel_display_finish_reset(struct drm_i915_private *dev_priv);
601void intel_dp_get_m_n(struct intel_crtc *crtc,
602 struct intel_crtc_state *pipe_config);
603void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
604 enum link_m_n_set m_n);
605int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
606
607bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
608void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
609void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
610enum intel_display_power_domain intel_port_to_power_domain(enum port port);
611enum intel_display_power_domain
612intel_aux_power_domain(struct intel_digital_port *dig_port);
613enum intel_display_power_domain
614intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
615void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
616 struct intel_crtc_state *crtc_state);
617void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
618
619int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
620unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
621
622bool
623intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
624 u64 modifier);
625
626int intel_plane_pin_fb(struct intel_plane_state *plane_state);
627void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
628struct intel_encoder *
629intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
630 const struct intel_crtc_state *crtc_state);
631
632unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
633 int color_plane);
634unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane);
635
636void intel_display_driver_register(struct drm_i915_private *i915);
637void intel_display_driver_unregister(struct drm_i915_private *i915);
638
639/* modesetting */
640void intel_modeset_init_hw(struct drm_i915_private *i915);
641int intel_modeset_init_noirq(struct drm_i915_private *i915);
642int intel_modeset_init_nogem(struct drm_i915_private *i915);
643int intel_modeset_init(struct drm_i915_private *i915);
644void intel_modeset_driver_remove(struct drm_i915_private *i915);
645void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
646void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
647void intel_display_resume(struct drm_device *dev);
648void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
649int intel_modeset_all_pipes(struct intel_atomic_state *state);
650
651/* modesetting asserts */
652void assert_panel_unlocked(struct drm_i915_private *dev_priv,
653 enum pipe pipe);
654void assert_pll(struct drm_i915_private *dev_priv,
655 enum pipe pipe, bool state);
656#define assert_pll_enabled(d, p) assert_pll(d, p, true)
657#define assert_pll_disabled(d, p) assert_pll(d, p, false)
658void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
659#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
660#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
661void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
662 enum pipe pipe, bool state);
663#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
664#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
665void assert_pipe(struct drm_i915_private *dev_priv,
666 enum transcoder cpu_transcoder, bool state);
667#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
668#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
669
670/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
671 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
672 * which may not necessarily be a user visible problem. This will either
673 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
674 * enable distros and users to tailor their preferred amount of i915 abrt
675 * spam.
676 */
677#define I915_STATE_WARN(condition, format...) ({ \
678 int __ret_warn_on = !!(condition); \
679 if (unlikely(__ret_warn_on)) \
680 if (!WARN(i915_modparams.verbose_state_checks, format)) \
681 DRM_ERROR(format); \
682 unlikely(__ret_warn_on); \
683})
684
685#define I915_STATE_WARN_ON(x) \
686 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
687
688#endif
1/*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29
30#include "i915_reg_defs.h"
31
32enum drm_scaling_filter;
33struct dpll;
34struct drm_connector;
35struct drm_device;
36struct drm_display_mode;
37struct drm_encoder;
38struct drm_file;
39struct drm_format_info;
40struct drm_framebuffer;
41struct drm_i915_gem_object;
42struct drm_i915_private;
43struct drm_mode_fb_cmd2;
44struct drm_modeset_acquire_ctx;
45struct drm_plane;
46struct drm_plane_state;
47struct i915_address_space;
48struct i915_gtt_view;
49struct intel_atomic_state;
50struct intel_crtc;
51struct intel_crtc_state;
52struct intel_digital_port;
53struct intel_dp;
54struct intel_encoder;
55struct intel_initial_plane_config;
56struct intel_link_m_n;
57struct intel_load_detect_pipe;
58struct intel_plane;
59struct intel_plane_state;
60struct intel_power_domain_mask;
61struct intel_remapped_info;
62struct intel_rotation_info;
63struct pci_dev;
64
65/*
66 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
67 * rest have consecutive values and match the enum values of transcoders
68 * with a 1:1 transcoder -> pipe mapping.
69 */
70enum pipe {
71 INVALID_PIPE = -1,
72
73 PIPE_A = 0,
74 PIPE_B,
75 PIPE_C,
76 PIPE_D,
77 _PIPE_EDP,
78
79 I915_MAX_PIPES = _PIPE_EDP
80};
81
82#define pipe_name(p) ((p) + 'A')
83
84enum transcoder {
85 INVALID_TRANSCODER = -1,
86 /*
87 * The following transcoders have a 1:1 transcoder -> pipe mapping,
88 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
89 * rest have consecutive values and match the enum values of the pipes
90 * they map to.
91 */
92 TRANSCODER_A = PIPE_A,
93 TRANSCODER_B = PIPE_B,
94 TRANSCODER_C = PIPE_C,
95 TRANSCODER_D = PIPE_D,
96
97 /*
98 * The following transcoders can map to any pipe, their enum value
99 * doesn't need to stay fixed.
100 */
101 TRANSCODER_EDP,
102 TRANSCODER_DSI_0,
103 TRANSCODER_DSI_1,
104 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
105 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
106
107 I915_MAX_TRANSCODERS
108};
109
110static inline const char *transcoder_name(enum transcoder transcoder)
111{
112 switch (transcoder) {
113 case TRANSCODER_A:
114 return "A";
115 case TRANSCODER_B:
116 return "B";
117 case TRANSCODER_C:
118 return "C";
119 case TRANSCODER_D:
120 return "D";
121 case TRANSCODER_EDP:
122 return "EDP";
123 case TRANSCODER_DSI_A:
124 return "DSI A";
125 case TRANSCODER_DSI_C:
126 return "DSI C";
127 default:
128 return "<invalid>";
129 }
130}
131
132static inline bool transcoder_is_dsi(enum transcoder transcoder)
133{
134 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
135}
136
137/*
138 * Global legacy plane identifier. Valid only for primary/sprite
139 * planes on pre-g4x, and only for primary planes on g4x-bdw.
140 */
141enum i9xx_plane_id {
142 PLANE_A,
143 PLANE_B,
144 PLANE_C,
145};
146
147#define plane_name(p) ((p) + 'A')
148#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
149
150/*
151 * Per-pipe plane identifier.
152 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
153 * number of planes per CRTC. Not all platforms really have this many planes,
154 * which means some arrays of size I915_MAX_PLANES may have unused entries
155 * between the topmost sprite plane and the cursor plane.
156 *
157 * This is expected to be passed to various register macros
158 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
159 */
160enum plane_id {
161 PLANE_PRIMARY,
162 PLANE_SPRITE0,
163 PLANE_SPRITE1,
164 PLANE_SPRITE2,
165 PLANE_SPRITE3,
166 PLANE_SPRITE4,
167 PLANE_SPRITE5,
168 PLANE_CURSOR,
169
170 I915_MAX_PLANES,
171};
172
173#define for_each_plane_id_on_crtc(__crtc, __p) \
174 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
175 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
176
177#define for_each_dbuf_slice(__dev_priv, __slice) \
178 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
179 for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
180
181#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
182 for_each_dbuf_slice((__dev_priv), (__slice)) \
183 for_each_if((__mask) & BIT(__slice))
184
185enum port {
186 PORT_NONE = -1,
187
188 PORT_A = 0,
189 PORT_B,
190 PORT_C,
191 PORT_D,
192 PORT_E,
193 PORT_F,
194 PORT_G,
195 PORT_H,
196 PORT_I,
197
198 /* tgl+ */
199 PORT_TC1 = PORT_D,
200 PORT_TC2,
201 PORT_TC3,
202 PORT_TC4,
203 PORT_TC5,
204 PORT_TC6,
205
206 /* XE_LPD repositions D/E offsets and bitfields */
207 PORT_D_XELPD = PORT_TC5,
208 PORT_E_XELPD,
209
210 I915_MAX_PORTS
211};
212
213#define port_name(p) ((p) + 'A')
214
215/*
216 * Ports identifier referenced from other drivers.
217 * Expected to remain stable over time
218 */
219static inline const char *port_identifier(enum port port)
220{
221 switch (port) {
222 case PORT_A:
223 return "Port A";
224 case PORT_B:
225 return "Port B";
226 case PORT_C:
227 return "Port C";
228 case PORT_D:
229 return "Port D";
230 case PORT_E:
231 return "Port E";
232 case PORT_F:
233 return "Port F";
234 case PORT_G:
235 return "Port G";
236 case PORT_H:
237 return "Port H";
238 case PORT_I:
239 return "Port I";
240 default:
241 return "<invalid>";
242 }
243}
244
245enum tc_port {
246 TC_PORT_NONE = -1,
247
248 TC_PORT_1 = 0,
249 TC_PORT_2,
250 TC_PORT_3,
251 TC_PORT_4,
252 TC_PORT_5,
253 TC_PORT_6,
254
255 I915_MAX_TC_PORTS
256};
257
258enum tc_port_mode {
259 TC_PORT_DISCONNECTED,
260 TC_PORT_TBT_ALT,
261 TC_PORT_DP_ALT,
262 TC_PORT_LEGACY,
263};
264
265enum aux_ch {
266 AUX_CH_A,
267 AUX_CH_B,
268 AUX_CH_C,
269 AUX_CH_D,
270 AUX_CH_E, /* ICL+ */
271 AUX_CH_F,
272 AUX_CH_G,
273 AUX_CH_H,
274 AUX_CH_I,
275
276 /* tgl+ */
277 AUX_CH_USBC1 = AUX_CH_D,
278 AUX_CH_USBC2,
279 AUX_CH_USBC3,
280 AUX_CH_USBC4,
281 AUX_CH_USBC5,
282 AUX_CH_USBC6,
283
284 /* XE_LPD repositions D/E offsets and bitfields */
285 AUX_CH_D_XELPD = AUX_CH_USBC5,
286 AUX_CH_E_XELPD,
287};
288
289#define aux_ch_name(a) ((a) + 'A')
290
291enum phy {
292 PHY_NONE = -1,
293
294 PHY_A = 0,
295 PHY_B,
296 PHY_C,
297 PHY_D,
298 PHY_E,
299 PHY_F,
300 PHY_G,
301 PHY_H,
302 PHY_I,
303
304 I915_MAX_PHYS
305};
306
307#define phy_name(a) ((a) + 'A')
308
309enum phy_fia {
310 FIA1,
311 FIA2,
312 FIA3,
313};
314
315enum hpd_pin {
316 HPD_NONE = 0,
317 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
318 HPD_CRT,
319 HPD_SDVO_B,
320 HPD_SDVO_C,
321 HPD_PORT_A,
322 HPD_PORT_B,
323 HPD_PORT_C,
324 HPD_PORT_D,
325 HPD_PORT_E,
326 HPD_PORT_TC1,
327 HPD_PORT_TC2,
328 HPD_PORT_TC3,
329 HPD_PORT_TC4,
330 HPD_PORT_TC5,
331 HPD_PORT_TC6,
332
333 HPD_NUM_PINS
334};
335
336#define for_each_hpd_pin(__pin) \
337 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
338
339#define for_each_pipe(__dev_priv, __p) \
340 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
341 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
342
343#define for_each_pipe_masked(__dev_priv, __p, __mask) \
344 for_each_pipe(__dev_priv, __p) \
345 for_each_if((__mask) & BIT(__p))
346
347#define for_each_cpu_transcoder(__dev_priv, __t) \
348 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
349 for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
350
351#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
352 for_each_cpu_transcoder(__dev_priv, __t) \
353 for_each_if ((__mask) & BIT(__t))
354
355#define for_each_sprite(__dev_priv, __p, __s) \
356 for ((__s) = 0; \
357 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
358 (__s)++)
359
360#define for_each_port(__port) \
361 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
362
363#define for_each_port_masked(__port, __ports_mask) \
364 for_each_port(__port) \
365 for_each_if((__ports_mask) & BIT(__port))
366
367#define for_each_phy_masked(__phy, __phys_mask) \
368 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
369 for_each_if((__phys_mask) & BIT(__phy))
370
371#define for_each_crtc(dev, crtc) \
372 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
373
374#define for_each_intel_plane(dev, intel_plane) \
375 list_for_each_entry(intel_plane, \
376 &(dev)->mode_config.plane_list, \
377 base.head)
378
379#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
380 list_for_each_entry(intel_plane, \
381 &(dev)->mode_config.plane_list, \
382 base.head) \
383 for_each_if((plane_mask) & \
384 drm_plane_mask(&intel_plane->base))
385
386#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
387 list_for_each_entry(intel_plane, \
388 &(dev)->mode_config.plane_list, \
389 base.head) \
390 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
391
392#define for_each_intel_crtc(dev, intel_crtc) \
393 list_for_each_entry(intel_crtc, \
394 &(dev)->mode_config.crtc_list, \
395 base.head)
396
397#define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
398 list_for_each_entry(intel_crtc, \
399 &(dev)->mode_config.crtc_list, \
400 base.head) \
401 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
402
403#define for_each_intel_encoder(dev, intel_encoder) \
404 list_for_each_entry(intel_encoder, \
405 &(dev)->mode_config.encoder_list, \
406 base.head)
407
408#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
409 list_for_each_entry(intel_encoder, \
410 &(dev)->mode_config.encoder_list, \
411 base.head) \
412 for_each_if((encoder_mask) & \
413 drm_encoder_mask(&intel_encoder->base))
414
415#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
416 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
417 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
418 intel_encoder_can_psr(intel_encoder))
419
420#define for_each_intel_dp(dev, intel_encoder) \
421 for_each_intel_encoder(dev, intel_encoder) \
422 for_each_if(intel_encoder_is_dp(intel_encoder))
423
424#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
425 for_each_intel_encoder((dev), (intel_encoder)) \
426 for_each_if(intel_encoder_can_psr(intel_encoder))
427
428#define for_each_intel_connector_iter(intel_connector, iter) \
429 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
430
431#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
432 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
433 for_each_if((intel_encoder)->base.crtc == (__crtc))
434
435#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
436 for ((__i) = 0; \
437 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
438 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
439 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
440 (__i)++) \
441 for_each_if(plane)
442
443#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
444 for ((__i) = 0; \
445 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
446 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
447 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
448 (__i)++) \
449 for_each_if(plane)
450
451#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
452 for ((__i) = 0; \
453 (__i) < (__state)->base.dev->mode_config.num_crtc && \
454 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
455 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
456 (__i)++) \
457 for_each_if(crtc)
458
459#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
460 for ((__i) = 0; \
461 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
462 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
463 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
464 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
465 (__i)++) \
466 for_each_if(plane)
467
468#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
469 for ((__i) = 0; \
470 (__i) < (__state)->base.dev->mode_config.num_crtc && \
471 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
472 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
473 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
474 (__i)++) \
475 for_each_if(crtc)
476
477#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
478 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
479 (__i) >= 0 && \
480 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
481 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
482 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
483 (__i)--) \
484 for_each_if(crtc)
485
486#define intel_atomic_crtc_state_for_each_plane_state( \
487 plane, plane_state, \
488 crtc_state) \
489 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
490 ((crtc_state)->uapi.plane_mask)) \
491 for_each_if ((plane_state = \
492 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
493
494#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
495 for ((__i) = 0; \
496 (__i) < (__state)->base.num_connector; \
497 (__i)++) \
498 for_each_if ((__state)->base.connectors[__i].ptr && \
499 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
500 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
501
502int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
503 struct intel_crtc *crtc);
504u8 intel_calc_active_pipes(struct intel_atomic_state *state,
505 u8 active_pipes);
506void intel_link_compute_m_n(u16 bpp, int nlanes,
507 int pixel_clock, int link_clock,
508 struct intel_link_m_n *m_n,
509 bool fec_enable);
510u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
511 u32 pixel_format, u64 modifier);
512enum drm_mode_status
513intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
514 const struct drm_display_mode *mode,
515 bool bigjoiner);
516enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
517bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
518bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
519bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
520u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
521struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
522bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
523bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
524 const struct intel_crtc_state *pipe_config,
525 bool fastset);
526void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
527
528void intel_plane_destroy(struct drm_plane *plane);
529void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
530void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
531void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
532void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
533void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
534void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
535int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
536int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
537 const char *name, u32 reg, int ref_freq);
538int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
539 const char *name, u32 reg);
540void intel_init_display_hooks(struct drm_i915_private *dev_priv);
541unsigned int intel_fb_xy_to_linear(int x, int y,
542 const struct intel_plane_state *state,
543 int plane);
544void intel_add_fb_offsets(int *x, int *y,
545 const struct intel_plane_state *state, int plane);
546unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
547unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
548bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
549int intel_display_suspend(struct drm_device *dev);
550void intel_encoder_destroy(struct drm_encoder *encoder);
551struct drm_display_mode *
552intel_encoder_current_mode(struct intel_encoder *encoder);
553void intel_encoder_get_config(struct intel_encoder *encoder,
554 struct intel_crtc_state *crtc_state);
555bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
556bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
557bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
558enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
559 enum port port);
560int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
561 struct drm_file *file_priv);
562
563int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
564void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
565 struct intel_digital_port *dig_port,
566 unsigned int expected_mask);
567int intel_get_load_detect_pipe(struct drm_connector *connector,
568 struct intel_load_detect_pipe *old,
569 struct drm_modeset_acquire_ctx *ctx);
570void intel_release_load_detect_pipe(struct drm_connector *connector,
571 struct intel_load_detect_pipe *old,
572 struct drm_modeset_acquire_ctx *ctx);
573struct drm_framebuffer *
574intel_framebuffer_create(struct drm_i915_gem_object *obj,
575 struct drm_mode_fb_cmd2 *mode_cmd);
576
577bool intel_fuzzy_clock_check(int clock1, int clock2);
578
579void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
580void intel_display_finish_reset(struct drm_i915_private *dev_priv);
581void intel_zero_m_n(struct intel_link_m_n *m_n);
582void intel_set_m_n(struct drm_i915_private *i915,
583 const struct intel_link_m_n *m_n,
584 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
585 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
586void intel_get_m_n(struct drm_i915_private *i915,
587 struct intel_link_m_n *m_n,
588 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
589 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
590bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
591 enum transcoder transcoder);
592void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
593 enum transcoder cpu_transcoder,
594 const struct intel_link_m_n *m_n);
595void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
596 enum transcoder cpu_transcoder,
597 const struct intel_link_m_n *m_n);
598void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
599 enum transcoder cpu_transcoder,
600 struct intel_link_m_n *m_n);
601void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
602 enum transcoder cpu_transcoder,
603 struct intel_link_m_n *m_n);
604void i9xx_crtc_clock_get(struct intel_crtc *crtc,
605 struct intel_crtc_state *pipe_config);
606int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
607int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
608enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
609enum intel_display_power_domain
610intel_aux_power_domain(struct intel_digital_port *dig_port);
611void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
612 struct intel_crtc_state *crtc_state);
613void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
614
615int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
616unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
617
618bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
619
620struct intel_encoder *
621intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
622 const struct intel_crtc_state *crtc_state);
623void intel_plane_disable_noatomic(struct intel_crtc *crtc,
624 struct intel_plane *plane);
625void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
626 struct intel_plane_state *plane_state,
627 bool visible);
628void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
629
630void intel_display_driver_register(struct drm_i915_private *i915);
631void intel_display_driver_unregister(struct drm_i915_private *i915);
632
633void intel_update_watermarks(struct drm_i915_private *i915);
634
635/* modesetting */
636bool intel_modeset_probe_defer(struct pci_dev *pdev);
637void intel_modeset_init_hw(struct drm_i915_private *i915);
638int intel_modeset_init_noirq(struct drm_i915_private *i915);
639int intel_modeset_init_nogem(struct drm_i915_private *i915);
640int intel_modeset_init(struct drm_i915_private *i915);
641void intel_modeset_driver_remove(struct drm_i915_private *i915);
642void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
643void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
644void intel_display_resume(struct drm_device *dev);
645int intel_modeset_all_pipes(struct intel_atomic_state *state,
646 const char *reason);
647void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
648 struct intel_power_domain_mask *old_domains);
649void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
650 struct intel_power_domain_mask *domains);
651
652/* modesetting asserts */
653void assert_transcoder(struct drm_i915_private *dev_priv,
654 enum transcoder cpu_transcoder, bool state);
655#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
656#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
657
658/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
659 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
660 * which may not necessarily be a user visible problem. This will either
661 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
662 * enable distros and users to tailor their preferred amount of i915 abrt
663 * spam.
664 */
665#define I915_STATE_WARN(condition, format...) ({ \
666 int __ret_warn_on = !!(condition); \
667 if (unlikely(__ret_warn_on)) \
668 if (!WARN(i915_modparams.verbose_state_checks, format)) \
669 DRM_ERROR(format); \
670 unlikely(__ret_warn_on); \
671})
672
673#define I915_STATE_WARN_ON(x) \
674 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
675
676bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
677
678#endif