1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_DE_H__
 7#define __INTEL_DE_H__
 8
 9#include "i915_drv.h"
10#include "i915_reg.h"
11#include "i915_trace.h"
12#include "intel_uncore.h"
13
14static inline u32
15intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
16{
17	return intel_uncore_read(&i915->uncore, reg);
18}
19
20static inline void
21intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
22{
23	intel_uncore_posting_read(&i915->uncore, reg);
24}
25
26static inline void
27intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
28{
29	intel_uncore_write(&i915->uncore, reg, val);
30}
31
32static inline void
33intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
34{
35	intel_uncore_rmw(&i915->uncore, reg, clear, set);
36}
37
38static inline int
39intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
40			   u32 mask, u32 value, unsigned int timeout)
41{
42	return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
43}
44
45static inline int
46intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
47		      u32 mask, unsigned int timeout)
48{
49	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
50}
51
52static inline int
53intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
54			u32 mask, unsigned int timeout)
55{
56	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
57}
58
59/*
60 * Unlocked mmio-accessors, think carefully before using these.
61 *
62 * Certain architectures will die if the same cacheline is concurrently accessed
63 * by different clients (e.g. on Ivybridge). Access to registers should
64 * therefore generally be serialised, by either the dev_priv->uncore.lock or
65 * a more localised lock guarding all access to that bank of registers.
66 */
67static inline u32
68intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
69{
70	u32 val;
71
72	val = intel_uncore_read_fw(&i915->uncore, reg);
73	trace_i915_reg_rw(false, reg, val, sizeof(val), true);
74
75	return val;
76}
77
78static inline void
79intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
80{
81	trace_i915_reg_rw(true, reg, val, sizeof(val), true);
82	intel_uncore_write_fw(&i915->uncore, reg, val);
83}
84
85#endif /* __INTEL_DE_H__ */

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_DE_H__
 7#define __INTEL_DE_H__
 8
 9#include "i915_drv.h"
 
10#include "i915_trace.h"
11#include "intel_uncore.h"
12
13static inline u32
14intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
15{
16	return intel_uncore_read(&i915->uncore, reg);
17}
18
19static inline void
20intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
21{
22	intel_uncore_posting_read(&i915->uncore, reg);
23}
24
25static inline void
26intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
27{
28	intel_uncore_write(&i915->uncore, reg, val);
29}
30
31static inline void
32intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
33{
34	intel_uncore_rmw(&i915->uncore, reg, clear, set);
35}
36
37static inline int
38intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
39			   u32 mask, u32 value, unsigned int timeout)
40{
41	return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
42}
43
44static inline int
45intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
46		      u32 mask, unsigned int timeout)
47{
48	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
49}
50
51static inline int
52intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
53			u32 mask, unsigned int timeout)
54{
55	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
56}
57
58/*
59 * Unlocked mmio-accessors, think carefully before using these.
60 *
61 * Certain architectures will die if the same cacheline is concurrently accessed
62 * by different clients (e.g. on Ivybridge). Access to registers should
63 * therefore generally be serialised, by either the dev_priv->uncore.lock or
64 * a more localised lock guarding all access to that bank of registers.
65 */
66static inline u32
67intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
68{
69	u32 val;
70
71	val = intel_uncore_read_fw(&i915->uncore, reg);
72	trace_i915_reg_rw(false, reg, val, sizeof(val), true);
73
74	return val;
75}
76
77static inline void
78intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
79{
80	trace_i915_reg_rw(true, reg, val, sizeof(val), true);
81	intel_uncore_write_fw(&i915->uncore, reg, val);
82}
83
84#endif /* __INTEL_DE_H__ */