1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_CDCLK_H__
 7#define __INTEL_CDCLK_H__
 8
 9#include <linux/types.h>
10
11#include "i915_drv.h"
12#include "intel_display.h"
13#include "intel_global_state.h"
14
15struct drm_i915_private;
16struct intel_atomic_state;
17struct intel_crtc_state;
18
19struct intel_cdclk_vals {
20	u32 cdclk;
21	u16 refclk;
22	u8 divider;	/* CD2X divider * 2 */
23	u8 ratio;
24};
25
26struct intel_cdclk_state {
27	struct intel_global_state base;
28
29	/*
30	 * Logical configuration of cdclk (used for all scaling,
31	 * watermark, etc. calculations and checks). This is
32	 * computed as if all enabled crtcs were active.
33	 */
34	struct intel_cdclk_config logical;
35
36	/*
37	 * Actual configuration of cdclk, can be different from the
38	 * logical configuration only when all crtc's are DPMS off.
39	 */
40	struct intel_cdclk_config actual;
41
 
 
42	/* minimum acceptable cdclk for each pipe */
43	int min_cdclk[I915_MAX_PIPES];
44	/* minimum acceptable voltage level for each pipe */
45	u8 min_voltage_level[I915_MAX_PIPES];
46
47	/* pipe to which cd2x update is synchronized */
48	enum pipe pipe;
49
50	/* forced minimum cdclk for glk+ audio w/a */
51	int force_min_cdclk;
52
53	/* bitmask of active pipes */
54	u8 active_pipes;
55};
56
57int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
58void intel_cdclk_init_hw(struct drm_i915_private *i915);
59void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
60void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
61void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
62void intel_update_cdclk(struct drm_i915_private *dev_priv);
63u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
64bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
65			       const struct intel_cdclk_config *b);
66void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
67void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
68void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
 
69			     const char *context);
70int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
71
 
 
 
72struct intel_cdclk_state *
73intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
74
75#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
76#define intel_atomic_get_old_cdclk_state(state) \
77	to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
78#define intel_atomic_get_new_cdclk_state(state) \
79	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
80
81int intel_cdclk_init(struct drm_i915_private *dev_priv);
82
83#endif /* __INTEL_CDCLK_H__ */

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_CDCLK_H__
 7#define __INTEL_CDCLK_H__
 8
 9#include <linux/types.h>
10
 
11#include "intel_display.h"
12#include "intel_global_state.h"
13
14struct drm_i915_private;
15struct intel_atomic_state;
16struct intel_crtc_state;
17
18struct intel_cdclk_config {
19	unsigned int cdclk, vco, ref, bypass;
20	u8 voltage_level;
 
 
21};
22
23struct intel_cdclk_state {
24	struct intel_global_state base;
25
26	/*
27	 * Logical configuration of cdclk (used for all scaling,
28	 * watermark, etc. calculations and checks). This is
29	 * computed as if all enabled crtcs were active.
30	 */
31	struct intel_cdclk_config logical;
32
33	/*
34	 * Actual configuration of cdclk, can be different from the
35	 * logical configuration only when all crtc's are DPMS off.
36	 */
37	struct intel_cdclk_config actual;
38
39	/* minimum acceptable cdclk to satisfy bandwidth requirements */
40	int bw_min_cdclk;
41	/* minimum acceptable cdclk for each pipe */
42	int min_cdclk[I915_MAX_PIPES];
43	/* minimum acceptable voltage level for each pipe */
44	u8 min_voltage_level[I915_MAX_PIPES];
45
46	/* pipe to which cd2x update is synchronized */
47	enum pipe pipe;
48
49	/* forced minimum cdclk for glk+ audio w/a */
50	int force_min_cdclk;
51
52	/* bitmask of active pipes */
53	u8 active_pipes;
54};
55
56int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
57void intel_cdclk_init_hw(struct drm_i915_private *i915);
58void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
59void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
60void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
61void intel_update_cdclk(struct drm_i915_private *dev_priv);
62u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
63bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
64			       const struct intel_cdclk_config *b);
65void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
66void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
67void intel_cdclk_dump_config(struct drm_i915_private *i915,
68			     const struct intel_cdclk_config *cdclk_config,
69			     const char *context);
70int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
71void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
72			   struct intel_cdclk_config *cdclk_config);
73int intel_cdclk_atomic_check(struct intel_atomic_state *state,
74			     bool *need_cdclk_calc);
75struct intel_cdclk_state *
76intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
77
78#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
79#define intel_atomic_get_old_cdclk_state(state) \
80	to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
81#define intel_atomic_get_new_cdclk_state(state) \
82	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
83
84int intel_cdclk_init(struct drm_i915_private *dev_priv);
85
86#endif /* __INTEL_CDCLK_H__ */