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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM625 SK: https://www.ti.com/lit/zip/sprr448
4 *
5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/net/ti-dp83867.h>
13#include "k3-am625.dtsi"
14
15/ {
16 compatible = "ti,am625-sk", "ti,am625";
17 model = "Texas Instruments AM625 SK";
18
19 aliases {
20 serial2 = &main_uart0;
21 mmc0 = &sdhci0;
22 mmc1 = &sdhci1;
23 mmc2 = &sdhci2;
24 spi0 = &ospi0;
25 ethernet0 = &cpsw_port1;
26 ethernet1 = &cpsw_port2;
27 };
28
29 chosen {
30 stdout-path = "serial2:115200n8";
31 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
32 };
33
34 opp-table {
35 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
36 opp-1400000000 {
37 opp-hz = /bits/ 64 <1400000000>;
38 opp-supported-hw = <0x01 0x0004>;
39 clock-latency-ns = <6000000>;
40 };
41 };
42
43 memory@80000000 {
44 device_type = "memory";
45 /* 2G RAM */
46 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
47
48 };
49
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 ranges;
54
55 ramoops@9ca00000 {
56 compatible = "ramoops";
57 reg = <0x00 0x9ca00000 0x00 0x00100000>;
58 record-size = <0x8000>;
59 console-size = <0x8000>;
60 ftrace-size = <0x00>;
61 pmsg-size = <0x8000>;
62 };
63
64 secure_tfa_ddr: tfa@9e780000 {
65 reg = <0x00 0x9e780000 0x00 0x80000>;
66 alignment = <0x1000>;
67 no-map;
68 };
69
70 secure_ddr: optee@9e800000 {
71 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
72 alignment = <0x1000>;
73 no-map;
74 };
75
76 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
77 compatible = "shared-dma-pool";
78 reg = <0x00 0x9db00000 0x00 0xc00000>;
79 no-map;
80 };
81 };
82
83 vmain_pd: regulator-0 {
84 /* TPS65988 PD CONTROLLER OUTPUT */
85 compatible = "regulator-fixed";
86 regulator-name = "vmain_pd";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 regulator-always-on;
90 regulator-boot-on;
91 };
92
93 vcc_5v0: regulator-1 {
94 /* Output of LM34936 */
95 compatible = "regulator-fixed";
96 regulator-name = "vcc_5v0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 vin-supply = <&vmain_pd>;
100 regulator-always-on;
101 regulator-boot-on;
102 };
103
104 vcc_3v3_sys: regulator-2 {
105 /* output of LM61460-Q1 */
106 compatible = "regulator-fixed";
107 regulator-name = "vcc_3v3_sys";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 vin-supply = <&vmain_pd>;
111 regulator-always-on;
112 regulator-boot-on;
113 };
114
115 vdd_mmc1: regulator-3 {
116 /* TPS22918DBVR */
117 compatible = "regulator-fixed";
118 regulator-name = "vdd_mmc1";
119 regulator-min-microvolt = <3300000>;
120 regulator-max-microvolt = <3300000>;
121 regulator-boot-on;
122 enable-active-high;
123 vin-supply = <&vcc_3v3_sys>;
124 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
125 };
126
127 vdd_sd_dv: regulator-4 {
128 /* Output of TLV71033 */
129 compatible = "regulator-gpio";
130 regulator-name = "tlv71033";
131 pinctrl-names = "default";
132 pinctrl-0 = <&vdd_sd_dv_pins_default>;
133 regulator-min-microvolt = <1800000>;
134 regulator-max-microvolt = <3300000>;
135 regulator-boot-on;
136 vin-supply = <&vcc_5v0>;
137 gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
138 states = <1800000 0x0>,
139 <3300000 0x1>;
140 };
141
142 leds {
143 compatible = "gpio-leds";
144 pinctrl-names = "default";
145 pinctrl-0 = <&usr_led_pins_default>;
146
147 led-0 {
148 label = "am62-sk:green:heartbeat";
149 gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
150 linux,default-trigger = "heartbeat";
151 function = LED_FUNCTION_HEARTBEAT;
152 default-state = "off";
153 };
154 };
155};
156
157&main_pmx0 {
158 main_uart0_pins_default: main-uart0-pins-default {
159 pinctrl-single,pins = <
160 AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
161 AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
162 >;
163 };
164
165 main_i2c0_pins_default: main-i2c0-pins-default {
166 pinctrl-single,pins = <
167 AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
168 AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
169 >;
170 };
171
172 main_i2c1_pins_default: main-i2c1-pins-default {
173 pinctrl-single,pins = <
174 AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
175 AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
176 >;
177 };
178
179 main_i2c2_pins_default: main-i2c2-pins-default {
180 pinctrl-single,pins = <
181 AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
182 AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
183 >;
184 };
185
186 main_mmc0_pins_default: main-mmc0-pins-default {
187 pinctrl-single,pins = <
188 AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
189 AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
190 AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
191 AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
192 AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
193 AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
194 AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
195 AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
196 AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
197 AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
198 >;
199 };
200
201 main_mmc1_pins_default: main-mmc1-pins-default {
202 pinctrl-single,pins = <
203 AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
204 AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
205 AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
206 AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
207 AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
208 AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
209 AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
210 >;
211 };
212
213 usr_led_pins_default: usr-led-pins-default {
214 pinctrl-single,pins = <
215 AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
216 >;
217 };
218
219 main_mdio1_pins_default: main-mdio1-pins-default {
220 pinctrl-single,pins = <
221 AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
222 AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
223 >;
224 };
225
226 main_rgmii1_pins_default: main-rgmii1-pins-default {
227 pinctrl-single,pins = <
228 AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
229 AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
230 AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
231 AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
232 AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
233 AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
234 AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
235 AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
236 AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
237 AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
238 AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
239 AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
240 >;
241 };
242
243 main_rgmii2_pins_default: main-rgmii2-pins-default {
244 pinctrl-single,pins = <
245 AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
246 AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
247 AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
248 AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
249 AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
250 AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
251 AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
252 AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
253 AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
254 AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
255 AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
256 AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
257 >;
258 };
259
260 ospi0_pins_default: ospi0-pins-default {
261 pinctrl-single,pins = <
262 AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
263 AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
264 AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
265 AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
266 AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
267 AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
268 AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
269 AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
270 AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
271 AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
272 AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
273 >;
274 };
275
276 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
277 pinctrl-single,pins = <
278 AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
279 >;
280 };
281
282 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
283 pinctrl-single,pins = <
284 AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
285 >;
286 };
287};
288
289&wkup_uart0 {
290 /* WKUP UART0 is used by DM firmware */
291 status = "reserved";
292};
293
294&main_uart0 {
295 status = "okay";
296 pinctrl-names = "default";
297 pinctrl-0 = <&main_uart0_pins_default>;
298};
299
300&main_uart1 {
301 /* Main UART1 is used by TIFS firmware */
302 status = "reserved";
303};
304
305&main_i2c0 {
306 status = "okay";
307 pinctrl-names = "default";
308 pinctrl-0 = <&main_i2c0_pins_default>;
309 clock-frequency = <400000>;
310};
311
312&main_i2c1 {
313 status = "okay";
314 pinctrl-names = "default";
315 pinctrl-0 = <&main_i2c1_pins_default>;
316 clock-frequency = <400000>;
317
318 exp1: gpio@22 {
319 compatible = "ti,tca6424";
320 reg = <0x22>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
324 "PRU_DETECT", "MMC1_SD_EN",
325 "VPP_LDO_EN", "EXP_PS_3V3_En",
326 "EXP_PS_5V0_En", "EXP_HAT_DETECT",
327 "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
328 "UART1_FET_BUF_EN", "WL_LT_EN",
329 "GPIO_HDMI_RSTn", "CSI_GPIO1",
330 "CSI_GPIO2", "PRU_3V3_EN",
331 "HDMI_INTn", "TEST_GPIO2",
332 "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
333 "MCASP1_FET_SEL", "UART1_FET_SEL",
334 "TSINT#", "IO_EXP_TEST_LED";
335
336 interrupt-parent = <&main_gpio1>;
337 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340
341 pinctrl-names = "default";
342 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
343 };
344};
345
346&sdhci0 {
347 status = "okay";
348 pinctrl-names = "default";
349 pinctrl-0 = <&main_mmc0_pins_default>;
350 ti,driver-strength-ohm = <50>;
351 disable-wp;
352};
353
354&sdhci1 {
355 /* SD/MMC */
356 status = "okay";
357 vmmc-supply = <&vdd_mmc1>;
358 vqmmc-supply = <&vdd_sd_dv>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&main_mmc1_pins_default>;
361 ti,driver-strength-ohm = <50>;
362 disable-wp;
363};
364
365&cpsw3g {
366 pinctrl-names = "default";
367 pinctrl-0 = <&main_rgmii1_pins_default
368 &main_rgmii2_pins_default>;
369};
370
371&cpsw_port1 {
372 phy-mode = "rgmii-rxid";
373 phy-handle = <&cpsw3g_phy0>;
374};
375
376&cpsw_port2 {
377 phy-mode = "rgmii-rxid";
378 phy-handle = <&cpsw3g_phy1>;
379};
380
381&cpsw3g_mdio {
382 status = "okay";
383 pinctrl-names = "default";
384 pinctrl-0 = <&main_mdio1_pins_default>;
385
386 cpsw3g_phy0: ethernet-phy@0 {
387 reg = <0>;
388 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
389 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
390 ti,min-output-impedance;
391 };
392
393 cpsw3g_phy1: ethernet-phy@1 {
394 reg = <1>;
395 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
396 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
397 ti,min-output-impedance;
398 };
399};
400
401&mailbox0_cluster0 {
402 mbox_m4_0: mbox-m4-0 {
403 ti,mbox-rx = <0 0 0>;
404 ti,mbox-tx = <1 0 0>;
405 };
406};
407
408&ospi0 {
409 status = "okay";
410 pinctrl-names = "default";
411 pinctrl-0 = <&ospi0_pins_default>;
412
413 flash@0{
414 compatible = "jedec,spi-nor";
415 reg = <0x0>;
416 spi-tx-bus-width = <8>;
417 spi-rx-bus-width = <8>;
418 spi-max-frequency = <25000000>;
419 cdns,tshsl-ns = <60>;
420 cdns,tsd2d-ns = <60>;
421 cdns,tchsh-ns = <60>;
422 cdns,tslch-ns = <60>;
423 cdns,read-delay = <4>;
424
425 partitions {
426 compatible = "fixed-partitions";
427 #address-cells = <1>;
428 #size-cells = <1>;
429
430 partition@0 {
431 label = "ospi.tiboot3";
432 reg = <0x0 0x80000>;
433 };
434
435 partition@80000 {
436 label = "ospi.tispl";
437 reg = <0x80000 0x200000>;
438 };
439
440 partition@280000 {
441 label = "ospi.u-boot";
442 reg = <0x280000 0x400000>;
443 };
444
445 partition@680000 {
446 label = "ospi.env";
447 reg = <0x680000 0x40000>;
448 };
449
450 partition@6c0000 {
451 label = "ospi.env.backup";
452 reg = <0x6c0000 0x40000>;
453 };
454
455 partition@800000 {
456 label = "ospi.rootfs";
457 reg = <0x800000 0x37c0000>;
458 };
459
460 partition@3fc0000 {
461 label = "ospi.phypattern";
462 reg = <0x3fc0000 0x40000>;
463 };
464 };
465 };
466};