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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (C) 2021, Intel Corporation. */
3
4#include "ice.h"
5#include "ice_lib.h"
6
7#define E810_OUT_PROP_DELAY_NS 1
8
9/**
10 * ice_set_tx_tstamp - Enable or disable Tx timestamping
11 * @pf: The PF pointer to search in
12 * @on: bool value for whether timestamps are enabled or disabled
13 */
14static void ice_set_tx_tstamp(struct ice_pf *pf, bool on)
15{
16 struct ice_vsi *vsi;
17 u32 val;
18 u16 i;
19
20 vsi = ice_get_main_vsi(pf);
21 if (!vsi)
22 return;
23
24 /* Set the timestamp enable flag for all the Tx rings */
25 ice_for_each_txq(vsi, i) {
26 if (!vsi->tx_rings[i])
27 continue;
28 vsi->tx_rings[i]->ptp_tx = on;
29 }
30
31 /* Configure the Tx timestamp interrupt */
32 val = rd32(&pf->hw, PFINT_OICR_ENA);
33 if (on)
34 val |= PFINT_OICR_TSYN_TX_M;
35 else
36 val &= ~PFINT_OICR_TSYN_TX_M;
37 wr32(&pf->hw, PFINT_OICR_ENA, val);
38}
39
40/**
41 * ice_set_rx_tstamp - Enable or disable Rx timestamping
42 * @pf: The PF pointer to search in
43 * @on: bool value for whether timestamps are enabled or disabled
44 */
45static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
46{
47 struct ice_vsi *vsi;
48 u16 i;
49
50 vsi = ice_get_main_vsi(pf);
51 if (!vsi)
52 return;
53
54 /* Set the timestamp flag for all the Rx rings */
55 ice_for_each_rxq(vsi, i) {
56 if (!vsi->rx_rings[i])
57 continue;
58 vsi->rx_rings[i]->ptp_rx = on;
59 }
60}
61
62/**
63 * ice_ptp_cfg_timestamp - Configure timestamp for init/deinit
64 * @pf: Board private structure
65 * @ena: bool value to enable or disable time stamp
66 *
67 * This function will configure timestamping during PTP initialization
68 * and deinitialization
69 */
70static void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena)
71{
72 ice_set_tx_tstamp(pf, ena);
73 ice_set_rx_tstamp(pf, ena);
74
75 if (ena) {
76 pf->ptp.tstamp_config.rx_filter = HWTSTAMP_FILTER_ALL;
77 pf->ptp.tstamp_config.tx_type = HWTSTAMP_TX_ON;
78 } else {
79 pf->ptp.tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
80 pf->ptp.tstamp_config.tx_type = HWTSTAMP_TX_OFF;
81 }
82}
83
84/**
85 * ice_get_ptp_clock_index - Get the PTP clock index
86 * @pf: the PF pointer
87 *
88 * Determine the clock index of the PTP clock associated with this device. If
89 * this is the PF controlling the clock, just use the local access to the
90 * clock device pointer.
91 *
92 * Otherwise, read from the driver shared parameters to determine the clock
93 * index value.
94 *
95 * Returns: the index of the PTP clock associated with this device, or -1 if
96 * there is no associated clock.
97 */
98int ice_get_ptp_clock_index(struct ice_pf *pf)
99{
100 struct device *dev = ice_pf_to_dev(pf);
101 enum ice_aqc_driver_params param_idx;
102 struct ice_hw *hw = &pf->hw;
103 u8 tmr_idx;
104 u32 value;
105 int err;
106
107 /* Use the ptp_clock structure if we're the main PF */
108 if (pf->ptp.clock)
109 return ptp_clock_index(pf->ptp.clock);
110
111 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
112 if (!tmr_idx)
113 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
114 else
115 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
116
117 err = ice_aq_get_driver_param(hw, param_idx, &value, NULL);
118 if (err) {
119 dev_err(dev, "Failed to read PTP clock index parameter, err %d aq_err %s\n",
120 err, ice_aq_str(hw->adminq.sq_last_status));
121 return -1;
122 }
123
124 /* The PTP clock index is an integer, and will be between 0 and
125 * INT_MAX. The highest bit of the driver shared parameter is used to
126 * indicate whether or not the currently stored clock index is valid.
127 */
128 if (!(value & PTP_SHARED_CLK_IDX_VALID))
129 return -1;
130
131 return value & ~PTP_SHARED_CLK_IDX_VALID;
132}
133
134/**
135 * ice_set_ptp_clock_index - Set the PTP clock index
136 * @pf: the PF pointer
137 *
138 * Set the PTP clock index for this device into the shared driver parameters,
139 * so that other PFs associated with this device can read it.
140 *
141 * If the PF is unable to store the clock index, it will log an error, but
142 * will continue operating PTP.
143 */
144static void ice_set_ptp_clock_index(struct ice_pf *pf)
145{
146 struct device *dev = ice_pf_to_dev(pf);
147 enum ice_aqc_driver_params param_idx;
148 struct ice_hw *hw = &pf->hw;
149 u8 tmr_idx;
150 u32 value;
151 int err;
152
153 if (!pf->ptp.clock)
154 return;
155
156 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
157 if (!tmr_idx)
158 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
159 else
160 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
161
162 value = (u32)ptp_clock_index(pf->ptp.clock);
163 if (value > INT_MAX) {
164 dev_err(dev, "PTP Clock index is too large to store\n");
165 return;
166 }
167 value |= PTP_SHARED_CLK_IDX_VALID;
168
169 err = ice_aq_set_driver_param(hw, param_idx, value, NULL);
170 if (err) {
171 dev_err(dev, "Failed to set PTP clock index parameter, err %d aq_err %s\n",
172 err, ice_aq_str(hw->adminq.sq_last_status));
173 }
174}
175
176/**
177 * ice_clear_ptp_clock_index - Clear the PTP clock index
178 * @pf: the PF pointer
179 *
180 * Clear the PTP clock index for this device. Must be called when
181 * unregistering the PTP clock, in order to ensure other PFs stop reporting
182 * a clock object that no longer exists.
183 */
184static void ice_clear_ptp_clock_index(struct ice_pf *pf)
185{
186 struct device *dev = ice_pf_to_dev(pf);
187 enum ice_aqc_driver_params param_idx;
188 struct ice_hw *hw = &pf->hw;
189 u8 tmr_idx;
190 int err;
191
192 /* Do not clear the index if we don't own the timer */
193 if (!hw->func_caps.ts_func_info.src_tmr_owned)
194 return;
195
196 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
197 if (!tmr_idx)
198 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
199 else
200 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
201
202 err = ice_aq_set_driver_param(hw, param_idx, 0, NULL);
203 if (err) {
204 dev_dbg(dev, "Failed to clear PTP clock index parameter, err %d aq_err %s\n",
205 err, ice_aq_str(hw->adminq.sq_last_status));
206 }
207}
208
209/**
210 * ice_ptp_read_src_clk_reg - Read the source clock register
211 * @pf: Board private structure
212 * @sts: Optional parameter for holding a pair of system timestamps from
213 * the system clock. Will be ignored if NULL is given.
214 */
215static u64
216ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
217{
218 struct ice_hw *hw = &pf->hw;
219 u32 hi, lo, lo2;
220 u8 tmr_idx;
221
222 tmr_idx = ice_get_ptp_src_clock_index(hw);
223 /* Read the system timestamp pre PHC read */
224 ptp_read_system_prets(sts);
225
226 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
227
228 /* Read the system timestamp post PHC read */
229 ptp_read_system_postts(sts);
230
231 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
232 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
233
234 if (lo2 < lo) {
235 /* if TIME_L rolled over read TIME_L again and update
236 * system timestamps
237 */
238 ptp_read_system_prets(sts);
239 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
240 ptp_read_system_postts(sts);
241 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
242 }
243
244 return ((u64)hi << 32) | lo;
245}
246
247/**
248 * ice_ptp_update_cached_phctime - Update the cached PHC time values
249 * @pf: Board specific private structure
250 *
251 * This function updates the system time values which are cached in the PF
252 * structure and the Rx rings.
253 *
254 * This function must be called periodically to ensure that the cached value
255 * is never more than 2 seconds old. It must also be called whenever the PHC
256 * time has been changed.
257 */
258static void ice_ptp_update_cached_phctime(struct ice_pf *pf)
259{
260 u64 systime;
261 int i;
262
263 /* Read the current PHC time */
264 systime = ice_ptp_read_src_clk_reg(pf, NULL);
265
266 /* Update the cached PHC time stored in the PF structure */
267 WRITE_ONCE(pf->ptp.cached_phc_time, systime);
268
269 ice_for_each_vsi(pf, i) {
270 struct ice_vsi *vsi = pf->vsi[i];
271 int j;
272
273 if (!vsi)
274 continue;
275
276 if (vsi->type != ICE_VSI_PF)
277 continue;
278
279 ice_for_each_rxq(vsi, j) {
280 if (!vsi->rx_rings[j])
281 continue;
282 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
283 }
284 }
285}
286
287/**
288 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
289 * @cached_phc_time: recently cached copy of PHC time
290 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
291 *
292 * Hardware captures timestamps which contain only 32 bits of nominal
293 * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
294 * Note that the captured timestamp values may be 40 bits, but the lower
295 * 8 bits are sub-nanoseconds and generally discarded.
296 *
297 * Extend the 32bit nanosecond timestamp using the following algorithm and
298 * assumptions:
299 *
300 * 1) have a recently cached copy of the PHC time
301 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
302 * seconds) before or after the PHC time was captured.
303 * 3) calculate the delta between the cached time and the timestamp
304 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
305 * captured after the PHC time. In this case, the full timestamp is just
306 * the cached PHC time plus the delta.
307 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
308 * timestamp was captured *before* the PHC time, i.e. because the PHC
309 * cache was updated after the timestamp was captured by hardware. In this
310 * case, the full timestamp is the cached time minus the inverse delta.
311 *
312 * This algorithm works even if the PHC time was updated after a Tx timestamp
313 * was requested, but before the Tx timestamp event was reported from
314 * hardware.
315 *
316 * This calculation primarily relies on keeping the cached PHC time up to
317 * date. If the timestamp was captured more than 2^31 nanoseconds after the
318 * PHC time, it is possible that the lower 32bits of PHC time have
319 * overflowed more than once, and we might generate an incorrect timestamp.
320 *
321 * This is prevented by (a) periodically updating the cached PHC time once
322 * a second, and (b) discarding any Tx timestamp packet if it has waited for
323 * a timestamp for more than one second.
324 */
325static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
326{
327 u32 delta, phc_time_lo;
328 u64 ns;
329
330 /* Extract the lower 32 bits of the PHC time */
331 phc_time_lo = (u32)cached_phc_time;
332
333 /* Calculate the delta between the lower 32bits of the cached PHC
334 * time and the in_tstamp value
335 */
336 delta = (in_tstamp - phc_time_lo);
337
338 /* Do not assume that the in_tstamp is always more recent than the
339 * cached PHC time. If the delta is large, it indicates that the
340 * in_tstamp was taken in the past, and should be converted
341 * forward.
342 */
343 if (delta > (U32_MAX / 2)) {
344 /* reverse the delta calculation here */
345 delta = (phc_time_lo - in_tstamp);
346 ns = cached_phc_time - delta;
347 } else {
348 ns = cached_phc_time + delta;
349 }
350
351 return ns;
352}
353
354/**
355 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
356 * @pf: Board private structure
357 * @in_tstamp: Ingress/egress 40b timestamp value
358 *
359 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
360 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
361 *
362 * *--------------------------------------------------------------*
363 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
364 * *--------------------------------------------------------------*
365 *
366 * The low bit is an indicator of whether the timestamp is valid. The next
367 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
368 * and the remaining 32 bits are the lower 32 bits of the PHC timer.
369 *
370 * It is assumed that the caller verifies the timestamp is valid prior to
371 * calling this function.
372 *
373 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
374 * time stored in the device private PTP structure as the basis for timestamp
375 * extension.
376 *
377 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
378 * algorithm.
379 */
380static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
381{
382 const u64 mask = GENMASK_ULL(31, 0);
383
384 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
385 (in_tstamp >> 8) & mask);
386}
387
388/**
389 * ice_ptp_read_time - Read the time from the device
390 * @pf: Board private structure
391 * @ts: timespec structure to hold the current time value
392 * @sts: Optional parameter for holding a pair of system timestamps from
393 * the system clock. Will be ignored if NULL is given.
394 *
395 * This function reads the source clock registers and stores them in a timespec.
396 * However, since the registers are 64 bits of nanoseconds, we must convert the
397 * result to a timespec before we can return.
398 */
399static void
400ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
401 struct ptp_system_timestamp *sts)
402{
403 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
404
405 *ts = ns_to_timespec64(time_ns);
406}
407
408/**
409 * ice_ptp_write_init - Set PHC time to provided value
410 * @pf: Board private structure
411 * @ts: timespec structure that holds the new time value
412 *
413 * Set the PHC time to the specified time provided in the timespec.
414 */
415static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
416{
417 u64 ns = timespec64_to_ns(ts);
418 struct ice_hw *hw = &pf->hw;
419
420 return ice_ptp_init_time(hw, ns);
421}
422
423/**
424 * ice_ptp_write_adj - Adjust PHC clock time atomically
425 * @pf: Board private structure
426 * @adj: Adjustment in nanoseconds
427 *
428 * Perform an atomic adjustment of the PHC time by the specified number of
429 * nanoseconds.
430 */
431static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
432{
433 struct ice_hw *hw = &pf->hw;
434
435 return ice_ptp_adj_clock(hw, adj);
436}
437
438/**
439 * ice_ptp_adjfine - Adjust clock increment rate
440 * @info: the driver's PTP info structure
441 * @scaled_ppm: Parts per million with 16-bit fractional field
442 *
443 * Adjust the frequency of the clock by the indicated scaled ppm from the
444 * base frequency.
445 */
446static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
447{
448 struct ice_pf *pf = ptp_info_to_pf(info);
449 u64 freq, divisor = 1000000ULL;
450 struct ice_hw *hw = &pf->hw;
451 s64 incval, diff;
452 int neg_adj = 0;
453 int err;
454
455 incval = ICE_PTP_NOMINAL_INCVAL_E810;
456
457 if (scaled_ppm < 0) {
458 neg_adj = 1;
459 scaled_ppm = -scaled_ppm;
460 }
461
462 while ((u64)scaled_ppm > div_u64(U64_MAX, incval)) {
463 /* handle overflow by scaling down the scaled_ppm and
464 * the divisor, losing some precision
465 */
466 scaled_ppm >>= 2;
467 divisor >>= 2;
468 }
469
470 freq = (incval * (u64)scaled_ppm) >> 16;
471 diff = div_u64(freq, divisor);
472
473 if (neg_adj)
474 incval -= diff;
475 else
476 incval += diff;
477
478 err = ice_ptp_write_incval_locked(hw, incval);
479 if (err) {
480 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
481 err);
482 return -EIO;
483 }
484
485 return 0;
486}
487
488/**
489 * ice_ptp_extts_work - Workqueue task function
490 * @work: external timestamp work structure
491 *
492 * Service for PTP external clock event
493 */
494static void ice_ptp_extts_work(struct kthread_work *work)
495{
496 struct ice_ptp *ptp = container_of(work, struct ice_ptp, extts_work);
497 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
498 struct ptp_clock_event event;
499 struct ice_hw *hw = &pf->hw;
500 u8 chan, tmr_idx;
501 u32 hi, lo;
502
503 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
504 /* Event time is captured by one of the two matched registers
505 * GLTSYN_EVNT_L: 32 LSB of sampled time event
506 * GLTSYN_EVNT_H: 32 MSB of sampled time event
507 * Event is defined in GLTSYN_EVNT_0 register
508 */
509 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
510 /* Check if channel is enabled */
511 if (pf->ptp.ext_ts_irq & (1 << chan)) {
512 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
513 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
514 event.timestamp = (((u64)hi) << 32) | lo;
515 event.type = PTP_CLOCK_EXTTS;
516 event.index = chan;
517
518 /* Fire event */
519 ptp_clock_event(pf->ptp.clock, &event);
520 pf->ptp.ext_ts_irq &= ~(1 << chan);
521 }
522 }
523}
524
525/**
526 * ice_ptp_cfg_extts - Configure EXTTS pin and channel
527 * @pf: Board private structure
528 * @ena: true to enable; false to disable
529 * @chan: GPIO channel (0-3)
530 * @gpio_pin: GPIO pin
531 * @extts_flags: request flags from the ptp_extts_request.flags
532 */
533static int
534ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
535 unsigned int extts_flags)
536{
537 u32 func, aux_reg, gpio_reg, irq_reg;
538 struct ice_hw *hw = &pf->hw;
539 u8 tmr_idx;
540
541 if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
542 return -EINVAL;
543
544 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
545
546 irq_reg = rd32(hw, PFINT_OICR_ENA);
547
548 if (ena) {
549 /* Enable the interrupt */
550 irq_reg |= PFINT_OICR_TSYN_EVNT_M;
551 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
552
553#define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0)
554#define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
555
556 /* set event level to requested edge */
557 if (extts_flags & PTP_FALLING_EDGE)
558 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
559 if (extts_flags & PTP_RISING_EDGE)
560 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
561
562 /* Write GPIO CTL reg.
563 * 0x1 is input sampled by EVENT register(channel)
564 * + num_in_channels * tmr_idx
565 */
566 func = 1 + chan + (tmr_idx * 3);
567 gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
568 GLGEN_GPIO_CTL_PIN_FUNC_M);
569 pf->ptp.ext_ts_chan |= (1 << chan);
570 } else {
571 /* clear the values we set to reset defaults */
572 aux_reg = 0;
573 gpio_reg = 0;
574 pf->ptp.ext_ts_chan &= ~(1 << chan);
575 if (!pf->ptp.ext_ts_chan)
576 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
577 }
578
579 wr32(hw, PFINT_OICR_ENA, irq_reg);
580 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
581 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
582
583 return 0;
584}
585
586/**
587 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
588 * @pf: Board private structure
589 * @chan: GPIO channel (0-3)
590 * @config: desired periodic clk configuration. NULL will disable channel
591 * @store: If set to true the values will be stored
592 *
593 * Configure the internal clock generator modules to generate the clock wave of
594 * specified period.
595 */
596static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
597 struct ice_perout_channel *config, bool store)
598{
599 u64 current_time, period, start_time, phase;
600 struct ice_hw *hw = &pf->hw;
601 u32 func, val, gpio_pin;
602 u8 tmr_idx;
603
604 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
605
606 /* 0. Reset mode & out_en in AUX_OUT */
607 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
608
609 /* If we're disabling the output, clear out CLKO and TGT and keep
610 * output level low
611 */
612 if (!config || !config->ena) {
613 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
614 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
615 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
616
617 val = GLGEN_GPIO_CTL_PIN_DIR_M;
618 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
619 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
620
621 /* Store the value if requested */
622 if (store)
623 memset(&pf->ptp.perout_channels[chan], 0,
624 sizeof(struct ice_perout_channel));
625
626 return 0;
627 }
628 period = config->period;
629 start_time = config->start_time;
630 div64_u64_rem(start_time, period, &phase);
631 gpio_pin = config->gpio_pin;
632
633 /* 1. Write clkout with half of required period value */
634 if (period & 0x1) {
635 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
636 goto err;
637 }
638
639 period >>= 1;
640
641 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick
642 */
643#define MIN_PULSE 3
644 if (period <= MIN_PULSE || period > U32_MAX) {
645 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
646 MIN_PULSE * 2);
647 goto err;
648 }
649
650 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
651
652 /* Allow time for programming before start_time is hit */
653 current_time = ice_ptp_read_src_clk_reg(pf, NULL);
654
655 /* if start time is in the past start the timer at the nearest second
656 * maintaining phase
657 */
658 if (start_time < current_time)
659 start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
660 NSEC_PER_SEC) * NSEC_PER_SEC + phase;
661
662 start_time -= E810_OUT_PROP_DELAY_NS;
663
664 /* 2. Write TARGET time */
665 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
666 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
667
668 /* 3. Write AUX_OUT register */
669 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
670 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
671
672 /* 4. write GPIO CTL reg */
673 func = 8 + chan + (tmr_idx * 4);
674 val = GLGEN_GPIO_CTL_PIN_DIR_M |
675 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M);
676 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
677
678 /* Store the value if requested */
679 if (store) {
680 memcpy(&pf->ptp.perout_channels[chan], config,
681 sizeof(struct ice_perout_channel));
682 pf->ptp.perout_channels[chan].start_time = phase;
683 }
684
685 return 0;
686err:
687 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
688 return -EFAULT;
689}
690
691/**
692 * ice_ptp_disable_all_clkout - Disable all currently configured outputs
693 * @pf: pointer to the PF structure
694 *
695 * Disable all currently configured clock outputs. This is necessary before
696 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
697 * re-enable the clocks again.
698 */
699static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
700{
701 uint i;
702
703 for (i = 0; i < pf->ptp.info.n_per_out; i++)
704 if (pf->ptp.perout_channels[i].ena)
705 ice_ptp_cfg_clkout(pf, i, NULL, false);
706}
707
708/**
709 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
710 * @pf: pointer to the PF structure
711 *
712 * Enable all currently configured clock outputs. Use this after
713 * ice_ptp_disable_all_clkout to reconfigure the output signals according to
714 * their configuration.
715 */
716static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
717{
718 uint i;
719
720 for (i = 0; i < pf->ptp.info.n_per_out; i++)
721 if (pf->ptp.perout_channels[i].ena)
722 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
723 false);
724}
725
726/**
727 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
728 * @info: the driver's PTP info structure
729 * @rq: The requested feature to change
730 * @on: Enable/disable flag
731 */
732static int
733ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
734 struct ptp_clock_request *rq, int on)
735{
736 struct ice_pf *pf = ptp_info_to_pf(info);
737 struct ice_perout_channel clk_cfg = {0};
738 unsigned int chan;
739 u32 gpio_pin;
740 int err;
741
742 switch (rq->type) {
743 case PTP_CLK_REQ_PEROUT:
744 chan = rq->perout.index;
745 if (chan == PPS_CLK_GEN_CHAN)
746 clk_cfg.gpio_pin = PPS_PIN_INDEX;
747 else
748 clk_cfg.gpio_pin = chan;
749
750 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
751 rq->perout.period.nsec);
752 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
753 rq->perout.start.nsec);
754 clk_cfg.ena = !!on;
755
756 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
757 break;
758 case PTP_CLK_REQ_EXTTS:
759 chan = rq->extts.index;
760 gpio_pin = chan;
761
762 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
763 rq->extts.flags);
764 break;
765 default:
766 return -EOPNOTSUPP;
767 }
768
769 return err;
770}
771
772/**
773 * ice_ptp_gettimex64 - Get the time of the clock
774 * @info: the driver's PTP info structure
775 * @ts: timespec64 structure to hold the current time value
776 * @sts: Optional parameter for holding a pair of system timestamps from
777 * the system clock. Will be ignored if NULL is given.
778 *
779 * Read the device clock and return the correct value on ns, after converting it
780 * into a timespec struct.
781 */
782static int
783ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
784 struct ptp_system_timestamp *sts)
785{
786 struct ice_pf *pf = ptp_info_to_pf(info);
787 struct ice_hw *hw = &pf->hw;
788
789 if (!ice_ptp_lock(hw)) {
790 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
791 return -EBUSY;
792 }
793
794 ice_ptp_read_time(pf, ts, sts);
795 ice_ptp_unlock(hw);
796
797 return 0;
798}
799
800/**
801 * ice_ptp_settime64 - Set the time of the clock
802 * @info: the driver's PTP info structure
803 * @ts: timespec64 structure that holds the new time value
804 *
805 * Set the device clock to the user input value. The conversion from timespec
806 * to ns happens in the write function.
807 */
808static int
809ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
810{
811 struct ice_pf *pf = ptp_info_to_pf(info);
812 struct timespec64 ts64 = *ts;
813 struct ice_hw *hw = &pf->hw;
814 int err;
815
816 if (!ice_ptp_lock(hw)) {
817 err = -EBUSY;
818 goto exit;
819 }
820
821 /* Disable periodic outputs */
822 ice_ptp_disable_all_clkout(pf);
823
824 err = ice_ptp_write_init(pf, &ts64);
825 ice_ptp_unlock(hw);
826
827 if (!err)
828 ice_ptp_update_cached_phctime(pf);
829
830 /* Reenable periodic outputs */
831 ice_ptp_enable_all_clkout(pf);
832exit:
833 if (err) {
834 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
835 return err;
836 }
837
838 return 0;
839}
840
841/**
842 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
843 * @info: the driver's PTP info structure
844 * @delta: Offset in nanoseconds to adjust the time by
845 */
846static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
847{
848 struct timespec64 now, then;
849
850 then = ns_to_timespec64(delta);
851 ice_ptp_gettimex64(info, &now, NULL);
852 now = timespec64_add(now, then);
853
854 return ice_ptp_settime64(info, (const struct timespec64 *)&now);
855}
856
857/**
858 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
859 * @info: the driver's PTP info structure
860 * @delta: Offset in nanoseconds to adjust the time by
861 */
862static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
863{
864 struct ice_pf *pf = ptp_info_to_pf(info);
865 struct ice_hw *hw = &pf->hw;
866 struct device *dev;
867 int err;
868
869 dev = ice_pf_to_dev(pf);
870
871 /* Hardware only supports atomic adjustments using signed 32-bit
872 * integers. For any adjustment outside this range, perform
873 * a non-atomic get->adjust->set flow.
874 */
875 if (delta > S32_MAX || delta < S32_MIN) {
876 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
877 return ice_ptp_adjtime_nonatomic(info, delta);
878 }
879
880 if (!ice_ptp_lock(hw)) {
881 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
882 return -EBUSY;
883 }
884
885 /* Disable periodic outputs */
886 ice_ptp_disable_all_clkout(pf);
887
888 err = ice_ptp_write_adj(pf, delta);
889
890 /* Reenable periodic outputs */
891 ice_ptp_enable_all_clkout(pf);
892
893 ice_ptp_unlock(hw);
894
895 if (err) {
896 dev_err(dev, "PTP failed to adjust time, err %d\n", err);
897 return err;
898 }
899
900 ice_ptp_update_cached_phctime(pf);
901
902 return 0;
903}
904
905/**
906 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
907 * @pf: Board private structure
908 * @ifr: ioctl data
909 *
910 * Copy the timestamping config to user buffer
911 */
912int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
913{
914 struct hwtstamp_config *config;
915
916 if (!test_bit(ICE_FLAG_PTP, pf->flags))
917 return -EIO;
918
919 config = &pf->ptp.tstamp_config;
920
921 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
922 -EFAULT : 0;
923}
924
925/**
926 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
927 * @pf: Board private structure
928 * @config: hwtstamp settings requested or saved
929 */
930static int
931ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
932{
933 /* Reserved for future extensions. */
934 if (config->flags)
935 return -EINVAL;
936
937 switch (config->tx_type) {
938 case HWTSTAMP_TX_OFF:
939 ice_set_tx_tstamp(pf, false);
940 break;
941 case HWTSTAMP_TX_ON:
942 ice_set_tx_tstamp(pf, true);
943 break;
944 default:
945 return -ERANGE;
946 }
947
948 switch (config->rx_filter) {
949 case HWTSTAMP_FILTER_NONE:
950 ice_set_rx_tstamp(pf, false);
951 break;
952 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
953 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
954 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
955 case HWTSTAMP_FILTER_PTP_V2_EVENT:
956 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
957 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
958 case HWTSTAMP_FILTER_PTP_V2_SYNC:
959 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
960 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
961 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
962 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
963 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
964 case HWTSTAMP_FILTER_NTP_ALL:
965 case HWTSTAMP_FILTER_ALL:
966 config->rx_filter = HWTSTAMP_FILTER_ALL;
967 ice_set_rx_tstamp(pf, true);
968 break;
969 default:
970 return -ERANGE;
971 }
972
973 return 0;
974}
975
976/**
977 * ice_ptp_set_ts_config - ioctl interface to control the timestamping
978 * @pf: Board private structure
979 * @ifr: ioctl data
980 *
981 * Get the user config and store it
982 */
983int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
984{
985 struct hwtstamp_config config;
986 int err;
987
988 if (!test_bit(ICE_FLAG_PTP, pf->flags))
989 return -EAGAIN;
990
991 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
992 return -EFAULT;
993
994 err = ice_ptp_set_timestamp_mode(pf, &config);
995 if (err)
996 return err;
997
998 /* Save these settings for future reference */
999 pf->ptp.tstamp_config = config;
1000
1001 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1002 -EFAULT : 0;
1003}
1004
1005/**
1006 * ice_ptp_rx_hwtstamp - Check for an Rx timestamp
1007 * @rx_ring: Ring to get the VSI info
1008 * @rx_desc: Receive descriptor
1009 * @skb: Particular skb to send timestamp with
1010 *
1011 * The driver receives a notification in the receive descriptor with timestamp.
1012 * The timestamp is in ns, so we must convert the result first.
1013 */
1014void
1015ice_ptp_rx_hwtstamp(struct ice_ring *rx_ring,
1016 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb)
1017{
1018 u32 ts_high;
1019 u64 ts_ns;
1020
1021 /* Populate timesync data into skb */
1022 if (rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID) {
1023 struct skb_shared_hwtstamps *hwtstamps;
1024
1025 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific
1026 * cached PHC value, rather than accessing the PF. This also
1027 * allows us to simply pass the upper 32bits of nanoseconds
1028 * directly. Calling ice_ptp_extend_40b_ts is unnecessary as
1029 * it would just discard these bits itself.
1030 */
1031 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
1032 ts_ns = ice_ptp_extend_32b_ts(rx_ring->cached_phctime, ts_high);
1033
1034 hwtstamps = skb_hwtstamps(skb);
1035 memset(hwtstamps, 0, sizeof(*hwtstamps));
1036 hwtstamps->hwtstamp = ns_to_ktime(ts_ns);
1037 }
1038}
1039
1040/**
1041 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
1042 * @info: PTP clock capabilities
1043 */
1044static void ice_ptp_setup_pins_e810(struct ptp_clock_info *info)
1045{
1046 info->n_per_out = E810_N_PER_OUT;
1047 info->n_ext_ts = E810_N_EXT_TS;
1048}
1049
1050/**
1051 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
1052 * @pf: Board private structure
1053 * @info: PTP info to fill
1054 *
1055 * Assign functions to the PTP capabiltiies structure for E810 devices.
1056 * Functions which operate across all device families should be set directly
1057 * in ice_ptp_set_caps. Only add functions here which are distinct for e810
1058 * devices.
1059 */
1060static void
1061ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
1062{
1063 info->enable = ice_ptp_gpio_enable_e810;
1064
1065 ice_ptp_setup_pins_e810(info);
1066}
1067
1068/**
1069 * ice_ptp_set_caps - Set PTP capabilities
1070 * @pf: Board private structure
1071 */
1072static void ice_ptp_set_caps(struct ice_pf *pf)
1073{
1074 struct ptp_clock_info *info = &pf->ptp.info;
1075 struct device *dev = ice_pf_to_dev(pf);
1076
1077 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
1078 dev_driver_string(dev), dev_name(dev));
1079 info->owner = THIS_MODULE;
1080 info->max_adj = 999999999;
1081 info->adjtime = ice_ptp_adjtime;
1082 info->adjfine = ice_ptp_adjfine;
1083 info->gettimex64 = ice_ptp_gettimex64;
1084 info->settime64 = ice_ptp_settime64;
1085
1086 ice_ptp_set_funcs_e810(pf, info);
1087}
1088
1089/**
1090 * ice_ptp_create_clock - Create PTP clock device for userspace
1091 * @pf: Board private structure
1092 *
1093 * This function creates a new PTP clock device. It only creates one if we
1094 * don't already have one. Will return error if it can't create one, but success
1095 * if we already have a device. Should be used by ice_ptp_init to create clock
1096 * initially, and prevent global resets from creating new clock devices.
1097 */
1098static long ice_ptp_create_clock(struct ice_pf *pf)
1099{
1100 struct ptp_clock_info *info;
1101 struct ptp_clock *clock;
1102 struct device *dev;
1103
1104 /* No need to create a clock device if we already have one */
1105 if (pf->ptp.clock)
1106 return 0;
1107
1108 ice_ptp_set_caps(pf);
1109
1110 info = &pf->ptp.info;
1111 dev = ice_pf_to_dev(pf);
1112
1113 /* Allocate memory for kernel pins interface */
1114 if (info->n_pins) {
1115 info->pin_config = devm_kcalloc(dev, info->n_pins,
1116 sizeof(*info->pin_config),
1117 GFP_KERNEL);
1118 if (!info->pin_config) {
1119 info->n_pins = 0;
1120 return -ENOMEM;
1121 }
1122 }
1123
1124 /* Attempt to register the clock before enabling the hardware. */
1125 clock = ptp_clock_register(info, dev);
1126 if (IS_ERR(clock))
1127 return PTR_ERR(clock);
1128
1129 pf->ptp.clock = clock;
1130
1131 return 0;
1132}
1133
1134/**
1135 * ice_ptp_tx_tstamp_work - Process Tx timestamps for a port
1136 * @work: pointer to the kthread_work struct
1137 *
1138 * Process timestamps captured by the PHY associated with this port. To do
1139 * this, loop over each index with a waiting skb.
1140 *
1141 * If a given index has a valid timestamp, perform the following steps:
1142 *
1143 * 1) copy the timestamp out of the PHY register
1144 * 4) clear the timestamp valid bit in the PHY register
1145 * 5) unlock the index by clearing the associated in_use bit.
1146 * 2) extend the 40b timestamp value to get a 64bit timestamp
1147 * 3) send that timestamp to the stack
1148 *
1149 * After looping, if we still have waiting SKBs, then re-queue the work. This
1150 * may cause us effectively poll even when not strictly necessary. We do this
1151 * because it's possible a new timestamp was requested around the same time as
1152 * the interrupt. In some cases hardware might not interrupt us again when the
1153 * timestamp is captured.
1154 *
1155 * Note that we only take the tracking lock when clearing the bit and when
1156 * checking if we need to re-queue this task. The only place where bits can be
1157 * set is the hard xmit routine where an SKB has a request flag set. The only
1158 * places where we clear bits are this work function, or the periodic cleanup
1159 * thread. If the cleanup thread clears a bit we're processing we catch it
1160 * when we lock to clear the bit and then grab the SKB pointer. If a Tx thread
1161 * starts a new timestamp, we might not begin processing it right away but we
1162 * will notice it at the end when we re-queue the work item. If a Tx thread
1163 * starts a new timestamp just after this function exits without re-queuing,
1164 * the interrupt when the timestamp finishes should trigger. Avoiding holding
1165 * the lock for the entire function is important in order to ensure that Tx
1166 * threads do not get blocked while waiting for the lock.
1167 */
1168static void ice_ptp_tx_tstamp_work(struct kthread_work *work)
1169{
1170 struct ice_ptp_port *ptp_port;
1171 struct ice_ptp_tx *tx;
1172 struct ice_pf *pf;
1173 struct ice_hw *hw;
1174 u8 idx;
1175
1176 tx = container_of(work, struct ice_ptp_tx, work);
1177 if (!tx->init)
1178 return;
1179
1180 ptp_port = container_of(tx, struct ice_ptp_port, tx);
1181 pf = ptp_port_to_pf(ptp_port);
1182 hw = &pf->hw;
1183
1184 for_each_set_bit(idx, tx->in_use, tx->len) {
1185 struct skb_shared_hwtstamps shhwtstamps = {};
1186 u8 phy_idx = idx + tx->quad_offset;
1187 u64 raw_tstamp, tstamp;
1188 struct sk_buff *skb;
1189 int err;
1190
1191 err = ice_read_phy_tstamp(hw, tx->quad, phy_idx,
1192 &raw_tstamp);
1193 if (err)
1194 continue;
1195
1196 /* Check if the timestamp is valid */
1197 if (!(raw_tstamp & ICE_PTP_TS_VALID))
1198 continue;
1199
1200 /* clear the timestamp register, so that it won't show valid
1201 * again when re-used.
1202 */
1203 ice_clear_phy_tstamp(hw, tx->quad, phy_idx);
1204
1205 /* The timestamp is valid, so we'll go ahead and clear this
1206 * index and then send the timestamp up to the stack.
1207 */
1208 spin_lock(&tx->lock);
1209 clear_bit(idx, tx->in_use);
1210 skb = tx->tstamps[idx].skb;
1211 tx->tstamps[idx].skb = NULL;
1212 spin_unlock(&tx->lock);
1213
1214 /* it's (unlikely but) possible we raced with the cleanup
1215 * thread for discarding old timestamp requests.
1216 */
1217 if (!skb)
1218 continue;
1219
1220 /* Extend the timestamp using cached PHC time */
1221 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
1222 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
1223
1224 skb_tstamp_tx(skb, &shhwtstamps);
1225 dev_kfree_skb_any(skb);
1226 }
1227
1228 /* Check if we still have work to do. If so, re-queue this task to
1229 * poll for remaining timestamps.
1230 */
1231 spin_lock(&tx->lock);
1232 if (!bitmap_empty(tx->in_use, tx->len))
1233 kthread_queue_work(pf->ptp.kworker, &tx->work);
1234 spin_unlock(&tx->lock);
1235}
1236
1237/**
1238 * ice_ptp_request_ts - Request an available Tx timestamp index
1239 * @tx: the PTP Tx timestamp tracker to request from
1240 * @skb: the SKB to associate with this timestamp request
1241 */
1242s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
1243{
1244 u8 idx;
1245
1246 /* Check if this tracker is initialized */
1247 if (!tx->init)
1248 return -1;
1249
1250 spin_lock(&tx->lock);
1251 /* Find and set the first available index */
1252 idx = find_first_zero_bit(tx->in_use, tx->len);
1253 if (idx < tx->len) {
1254 /* We got a valid index that no other thread could have set. Store
1255 * a reference to the skb and the start time to allow discarding old
1256 * requests.
1257 */
1258 set_bit(idx, tx->in_use);
1259 tx->tstamps[idx].start = jiffies;
1260 tx->tstamps[idx].skb = skb_get(skb);
1261 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1262 }
1263
1264 spin_unlock(&tx->lock);
1265
1266 /* return the appropriate PHY timestamp register index, -1 if no
1267 * indexes were available.
1268 */
1269 if (idx >= tx->len)
1270 return -1;
1271 else
1272 return idx + tx->quad_offset;
1273}
1274
1275/**
1276 * ice_ptp_process_ts - Spawn kthread work to handle timestamps
1277 * @pf: Board private structure
1278 *
1279 * Queue work required to process the PTP Tx timestamps outside of interrupt
1280 * context.
1281 */
1282void ice_ptp_process_ts(struct ice_pf *pf)
1283{
1284 if (pf->ptp.port.tx.init)
1285 kthread_queue_work(pf->ptp.kworker, &pf->ptp.port.tx.work);
1286}
1287
1288/**
1289 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
1290 * @tx: Tx tracking structure to initialize
1291 *
1292 * Assumes that the length has already been initialized. Do not call directly,
1293 * use the ice_ptp_init_tx_e822 or ice_ptp_init_tx_e810 instead.
1294 */
1295static int
1296ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
1297{
1298 tx->tstamps = kcalloc(tx->len, sizeof(*tx->tstamps), GFP_KERNEL);
1299 if (!tx->tstamps)
1300 return -ENOMEM;
1301
1302 tx->in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
1303 if (!tx->in_use) {
1304 kfree(tx->tstamps);
1305 tx->tstamps = NULL;
1306 return -ENOMEM;
1307 }
1308
1309 spin_lock_init(&tx->lock);
1310 kthread_init_work(&tx->work, ice_ptp_tx_tstamp_work);
1311
1312 tx->init = 1;
1313
1314 return 0;
1315}
1316
1317/**
1318 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
1319 * @pf: Board private structure
1320 * @tx: the tracker to flush
1321 */
1322static void
1323ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
1324{
1325 u8 idx;
1326
1327 for (idx = 0; idx < tx->len; idx++) {
1328 u8 phy_idx = idx + tx->quad_offset;
1329
1330 spin_lock(&tx->lock);
1331 if (tx->tstamps[idx].skb) {
1332 dev_kfree_skb_any(tx->tstamps[idx].skb);
1333 tx->tstamps[idx].skb = NULL;
1334 }
1335 clear_bit(idx, tx->in_use);
1336 spin_unlock(&tx->lock);
1337
1338 /* Clear any potential residual timestamp in the PHY block */
1339 if (!pf->hw.reset_ongoing)
1340 ice_clear_phy_tstamp(&pf->hw, tx->quad, phy_idx);
1341 }
1342}
1343
1344/**
1345 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
1346 * @pf: Board private structure
1347 * @tx: Tx tracking structure to release
1348 *
1349 * Free memory associated with the Tx timestamp tracker.
1350 */
1351static void
1352ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
1353{
1354 tx->init = 0;
1355
1356 kthread_cancel_work_sync(&tx->work);
1357
1358 ice_ptp_flush_tx_tracker(pf, tx);
1359
1360 kfree(tx->tstamps);
1361 tx->tstamps = NULL;
1362
1363 kfree(tx->in_use);
1364 tx->in_use = NULL;
1365
1366 tx->len = 0;
1367}
1368
1369/**
1370 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
1371 * @pf: Board private structure
1372 * @tx: the Tx tracking structure to initialize
1373 *
1374 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
1375 * port has its own block of timestamps, independent of the other ports.
1376 */
1377static int
1378ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
1379{
1380 tx->quad = pf->hw.port_info->lport;
1381 tx->quad_offset = 0;
1382 tx->len = INDEX_PER_QUAD;
1383
1384 return ice_ptp_alloc_tx_tracker(tx);
1385}
1386
1387/**
1388 * ice_ptp_tx_tstamp_cleanup - Cleanup old timestamp requests that got dropped
1389 * @tx: PTP Tx tracker to clean up
1390 *
1391 * Loop through the Tx timestamp requests and see if any of them have been
1392 * waiting for a long time. Discard any SKBs that have been waiting for more
1393 * than 2 seconds. This is long enough to be reasonably sure that the
1394 * timestamp will never be captured. This might happen if the packet gets
1395 * discarded before it reaches the PHY timestamping block.
1396 */
1397static void ice_ptp_tx_tstamp_cleanup(struct ice_ptp_tx *tx)
1398{
1399 u8 idx;
1400
1401 if (!tx->init)
1402 return;
1403
1404 for_each_set_bit(idx, tx->in_use, tx->len) {
1405 struct sk_buff *skb;
1406
1407 /* Check if this SKB has been waiting for too long */
1408 if (time_is_after_jiffies(tx->tstamps[idx].start + 2 * HZ))
1409 continue;
1410
1411 spin_lock(&tx->lock);
1412 skb = tx->tstamps[idx].skb;
1413 tx->tstamps[idx].skb = NULL;
1414 clear_bit(idx, tx->in_use);
1415 spin_unlock(&tx->lock);
1416
1417 /* Free the SKB after we've cleared the bit */
1418 dev_kfree_skb_any(skb);
1419 }
1420}
1421
1422static void ice_ptp_periodic_work(struct kthread_work *work)
1423{
1424 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
1425 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
1426
1427 if (!test_bit(ICE_FLAG_PTP, pf->flags))
1428 return;
1429
1430 ice_ptp_update_cached_phctime(pf);
1431
1432 ice_ptp_tx_tstamp_cleanup(&pf->ptp.port.tx);
1433
1434 /* Run twice a second */
1435 kthread_queue_delayed_work(ptp->kworker, &ptp->work,
1436 msecs_to_jiffies(500));
1437}
1438
1439/**
1440 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
1441 * @pf: Board private structure
1442 *
1443 * Setup and initialize a PTP clock device that represents the device hardware
1444 * clock. Save the clock index for other functions connected to the same
1445 * hardware resource.
1446 */
1447static int ice_ptp_init_owner(struct ice_pf *pf)
1448{
1449 struct device *dev = ice_pf_to_dev(pf);
1450 struct ice_hw *hw = &pf->hw;
1451 struct timespec64 ts;
1452 u8 src_idx;
1453 int err;
1454
1455 wr32(hw, GLTSYN_SYNC_DLAY, 0);
1456
1457 /* Clear some HW residue and enable source clock */
1458 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1459
1460 /* Enable source clocks */
1461 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
1462
1463 /* Enable PHY time sync */
1464 err = ice_ptp_init_phy_e810(hw);
1465 if (err)
1466 goto err_exit;
1467
1468 /* Clear event status indications for auxiliary pins */
1469 (void)rd32(hw, GLTSYN_STAT(src_idx));
1470
1471 /* Acquire the global hardware lock */
1472 if (!ice_ptp_lock(hw)) {
1473 err = -EBUSY;
1474 goto err_exit;
1475 }
1476
1477 /* Write the increment time value to PHY and LAN */
1478 err = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810);
1479 if (err) {
1480 ice_ptp_unlock(hw);
1481 goto err_exit;
1482 }
1483
1484 ts = ktime_to_timespec64(ktime_get_real());
1485 /* Write the initial Time value to PHY and LAN */
1486 err = ice_ptp_write_init(pf, &ts);
1487 if (err) {
1488 ice_ptp_unlock(hw);
1489 goto err_exit;
1490 }
1491
1492 /* Release the global hardware lock */
1493 ice_ptp_unlock(hw);
1494
1495 /* Ensure we have a clock device */
1496 err = ice_ptp_create_clock(pf);
1497 if (err)
1498 goto err_clk;
1499
1500 /* Store the PTP clock index for other PFs */
1501 ice_set_ptp_clock_index(pf);
1502
1503 return 0;
1504
1505err_clk:
1506 pf->ptp.clock = NULL;
1507err_exit:
1508 dev_err(dev, "PTP failed to register clock, err %d\n", err);
1509
1510 return err;
1511}
1512
1513/**
1514 * ice_ptp_init - Initialize the PTP support after device probe or reset
1515 * @pf: Board private structure
1516 *
1517 * This function sets device up for PTP support. The first time it is run, it
1518 * will create a clock device. It does not create a clock device if one
1519 * already exists. It also reconfigures the device after a reset.
1520 */
1521void ice_ptp_init(struct ice_pf *pf)
1522{
1523 struct device *dev = ice_pf_to_dev(pf);
1524 struct kthread_worker *kworker;
1525 struct ice_hw *hw = &pf->hw;
1526 int err;
1527
1528 /* PTP is currently only supported on E810 devices */
1529 if (!ice_is_e810(hw))
1530 return;
1531
1532 /* Check if this PF owns the source timer */
1533 if (hw->func_caps.ts_func_info.src_tmr_owned) {
1534 err = ice_ptp_init_owner(pf);
1535 if (err)
1536 return;
1537 }
1538
1539 /* Disable timestamping for both Tx and Rx */
1540 ice_ptp_cfg_timestamp(pf, false);
1541
1542 /* Initialize the PTP port Tx timestamp tracker */
1543 ice_ptp_init_tx_e810(pf, &pf->ptp.port.tx);
1544
1545 /* Initialize work functions */
1546 kthread_init_delayed_work(&pf->ptp.work, ice_ptp_periodic_work);
1547 kthread_init_work(&pf->ptp.extts_work, ice_ptp_extts_work);
1548
1549 /* Allocate a kworker for handling work required for the ports
1550 * connected to the PTP hardware clock.
1551 */
1552 kworker = kthread_create_worker(0, "ice-ptp-%s", dev_name(dev));
1553 if (IS_ERR(kworker)) {
1554 err = PTR_ERR(kworker);
1555 goto err_kworker;
1556 }
1557 pf->ptp.kworker = kworker;
1558
1559 set_bit(ICE_FLAG_PTP, pf->flags);
1560
1561 /* Start periodic work going */
1562 kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work, 0);
1563
1564 dev_info(dev, "PTP init successful\n");
1565 return;
1566
1567err_kworker:
1568 /* If we registered a PTP clock, release it */
1569 if (pf->ptp.clock) {
1570 ptp_clock_unregister(pf->ptp.clock);
1571 pf->ptp.clock = NULL;
1572 }
1573 dev_err(dev, "PTP failed %d\n", err);
1574}
1575
1576/**
1577 * ice_ptp_release - Disable the driver/HW support and unregister the clock
1578 * @pf: Board private structure
1579 *
1580 * This function handles the cleanup work required from the initialization by
1581 * clearing out the important information and unregistering the clock
1582 */
1583void ice_ptp_release(struct ice_pf *pf)
1584{
1585 /* Disable timestamping for both Tx and Rx */
1586 ice_ptp_cfg_timestamp(pf, false);
1587
1588 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
1589
1590 clear_bit(ICE_FLAG_PTP, pf->flags);
1591
1592 kthread_cancel_delayed_work_sync(&pf->ptp.work);
1593
1594 if (pf->ptp.kworker) {
1595 kthread_destroy_worker(pf->ptp.kworker);
1596 pf->ptp.kworker = NULL;
1597 }
1598
1599 if (!pf->ptp.clock)
1600 return;
1601
1602 /* Disable periodic outputs */
1603 ice_ptp_disable_all_clkout(pf);
1604
1605 ice_clear_ptp_clock_index(pf);
1606 ptp_clock_unregister(pf->ptp.clock);
1607 pf->ptp.clock = NULL;
1608
1609 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");
1610}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (C) 2021, Intel Corporation. */
3
4#include "ice.h"
5#include "ice_lib.h"
6#include "ice_trace.h"
7
8#define E810_OUT_PROP_DELAY_NS 1
9
10#define UNKNOWN_INCVAL_E822 0x100000000ULL
11
12static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
13 /* name idx func chan */
14 { "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
15 { "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } },
16 { "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
17 { "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } },
18 { "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
19};
20
21/**
22 * ice_get_sma_config_e810t
23 * @hw: pointer to the hw struct
24 * @ptp_pins: pointer to the ptp_pin_desc struture
25 *
26 * Read the configuration of the SMA control logic and put it into the
27 * ptp_pin_desc structure
28 */
29static int
30ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
31{
32 u8 data, i;
33 int status;
34
35 /* Read initial pin state */
36 status = ice_read_sma_ctrl_e810t(hw, &data);
37 if (status)
38 return status;
39
40 /* initialize with defaults */
41 for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
42 snprintf(ptp_pins[i].name, sizeof(ptp_pins[i].name),
43 "%s", ice_pin_desc_e810t[i].name);
44 ptp_pins[i].index = ice_pin_desc_e810t[i].index;
45 ptp_pins[i].func = ice_pin_desc_e810t[i].func;
46 ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
47 }
48
49 /* Parse SMA1/UFL1 */
50 switch (data & ICE_SMA1_MASK_E810T) {
51 case ICE_SMA1_MASK_E810T:
52 default:
53 ptp_pins[SMA1].func = PTP_PF_NONE;
54 ptp_pins[UFL1].func = PTP_PF_NONE;
55 break;
56 case ICE_SMA1_DIR_EN_E810T:
57 ptp_pins[SMA1].func = PTP_PF_PEROUT;
58 ptp_pins[UFL1].func = PTP_PF_NONE;
59 break;
60 case ICE_SMA1_TX_EN_E810T:
61 ptp_pins[SMA1].func = PTP_PF_EXTTS;
62 ptp_pins[UFL1].func = PTP_PF_NONE;
63 break;
64 case 0:
65 ptp_pins[SMA1].func = PTP_PF_EXTTS;
66 ptp_pins[UFL1].func = PTP_PF_PEROUT;
67 break;
68 }
69
70 /* Parse SMA2/UFL2 */
71 switch (data & ICE_SMA2_MASK_E810T) {
72 case ICE_SMA2_MASK_E810T:
73 default:
74 ptp_pins[SMA2].func = PTP_PF_NONE;
75 ptp_pins[UFL2].func = PTP_PF_NONE;
76 break;
77 case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
78 ptp_pins[SMA2].func = PTP_PF_EXTTS;
79 ptp_pins[UFL2].func = PTP_PF_NONE;
80 break;
81 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
82 ptp_pins[SMA2].func = PTP_PF_PEROUT;
83 ptp_pins[UFL2].func = PTP_PF_NONE;
84 break;
85 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
86 ptp_pins[SMA2].func = PTP_PF_NONE;
87 ptp_pins[UFL2].func = PTP_PF_EXTTS;
88 break;
89 case ICE_SMA2_DIR_EN_E810T:
90 ptp_pins[SMA2].func = PTP_PF_PEROUT;
91 ptp_pins[UFL2].func = PTP_PF_EXTTS;
92 break;
93 }
94
95 return 0;
96}
97
98/**
99 * ice_ptp_set_sma_config_e810t
100 * @hw: pointer to the hw struct
101 * @ptp_pins: pointer to the ptp_pin_desc struture
102 *
103 * Set the configuration of the SMA control logic based on the configuration in
104 * num_pins parameter
105 */
106static int
107ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
108 const struct ptp_pin_desc *ptp_pins)
109{
110 int status;
111 u8 data;
112
113 /* SMA1 and UFL1 cannot be set to TX at the same time */
114 if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
115 ptp_pins[UFL1].func == PTP_PF_PEROUT)
116 return -EINVAL;
117
118 /* SMA2 and UFL2 cannot be set to RX at the same time */
119 if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
120 ptp_pins[UFL2].func == PTP_PF_EXTTS)
121 return -EINVAL;
122
123 /* Read initial pin state value */
124 status = ice_read_sma_ctrl_e810t(hw, &data);
125 if (status)
126 return status;
127
128 /* Set the right sate based on the desired configuration */
129 data &= ~ICE_SMA1_MASK_E810T;
130 if (ptp_pins[SMA1].func == PTP_PF_NONE &&
131 ptp_pins[UFL1].func == PTP_PF_NONE) {
132 dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
133 data |= ICE_SMA1_MASK_E810T;
134 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
135 ptp_pins[UFL1].func == PTP_PF_NONE) {
136 dev_info(ice_hw_to_dev(hw), "SMA1 RX");
137 data |= ICE_SMA1_TX_EN_E810T;
138 } else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
139 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
140 /* U.FL 1 TX will always enable SMA 1 RX */
141 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
142 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
143 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
144 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
145 } else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
146 ptp_pins[UFL1].func == PTP_PF_NONE) {
147 dev_info(ice_hw_to_dev(hw), "SMA1 TX");
148 data |= ICE_SMA1_DIR_EN_E810T;
149 }
150
151 data &= ~ICE_SMA2_MASK_E810T;
152 if (ptp_pins[SMA2].func == PTP_PF_NONE &&
153 ptp_pins[UFL2].func == PTP_PF_NONE) {
154 dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
155 data |= ICE_SMA2_MASK_E810T;
156 } else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
157 ptp_pins[UFL2].func == PTP_PF_NONE) {
158 dev_info(ice_hw_to_dev(hw), "SMA2 RX");
159 data |= (ICE_SMA2_TX_EN_E810T |
160 ICE_SMA2_UFL2_RX_DIS_E810T);
161 } else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
162 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
163 dev_info(ice_hw_to_dev(hw), "UFL2 RX");
164 data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
165 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
166 ptp_pins[UFL2].func == PTP_PF_NONE) {
167 dev_info(ice_hw_to_dev(hw), "SMA2 TX");
168 data |= (ICE_SMA2_DIR_EN_E810T |
169 ICE_SMA2_UFL2_RX_DIS_E810T);
170 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
171 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
172 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
173 data |= ICE_SMA2_DIR_EN_E810T;
174 }
175
176 return ice_write_sma_ctrl_e810t(hw, data);
177}
178
179/**
180 * ice_ptp_set_sma_e810t
181 * @info: the driver's PTP info structure
182 * @pin: pin index in kernel structure
183 * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
184 *
185 * Set the configuration of a single SMA pin
186 */
187static int
188ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
189 enum ptp_pin_function func)
190{
191 struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
192 struct ice_pf *pf = ptp_info_to_pf(info);
193 struct ice_hw *hw = &pf->hw;
194 int err;
195
196 if (pin < SMA1 || func > PTP_PF_PEROUT)
197 return -EOPNOTSUPP;
198
199 err = ice_get_sma_config_e810t(hw, ptp_pins);
200 if (err)
201 return err;
202
203 /* Disable the same function on the other pin sharing the channel */
204 if (pin == SMA1 && ptp_pins[UFL1].func == func)
205 ptp_pins[UFL1].func = PTP_PF_NONE;
206 if (pin == UFL1 && ptp_pins[SMA1].func == func)
207 ptp_pins[SMA1].func = PTP_PF_NONE;
208
209 if (pin == SMA2 && ptp_pins[UFL2].func == func)
210 ptp_pins[UFL2].func = PTP_PF_NONE;
211 if (pin == UFL2 && ptp_pins[SMA2].func == func)
212 ptp_pins[SMA2].func = PTP_PF_NONE;
213
214 /* Set up new pin function in the temp table */
215 ptp_pins[pin].func = func;
216
217 return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
218}
219
220/**
221 * ice_verify_pin_e810t
222 * @info: the driver's PTP info structure
223 * @pin: Pin index
224 * @func: Assigned function
225 * @chan: Assigned channel
226 *
227 * Verify if pin supports requested pin function. If the Check pins consistency.
228 * Reconfigure the SMA logic attached to the given pin to enable its
229 * desired functionality
230 */
231static int
232ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
233 enum ptp_pin_function func, unsigned int chan)
234{
235 /* Don't allow channel reassignment */
236 if (chan != ice_pin_desc_e810t[pin].chan)
237 return -EOPNOTSUPP;
238
239 /* Check if functions are properly assigned */
240 switch (func) {
241 case PTP_PF_NONE:
242 break;
243 case PTP_PF_EXTTS:
244 if (pin == UFL1)
245 return -EOPNOTSUPP;
246 break;
247 case PTP_PF_PEROUT:
248 if (pin == UFL2 || pin == GNSS)
249 return -EOPNOTSUPP;
250 break;
251 case PTP_PF_PHYSYNC:
252 return -EOPNOTSUPP;
253 }
254
255 return ice_ptp_set_sma_e810t(info, pin, func);
256}
257
258/**
259 * ice_set_tx_tstamp - Enable or disable Tx timestamping
260 * @pf: The PF pointer to search in
261 * @on: bool value for whether timestamps are enabled or disabled
262 */
263static void ice_set_tx_tstamp(struct ice_pf *pf, bool on)
264{
265 struct ice_vsi *vsi;
266 u32 val;
267 u16 i;
268
269 vsi = ice_get_main_vsi(pf);
270 if (!vsi)
271 return;
272
273 /* Set the timestamp enable flag for all the Tx rings */
274 ice_for_each_txq(vsi, i) {
275 if (!vsi->tx_rings[i])
276 continue;
277 vsi->tx_rings[i]->ptp_tx = on;
278 }
279
280 /* Configure the Tx timestamp interrupt */
281 val = rd32(&pf->hw, PFINT_OICR_ENA);
282 if (on)
283 val |= PFINT_OICR_TSYN_TX_M;
284 else
285 val &= ~PFINT_OICR_TSYN_TX_M;
286 wr32(&pf->hw, PFINT_OICR_ENA, val);
287
288 pf->ptp.tstamp_config.tx_type = on ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
289}
290
291/**
292 * ice_set_rx_tstamp - Enable or disable Rx timestamping
293 * @pf: The PF pointer to search in
294 * @on: bool value for whether timestamps are enabled or disabled
295 */
296static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
297{
298 struct ice_vsi *vsi;
299 u16 i;
300
301 vsi = ice_get_main_vsi(pf);
302 if (!vsi)
303 return;
304
305 /* Set the timestamp flag for all the Rx rings */
306 ice_for_each_rxq(vsi, i) {
307 if (!vsi->rx_rings[i])
308 continue;
309 vsi->rx_rings[i]->ptp_rx = on;
310 }
311
312 pf->ptp.tstamp_config.rx_filter = on ? HWTSTAMP_FILTER_ALL :
313 HWTSTAMP_FILTER_NONE;
314}
315
316/**
317 * ice_ptp_cfg_timestamp - Configure timestamp for init/deinit
318 * @pf: Board private structure
319 * @ena: bool value to enable or disable time stamp
320 *
321 * This function will configure timestamping during PTP initialization
322 * and deinitialization
323 */
324void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena)
325{
326 ice_set_tx_tstamp(pf, ena);
327 ice_set_rx_tstamp(pf, ena);
328}
329
330/**
331 * ice_get_ptp_clock_index - Get the PTP clock index
332 * @pf: the PF pointer
333 *
334 * Determine the clock index of the PTP clock associated with this device. If
335 * this is the PF controlling the clock, just use the local access to the
336 * clock device pointer.
337 *
338 * Otherwise, read from the driver shared parameters to determine the clock
339 * index value.
340 *
341 * Returns: the index of the PTP clock associated with this device, or -1 if
342 * there is no associated clock.
343 */
344int ice_get_ptp_clock_index(struct ice_pf *pf)
345{
346 struct device *dev = ice_pf_to_dev(pf);
347 enum ice_aqc_driver_params param_idx;
348 struct ice_hw *hw = &pf->hw;
349 u8 tmr_idx;
350 u32 value;
351 int err;
352
353 /* Use the ptp_clock structure if we're the main PF */
354 if (pf->ptp.clock)
355 return ptp_clock_index(pf->ptp.clock);
356
357 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
358 if (!tmr_idx)
359 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
360 else
361 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
362
363 err = ice_aq_get_driver_param(hw, param_idx, &value, NULL);
364 if (err) {
365 dev_err(dev, "Failed to read PTP clock index parameter, err %d aq_err %s\n",
366 err, ice_aq_str(hw->adminq.sq_last_status));
367 return -1;
368 }
369
370 /* The PTP clock index is an integer, and will be between 0 and
371 * INT_MAX. The highest bit of the driver shared parameter is used to
372 * indicate whether or not the currently stored clock index is valid.
373 */
374 if (!(value & PTP_SHARED_CLK_IDX_VALID))
375 return -1;
376
377 return value & ~PTP_SHARED_CLK_IDX_VALID;
378}
379
380/**
381 * ice_set_ptp_clock_index - Set the PTP clock index
382 * @pf: the PF pointer
383 *
384 * Set the PTP clock index for this device into the shared driver parameters,
385 * so that other PFs associated with this device can read it.
386 *
387 * If the PF is unable to store the clock index, it will log an error, but
388 * will continue operating PTP.
389 */
390static void ice_set_ptp_clock_index(struct ice_pf *pf)
391{
392 struct device *dev = ice_pf_to_dev(pf);
393 enum ice_aqc_driver_params param_idx;
394 struct ice_hw *hw = &pf->hw;
395 u8 tmr_idx;
396 u32 value;
397 int err;
398
399 if (!pf->ptp.clock)
400 return;
401
402 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
403 if (!tmr_idx)
404 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
405 else
406 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
407
408 value = (u32)ptp_clock_index(pf->ptp.clock);
409 if (value > INT_MAX) {
410 dev_err(dev, "PTP Clock index is too large to store\n");
411 return;
412 }
413 value |= PTP_SHARED_CLK_IDX_VALID;
414
415 err = ice_aq_set_driver_param(hw, param_idx, value, NULL);
416 if (err) {
417 dev_err(dev, "Failed to set PTP clock index parameter, err %d aq_err %s\n",
418 err, ice_aq_str(hw->adminq.sq_last_status));
419 }
420}
421
422/**
423 * ice_clear_ptp_clock_index - Clear the PTP clock index
424 * @pf: the PF pointer
425 *
426 * Clear the PTP clock index for this device. Must be called when
427 * unregistering the PTP clock, in order to ensure other PFs stop reporting
428 * a clock object that no longer exists.
429 */
430static void ice_clear_ptp_clock_index(struct ice_pf *pf)
431{
432 struct device *dev = ice_pf_to_dev(pf);
433 enum ice_aqc_driver_params param_idx;
434 struct ice_hw *hw = &pf->hw;
435 u8 tmr_idx;
436 int err;
437
438 /* Do not clear the index if we don't own the timer */
439 if (!hw->func_caps.ts_func_info.src_tmr_owned)
440 return;
441
442 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
443 if (!tmr_idx)
444 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
445 else
446 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
447
448 err = ice_aq_set_driver_param(hw, param_idx, 0, NULL);
449 if (err) {
450 dev_dbg(dev, "Failed to clear PTP clock index parameter, err %d aq_err %s\n",
451 err, ice_aq_str(hw->adminq.sq_last_status));
452 }
453}
454
455/**
456 * ice_ptp_read_src_clk_reg - Read the source clock register
457 * @pf: Board private structure
458 * @sts: Optional parameter for holding a pair of system timestamps from
459 * the system clock. Will be ignored if NULL is given.
460 */
461static u64
462ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
463{
464 struct ice_hw *hw = &pf->hw;
465 u32 hi, lo, lo2;
466 u8 tmr_idx;
467
468 tmr_idx = ice_get_ptp_src_clock_index(hw);
469 /* Read the system timestamp pre PHC read */
470 ptp_read_system_prets(sts);
471
472 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
473
474 /* Read the system timestamp post PHC read */
475 ptp_read_system_postts(sts);
476
477 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
478 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
479
480 if (lo2 < lo) {
481 /* if TIME_L rolled over read TIME_L again and update
482 * system timestamps
483 */
484 ptp_read_system_prets(sts);
485 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
486 ptp_read_system_postts(sts);
487 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
488 }
489
490 return ((u64)hi << 32) | lo;
491}
492
493/**
494 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
495 * @cached_phc_time: recently cached copy of PHC time
496 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
497 *
498 * Hardware captures timestamps which contain only 32 bits of nominal
499 * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
500 * Note that the captured timestamp values may be 40 bits, but the lower
501 * 8 bits are sub-nanoseconds and generally discarded.
502 *
503 * Extend the 32bit nanosecond timestamp using the following algorithm and
504 * assumptions:
505 *
506 * 1) have a recently cached copy of the PHC time
507 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
508 * seconds) before or after the PHC time was captured.
509 * 3) calculate the delta between the cached time and the timestamp
510 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
511 * captured after the PHC time. In this case, the full timestamp is just
512 * the cached PHC time plus the delta.
513 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
514 * timestamp was captured *before* the PHC time, i.e. because the PHC
515 * cache was updated after the timestamp was captured by hardware. In this
516 * case, the full timestamp is the cached time minus the inverse delta.
517 *
518 * This algorithm works even if the PHC time was updated after a Tx timestamp
519 * was requested, but before the Tx timestamp event was reported from
520 * hardware.
521 *
522 * This calculation primarily relies on keeping the cached PHC time up to
523 * date. If the timestamp was captured more than 2^31 nanoseconds after the
524 * PHC time, it is possible that the lower 32bits of PHC time have
525 * overflowed more than once, and we might generate an incorrect timestamp.
526 *
527 * This is prevented by (a) periodically updating the cached PHC time once
528 * a second, and (b) discarding any Tx timestamp packet if it has waited for
529 * a timestamp for more than one second.
530 */
531static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
532{
533 u32 delta, phc_time_lo;
534 u64 ns;
535
536 /* Extract the lower 32 bits of the PHC time */
537 phc_time_lo = (u32)cached_phc_time;
538
539 /* Calculate the delta between the lower 32bits of the cached PHC
540 * time and the in_tstamp value
541 */
542 delta = (in_tstamp - phc_time_lo);
543
544 /* Do not assume that the in_tstamp is always more recent than the
545 * cached PHC time. If the delta is large, it indicates that the
546 * in_tstamp was taken in the past, and should be converted
547 * forward.
548 */
549 if (delta > (U32_MAX / 2)) {
550 /* reverse the delta calculation here */
551 delta = (phc_time_lo - in_tstamp);
552 ns = cached_phc_time - delta;
553 } else {
554 ns = cached_phc_time + delta;
555 }
556
557 return ns;
558}
559
560/**
561 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
562 * @pf: Board private structure
563 * @in_tstamp: Ingress/egress 40b timestamp value
564 *
565 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
566 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
567 *
568 * *--------------------------------------------------------------*
569 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
570 * *--------------------------------------------------------------*
571 *
572 * The low bit is an indicator of whether the timestamp is valid. The next
573 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
574 * and the remaining 32 bits are the lower 32 bits of the PHC timer.
575 *
576 * It is assumed that the caller verifies the timestamp is valid prior to
577 * calling this function.
578 *
579 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
580 * time stored in the device private PTP structure as the basis for timestamp
581 * extension.
582 *
583 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
584 * algorithm.
585 */
586static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
587{
588 const u64 mask = GENMASK_ULL(31, 0);
589 unsigned long discard_time;
590
591 /* Discard the hardware timestamp if the cached PHC time is too old */
592 discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
593 if (time_is_before_jiffies(discard_time)) {
594 pf->ptp.tx_hwtstamp_discarded++;
595 return 0;
596 }
597
598 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
599 (in_tstamp >> 8) & mask);
600}
601
602/**
603 * ice_ptp_is_tx_tracker_up - Check if Tx tracker is ready for new timestamps
604 * @tx: the PTP Tx timestamp tracker to check
605 *
606 * Check that a given PTP Tx timestamp tracker is up, i.e. that it is ready
607 * to accept new timestamp requests.
608 *
609 * Assumes the tx->lock spinlock is already held.
610 */
611static bool
612ice_ptp_is_tx_tracker_up(struct ice_ptp_tx *tx)
613{
614 lockdep_assert_held(&tx->lock);
615
616 return tx->init && !tx->calibrating;
617}
618
619/**
620 * ice_ptp_tx_tstamp - Process Tx timestamps for a port
621 * @tx: the PTP Tx timestamp tracker
622 *
623 * Process timestamps captured by the PHY associated with this port. To do
624 * this, loop over each index with a waiting skb.
625 *
626 * If a given index has a valid timestamp, perform the following steps:
627 *
628 * 1) check that the timestamp request is not stale
629 * 2) check that a timestamp is ready and available in the PHY memory bank
630 * 3) read and copy the timestamp out of the PHY register
631 * 4) unlock the index by clearing the associated in_use bit
632 * 5) check if the timestamp is stale, and discard if so
633 * 6) extend the 40 bit timestamp value to get a 64 bit timestamp value
634 * 7) send this 64 bit timestamp to the stack
635 *
636 * Returns true if all timestamps were handled, and false if any slots remain
637 * without a timestamp.
638 *
639 * After looping, if we still have waiting SKBs, return false. This may cause
640 * us effectively poll even when not strictly necessary. We do this because
641 * it's possible a new timestamp was requested around the same time as the
642 * interrupt. In some cases hardware might not interrupt us again when the
643 * timestamp is captured.
644 *
645 * Note that we do not hold the tracking lock while reading the Tx timestamp.
646 * This is because reading the timestamp requires taking a mutex that might
647 * sleep.
648 *
649 * The only place where we set in_use is when a new timestamp is initiated
650 * with a slot index. This is only called in the hard xmit routine where an
651 * SKB has a request flag set. The only places where we clear this bit is this
652 * function, or during teardown when the Tx timestamp tracker is being
653 * removed. A timestamp index will never be re-used until the in_use bit for
654 * that index is cleared.
655 *
656 * If a Tx thread starts a new timestamp, we might not begin processing it
657 * right away but we will notice it at the end when we re-queue the task.
658 *
659 * If a Tx thread starts a new timestamp just after this function exits, the
660 * interrupt for that timestamp should re-trigger this function once
661 * a timestamp is ready.
662 *
663 * In cases where the PTP hardware clock was directly adjusted, some
664 * timestamps may not be able to safely use the timestamp extension math. In
665 * this case, software will set the stale bit for any outstanding Tx
666 * timestamps when the clock is adjusted. Then this function will discard
667 * those captured timestamps instead of sending them to the stack.
668 *
669 * If a Tx packet has been waiting for more than 2 seconds, it is not possible
670 * to correctly extend the timestamp using the cached PHC time. It is
671 * extremely unlikely that a packet will ever take this long to timestamp. If
672 * we detect a Tx timestamp request that has waited for this long we assume
673 * the packet will never be sent by hardware and discard it without reading
674 * the timestamp register.
675 */
676static bool ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)
677{
678 struct ice_ptp_port *ptp_port;
679 bool more_timestamps;
680 struct ice_pf *pf;
681 struct ice_hw *hw;
682 u64 tstamp_ready;
683 int err;
684 u8 idx;
685
686 if (!tx->init)
687 return true;
688
689 ptp_port = container_of(tx, struct ice_ptp_port, tx);
690 pf = ptp_port_to_pf(ptp_port);
691 hw = &pf->hw;
692
693 /* Read the Tx ready status first */
694 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
695 if (err)
696 return false;
697
698 for_each_set_bit(idx, tx->in_use, tx->len) {
699 struct skb_shared_hwtstamps shhwtstamps = {};
700 u8 phy_idx = idx + tx->offset;
701 u64 raw_tstamp = 0, tstamp;
702 bool drop_ts = false;
703 struct sk_buff *skb;
704
705 /* Drop packets which have waited for more than 2 seconds */
706 if (time_is_before_jiffies(tx->tstamps[idx].start + 2 * HZ)) {
707 drop_ts = true;
708
709 /* Count the number of Tx timestamps that timed out */
710 pf->ptp.tx_hwtstamp_timeouts++;
711 }
712
713 /* Only read a timestamp from the PHY if its marked as ready
714 * by the tstamp_ready register. This avoids unnecessary
715 * reading of timestamps which are not yet valid. This is
716 * important as we must read all timestamps which are valid
717 * and only timestamps which are valid during each interrupt.
718 * If we do not, the hardware logic for generating a new
719 * interrupt can get stuck on some devices.
720 */
721 if (!(tstamp_ready & BIT_ULL(phy_idx))) {
722 if (drop_ts)
723 goto skip_ts_read;
724
725 continue;
726 }
727
728 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
729
730 err = ice_read_phy_tstamp(hw, tx->block, phy_idx, &raw_tstamp);
731 if (err)
732 continue;
733
734 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
735
736 /* For PHYs which don't implement a proper timestamp ready
737 * bitmap, verify that the timestamp value is different
738 * from the last cached timestamp. If it is not, skip this for
739 * now assuming it hasn't yet been captured by hardware.
740 */
741 if (!drop_ts && tx->verify_cached &&
742 raw_tstamp == tx->tstamps[idx].cached_tstamp)
743 continue;
744
745 /* Discard any timestamp value without the valid bit set */
746 if (!(raw_tstamp & ICE_PTP_TS_VALID))
747 drop_ts = true;
748
749skip_ts_read:
750 spin_lock(&tx->lock);
751 if (tx->verify_cached && raw_tstamp)
752 tx->tstamps[idx].cached_tstamp = raw_tstamp;
753 clear_bit(idx, tx->in_use);
754 skb = tx->tstamps[idx].skb;
755 tx->tstamps[idx].skb = NULL;
756 if (test_and_clear_bit(idx, tx->stale))
757 drop_ts = true;
758 spin_unlock(&tx->lock);
759
760 /* It is unlikely but possible that the SKB will have been
761 * flushed at this point due to link change or teardown.
762 */
763 if (!skb)
764 continue;
765
766 if (drop_ts) {
767 dev_kfree_skb_any(skb);
768 continue;
769 }
770
771 /* Extend the timestamp using cached PHC time */
772 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
773 if (tstamp) {
774 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
775 ice_trace(tx_tstamp_complete, skb, idx);
776 }
777
778 skb_tstamp_tx(skb, &shhwtstamps);
779 dev_kfree_skb_any(skb);
780 }
781
782 /* Check if we still have work to do. If so, re-queue this task to
783 * poll for remaining timestamps.
784 */
785 spin_lock(&tx->lock);
786 more_timestamps = tx->init && !bitmap_empty(tx->in_use, tx->len);
787 spin_unlock(&tx->lock);
788
789 return !more_timestamps;
790}
791
792/**
793 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
794 * @tx: Tx tracking structure to initialize
795 *
796 * Assumes that the length has already been initialized. Do not call directly,
797 * use the ice_ptp_init_tx_* instead.
798 */
799static int
800ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
801{
802 unsigned long *in_use, *stale;
803 struct ice_tx_tstamp *tstamps;
804
805 tstamps = kcalloc(tx->len, sizeof(*tstamps), GFP_KERNEL);
806 in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
807 stale = bitmap_zalloc(tx->len, GFP_KERNEL);
808
809 if (!tstamps || !in_use || !stale) {
810 kfree(tstamps);
811 bitmap_free(in_use);
812 bitmap_free(stale);
813
814 return -ENOMEM;
815 }
816
817 tx->tstamps = tstamps;
818 tx->in_use = in_use;
819 tx->stale = stale;
820 tx->init = 1;
821
822 spin_lock_init(&tx->lock);
823
824 return 0;
825}
826
827/**
828 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
829 * @pf: Board private structure
830 * @tx: the tracker to flush
831 *
832 * Called during teardown when a Tx tracker is being removed.
833 */
834static void
835ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
836{
837 struct ice_hw *hw = &pf->hw;
838 u64 tstamp_ready;
839 int err;
840 u8 idx;
841
842 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
843 if (err) {
844 dev_dbg(ice_pf_to_dev(pf), "Failed to get the Tx tstamp ready bitmap for block %u, err %d\n",
845 tx->block, err);
846
847 /* If we fail to read the Tx timestamp ready bitmap just
848 * skip clearing the PHY timestamps.
849 */
850 tstamp_ready = 0;
851 }
852
853 for_each_set_bit(idx, tx->in_use, tx->len) {
854 u8 phy_idx = idx + tx->offset;
855 struct sk_buff *skb;
856
857 /* In case this timestamp is ready, we need to clear it. */
858 if (!hw->reset_ongoing && (tstamp_ready & BIT_ULL(phy_idx)))
859 ice_clear_phy_tstamp(hw, tx->block, phy_idx);
860
861 spin_lock(&tx->lock);
862 skb = tx->tstamps[idx].skb;
863 tx->tstamps[idx].skb = NULL;
864 clear_bit(idx, tx->in_use);
865 clear_bit(idx, tx->stale);
866 spin_unlock(&tx->lock);
867
868 /* Count the number of Tx timestamps flushed */
869 pf->ptp.tx_hwtstamp_flushed++;
870
871 /* Free the SKB after we've cleared the bit */
872 dev_kfree_skb_any(skb);
873 }
874}
875
876/**
877 * ice_ptp_mark_tx_tracker_stale - Mark unfinished timestamps as stale
878 * @tx: the tracker to mark
879 *
880 * Mark currently outstanding Tx timestamps as stale. This prevents sending
881 * their timestamp value to the stack. This is required to prevent extending
882 * the 40bit hardware timestamp incorrectly.
883 *
884 * This should be called when the PTP clock is modified such as after a set
885 * time request.
886 */
887static void
888ice_ptp_mark_tx_tracker_stale(struct ice_ptp_tx *tx)
889{
890 spin_lock(&tx->lock);
891 bitmap_or(tx->stale, tx->stale, tx->in_use, tx->len);
892 spin_unlock(&tx->lock);
893}
894
895/**
896 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
897 * @pf: Board private structure
898 * @tx: Tx tracking structure to release
899 *
900 * Free memory associated with the Tx timestamp tracker.
901 */
902static void
903ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
904{
905 spin_lock(&tx->lock);
906 tx->init = 0;
907 spin_unlock(&tx->lock);
908
909 /* wait for potentially outstanding interrupt to complete */
910 synchronize_irq(pf->msix_entries[pf->oicr_idx].vector);
911
912 ice_ptp_flush_tx_tracker(pf, tx);
913
914 kfree(tx->tstamps);
915 tx->tstamps = NULL;
916
917 bitmap_free(tx->in_use);
918 tx->in_use = NULL;
919
920 bitmap_free(tx->stale);
921 tx->stale = NULL;
922
923 tx->len = 0;
924}
925
926/**
927 * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps
928 * @pf: Board private structure
929 * @tx: the Tx tracking structure to initialize
930 * @port: the port this structure tracks
931 *
932 * Initialize the Tx timestamp tracker for this port. For generic MAC devices,
933 * the timestamp block is shared for all ports in the same quad. To avoid
934 * ports using the same timestamp index, logically break the block of
935 * registers into chunks based on the port number.
936 */
937static int
938ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
939{
940 tx->block = port / ICE_PORTS_PER_QUAD;
941 tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E822;
942 tx->len = INDEX_PER_PORT_E822;
943 tx->verify_cached = 0;
944
945 return ice_ptp_alloc_tx_tracker(tx);
946}
947
948/**
949 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
950 * @pf: Board private structure
951 * @tx: the Tx tracking structure to initialize
952 *
953 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
954 * port has its own block of timestamps, independent of the other ports.
955 */
956static int
957ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
958{
959 tx->block = pf->hw.port_info->lport;
960 tx->offset = 0;
961 tx->len = INDEX_PER_PORT_E810;
962 /* The E810 PHY does not provide a timestamp ready bitmap. Instead,
963 * verify new timestamps against cached copy of the last read
964 * timestamp.
965 */
966 tx->verify_cached = 1;
967
968 return ice_ptp_alloc_tx_tracker(tx);
969}
970
971/**
972 * ice_ptp_update_cached_phctime - Update the cached PHC time values
973 * @pf: Board specific private structure
974 *
975 * This function updates the system time values which are cached in the PF
976 * structure and the Rx rings.
977 *
978 * This function must be called periodically to ensure that the cached value
979 * is never more than 2 seconds old.
980 *
981 * Note that the cached copy in the PF PTP structure is always updated, even
982 * if we can't update the copy in the Rx rings.
983 *
984 * Return:
985 * * 0 - OK, successfully updated
986 * * -EAGAIN - PF was busy, need to reschedule the update
987 */
988static int ice_ptp_update_cached_phctime(struct ice_pf *pf)
989{
990 struct device *dev = ice_pf_to_dev(pf);
991 unsigned long update_before;
992 u64 systime;
993 int i;
994
995 update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
996 if (pf->ptp.cached_phc_time &&
997 time_is_before_jiffies(update_before)) {
998 unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies;
999
1000 dev_warn(dev, "%u msecs passed between update to cached PHC time\n",
1001 jiffies_to_msecs(time_taken));
1002 pf->ptp.late_cached_phc_updates++;
1003 }
1004
1005 /* Read the current PHC time */
1006 systime = ice_ptp_read_src_clk_reg(pf, NULL);
1007
1008 /* Update the cached PHC time stored in the PF structure */
1009 WRITE_ONCE(pf->ptp.cached_phc_time, systime);
1010 WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies);
1011
1012 if (test_and_set_bit(ICE_CFG_BUSY, pf->state))
1013 return -EAGAIN;
1014
1015 ice_for_each_vsi(pf, i) {
1016 struct ice_vsi *vsi = pf->vsi[i];
1017 int j;
1018
1019 if (!vsi)
1020 continue;
1021
1022 if (vsi->type != ICE_VSI_PF)
1023 continue;
1024
1025 ice_for_each_rxq(vsi, j) {
1026 if (!vsi->rx_rings[j])
1027 continue;
1028 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
1029 }
1030 }
1031 clear_bit(ICE_CFG_BUSY, pf->state);
1032
1033 return 0;
1034}
1035
1036/**
1037 * ice_ptp_reset_cached_phctime - Reset cached PHC time after an update
1038 * @pf: Board specific private structure
1039 *
1040 * This function must be called when the cached PHC time is no longer valid,
1041 * such as after a time adjustment. It marks any currently outstanding Tx
1042 * timestamps as stale and updates the cached PHC time for both the PF and Rx
1043 * rings.
1044 *
1045 * If updating the PHC time cannot be done immediately, a warning message is
1046 * logged and the work item is scheduled immediately to minimize the window
1047 * with a wrong cached timestamp.
1048 */
1049static void ice_ptp_reset_cached_phctime(struct ice_pf *pf)
1050{
1051 struct device *dev = ice_pf_to_dev(pf);
1052 int err;
1053
1054 /* Update the cached PHC time immediately if possible, otherwise
1055 * schedule the work item to execute soon.
1056 */
1057 err = ice_ptp_update_cached_phctime(pf);
1058 if (err) {
1059 /* If another thread is updating the Rx rings, we won't
1060 * properly reset them here. This could lead to reporting of
1061 * invalid timestamps, but there isn't much we can do.
1062 */
1063 dev_warn(dev, "%s: ICE_CFG_BUSY, unable to immediately update cached PHC time\n",
1064 __func__);
1065
1066 /* Queue the work item to update the Rx rings when possible */
1067 kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work,
1068 msecs_to_jiffies(10));
1069 }
1070
1071 /* Mark any outstanding timestamps as stale, since they might have
1072 * been captured in hardware before the time update. This could lead
1073 * to us extending them with the wrong cached value resulting in
1074 * incorrect timestamp values.
1075 */
1076 ice_ptp_mark_tx_tracker_stale(&pf->ptp.port.tx);
1077}
1078
1079/**
1080 * ice_ptp_read_time - Read the time from the device
1081 * @pf: Board private structure
1082 * @ts: timespec structure to hold the current time value
1083 * @sts: Optional parameter for holding a pair of system timestamps from
1084 * the system clock. Will be ignored if NULL is given.
1085 *
1086 * This function reads the source clock registers and stores them in a timespec.
1087 * However, since the registers are 64 bits of nanoseconds, we must convert the
1088 * result to a timespec before we can return.
1089 */
1090static void
1091ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
1092 struct ptp_system_timestamp *sts)
1093{
1094 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
1095
1096 *ts = ns_to_timespec64(time_ns);
1097}
1098
1099/**
1100 * ice_ptp_write_init - Set PHC time to provided value
1101 * @pf: Board private structure
1102 * @ts: timespec structure that holds the new time value
1103 *
1104 * Set the PHC time to the specified time provided in the timespec.
1105 */
1106static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
1107{
1108 u64 ns = timespec64_to_ns(ts);
1109 struct ice_hw *hw = &pf->hw;
1110
1111 return ice_ptp_init_time(hw, ns);
1112}
1113
1114/**
1115 * ice_ptp_write_adj - Adjust PHC clock time atomically
1116 * @pf: Board private structure
1117 * @adj: Adjustment in nanoseconds
1118 *
1119 * Perform an atomic adjustment of the PHC time by the specified number of
1120 * nanoseconds.
1121 */
1122static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
1123{
1124 struct ice_hw *hw = &pf->hw;
1125
1126 return ice_ptp_adj_clock(hw, adj);
1127}
1128
1129/**
1130 * ice_base_incval - Get base timer increment value
1131 * @pf: Board private structure
1132 *
1133 * Look up the base timer increment value for this device. The base increment
1134 * value is used to define the nominal clock tick rate. This increment value
1135 * is programmed during device initialization. It is also used as the basis
1136 * for calculating adjustments using scaled_ppm.
1137 */
1138static u64 ice_base_incval(struct ice_pf *pf)
1139{
1140 struct ice_hw *hw = &pf->hw;
1141 u64 incval;
1142
1143 if (ice_is_e810(hw))
1144 incval = ICE_PTP_NOMINAL_INCVAL_E810;
1145 else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
1146 incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));
1147 else
1148 incval = UNKNOWN_INCVAL_E822;
1149
1150 dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
1151 incval);
1152
1153 return incval;
1154}
1155
1156/**
1157 * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state
1158 * @port: PTP port for which Tx FIFO is checked
1159 */
1160static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
1161{
1162 int quad = port->port_num / ICE_PORTS_PER_QUAD;
1163 int offs = port->port_num % ICE_PORTS_PER_QUAD;
1164 struct ice_pf *pf;
1165 struct ice_hw *hw;
1166 u32 val, phy_sts;
1167 int err;
1168
1169 pf = ptp_port_to_pf(port);
1170 hw = &pf->hw;
1171
1172 if (port->tx_fifo_busy_cnt == FIFO_OK)
1173 return 0;
1174
1175 /* need to read FIFO state */
1176 if (offs == 0 || offs == 1)
1177 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS,
1178 &val);
1179 else
1180 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS,
1181 &val);
1182
1183 if (err) {
1184 dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n",
1185 port->port_num, err);
1186 return err;
1187 }
1188
1189 if (offs & 0x1)
1190 phy_sts = (val & Q_REG_FIFO13_M) >> Q_REG_FIFO13_S;
1191 else
1192 phy_sts = (val & Q_REG_FIFO02_M) >> Q_REG_FIFO02_S;
1193
1194 if (phy_sts & FIFO_EMPTY) {
1195 port->tx_fifo_busy_cnt = FIFO_OK;
1196 return 0;
1197 }
1198
1199 port->tx_fifo_busy_cnt++;
1200
1201 dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n",
1202 port->tx_fifo_busy_cnt, port->port_num);
1203
1204 if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) {
1205 dev_dbg(ice_pf_to_dev(pf),
1206 "Port %d Tx FIFO still not empty; resetting quad %d\n",
1207 port->port_num, quad);
1208 ice_ptp_reset_ts_memory_quad_e822(hw, quad);
1209 port->tx_fifo_busy_cnt = FIFO_OK;
1210 return 0;
1211 }
1212
1213 return -EAGAIN;
1214}
1215
1216/**
1217 * ice_ptp_wait_for_offsets - Check for valid Tx and Rx offsets
1218 * @work: Pointer to the kthread_work structure for this task
1219 *
1220 * Check whether hardware has completed measuring the Tx and Rx offset values
1221 * used to configure and enable vernier timestamp calibration.
1222 *
1223 * Once the offset in either direction is measured, configure the associated
1224 * registers with the calibrated offset values and enable timestamping. The Tx
1225 * and Rx directions are configured independently as soon as their associated
1226 * offsets are known.
1227 *
1228 * This function reschedules itself until both Tx and Rx calibration have
1229 * completed.
1230 */
1231static void ice_ptp_wait_for_offsets(struct kthread_work *work)
1232{
1233 struct ice_ptp_port *port;
1234 struct ice_pf *pf;
1235 struct ice_hw *hw;
1236 int tx_err;
1237 int rx_err;
1238
1239 port = container_of(work, struct ice_ptp_port, ov_work.work);
1240 pf = ptp_port_to_pf(port);
1241 hw = &pf->hw;
1242
1243 if (ice_is_reset_in_progress(pf->state)) {
1244 /* wait for device driver to complete reset */
1245 kthread_queue_delayed_work(pf->ptp.kworker,
1246 &port->ov_work,
1247 msecs_to_jiffies(100));
1248 return;
1249 }
1250
1251 tx_err = ice_ptp_check_tx_fifo(port);
1252 if (!tx_err)
1253 tx_err = ice_phy_cfg_tx_offset_e822(hw, port->port_num);
1254 rx_err = ice_phy_cfg_rx_offset_e822(hw, port->port_num);
1255 if (tx_err || rx_err) {
1256 /* Tx and/or Rx offset not yet configured, try again later */
1257 kthread_queue_delayed_work(pf->ptp.kworker,
1258 &port->ov_work,
1259 msecs_to_jiffies(100));
1260 return;
1261 }
1262}
1263
1264/**
1265 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port
1266 * @ptp_port: PTP port to stop
1267 */
1268static int
1269ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
1270{
1271 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1272 u8 port = ptp_port->port_num;
1273 struct ice_hw *hw = &pf->hw;
1274 int err;
1275
1276 if (ice_is_e810(hw))
1277 return 0;
1278
1279 mutex_lock(&ptp_port->ps_lock);
1280
1281 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1282
1283 err = ice_stop_phy_timer_e822(hw, port, true);
1284 if (err)
1285 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
1286 port, err);
1287
1288 mutex_unlock(&ptp_port->ps_lock);
1289
1290 return err;
1291}
1292
1293/**
1294 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping
1295 * @ptp_port: PTP port for which the PHY start is set
1296 *
1297 * Start the PHY timestamping block, and initiate Vernier timestamping
1298 * calibration. If timestamping cannot be calibrated (such as if link is down)
1299 * then disable the timestamping block instead.
1300 */
1301static int
1302ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
1303{
1304 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1305 u8 port = ptp_port->port_num;
1306 struct ice_hw *hw = &pf->hw;
1307 int err;
1308
1309 if (ice_is_e810(hw))
1310 return 0;
1311
1312 if (!ptp_port->link_up)
1313 return ice_ptp_port_phy_stop(ptp_port);
1314
1315 mutex_lock(&ptp_port->ps_lock);
1316
1317 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1318
1319 /* temporarily disable Tx timestamps while calibrating PHY offset */
1320 spin_lock(&ptp_port->tx.lock);
1321 ptp_port->tx.calibrating = true;
1322 spin_unlock(&ptp_port->tx.lock);
1323 ptp_port->tx_fifo_busy_cnt = 0;
1324
1325 /* Start the PHY timer in Vernier mode */
1326 err = ice_start_phy_timer_e822(hw, port);
1327 if (err)
1328 goto out_unlock;
1329
1330 /* Enable Tx timestamps right away */
1331 spin_lock(&ptp_port->tx.lock);
1332 ptp_port->tx.calibrating = false;
1333 spin_unlock(&ptp_port->tx.lock);
1334
1335 kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
1336
1337out_unlock:
1338 if (err)
1339 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
1340 port, err);
1341
1342 mutex_unlock(&ptp_port->ps_lock);
1343
1344 return err;
1345}
1346
1347/**
1348 * ice_ptp_link_change - Reconfigure PTP after link status change
1349 * @pf: Board private structure
1350 * @port: Port for which the PHY start is set
1351 * @linkup: Link is up or down
1352 */
1353void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
1354{
1355 struct ice_ptp_port *ptp_port;
1356
1357 if (!test_bit(ICE_FLAG_PTP, pf->flags))
1358 return;
1359
1360 if (WARN_ON_ONCE(port >= ICE_NUM_EXTERNAL_PORTS))
1361 return;
1362
1363 ptp_port = &pf->ptp.port;
1364 if (WARN_ON_ONCE(ptp_port->port_num != port))
1365 return;
1366
1367 /* Update cached link status for this port immediately */
1368 ptp_port->link_up = linkup;
1369
1370 /* E810 devices do not need to reconfigure the PHY */
1371 if (ice_is_e810(&pf->hw))
1372 return;
1373
1374 ice_ptp_port_phy_restart(ptp_port);
1375}
1376
1377/**
1378 * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt
1379 * @pf: PF private structure
1380 * @ena: bool value to enable or disable interrupt
1381 * @threshold: Minimum number of packets at which intr is triggered
1382 *
1383 * Utility function to enable or disable Tx timestamp interrupt and threshold
1384 */
1385static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)
1386{
1387 struct ice_hw *hw = &pf->hw;
1388 int err = 0;
1389 int quad;
1390 u32 val;
1391
1392 ice_ptp_reset_ts_memory(hw);
1393
1394 for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
1395 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1396 &val);
1397 if (err)
1398 break;
1399
1400 if (ena) {
1401 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1402 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
1403 val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &
1404 Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);
1405 } else {
1406 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1407 }
1408
1409 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1410 val);
1411 if (err)
1412 break;
1413 }
1414
1415 if (err)
1416 dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
1417 err);
1418 return err;
1419}
1420
1421/**
1422 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block
1423 * @pf: Board private structure
1424 */
1425static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)
1426{
1427 ice_ptp_port_phy_restart(&pf->ptp.port);
1428}
1429
1430/**
1431 * ice_ptp_adjfine - Adjust clock increment rate
1432 * @info: the driver's PTP info structure
1433 * @scaled_ppm: Parts per million with 16-bit fractional field
1434 *
1435 * Adjust the frequency of the clock by the indicated scaled ppm from the
1436 * base frequency.
1437 */
1438static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
1439{
1440 struct ice_pf *pf = ptp_info_to_pf(info);
1441 struct ice_hw *hw = &pf->hw;
1442 u64 incval;
1443 int err;
1444
1445 incval = adjust_by_scaled_ppm(ice_base_incval(pf), scaled_ppm);
1446 err = ice_ptp_write_incval_locked(hw, incval);
1447 if (err) {
1448 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
1449 err);
1450 return -EIO;
1451 }
1452
1453 return 0;
1454}
1455
1456/**
1457 * ice_ptp_extts_work - Workqueue task function
1458 * @work: external timestamp work structure
1459 *
1460 * Service for PTP external clock event
1461 */
1462static void ice_ptp_extts_work(struct kthread_work *work)
1463{
1464 struct ice_ptp *ptp = container_of(work, struct ice_ptp, extts_work);
1465 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
1466 struct ptp_clock_event event;
1467 struct ice_hw *hw = &pf->hw;
1468 u8 chan, tmr_idx;
1469 u32 hi, lo;
1470
1471 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1472 /* Event time is captured by one of the two matched registers
1473 * GLTSYN_EVNT_L: 32 LSB of sampled time event
1474 * GLTSYN_EVNT_H: 32 MSB of sampled time event
1475 * Event is defined in GLTSYN_EVNT_0 register
1476 */
1477 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1478 /* Check if channel is enabled */
1479 if (pf->ptp.ext_ts_irq & (1 << chan)) {
1480 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1481 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1482 event.timestamp = (((u64)hi) << 32) | lo;
1483 event.type = PTP_CLOCK_EXTTS;
1484 event.index = chan;
1485
1486 /* Fire event */
1487 ptp_clock_event(pf->ptp.clock, &event);
1488 pf->ptp.ext_ts_irq &= ~(1 << chan);
1489 }
1490 }
1491}
1492
1493/**
1494 * ice_ptp_cfg_extts - Configure EXTTS pin and channel
1495 * @pf: Board private structure
1496 * @ena: true to enable; false to disable
1497 * @chan: GPIO channel (0-3)
1498 * @gpio_pin: GPIO pin
1499 * @extts_flags: request flags from the ptp_extts_request.flags
1500 */
1501static int
1502ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
1503 unsigned int extts_flags)
1504{
1505 u32 func, aux_reg, gpio_reg, irq_reg;
1506 struct ice_hw *hw = &pf->hw;
1507 u8 tmr_idx;
1508
1509 if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
1510 return -EINVAL;
1511
1512 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1513
1514 irq_reg = rd32(hw, PFINT_OICR_ENA);
1515
1516 if (ena) {
1517 /* Enable the interrupt */
1518 irq_reg |= PFINT_OICR_TSYN_EVNT_M;
1519 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
1520
1521#define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0)
1522#define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
1523
1524 /* set event level to requested edge */
1525 if (extts_flags & PTP_FALLING_EDGE)
1526 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
1527 if (extts_flags & PTP_RISING_EDGE)
1528 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
1529
1530 /* Write GPIO CTL reg.
1531 * 0x1 is input sampled by EVENT register(channel)
1532 * + num_in_channels * tmr_idx
1533 */
1534 func = 1 + chan + (tmr_idx * 3);
1535 gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
1536 GLGEN_GPIO_CTL_PIN_FUNC_M);
1537 pf->ptp.ext_ts_chan |= (1 << chan);
1538 } else {
1539 /* clear the values we set to reset defaults */
1540 aux_reg = 0;
1541 gpio_reg = 0;
1542 pf->ptp.ext_ts_chan &= ~(1 << chan);
1543 if (!pf->ptp.ext_ts_chan)
1544 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
1545 }
1546
1547 wr32(hw, PFINT_OICR_ENA, irq_reg);
1548 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
1549 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
1550
1551 return 0;
1552}
1553
1554/**
1555 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
1556 * @pf: Board private structure
1557 * @chan: GPIO channel (0-3)
1558 * @config: desired periodic clk configuration. NULL will disable channel
1559 * @store: If set to true the values will be stored
1560 *
1561 * Configure the internal clock generator modules to generate the clock wave of
1562 * specified period.
1563 */
1564static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
1565 struct ice_perout_channel *config, bool store)
1566{
1567 u64 current_time, period, start_time, phase;
1568 struct ice_hw *hw = &pf->hw;
1569 u32 func, val, gpio_pin;
1570 u8 tmr_idx;
1571
1572 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1573
1574 /* 0. Reset mode & out_en in AUX_OUT */
1575 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
1576
1577 /* If we're disabling the output, clear out CLKO and TGT and keep
1578 * output level low
1579 */
1580 if (!config || !config->ena) {
1581 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
1582 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
1583 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
1584
1585 val = GLGEN_GPIO_CTL_PIN_DIR_M;
1586 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
1587 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1588
1589 /* Store the value if requested */
1590 if (store)
1591 memset(&pf->ptp.perout_channels[chan], 0,
1592 sizeof(struct ice_perout_channel));
1593
1594 return 0;
1595 }
1596 period = config->period;
1597 start_time = config->start_time;
1598 div64_u64_rem(start_time, period, &phase);
1599 gpio_pin = config->gpio_pin;
1600
1601 /* 1. Write clkout with half of required period value */
1602 if (period & 0x1) {
1603 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
1604 goto err;
1605 }
1606
1607 period >>= 1;
1608
1609 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick
1610 */
1611#define MIN_PULSE 3
1612 if (period <= MIN_PULSE || period > U32_MAX) {
1613 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
1614 MIN_PULSE * 2);
1615 goto err;
1616 }
1617
1618 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
1619
1620 /* Allow time for programming before start_time is hit */
1621 current_time = ice_ptp_read_src_clk_reg(pf, NULL);
1622
1623 /* if start time is in the past start the timer at the nearest second
1624 * maintaining phase
1625 */
1626 if (start_time < current_time)
1627 start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
1628 NSEC_PER_SEC) * NSEC_PER_SEC + phase;
1629
1630 if (ice_is_e810(hw))
1631 start_time -= E810_OUT_PROP_DELAY_NS;
1632 else
1633 start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));
1634
1635 /* 2. Write TARGET time */
1636 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
1637 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
1638
1639 /* 3. Write AUX_OUT register */
1640 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
1641 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
1642
1643 /* 4. write GPIO CTL reg */
1644 func = 8 + chan + (tmr_idx * 4);
1645 val = GLGEN_GPIO_CTL_PIN_DIR_M |
1646 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M);
1647 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1648
1649 /* Store the value if requested */
1650 if (store) {
1651 memcpy(&pf->ptp.perout_channels[chan], config,
1652 sizeof(struct ice_perout_channel));
1653 pf->ptp.perout_channels[chan].start_time = phase;
1654 }
1655
1656 return 0;
1657err:
1658 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
1659 return -EFAULT;
1660}
1661
1662/**
1663 * ice_ptp_disable_all_clkout - Disable all currently configured outputs
1664 * @pf: pointer to the PF structure
1665 *
1666 * Disable all currently configured clock outputs. This is necessary before
1667 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
1668 * re-enable the clocks again.
1669 */
1670static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
1671{
1672 uint i;
1673
1674 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1675 if (pf->ptp.perout_channels[i].ena)
1676 ice_ptp_cfg_clkout(pf, i, NULL, false);
1677}
1678
1679/**
1680 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
1681 * @pf: pointer to the PF structure
1682 *
1683 * Enable all currently configured clock outputs. Use this after
1684 * ice_ptp_disable_all_clkout to reconfigure the output signals according to
1685 * their configuration.
1686 */
1687static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
1688{
1689 uint i;
1690
1691 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1692 if (pf->ptp.perout_channels[i].ena)
1693 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
1694 false);
1695}
1696
1697/**
1698 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
1699 * @info: the driver's PTP info structure
1700 * @rq: The requested feature to change
1701 * @on: Enable/disable flag
1702 */
1703static int
1704ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
1705 struct ptp_clock_request *rq, int on)
1706{
1707 struct ice_pf *pf = ptp_info_to_pf(info);
1708 struct ice_perout_channel clk_cfg = {0};
1709 bool sma_pres = false;
1710 unsigned int chan;
1711 u32 gpio_pin;
1712 int err;
1713
1714 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
1715 sma_pres = true;
1716
1717 switch (rq->type) {
1718 case PTP_CLK_REQ_PEROUT:
1719 chan = rq->perout.index;
1720 if (sma_pres) {
1721 if (chan == ice_pin_desc_e810t[SMA1].chan)
1722 clk_cfg.gpio_pin = GPIO_20;
1723 else if (chan == ice_pin_desc_e810t[SMA2].chan)
1724 clk_cfg.gpio_pin = GPIO_22;
1725 else
1726 return -1;
1727 } else if (ice_is_e810t(&pf->hw)) {
1728 if (chan == 0)
1729 clk_cfg.gpio_pin = GPIO_20;
1730 else
1731 clk_cfg.gpio_pin = GPIO_22;
1732 } else if (chan == PPS_CLK_GEN_CHAN) {
1733 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1734 } else {
1735 clk_cfg.gpio_pin = chan;
1736 }
1737
1738 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
1739 rq->perout.period.nsec);
1740 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
1741 rq->perout.start.nsec);
1742 clk_cfg.ena = !!on;
1743
1744 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
1745 break;
1746 case PTP_CLK_REQ_EXTTS:
1747 chan = rq->extts.index;
1748 if (sma_pres) {
1749 if (chan < ice_pin_desc_e810t[SMA2].chan)
1750 gpio_pin = GPIO_21;
1751 else
1752 gpio_pin = GPIO_23;
1753 } else if (ice_is_e810t(&pf->hw)) {
1754 if (chan == 0)
1755 gpio_pin = GPIO_21;
1756 else
1757 gpio_pin = GPIO_23;
1758 } else {
1759 gpio_pin = chan;
1760 }
1761
1762 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
1763 rq->extts.flags);
1764 break;
1765 default:
1766 return -EOPNOTSUPP;
1767 }
1768
1769 return err;
1770}
1771
1772/**
1773 * ice_ptp_gettimex64 - Get the time of the clock
1774 * @info: the driver's PTP info structure
1775 * @ts: timespec64 structure to hold the current time value
1776 * @sts: Optional parameter for holding a pair of system timestamps from
1777 * the system clock. Will be ignored if NULL is given.
1778 *
1779 * Read the device clock and return the correct value on ns, after converting it
1780 * into a timespec struct.
1781 */
1782static int
1783ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
1784 struct ptp_system_timestamp *sts)
1785{
1786 struct ice_pf *pf = ptp_info_to_pf(info);
1787 struct ice_hw *hw = &pf->hw;
1788
1789 if (!ice_ptp_lock(hw)) {
1790 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
1791 return -EBUSY;
1792 }
1793
1794 ice_ptp_read_time(pf, ts, sts);
1795 ice_ptp_unlock(hw);
1796
1797 return 0;
1798}
1799
1800/**
1801 * ice_ptp_settime64 - Set the time of the clock
1802 * @info: the driver's PTP info structure
1803 * @ts: timespec64 structure that holds the new time value
1804 *
1805 * Set the device clock to the user input value. The conversion from timespec
1806 * to ns happens in the write function.
1807 */
1808static int
1809ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
1810{
1811 struct ice_pf *pf = ptp_info_to_pf(info);
1812 struct timespec64 ts64 = *ts;
1813 struct ice_hw *hw = &pf->hw;
1814 int err;
1815
1816 /* For Vernier mode, we need to recalibrate after new settime
1817 * Start with disabling timestamp block
1818 */
1819 if (pf->ptp.port.link_up)
1820 ice_ptp_port_phy_stop(&pf->ptp.port);
1821
1822 if (!ice_ptp_lock(hw)) {
1823 err = -EBUSY;
1824 goto exit;
1825 }
1826
1827 /* Disable periodic outputs */
1828 ice_ptp_disable_all_clkout(pf);
1829
1830 err = ice_ptp_write_init(pf, &ts64);
1831 ice_ptp_unlock(hw);
1832
1833 if (!err)
1834 ice_ptp_reset_cached_phctime(pf);
1835
1836 /* Reenable periodic outputs */
1837 ice_ptp_enable_all_clkout(pf);
1838
1839 /* Recalibrate and re-enable timestamp block */
1840 if (pf->ptp.port.link_up)
1841 ice_ptp_port_phy_restart(&pf->ptp.port);
1842exit:
1843 if (err) {
1844 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
1845 return err;
1846 }
1847
1848 return 0;
1849}
1850
1851/**
1852 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
1853 * @info: the driver's PTP info structure
1854 * @delta: Offset in nanoseconds to adjust the time by
1855 */
1856static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
1857{
1858 struct timespec64 now, then;
1859 int ret;
1860
1861 then = ns_to_timespec64(delta);
1862 ret = ice_ptp_gettimex64(info, &now, NULL);
1863 if (ret)
1864 return ret;
1865 now = timespec64_add(now, then);
1866
1867 return ice_ptp_settime64(info, (const struct timespec64 *)&now);
1868}
1869
1870/**
1871 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
1872 * @info: the driver's PTP info structure
1873 * @delta: Offset in nanoseconds to adjust the time by
1874 */
1875static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
1876{
1877 struct ice_pf *pf = ptp_info_to_pf(info);
1878 struct ice_hw *hw = &pf->hw;
1879 struct device *dev;
1880 int err;
1881
1882 dev = ice_pf_to_dev(pf);
1883
1884 /* Hardware only supports atomic adjustments using signed 32-bit
1885 * integers. For any adjustment outside this range, perform
1886 * a non-atomic get->adjust->set flow.
1887 */
1888 if (delta > S32_MAX || delta < S32_MIN) {
1889 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
1890 return ice_ptp_adjtime_nonatomic(info, delta);
1891 }
1892
1893 if (!ice_ptp_lock(hw)) {
1894 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
1895 return -EBUSY;
1896 }
1897
1898 /* Disable periodic outputs */
1899 ice_ptp_disable_all_clkout(pf);
1900
1901 err = ice_ptp_write_adj(pf, delta);
1902
1903 /* Reenable periodic outputs */
1904 ice_ptp_enable_all_clkout(pf);
1905
1906 ice_ptp_unlock(hw);
1907
1908 if (err) {
1909 dev_err(dev, "PTP failed to adjust time, err %d\n", err);
1910 return err;
1911 }
1912
1913 ice_ptp_reset_cached_phctime(pf);
1914
1915 return 0;
1916}
1917
1918#ifdef CONFIG_ICE_HWTS
1919/**
1920 * ice_ptp_get_syncdevicetime - Get the cross time stamp info
1921 * @device: Current device time
1922 * @system: System counter value read synchronously with device time
1923 * @ctx: Context provided by timekeeping code
1924 *
1925 * Read device and system (ART) clock simultaneously and return the corrected
1926 * clock values in ns.
1927 */
1928static int
1929ice_ptp_get_syncdevicetime(ktime_t *device,
1930 struct system_counterval_t *system,
1931 void *ctx)
1932{
1933 struct ice_pf *pf = (struct ice_pf *)ctx;
1934 struct ice_hw *hw = &pf->hw;
1935 u32 hh_lock, hh_art_ctl;
1936 int i;
1937
1938 /* Get the HW lock */
1939 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1940 if (hh_lock & PFHH_SEM_BUSY_M) {
1941 dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n");
1942 return -EFAULT;
1943 }
1944
1945 /* Start the ART and device clock sync sequence */
1946 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1947 hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M;
1948 wr32(hw, GLHH_ART_CTL, hh_art_ctl);
1949
1950#define MAX_HH_LOCK_TRIES 100
1951
1952 for (i = 0; i < MAX_HH_LOCK_TRIES; i++) {
1953 /* Wait for sync to complete */
1954 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1955 if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) {
1956 udelay(1);
1957 continue;
1958 } else {
1959 u32 hh_ts_lo, hh_ts_hi, tmr_idx;
1960 u64 hh_ts;
1961
1962 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
1963 /* Read ART time */
1964 hh_ts_lo = rd32(hw, GLHH_ART_TIME_L);
1965 hh_ts_hi = rd32(hw, GLHH_ART_TIME_H);
1966 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1967 *system = convert_art_ns_to_tsc(hh_ts);
1968 /* Read Device source clock time */
1969 hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx));
1970 hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx));
1971 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1972 *device = ns_to_ktime(hh_ts);
1973 break;
1974 }
1975 }
1976 /* Release HW lock */
1977 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1978 hh_lock = hh_lock & ~PFHH_SEM_BUSY_M;
1979 wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock);
1980
1981 if (i == MAX_HH_LOCK_TRIES)
1982 return -ETIMEDOUT;
1983
1984 return 0;
1985}
1986
1987/**
1988 * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp
1989 * @info: the driver's PTP info structure
1990 * @cts: The memory to fill the cross timestamp info
1991 *
1992 * Capture a cross timestamp between the ART and the device PTP hardware
1993 * clock. Fill the cross timestamp information and report it back to the
1994 * caller.
1995 *
1996 * This is only valid for E822 devices which have support for generating the
1997 * cross timestamp via PCIe PTM.
1998 *
1999 * In order to correctly correlate the ART timestamp back to the TSC time, the
2000 * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
2001 */
2002static int
2003ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info,
2004 struct system_device_crosststamp *cts)
2005{
2006 struct ice_pf *pf = ptp_info_to_pf(info);
2007
2008 return get_device_system_crosststamp(ice_ptp_get_syncdevicetime,
2009 pf, NULL, cts);
2010}
2011#endif /* CONFIG_ICE_HWTS */
2012
2013/**
2014 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
2015 * @pf: Board private structure
2016 * @ifr: ioctl data
2017 *
2018 * Copy the timestamping config to user buffer
2019 */
2020int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2021{
2022 struct hwtstamp_config *config;
2023
2024 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2025 return -EIO;
2026
2027 config = &pf->ptp.tstamp_config;
2028
2029 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
2030 -EFAULT : 0;
2031}
2032
2033/**
2034 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
2035 * @pf: Board private structure
2036 * @config: hwtstamp settings requested or saved
2037 */
2038static int
2039ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
2040{
2041 switch (config->tx_type) {
2042 case HWTSTAMP_TX_OFF:
2043 ice_set_tx_tstamp(pf, false);
2044 break;
2045 case HWTSTAMP_TX_ON:
2046 ice_set_tx_tstamp(pf, true);
2047 break;
2048 default:
2049 return -ERANGE;
2050 }
2051
2052 switch (config->rx_filter) {
2053 case HWTSTAMP_FILTER_NONE:
2054 ice_set_rx_tstamp(pf, false);
2055 break;
2056 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2057 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2058 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2059 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2060 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2061 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2062 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2063 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2064 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2065 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2066 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2067 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2068 case HWTSTAMP_FILTER_NTP_ALL:
2069 case HWTSTAMP_FILTER_ALL:
2070 ice_set_rx_tstamp(pf, true);
2071 break;
2072 default:
2073 return -ERANGE;
2074 }
2075
2076 return 0;
2077}
2078
2079/**
2080 * ice_ptp_set_ts_config - ioctl interface to control the timestamping
2081 * @pf: Board private structure
2082 * @ifr: ioctl data
2083 *
2084 * Get the user config and store it
2085 */
2086int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2087{
2088 struct hwtstamp_config config;
2089 int err;
2090
2091 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2092 return -EAGAIN;
2093
2094 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2095 return -EFAULT;
2096
2097 err = ice_ptp_set_timestamp_mode(pf, &config);
2098 if (err)
2099 return err;
2100
2101 /* Return the actual configuration set */
2102 config = pf->ptp.tstamp_config;
2103
2104 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2105 -EFAULT : 0;
2106}
2107
2108/**
2109 * ice_ptp_rx_hwtstamp - Check for an Rx timestamp
2110 * @rx_ring: Ring to get the VSI info
2111 * @rx_desc: Receive descriptor
2112 * @skb: Particular skb to send timestamp with
2113 *
2114 * The driver receives a notification in the receive descriptor with timestamp.
2115 * The timestamp is in ns, so we must convert the result first.
2116 */
2117void
2118ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
2119 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb)
2120{
2121 struct skb_shared_hwtstamps *hwtstamps;
2122 u64 ts_ns, cached_time;
2123 u32 ts_high;
2124
2125 if (!(rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID))
2126 return;
2127
2128 cached_time = READ_ONCE(rx_ring->cached_phctime);
2129
2130 /* Do not report a timestamp if we don't have a cached PHC time */
2131 if (!cached_time)
2132 return;
2133
2134 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached
2135 * PHC value, rather than accessing the PF. This also allows us to
2136 * simply pass the upper 32bits of nanoseconds directly. Calling
2137 * ice_ptp_extend_40b_ts is unnecessary as it would just discard these
2138 * bits itself.
2139 */
2140 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
2141 ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high);
2142
2143 hwtstamps = skb_hwtstamps(skb);
2144 memset(hwtstamps, 0, sizeof(*hwtstamps));
2145 hwtstamps->hwtstamp = ns_to_ktime(ts_ns);
2146}
2147
2148/**
2149 * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
2150 * @pf: pointer to the PF structure
2151 * @info: PTP clock info structure
2152 *
2153 * Disable the OS access to the SMA pins. Called to clear out the OS
2154 * indications of pin support when we fail to setup the E810-T SMA control
2155 * register.
2156 */
2157static void
2158ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2159{
2160 struct device *dev = ice_pf_to_dev(pf);
2161
2162 dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
2163
2164 info->enable = NULL;
2165 info->verify = NULL;
2166 info->n_pins = 0;
2167 info->n_ext_ts = 0;
2168 info->n_per_out = 0;
2169}
2170
2171/**
2172 * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
2173 * @pf: pointer to the PF structure
2174 * @info: PTP clock info structure
2175 *
2176 * Finish setting up the SMA pins by allocating pin_config, and setting it up
2177 * according to the current status of the SMA. On failure, disable all of the
2178 * extended SMA pin support.
2179 */
2180static void
2181ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2182{
2183 struct device *dev = ice_pf_to_dev(pf);
2184 int err;
2185
2186 /* Allocate memory for kernel pins interface */
2187 info->pin_config = devm_kcalloc(dev, info->n_pins,
2188 sizeof(*info->pin_config), GFP_KERNEL);
2189 if (!info->pin_config) {
2190 ice_ptp_disable_sma_pins_e810t(pf, info);
2191 return;
2192 }
2193
2194 /* Read current SMA status */
2195 err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
2196 if (err)
2197 ice_ptp_disable_sma_pins_e810t(pf, info);
2198}
2199
2200/**
2201 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
2202 * @pf: pointer to the PF instance
2203 * @info: PTP clock capabilities
2204 */
2205static void
2206ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2207{
2208 info->n_per_out = N_PER_OUT_E810;
2209
2210 if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS))
2211 info->n_ext_ts = N_EXT_TS_E810;
2212
2213 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
2214 info->n_ext_ts = N_EXT_TS_E810;
2215 info->n_pins = NUM_PTP_PINS_E810T;
2216 info->verify = ice_verify_pin_e810t;
2217
2218 /* Complete setup of the SMA pins */
2219 ice_ptp_setup_sma_pins_e810t(pf, info);
2220 }
2221}
2222
2223/**
2224 * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support
2225 * @pf: Board private structure
2226 * @info: PTP info to fill
2227 *
2228 * Assign functions to the PTP capabiltiies structure for E822 devices.
2229 * Functions which operate across all device families should be set directly
2230 * in ice_ptp_set_caps. Only add functions here which are distinct for E822
2231 * devices.
2232 */
2233static void
2234ice_ptp_set_funcs_e822(struct ice_pf *pf, struct ptp_clock_info *info)
2235{
2236#ifdef CONFIG_ICE_HWTS
2237 if (boot_cpu_has(X86_FEATURE_ART) &&
2238 boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
2239 info->getcrosststamp = ice_ptp_getcrosststamp_e822;
2240#endif /* CONFIG_ICE_HWTS */
2241}
2242
2243/**
2244 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
2245 * @pf: Board private structure
2246 * @info: PTP info to fill
2247 *
2248 * Assign functions to the PTP capabiltiies structure for E810 devices.
2249 * Functions which operate across all device families should be set directly
2250 * in ice_ptp_set_caps. Only add functions here which are distinct for e810
2251 * devices.
2252 */
2253static void
2254ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2255{
2256 info->enable = ice_ptp_gpio_enable_e810;
2257 ice_ptp_setup_pins_e810(pf, info);
2258}
2259
2260/**
2261 * ice_ptp_set_caps - Set PTP capabilities
2262 * @pf: Board private structure
2263 */
2264static void ice_ptp_set_caps(struct ice_pf *pf)
2265{
2266 struct ptp_clock_info *info = &pf->ptp.info;
2267 struct device *dev = ice_pf_to_dev(pf);
2268
2269 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
2270 dev_driver_string(dev), dev_name(dev));
2271 info->owner = THIS_MODULE;
2272 info->max_adj = 999999999;
2273 info->adjtime = ice_ptp_adjtime;
2274 info->adjfine = ice_ptp_adjfine;
2275 info->gettimex64 = ice_ptp_gettimex64;
2276 info->settime64 = ice_ptp_settime64;
2277
2278 if (ice_is_e810(&pf->hw))
2279 ice_ptp_set_funcs_e810(pf, info);
2280 else
2281 ice_ptp_set_funcs_e822(pf, info);
2282}
2283
2284/**
2285 * ice_ptp_create_clock - Create PTP clock device for userspace
2286 * @pf: Board private structure
2287 *
2288 * This function creates a new PTP clock device. It only creates one if we
2289 * don't already have one. Will return error if it can't create one, but success
2290 * if we already have a device. Should be used by ice_ptp_init to create clock
2291 * initially, and prevent global resets from creating new clock devices.
2292 */
2293static long ice_ptp_create_clock(struct ice_pf *pf)
2294{
2295 struct ptp_clock_info *info;
2296 struct ptp_clock *clock;
2297 struct device *dev;
2298
2299 /* No need to create a clock device if we already have one */
2300 if (pf->ptp.clock)
2301 return 0;
2302
2303 ice_ptp_set_caps(pf);
2304
2305 info = &pf->ptp.info;
2306 dev = ice_pf_to_dev(pf);
2307
2308 /* Attempt to register the clock before enabling the hardware. */
2309 clock = ptp_clock_register(info, dev);
2310 if (IS_ERR(clock))
2311 return PTR_ERR(clock);
2312
2313 pf->ptp.clock = clock;
2314
2315 return 0;
2316}
2317
2318/**
2319 * ice_ptp_request_ts - Request an available Tx timestamp index
2320 * @tx: the PTP Tx timestamp tracker to request from
2321 * @skb: the SKB to associate with this timestamp request
2322 */
2323s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
2324{
2325 u8 idx;
2326
2327 spin_lock(&tx->lock);
2328
2329 /* Check that this tracker is accepting new timestamp requests */
2330 if (!ice_ptp_is_tx_tracker_up(tx)) {
2331 spin_unlock(&tx->lock);
2332 return -1;
2333 }
2334
2335 /* Find and set the first available index */
2336 idx = find_first_zero_bit(tx->in_use, tx->len);
2337 if (idx < tx->len) {
2338 /* We got a valid index that no other thread could have set. Store
2339 * a reference to the skb and the start time to allow discarding old
2340 * requests.
2341 */
2342 set_bit(idx, tx->in_use);
2343 clear_bit(idx, tx->stale);
2344 tx->tstamps[idx].start = jiffies;
2345 tx->tstamps[idx].skb = skb_get(skb);
2346 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2347 ice_trace(tx_tstamp_request, skb, idx);
2348 }
2349
2350 spin_unlock(&tx->lock);
2351
2352 /* return the appropriate PHY timestamp register index, -1 if no
2353 * indexes were available.
2354 */
2355 if (idx >= tx->len)
2356 return -1;
2357 else
2358 return idx + tx->offset;
2359}
2360
2361/**
2362 * ice_ptp_process_ts - Process the PTP Tx timestamps
2363 * @pf: Board private structure
2364 *
2365 * Returns true if timestamps are processed.
2366 */
2367bool ice_ptp_process_ts(struct ice_pf *pf)
2368{
2369 return ice_ptp_tx_tstamp(&pf->ptp.port.tx);
2370}
2371
2372static void ice_ptp_periodic_work(struct kthread_work *work)
2373{
2374 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
2375 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
2376 int err;
2377
2378 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2379 return;
2380
2381 err = ice_ptp_update_cached_phctime(pf);
2382
2383 /* Run twice a second or reschedule if phc update failed */
2384 kthread_queue_delayed_work(ptp->kworker, &ptp->work,
2385 msecs_to_jiffies(err ? 10 : 500));
2386}
2387
2388/**
2389 * ice_ptp_reset - Initialize PTP hardware clock support after reset
2390 * @pf: Board private structure
2391 */
2392void ice_ptp_reset(struct ice_pf *pf)
2393{
2394 struct ice_ptp *ptp = &pf->ptp;
2395 struct ice_hw *hw = &pf->hw;
2396 struct timespec64 ts;
2397 int err, itr = 1;
2398 u64 time_diff;
2399
2400 if (test_bit(ICE_PFR_REQ, pf->state))
2401 goto pfr;
2402
2403 if (!hw->func_caps.ts_func_info.src_tmr_owned)
2404 goto reset_ts;
2405
2406 err = ice_ptp_init_phc(hw);
2407 if (err)
2408 goto err;
2409
2410 /* Acquire the global hardware lock */
2411 if (!ice_ptp_lock(hw)) {
2412 err = -EBUSY;
2413 goto err;
2414 }
2415
2416 /* Write the increment time value to PHY and LAN */
2417 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2418 if (err) {
2419 ice_ptp_unlock(hw);
2420 goto err;
2421 }
2422
2423 /* Write the initial Time value to PHY and LAN using the cached PHC
2424 * time before the reset and time difference between stopping and
2425 * starting the clock.
2426 */
2427 if (ptp->cached_phc_time) {
2428 time_diff = ktime_get_real_ns() - ptp->reset_time;
2429 ts = ns_to_timespec64(ptp->cached_phc_time + time_diff);
2430 } else {
2431 ts = ktime_to_timespec64(ktime_get_real());
2432 }
2433 err = ice_ptp_write_init(pf, &ts);
2434 if (err) {
2435 ice_ptp_unlock(hw);
2436 goto err;
2437 }
2438
2439 /* Release the global hardware lock */
2440 ice_ptp_unlock(hw);
2441
2442 if (!ice_is_e810(hw)) {
2443 /* Enable quad interrupts */
2444 err = ice_ptp_tx_ena_intr(pf, true, itr);
2445 if (err)
2446 goto err;
2447 }
2448
2449reset_ts:
2450 /* Restart the PHY timestamping block */
2451 ice_ptp_reset_phy_timestamping(pf);
2452
2453pfr:
2454 /* Init Tx structures */
2455 if (ice_is_e810(&pf->hw)) {
2456 err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);
2457 } else {
2458 kthread_init_delayed_work(&ptp->port.ov_work,
2459 ice_ptp_wait_for_offsets);
2460 err = ice_ptp_init_tx_e822(pf, &ptp->port.tx,
2461 ptp->port.port_num);
2462 }
2463 if (err)
2464 goto err;
2465
2466 set_bit(ICE_FLAG_PTP, pf->flags);
2467
2468 /* Start periodic work going */
2469 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2470
2471 dev_info(ice_pf_to_dev(pf), "PTP reset successful\n");
2472 return;
2473
2474err:
2475 dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err);
2476}
2477
2478/**
2479 * ice_ptp_prepare_for_reset - Prepare PTP for reset
2480 * @pf: Board private structure
2481 */
2482void ice_ptp_prepare_for_reset(struct ice_pf *pf)
2483{
2484 struct ice_ptp *ptp = &pf->ptp;
2485 u8 src_tmr;
2486
2487 clear_bit(ICE_FLAG_PTP, pf->flags);
2488
2489 /* Disable timestamping for both Tx and Rx */
2490 ice_ptp_cfg_timestamp(pf, false);
2491
2492 kthread_cancel_delayed_work_sync(&ptp->work);
2493 kthread_cancel_work_sync(&ptp->extts_work);
2494
2495 if (test_bit(ICE_PFR_REQ, pf->state))
2496 return;
2497
2498 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2499
2500 /* Disable periodic outputs */
2501 ice_ptp_disable_all_clkout(pf);
2502
2503 src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
2504
2505 /* Disable source clock */
2506 wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
2507
2508 /* Acquire PHC and system timer to restore after reset */
2509 ptp->reset_time = ktime_get_real_ns();
2510}
2511
2512/**
2513 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
2514 * @pf: Board private structure
2515 *
2516 * Setup and initialize a PTP clock device that represents the device hardware
2517 * clock. Save the clock index for other functions connected to the same
2518 * hardware resource.
2519 */
2520static int ice_ptp_init_owner(struct ice_pf *pf)
2521{
2522 struct ice_hw *hw = &pf->hw;
2523 struct timespec64 ts;
2524 int err, itr = 1;
2525
2526 err = ice_ptp_init_phc(hw);
2527 if (err) {
2528 dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
2529 err);
2530 return err;
2531 }
2532
2533 /* Acquire the global hardware lock */
2534 if (!ice_ptp_lock(hw)) {
2535 err = -EBUSY;
2536 goto err_exit;
2537 }
2538
2539 /* Write the increment time value to PHY and LAN */
2540 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2541 if (err) {
2542 ice_ptp_unlock(hw);
2543 goto err_exit;
2544 }
2545
2546 ts = ktime_to_timespec64(ktime_get_real());
2547 /* Write the initial Time value to PHY and LAN */
2548 err = ice_ptp_write_init(pf, &ts);
2549 if (err) {
2550 ice_ptp_unlock(hw);
2551 goto err_exit;
2552 }
2553
2554 /* Release the global hardware lock */
2555 ice_ptp_unlock(hw);
2556
2557 if (!ice_is_e810(hw)) {
2558 /* Enable quad interrupts */
2559 err = ice_ptp_tx_ena_intr(pf, true, itr);
2560 if (err)
2561 goto err_exit;
2562 }
2563
2564 /* Ensure we have a clock device */
2565 err = ice_ptp_create_clock(pf);
2566 if (err)
2567 goto err_clk;
2568
2569 /* Store the PTP clock index for other PFs */
2570 ice_set_ptp_clock_index(pf);
2571
2572 return 0;
2573
2574err_clk:
2575 pf->ptp.clock = NULL;
2576err_exit:
2577 return err;
2578}
2579
2580/**
2581 * ice_ptp_init_work - Initialize PTP work threads
2582 * @pf: Board private structure
2583 * @ptp: PF PTP structure
2584 */
2585static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
2586{
2587 struct kthread_worker *kworker;
2588
2589 /* Initialize work functions */
2590 kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work);
2591 kthread_init_work(&ptp->extts_work, ice_ptp_extts_work);
2592
2593 /* Allocate a kworker for handling work required for the ports
2594 * connected to the PTP hardware clock.
2595 */
2596 kworker = kthread_create_worker(0, "ice-ptp-%s",
2597 dev_name(ice_pf_to_dev(pf)));
2598 if (IS_ERR(kworker))
2599 return PTR_ERR(kworker);
2600
2601 ptp->kworker = kworker;
2602
2603 /* Start periodic work going */
2604 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2605
2606 return 0;
2607}
2608
2609/**
2610 * ice_ptp_init_port - Initialize PTP port structure
2611 * @pf: Board private structure
2612 * @ptp_port: PTP port structure
2613 */
2614static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
2615{
2616 mutex_init(&ptp_port->ps_lock);
2617
2618 if (ice_is_e810(&pf->hw))
2619 return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
2620
2621 kthread_init_delayed_work(&ptp_port->ov_work,
2622 ice_ptp_wait_for_offsets);
2623 return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num);
2624}
2625
2626/**
2627 * ice_ptp_init - Initialize PTP hardware clock support
2628 * @pf: Board private structure
2629 *
2630 * Set up the device for interacting with the PTP hardware clock for all
2631 * functions, both the function that owns the clock hardware, and the
2632 * functions connected to the clock hardware.
2633 *
2634 * The clock owner will allocate and register a ptp_clock with the
2635 * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
2636 * items used for asynchronous work such as Tx timestamps and periodic work.
2637 */
2638void ice_ptp_init(struct ice_pf *pf)
2639{
2640 struct ice_ptp *ptp = &pf->ptp;
2641 struct ice_hw *hw = &pf->hw;
2642 int err;
2643
2644 /* If this function owns the clock hardware, it must allocate and
2645 * configure the PTP clock device to represent it.
2646 */
2647 if (hw->func_caps.ts_func_info.src_tmr_owned) {
2648 err = ice_ptp_init_owner(pf);
2649 if (err)
2650 goto err;
2651 }
2652
2653 ptp->port.port_num = hw->pf_id;
2654 err = ice_ptp_init_port(pf, &ptp->port);
2655 if (err)
2656 goto err;
2657
2658 /* Start the PHY timestamping block */
2659 ice_ptp_reset_phy_timestamping(pf);
2660
2661 set_bit(ICE_FLAG_PTP, pf->flags);
2662 err = ice_ptp_init_work(pf, ptp);
2663 if (err)
2664 goto err;
2665
2666 dev_info(ice_pf_to_dev(pf), "PTP init successful\n");
2667 return;
2668
2669err:
2670 /* If we registered a PTP clock, release it */
2671 if (pf->ptp.clock) {
2672 ptp_clock_unregister(ptp->clock);
2673 pf->ptp.clock = NULL;
2674 }
2675 clear_bit(ICE_FLAG_PTP, pf->flags);
2676 dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err);
2677}
2678
2679/**
2680 * ice_ptp_release - Disable the driver/HW support and unregister the clock
2681 * @pf: Board private structure
2682 *
2683 * This function handles the cleanup work required from the initialization by
2684 * clearing out the important information and unregistering the clock
2685 */
2686void ice_ptp_release(struct ice_pf *pf)
2687{
2688 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2689 return;
2690
2691 /* Disable timestamping for both Tx and Rx */
2692 ice_ptp_cfg_timestamp(pf, false);
2693
2694 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2695
2696 clear_bit(ICE_FLAG_PTP, pf->flags);
2697
2698 kthread_cancel_delayed_work_sync(&pf->ptp.work);
2699
2700 ice_ptp_port_phy_stop(&pf->ptp.port);
2701 mutex_destroy(&pf->ptp.port.ps_lock);
2702 if (pf->ptp.kworker) {
2703 kthread_destroy_worker(pf->ptp.kworker);
2704 pf->ptp.kworker = NULL;
2705 }
2706
2707 if (!pf->ptp.clock)
2708 return;
2709
2710 /* Disable periodic outputs */
2711 ice_ptp_disable_all_clkout(pf);
2712
2713 ice_clear_ptp_clock_index(pf);
2714 ptp_clock_unregister(pf->ptp.clock);
2715 pf->ptp.clock = NULL;
2716
2717 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");
2718}