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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020-2021 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "i915_trace.h"
8#include "intel_display_types.h"
9#include "intel_dp_aux.h"
10#include "intel_pps.h"
11#include "intel_tc.h"
12
13u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
14{
15 int i;
16 u32 v = 0;
17
18 if (src_bytes > 4)
19 src_bytes = 4;
20 for (i = 0; i < src_bytes; i++)
21 v |= ((u32)src[i]) << ((3 - i) * 8);
22 return v;
23}
24
25static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
26{
27 int i;
28
29 if (dst_bytes > 4)
30 dst_bytes = 4;
31 for (i = 0; i < dst_bytes; i++)
32 dst[i] = src >> ((3 - i) * 8);
33}
34
35static u32
36intel_dp_aux_wait_done(struct intel_dp *intel_dp)
37{
38 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
39 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
40 const unsigned int timeout_ms = 10;
41 u32 status;
42 bool done;
43
44#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
45 done = wait_event_timeout(i915->gmbus_wait_queue, C,
46 msecs_to_jiffies_timeout(timeout_ms));
47
48 /* just trace the final value */
49 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
50
51 if (!done)
52 drm_err(&i915->drm,
53 "%s: did not complete or timeout within %ums (status 0x%08x)\n",
54 intel_dp->aux.name, timeout_ms, status);
55#undef C
56
57 return status;
58}
59
60static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
61{
62 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
63
64 if (index)
65 return 0;
66
67 /*
68 * The clock divider is based off the hrawclk, and would like to run at
69 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
70 */
71 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
72}
73
74static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
75{
76 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
77 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
78 u32 freq;
79
80 if (index)
81 return 0;
82
83 /*
84 * The clock divider is based off the cdclk or PCH rawclk, and would
85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
86 * divide by 2000 and use that
87 */
88 if (dig_port->aux_ch == AUX_CH_A)
89 freq = dev_priv->cdclk.hw.cdclk;
90 else
91 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
92 return DIV_ROUND_CLOSEST(freq, 2000);
93}
94
95static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
96{
97 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
98 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
99
100 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
101 /* Workaround for non-ULT HSW */
102 switch (index) {
103 case 0: return 63;
104 case 1: return 72;
105 default: return 0;
106 }
107 }
108
109 return ilk_get_aux_clock_divider(intel_dp, index);
110}
111
112static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
113{
114 /*
115 * SKL doesn't need us to program the AUX clock divider (Hardware will
116 * derive the clock from CDCLK automatically). We still implement the
117 * get_aux_clock_divider vfunc to plug-in into the existing code.
118 */
119 return index ? 0 : 1;
120}
121
122static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
123 int send_bytes,
124 u32 aux_clock_divider)
125{
126 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
127 struct drm_i915_private *dev_priv =
128 to_i915(dig_port->base.base.dev);
129 u32 timeout;
130
131 /* Max timeout value on G4x-BDW: 1.6ms */
132 if (IS_BROADWELL(dev_priv))
133 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
134 else
135 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
136
137 return DP_AUX_CH_CTL_SEND_BUSY |
138 DP_AUX_CH_CTL_DONE |
139 DP_AUX_CH_CTL_INTERRUPT |
140 DP_AUX_CH_CTL_TIME_OUT_ERROR |
141 timeout |
142 DP_AUX_CH_CTL_RECEIVE_ERROR |
143 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
144 (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
145 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
146}
147
148static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
149 int send_bytes,
150 u32 unused)
151{
152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
153 struct drm_i915_private *i915 =
154 to_i915(dig_port->base.base.dev);
155 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
156 u32 ret;
157
158 /*
159 * Max timeout values:
160 * SKL-GLK: 1.6ms
161 * CNL: 3.2ms
162 * ICL+: 4ms
163 */
164 ret = DP_AUX_CH_CTL_SEND_BUSY |
165 DP_AUX_CH_CTL_DONE |
166 DP_AUX_CH_CTL_INTERRUPT |
167 DP_AUX_CH_CTL_TIME_OUT_ERROR |
168 DP_AUX_CH_CTL_TIME_OUT_MAX |
169 DP_AUX_CH_CTL_RECEIVE_ERROR |
170 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
171 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
172 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
173
174 if (intel_phy_is_tc(i915, phy) &&
175 dig_port->tc_mode == TC_PORT_TBT_ALT)
176 ret |= DP_AUX_CH_CTL_TBT_IO;
177
178 return ret;
179}
180
181static int
182intel_dp_aux_xfer(struct intel_dp *intel_dp,
183 const u8 *send, int send_bytes,
184 u8 *recv, int recv_size,
185 u32 aux_send_ctl_flags)
186{
187 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
188 struct drm_i915_private *i915 =
189 to_i915(dig_port->base.base.dev);
190 struct intel_uncore *uncore = &i915->uncore;
191 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
192 bool is_tc_port = intel_phy_is_tc(i915, phy);
193 i915_reg_t ch_ctl, ch_data[5];
194 u32 aux_clock_divider;
195 enum intel_display_power_domain aux_domain;
196 intel_wakeref_t aux_wakeref;
197 intel_wakeref_t pps_wakeref;
198 int i, ret, recv_bytes;
199 int try, clock = 0;
200 u32 status;
201 bool vdd;
202
203 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
204 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
205 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
206
207 if (is_tc_port)
208 intel_tc_port_lock(dig_port);
209
210 aux_domain = intel_aux_power_domain(dig_port);
211
212 aux_wakeref = intel_display_power_get(i915, aux_domain);
213 pps_wakeref = intel_pps_lock(intel_dp);
214
215 /*
216 * We will be called with VDD already enabled for dpcd/edid/oui reads.
217 * In such cases we want to leave VDD enabled and it's up to upper layers
218 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
219 * ourselves.
220 */
221 vdd = intel_pps_vdd_on_unlocked(intel_dp);
222
223 /*
224 * dp aux is extremely sensitive to irq latency, hence request the
225 * lowest possible wakeup latency and so prevent the cpu from going into
226 * deep sleep states.
227 */
228 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
229
230 intel_pps_check_power_unlocked(intel_dp);
231
232 /* Try to wait for any previous AUX channel activity */
233 for (try = 0; try < 3; try++) {
234 status = intel_uncore_read_notrace(uncore, ch_ctl);
235 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
236 break;
237 msleep(1);
238 }
239 /* just trace the final value */
240 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
241
242 if (try == 3) {
243 const u32 status = intel_uncore_read(uncore, ch_ctl);
244
245 if (status != intel_dp->aux_busy_last_status) {
246 drm_WARN(&i915->drm, 1,
247 "%s: not started (status 0x%08x)\n",
248 intel_dp->aux.name, status);
249 intel_dp->aux_busy_last_status = status;
250 }
251
252 ret = -EBUSY;
253 goto out;
254 }
255
256 /* Only 5 data registers! */
257 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
258 ret = -E2BIG;
259 goto out;
260 }
261
262 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
263 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
264 send_bytes,
265 aux_clock_divider);
266
267 send_ctl |= aux_send_ctl_flags;
268
269 /* Must try at least 3 times according to DP spec */
270 for (try = 0; try < 5; try++) {
271 /* Load the send data into the aux channel data registers */
272 for (i = 0; i < send_bytes; i += 4)
273 intel_uncore_write(uncore,
274 ch_data[i >> 2],
275 intel_dp_pack_aux(send + i,
276 send_bytes - i));
277
278 /* Send the command and wait for it to complete */
279 intel_uncore_write(uncore, ch_ctl, send_ctl);
280
281 status = intel_dp_aux_wait_done(intel_dp);
282
283 /* Clear done status and any errors */
284 intel_uncore_write(uncore,
285 ch_ctl,
286 status |
287 DP_AUX_CH_CTL_DONE |
288 DP_AUX_CH_CTL_TIME_OUT_ERROR |
289 DP_AUX_CH_CTL_RECEIVE_ERROR);
290
291 /*
292 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
293 * 400us delay required for errors and timeouts
294 * Timeout errors from the HW already meet this
295 * requirement so skip to next iteration
296 */
297 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
298 continue;
299
300 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
301 usleep_range(400, 500);
302 continue;
303 }
304 if (status & DP_AUX_CH_CTL_DONE)
305 goto done;
306 }
307 }
308
309 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
310 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
311 intel_dp->aux.name, status);
312 ret = -EBUSY;
313 goto out;
314 }
315
316done:
317 /*
318 * Check for timeout or receive error. Timeouts occur when the sink is
319 * not connected.
320 */
321 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
322 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
323 intel_dp->aux.name, status);
324 ret = -EIO;
325 goto out;
326 }
327
328 /*
329 * Timeouts occur when the device isn't connected, so they're "normal"
330 * -- don't fill the kernel log with these
331 */
332 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
333 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
334 intel_dp->aux.name, status);
335 ret = -ETIMEDOUT;
336 goto out;
337 }
338
339 /* Unload any bytes sent back from the other side */
340 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
341 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
342
343 /*
344 * By BSpec: "Message sizes of 0 or >20 are not allowed."
345 * We have no idea of what happened so we return -EBUSY so
346 * drm layer takes care for the necessary retries.
347 */
348 if (recv_bytes == 0 || recv_bytes > 20) {
349 drm_dbg_kms(&i915->drm,
350 "%s: Forbidden recv_bytes = %d on aux transaction\n",
351 intel_dp->aux.name, recv_bytes);
352 ret = -EBUSY;
353 goto out;
354 }
355
356 if (recv_bytes > recv_size)
357 recv_bytes = recv_size;
358
359 for (i = 0; i < recv_bytes; i += 4)
360 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
361 recv + i, recv_bytes - i);
362
363 ret = recv_bytes;
364out:
365 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
366
367 if (vdd)
368 intel_pps_vdd_off_unlocked(intel_dp, false);
369
370 intel_pps_unlock(intel_dp, pps_wakeref);
371 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
372
373 if (is_tc_port)
374 intel_tc_port_unlock(dig_port);
375
376 return ret;
377}
378
379#define BARE_ADDRESS_SIZE 3
380#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
381
382static void
383intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
384 const struct drm_dp_aux_msg *msg)
385{
386 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
387 txbuf[1] = (msg->address >> 8) & 0xff;
388 txbuf[2] = msg->address & 0xff;
389 txbuf[3] = msg->size - 1;
390}
391
392static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
393{
394 /*
395 * If we're trying to send the HDCP Aksv, we need to set a the Aksv
396 * select bit to inform the hardware to send the Aksv after our header
397 * since we can't access that data from software.
398 */
399 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
400 msg->address == DP_AUX_HDCP_AKSV)
401 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
402
403 return 0;
404}
405
406static ssize_t
407intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
408{
409 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
410 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
411 u8 txbuf[20], rxbuf[20];
412 size_t txsize, rxsize;
413 u32 flags = intel_dp_aux_xfer_flags(msg);
414 int ret;
415
416 intel_dp_aux_header(txbuf, msg);
417
418 switch (msg->request & ~DP_AUX_I2C_MOT) {
419 case DP_AUX_NATIVE_WRITE:
420 case DP_AUX_I2C_WRITE:
421 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
422 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
423 rxsize = 2; /* 0 or 1 data bytes */
424
425 if (drm_WARN_ON(&i915->drm, txsize > 20))
426 return -E2BIG;
427
428 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
429
430 if (msg->buffer)
431 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
432
433 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
434 rxbuf, rxsize, flags);
435 if (ret > 0) {
436 msg->reply = rxbuf[0] >> 4;
437
438 if (ret > 1) {
439 /* Number of bytes written in a short write. */
440 ret = clamp_t(int, rxbuf[1], 0, msg->size);
441 } else {
442 /* Return payload size. */
443 ret = msg->size;
444 }
445 }
446 break;
447
448 case DP_AUX_NATIVE_READ:
449 case DP_AUX_I2C_READ:
450 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
451 rxsize = msg->size + 1;
452
453 if (drm_WARN_ON(&i915->drm, rxsize > 20))
454 return -E2BIG;
455
456 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
457 rxbuf, rxsize, flags);
458 if (ret > 0) {
459 msg->reply = rxbuf[0] >> 4;
460 /*
461 * Assume happy day, and copy the data. The caller is
462 * expected to check msg->reply before touching it.
463 *
464 * Return payload size.
465 */
466 ret--;
467 memcpy(msg->buffer, rxbuf + 1, ret);
468 }
469 break;
470
471 default:
472 ret = -EINVAL;
473 break;
474 }
475
476 return ret;
477}
478
479static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
480{
481 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
482 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
483 enum aux_ch aux_ch = dig_port->aux_ch;
484
485 switch (aux_ch) {
486 case AUX_CH_B:
487 case AUX_CH_C:
488 case AUX_CH_D:
489 return DP_AUX_CH_CTL(aux_ch);
490 default:
491 MISSING_CASE(aux_ch);
492 return DP_AUX_CH_CTL(AUX_CH_B);
493 }
494}
495
496static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
497{
498 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
499 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
500 enum aux_ch aux_ch = dig_port->aux_ch;
501
502 switch (aux_ch) {
503 case AUX_CH_B:
504 case AUX_CH_C:
505 case AUX_CH_D:
506 return DP_AUX_CH_DATA(aux_ch, index);
507 default:
508 MISSING_CASE(aux_ch);
509 return DP_AUX_CH_DATA(AUX_CH_B, index);
510 }
511}
512
513static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
514{
515 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
516 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
517 enum aux_ch aux_ch = dig_port->aux_ch;
518
519 switch (aux_ch) {
520 case AUX_CH_A:
521 return DP_AUX_CH_CTL(aux_ch);
522 case AUX_CH_B:
523 case AUX_CH_C:
524 case AUX_CH_D:
525 return PCH_DP_AUX_CH_CTL(aux_ch);
526 default:
527 MISSING_CASE(aux_ch);
528 return DP_AUX_CH_CTL(AUX_CH_A);
529 }
530}
531
532static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
533{
534 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
535 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
536 enum aux_ch aux_ch = dig_port->aux_ch;
537
538 switch (aux_ch) {
539 case AUX_CH_A:
540 return DP_AUX_CH_DATA(aux_ch, index);
541 case AUX_CH_B:
542 case AUX_CH_C:
543 case AUX_CH_D:
544 return PCH_DP_AUX_CH_DATA(aux_ch, index);
545 default:
546 MISSING_CASE(aux_ch);
547 return DP_AUX_CH_DATA(AUX_CH_A, index);
548 }
549}
550
551static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
552{
553 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
554 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
555 enum aux_ch aux_ch = dig_port->aux_ch;
556
557 switch (aux_ch) {
558 case AUX_CH_A:
559 case AUX_CH_B:
560 case AUX_CH_C:
561 case AUX_CH_D:
562 case AUX_CH_E:
563 case AUX_CH_F:
564 return DP_AUX_CH_CTL(aux_ch);
565 default:
566 MISSING_CASE(aux_ch);
567 return DP_AUX_CH_CTL(AUX_CH_A);
568 }
569}
570
571static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
572{
573 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
574 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
575 enum aux_ch aux_ch = dig_port->aux_ch;
576
577 switch (aux_ch) {
578 case AUX_CH_A:
579 case AUX_CH_B:
580 case AUX_CH_C:
581 case AUX_CH_D:
582 case AUX_CH_E:
583 case AUX_CH_F:
584 return DP_AUX_CH_DATA(aux_ch, index);
585 default:
586 MISSING_CASE(aux_ch);
587 return DP_AUX_CH_DATA(AUX_CH_A, index);
588 }
589}
590
591static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
592{
593 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
594 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
595 enum aux_ch aux_ch = dig_port->aux_ch;
596
597 switch (aux_ch) {
598 case AUX_CH_A:
599 case AUX_CH_B:
600 case AUX_CH_C:
601 case AUX_CH_USBC1:
602 case AUX_CH_USBC2:
603 case AUX_CH_USBC3:
604 case AUX_CH_USBC4:
605 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
606 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
607 return DP_AUX_CH_CTL(aux_ch);
608 default:
609 MISSING_CASE(aux_ch);
610 return DP_AUX_CH_CTL(AUX_CH_A);
611 }
612}
613
614static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
615{
616 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
617 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
618 enum aux_ch aux_ch = dig_port->aux_ch;
619
620 switch (aux_ch) {
621 case AUX_CH_A:
622 case AUX_CH_B:
623 case AUX_CH_C:
624 case AUX_CH_USBC1:
625 case AUX_CH_USBC2:
626 case AUX_CH_USBC3:
627 case AUX_CH_USBC4:
628 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
629 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
630 return DP_AUX_CH_DATA(aux_ch, index);
631 default:
632 MISSING_CASE(aux_ch);
633 return DP_AUX_CH_DATA(AUX_CH_A, index);
634 }
635}
636
637void intel_dp_aux_fini(struct intel_dp *intel_dp)
638{
639 if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
640 cpu_latency_qos_remove_request(&intel_dp->pm_qos);
641
642 kfree(intel_dp->aux.name);
643}
644
645void intel_dp_aux_init(struct intel_dp *intel_dp)
646{
647 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
648 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
649 struct intel_encoder *encoder = &dig_port->base;
650 enum aux_ch aux_ch = dig_port->aux_ch;
651
652 if (DISPLAY_VER(dev_priv) >= 12) {
653 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
654 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
655 } else if (DISPLAY_VER(dev_priv) >= 9) {
656 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
657 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
658 } else if (HAS_PCH_SPLIT(dev_priv)) {
659 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
660 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
661 } else {
662 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
663 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
664 }
665
666 if (DISPLAY_VER(dev_priv) >= 9)
667 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
668 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
669 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
670 else if (HAS_PCH_SPLIT(dev_priv))
671 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
672 else
673 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
674
675 if (DISPLAY_VER(dev_priv) >= 9)
676 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
677 else
678 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
679
680 intel_dp->aux.drm_dev = &dev_priv->drm;
681 drm_dp_aux_init(&intel_dp->aux);
682
683 /* Failure to allocate our preferred name is not critical */
684 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
685 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
686 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
687 encoder->base.name);
688 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
689 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
690 aux_ch - AUX_CH_USBC1 + '1',
691 encoder->base.name);
692 else
693 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
694 aux_ch_name(aux_ch),
695 encoder->base.name);
696
697 intel_dp->aux.transfer = intel_dp_aux_transfer;
698 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
699}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020-2021 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "i915_reg.h"
8#include "i915_trace.h"
9#include "intel_display_types.h"
10#include "intel_dp_aux.h"
11#include "intel_pps.h"
12#include "intel_tc.h"
13
14static u32 intel_dp_aux_pack(const u8 *src, int src_bytes)
15{
16 int i;
17 u32 v = 0;
18
19 if (src_bytes > 4)
20 src_bytes = 4;
21 for (i = 0; i < src_bytes; i++)
22 v |= ((u32)src[i]) << ((3 - i) * 8);
23 return v;
24}
25
26static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes)
27{
28 int i;
29
30 if (dst_bytes > 4)
31 dst_bytes = 4;
32 for (i = 0; i < dst_bytes; i++)
33 dst[i] = src >> ((3 - i) * 8);
34}
35
36static u32
37intel_dp_aux_wait_done(struct intel_dp *intel_dp)
38{
39 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
40 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
41 const unsigned int timeout_ms = 10;
42 u32 status;
43 bool done;
44
45#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
46 done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
47 msecs_to_jiffies_timeout(timeout_ms));
48
49 /* just trace the final value */
50 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
51
52 if (!done)
53 drm_err(&i915->drm,
54 "%s: did not complete or timeout within %ums (status 0x%08x)\n",
55 intel_dp->aux.name, timeout_ms, status);
56#undef C
57
58 return status;
59}
60
61static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
62{
63 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
64
65 if (index)
66 return 0;
67
68 /*
69 * The clock divider is based off the hrawclk, and would like to run at
70 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
71 */
72 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
73}
74
75static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
76{
77 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
78 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
79 u32 freq;
80
81 if (index)
82 return 0;
83
84 /*
85 * The clock divider is based off the cdclk or PCH rawclk, and would
86 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
87 * divide by 2000 and use that
88 */
89 if (dig_port->aux_ch == AUX_CH_A)
90 freq = dev_priv->display.cdclk.hw.cdclk;
91 else
92 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
93 return DIV_ROUND_CLOSEST(freq, 2000);
94}
95
96static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
97{
98 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
99 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
100
101 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
102 /* Workaround for non-ULT HSW */
103 switch (index) {
104 case 0: return 63;
105 case 1: return 72;
106 default: return 0;
107 }
108 }
109
110 return ilk_get_aux_clock_divider(intel_dp, index);
111}
112
113static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
114{
115 /*
116 * SKL doesn't need us to program the AUX clock divider (Hardware will
117 * derive the clock from CDCLK automatically). We still implement the
118 * get_aux_clock_divider vfunc to plug-in into the existing code.
119 */
120 return index ? 0 : 1;
121}
122
123static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
124 int send_bytes,
125 u32 aux_clock_divider)
126{
127 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
128 struct drm_i915_private *dev_priv =
129 to_i915(dig_port->base.base.dev);
130 u32 timeout;
131
132 /* Max timeout value on G4x-BDW: 1.6ms */
133 if (IS_BROADWELL(dev_priv))
134 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
135 else
136 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
137
138 return DP_AUX_CH_CTL_SEND_BUSY |
139 DP_AUX_CH_CTL_DONE |
140 DP_AUX_CH_CTL_INTERRUPT |
141 DP_AUX_CH_CTL_TIME_OUT_ERROR |
142 timeout |
143 DP_AUX_CH_CTL_RECEIVE_ERROR |
144 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
145 (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
146 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
147}
148
149static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
150 int send_bytes,
151 u32 unused)
152{
153 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
154 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
155 u32 ret;
156
157 /*
158 * Max timeout values:
159 * SKL-GLK: 1.6ms
160 * ICL+: 4ms
161 */
162 ret = DP_AUX_CH_CTL_SEND_BUSY |
163 DP_AUX_CH_CTL_DONE |
164 DP_AUX_CH_CTL_INTERRUPT |
165 DP_AUX_CH_CTL_TIME_OUT_ERROR |
166 DP_AUX_CH_CTL_TIME_OUT_MAX |
167 DP_AUX_CH_CTL_RECEIVE_ERROR |
168 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
169 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
170 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
171
172 if (intel_tc_port_in_tbt_alt_mode(dig_port))
173 ret |= DP_AUX_CH_CTL_TBT_IO;
174
175 /*
176 * Power request bit is already set during aux power well enable.
177 * Preserve the bit across aux transactions.
178 */
179 if (DISPLAY_VER(i915) >= 14)
180 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST;
181
182 return ret;
183}
184
185static int
186intel_dp_aux_xfer(struct intel_dp *intel_dp,
187 const u8 *send, int send_bytes,
188 u8 *recv, int recv_size,
189 u32 aux_send_ctl_flags)
190{
191 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
192 struct drm_i915_private *i915 =
193 to_i915(dig_port->base.base.dev);
194 struct intel_uncore *uncore = &i915->uncore;
195 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
196 bool is_tc_port = intel_phy_is_tc(i915, phy);
197 i915_reg_t ch_ctl, ch_data[5];
198 u32 aux_clock_divider;
199 enum intel_display_power_domain aux_domain;
200 intel_wakeref_t aux_wakeref;
201 intel_wakeref_t pps_wakeref;
202 int i, ret, recv_bytes;
203 int try, clock = 0;
204 u32 status;
205 bool vdd;
206
207 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
208 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
209 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
210
211 if (is_tc_port)
212 intel_tc_port_lock(dig_port);
213
214 aux_domain = intel_aux_power_domain(dig_port);
215
216 aux_wakeref = intel_display_power_get(i915, aux_domain);
217 pps_wakeref = intel_pps_lock(intel_dp);
218
219 /*
220 * We will be called with VDD already enabled for dpcd/edid/oui reads.
221 * In such cases we want to leave VDD enabled and it's up to upper layers
222 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
223 * ourselves.
224 */
225 vdd = intel_pps_vdd_on_unlocked(intel_dp);
226
227 /*
228 * dp aux is extremely sensitive to irq latency, hence request the
229 * lowest possible wakeup latency and so prevent the cpu from going into
230 * deep sleep states.
231 */
232 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
233
234 intel_pps_check_power_unlocked(intel_dp);
235
236 /* Try to wait for any previous AUX channel activity */
237 for (try = 0; try < 3; try++) {
238 status = intel_uncore_read_notrace(uncore, ch_ctl);
239 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
240 break;
241 msleep(1);
242 }
243 /* just trace the final value */
244 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
245
246 if (try == 3) {
247 const u32 status = intel_uncore_read(uncore, ch_ctl);
248
249 if (status != intel_dp->aux_busy_last_status) {
250 drm_WARN(&i915->drm, 1,
251 "%s: not started (status 0x%08x)\n",
252 intel_dp->aux.name, status);
253 intel_dp->aux_busy_last_status = status;
254 }
255
256 ret = -EBUSY;
257 goto out;
258 }
259
260 /* Only 5 data registers! */
261 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
262 ret = -E2BIG;
263 goto out;
264 }
265
266 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
267 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
268 send_bytes,
269 aux_clock_divider);
270
271 send_ctl |= aux_send_ctl_flags;
272
273 /* Must try at least 3 times according to DP spec */
274 for (try = 0; try < 5; try++) {
275 /* Load the send data into the aux channel data registers */
276 for (i = 0; i < send_bytes; i += 4)
277 intel_uncore_write(uncore,
278 ch_data[i >> 2],
279 intel_dp_aux_pack(send + i,
280 send_bytes - i));
281
282 /* Send the command and wait for it to complete */
283 intel_uncore_write(uncore, ch_ctl, send_ctl);
284
285 status = intel_dp_aux_wait_done(intel_dp);
286
287 /* Clear done status and any errors */
288 intel_uncore_write(uncore,
289 ch_ctl,
290 status |
291 DP_AUX_CH_CTL_DONE |
292 DP_AUX_CH_CTL_TIME_OUT_ERROR |
293 DP_AUX_CH_CTL_RECEIVE_ERROR);
294
295 /*
296 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
297 * 400us delay required for errors and timeouts
298 * Timeout errors from the HW already meet this
299 * requirement so skip to next iteration
300 */
301 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
302 continue;
303
304 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
305 usleep_range(400, 500);
306 continue;
307 }
308 if (status & DP_AUX_CH_CTL_DONE)
309 goto done;
310 }
311 }
312
313 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
314 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
315 intel_dp->aux.name, status);
316 ret = -EBUSY;
317 goto out;
318 }
319
320done:
321 /*
322 * Check for timeout or receive error. Timeouts occur when the sink is
323 * not connected.
324 */
325 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
326 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
327 intel_dp->aux.name, status);
328 ret = -EIO;
329 goto out;
330 }
331
332 /*
333 * Timeouts occur when the device isn't connected, so they're "normal"
334 * -- don't fill the kernel log with these
335 */
336 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
337 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
338 intel_dp->aux.name, status);
339 ret = -ETIMEDOUT;
340 goto out;
341 }
342
343 /* Unload any bytes sent back from the other side */
344 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
345 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
346
347 /*
348 * By BSpec: "Message sizes of 0 or >20 are not allowed."
349 * We have no idea of what happened so we return -EBUSY so
350 * drm layer takes care for the necessary retries.
351 */
352 if (recv_bytes == 0 || recv_bytes > 20) {
353 drm_dbg_kms(&i915->drm,
354 "%s: Forbidden recv_bytes = %d on aux transaction\n",
355 intel_dp->aux.name, recv_bytes);
356 ret = -EBUSY;
357 goto out;
358 }
359
360 if (recv_bytes > recv_size)
361 recv_bytes = recv_size;
362
363 for (i = 0; i < recv_bytes; i += 4)
364 intel_dp_aux_unpack(intel_uncore_read(uncore, ch_data[i >> 2]),
365 recv + i, recv_bytes - i);
366
367 ret = recv_bytes;
368out:
369 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
370
371 if (vdd)
372 intel_pps_vdd_off_unlocked(intel_dp, false);
373
374 intel_pps_unlock(intel_dp, pps_wakeref);
375 intel_display_power_put_async(i915, aux_domain, aux_wakeref);
376
377 if (is_tc_port)
378 intel_tc_port_unlock(dig_port);
379
380 return ret;
381}
382
383#define BARE_ADDRESS_SIZE 3
384#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
385
386static void
387intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
388 const struct drm_dp_aux_msg *msg)
389{
390 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
391 txbuf[1] = (msg->address >> 8) & 0xff;
392 txbuf[2] = msg->address & 0xff;
393 txbuf[3] = msg->size - 1;
394}
395
396static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
397{
398 /*
399 * If we're trying to send the HDCP Aksv, we need to set a the Aksv
400 * select bit to inform the hardware to send the Aksv after our header
401 * since we can't access that data from software.
402 */
403 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
404 msg->address == DP_AUX_HDCP_AKSV)
405 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
406
407 return 0;
408}
409
410static ssize_t
411intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
412{
413 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
414 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
415 u8 txbuf[20], rxbuf[20];
416 size_t txsize, rxsize;
417 u32 flags = intel_dp_aux_xfer_flags(msg);
418 int ret;
419
420 intel_dp_aux_header(txbuf, msg);
421
422 switch (msg->request & ~DP_AUX_I2C_MOT) {
423 case DP_AUX_NATIVE_WRITE:
424 case DP_AUX_I2C_WRITE:
425 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
426 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
427 rxsize = 2; /* 0 or 1 data bytes */
428
429 if (drm_WARN_ON(&i915->drm, txsize > 20))
430 return -E2BIG;
431
432 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
433
434 if (msg->buffer)
435 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
436
437 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
438 rxbuf, rxsize, flags);
439 if (ret > 0) {
440 msg->reply = rxbuf[0] >> 4;
441
442 if (ret > 1) {
443 /* Number of bytes written in a short write. */
444 ret = clamp_t(int, rxbuf[1], 0, msg->size);
445 } else {
446 /* Return payload size. */
447 ret = msg->size;
448 }
449 }
450 break;
451
452 case DP_AUX_NATIVE_READ:
453 case DP_AUX_I2C_READ:
454 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
455 rxsize = msg->size + 1;
456
457 if (drm_WARN_ON(&i915->drm, rxsize > 20))
458 return -E2BIG;
459
460 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
461 rxbuf, rxsize, flags);
462 if (ret > 0) {
463 msg->reply = rxbuf[0] >> 4;
464 /*
465 * Assume happy day, and copy the data. The caller is
466 * expected to check msg->reply before touching it.
467 *
468 * Return payload size.
469 */
470 ret--;
471 memcpy(msg->buffer, rxbuf + 1, ret);
472 }
473 break;
474
475 default:
476 ret = -EINVAL;
477 break;
478 }
479
480 return ret;
481}
482
483static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
484{
485 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
486 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
487 enum aux_ch aux_ch = dig_port->aux_ch;
488
489 switch (aux_ch) {
490 case AUX_CH_B:
491 case AUX_CH_C:
492 case AUX_CH_D:
493 return DP_AUX_CH_CTL(aux_ch);
494 default:
495 MISSING_CASE(aux_ch);
496 return DP_AUX_CH_CTL(AUX_CH_B);
497 }
498}
499
500static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
501{
502 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
503 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
504 enum aux_ch aux_ch = dig_port->aux_ch;
505
506 switch (aux_ch) {
507 case AUX_CH_B:
508 case AUX_CH_C:
509 case AUX_CH_D:
510 return DP_AUX_CH_DATA(aux_ch, index);
511 default:
512 MISSING_CASE(aux_ch);
513 return DP_AUX_CH_DATA(AUX_CH_B, index);
514 }
515}
516
517static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
518{
519 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
520 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
521 enum aux_ch aux_ch = dig_port->aux_ch;
522
523 switch (aux_ch) {
524 case AUX_CH_A:
525 return DP_AUX_CH_CTL(aux_ch);
526 case AUX_CH_B:
527 case AUX_CH_C:
528 case AUX_CH_D:
529 return PCH_DP_AUX_CH_CTL(aux_ch);
530 default:
531 MISSING_CASE(aux_ch);
532 return DP_AUX_CH_CTL(AUX_CH_A);
533 }
534}
535
536static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
537{
538 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
539 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
540 enum aux_ch aux_ch = dig_port->aux_ch;
541
542 switch (aux_ch) {
543 case AUX_CH_A:
544 return DP_AUX_CH_DATA(aux_ch, index);
545 case AUX_CH_B:
546 case AUX_CH_C:
547 case AUX_CH_D:
548 return PCH_DP_AUX_CH_DATA(aux_ch, index);
549 default:
550 MISSING_CASE(aux_ch);
551 return DP_AUX_CH_DATA(AUX_CH_A, index);
552 }
553}
554
555static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
556{
557 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
558 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
559 enum aux_ch aux_ch = dig_port->aux_ch;
560
561 switch (aux_ch) {
562 case AUX_CH_A:
563 case AUX_CH_B:
564 case AUX_CH_C:
565 case AUX_CH_D:
566 case AUX_CH_E:
567 case AUX_CH_F:
568 return DP_AUX_CH_CTL(aux_ch);
569 default:
570 MISSING_CASE(aux_ch);
571 return DP_AUX_CH_CTL(AUX_CH_A);
572 }
573}
574
575static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
576{
577 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
578 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
579 enum aux_ch aux_ch = dig_port->aux_ch;
580
581 switch (aux_ch) {
582 case AUX_CH_A:
583 case AUX_CH_B:
584 case AUX_CH_C:
585 case AUX_CH_D:
586 case AUX_CH_E:
587 case AUX_CH_F:
588 return DP_AUX_CH_DATA(aux_ch, index);
589 default:
590 MISSING_CASE(aux_ch);
591 return DP_AUX_CH_DATA(AUX_CH_A, index);
592 }
593}
594
595static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
596{
597 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
598 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
599 enum aux_ch aux_ch = dig_port->aux_ch;
600
601 switch (aux_ch) {
602 case AUX_CH_A:
603 case AUX_CH_B:
604 case AUX_CH_C:
605 case AUX_CH_USBC1:
606 case AUX_CH_USBC2:
607 case AUX_CH_USBC3:
608 case AUX_CH_USBC4:
609 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
610 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
611 return DP_AUX_CH_CTL(aux_ch);
612 default:
613 MISSING_CASE(aux_ch);
614 return DP_AUX_CH_CTL(AUX_CH_A);
615 }
616}
617
618static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
619{
620 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
621 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
622 enum aux_ch aux_ch = dig_port->aux_ch;
623
624 switch (aux_ch) {
625 case AUX_CH_A:
626 case AUX_CH_B:
627 case AUX_CH_C:
628 case AUX_CH_USBC1:
629 case AUX_CH_USBC2:
630 case AUX_CH_USBC3:
631 case AUX_CH_USBC4:
632 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
633 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
634 return DP_AUX_CH_DATA(aux_ch, index);
635 default:
636 MISSING_CASE(aux_ch);
637 return DP_AUX_CH_DATA(AUX_CH_A, index);
638 }
639}
640
641static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
642{
643 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
644 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
645 enum aux_ch aux_ch = dig_port->aux_ch;
646
647 switch (aux_ch) {
648 case AUX_CH_A:
649 case AUX_CH_B:
650 case AUX_CH_USBC1:
651 case AUX_CH_USBC2:
652 case AUX_CH_USBC3:
653 case AUX_CH_USBC4:
654 return XELPDP_DP_AUX_CH_CTL(aux_ch);
655 default:
656 MISSING_CASE(aux_ch);
657 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
658 }
659}
660
661static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
662{
663 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
664 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
665 enum aux_ch aux_ch = dig_port->aux_ch;
666
667 switch (aux_ch) {
668 case AUX_CH_A:
669 case AUX_CH_B:
670 case AUX_CH_USBC1:
671 case AUX_CH_USBC2:
672 case AUX_CH_USBC3:
673 case AUX_CH_USBC4:
674 return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
675 default:
676 MISSING_CASE(aux_ch);
677 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
678 }
679}
680
681void intel_dp_aux_fini(struct intel_dp *intel_dp)
682{
683 if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
684 cpu_latency_qos_remove_request(&intel_dp->pm_qos);
685
686 kfree(intel_dp->aux.name);
687}
688
689void intel_dp_aux_init(struct intel_dp *intel_dp)
690{
691 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
692 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
693 struct intel_encoder *encoder = &dig_port->base;
694 enum aux_ch aux_ch = dig_port->aux_ch;
695
696 if (DISPLAY_VER(dev_priv) >= 14) {
697 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
698 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
699 } else if (DISPLAY_VER(dev_priv) >= 12) {
700 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
701 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
702 } else if (DISPLAY_VER(dev_priv) >= 9) {
703 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
704 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
705 } else if (HAS_PCH_SPLIT(dev_priv)) {
706 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
707 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
708 } else {
709 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
710 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
711 }
712
713 if (DISPLAY_VER(dev_priv) >= 9)
714 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
715 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
716 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
717 else if (HAS_PCH_SPLIT(dev_priv))
718 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
719 else
720 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
721
722 if (DISPLAY_VER(dev_priv) >= 9)
723 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
724 else
725 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
726
727 intel_dp->aux.drm_dev = &dev_priv->drm;
728 drm_dp_aux_init(&intel_dp->aux);
729
730 /* Failure to allocate our preferred name is not critical */
731 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
732 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
733 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
734 encoder->base.name);
735 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
736 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
737 aux_ch - AUX_CH_USBC1 + '1',
738 encoder->base.name);
739 else
740 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
741 aux_ch_name(aux_ch),
742 encoder->base.name);
743
744 intel_dp->aux.transfer = intel_dp_aux_transfer;
745 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
746}