Loading...
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "intel_ddi.h"
8#include "intel_ddi_buf_trans.h"
9#include "intel_de.h"
10#include "intel_display_types.h"
11
12/* HDMI/DVI modes ignore everything but the last 2 items. So we share
13 * them for both DP and FDI transports, allowing those ports to
14 * automatically adapt to HDMI connections as well
15 */
16static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
17 { 0x00FFFFFF, 0x0006000E, 0x0 },
18 { 0x00D75FFF, 0x0005000A, 0x0 },
19 { 0x00C30FFF, 0x00040006, 0x0 },
20 { 0x80AAAFFF, 0x000B0000, 0x0 },
21 { 0x00FFFFFF, 0x0005000A, 0x0 },
22 { 0x00D75FFF, 0x000C0004, 0x0 },
23 { 0x80C30FFF, 0x000B0000, 0x0 },
24 { 0x00FFFFFF, 0x00040006, 0x0 },
25 { 0x80D75FFF, 0x000B0000, 0x0 },
26};
27
28static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
29 { 0x00FFFFFF, 0x0007000E, 0x0 },
30 { 0x00D75FFF, 0x000F000A, 0x0 },
31 { 0x00C30FFF, 0x00060006, 0x0 },
32 { 0x00AAAFFF, 0x001E0000, 0x0 },
33 { 0x00FFFFFF, 0x000F000A, 0x0 },
34 { 0x00D75FFF, 0x00160004, 0x0 },
35 { 0x00C30FFF, 0x001E0000, 0x0 },
36 { 0x00FFFFFF, 0x00060006, 0x0 },
37 { 0x00D75FFF, 0x001E0000, 0x0 },
38};
39
40static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
41 /* Idx NT mV d T mV d db */
42 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
43 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
44 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
45 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
46 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
47 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
48 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
49 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
50 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
51 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
52 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
53 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
54};
55
56static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
57 { 0x00FFFFFF, 0x00000012, 0x0 },
58 { 0x00EBAFFF, 0x00020011, 0x0 },
59 { 0x00C71FFF, 0x0006000F, 0x0 },
60 { 0x00AAAFFF, 0x000E000A, 0x0 },
61 { 0x00FFFFFF, 0x00020011, 0x0 },
62 { 0x00DB6FFF, 0x0005000F, 0x0 },
63 { 0x00BEEFFF, 0x000A000C, 0x0 },
64 { 0x00FFFFFF, 0x0005000F, 0x0 },
65 { 0x00DB6FFF, 0x000A000C, 0x0 },
66};
67
68static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
69 { 0x00FFFFFF, 0x0007000E, 0x0 },
70 { 0x00D75FFF, 0x000E000A, 0x0 },
71 { 0x00BEFFFF, 0x00140006, 0x0 },
72 { 0x80B2CFFF, 0x001B0002, 0x0 },
73 { 0x00FFFFFF, 0x000E000A, 0x0 },
74 { 0x00DB6FFF, 0x00160005, 0x0 },
75 { 0x80C71FFF, 0x001A0002, 0x0 },
76 { 0x00F7DFFF, 0x00180004, 0x0 },
77 { 0x80D75FFF, 0x001B0002, 0x0 },
78};
79
80static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
81 { 0x00FFFFFF, 0x0001000E, 0x0 },
82 { 0x00D75FFF, 0x0004000A, 0x0 },
83 { 0x00C30FFF, 0x00070006, 0x0 },
84 { 0x00AAAFFF, 0x000C0000, 0x0 },
85 { 0x00FFFFFF, 0x0004000A, 0x0 },
86 { 0x00D75FFF, 0x00090004, 0x0 },
87 { 0x00C30FFF, 0x000C0000, 0x0 },
88 { 0x00FFFFFF, 0x00070006, 0x0 },
89 { 0x00D75FFF, 0x000C0000, 0x0 },
90};
91
92static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
93 /* Idx NT mV d T mV df db */
94 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
95 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
96 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
97 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
98 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
99 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
100 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
101 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
102 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
103 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
104};
105
106/* Skylake H and S */
107static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
108 { 0x00002016, 0x000000A0, 0x0 },
109 { 0x00005012, 0x0000009B, 0x0 },
110 { 0x00007011, 0x00000088, 0x0 },
111 { 0x80009010, 0x000000C0, 0x1 },
112 { 0x00002016, 0x0000009B, 0x0 },
113 { 0x00005012, 0x00000088, 0x0 },
114 { 0x80007011, 0x000000C0, 0x1 },
115 { 0x00002016, 0x000000DF, 0x0 },
116 { 0x80005012, 0x000000C0, 0x1 },
117};
118
119/* Skylake U */
120static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
121 { 0x0000201B, 0x000000A2, 0x0 },
122 { 0x00005012, 0x00000088, 0x0 },
123 { 0x80007011, 0x000000CD, 0x1 },
124 { 0x80009010, 0x000000C0, 0x1 },
125 { 0x0000201B, 0x0000009D, 0x0 },
126 { 0x80005012, 0x000000C0, 0x1 },
127 { 0x80007011, 0x000000C0, 0x1 },
128 { 0x00002016, 0x00000088, 0x0 },
129 { 0x80005012, 0x000000C0, 0x1 },
130};
131
132/* Skylake Y */
133static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
134 { 0x00000018, 0x000000A2, 0x0 },
135 { 0x00005012, 0x00000088, 0x0 },
136 { 0x80007011, 0x000000CD, 0x3 },
137 { 0x80009010, 0x000000C0, 0x3 },
138 { 0x00000018, 0x0000009D, 0x0 },
139 { 0x80005012, 0x000000C0, 0x3 },
140 { 0x80007011, 0x000000C0, 0x3 },
141 { 0x00000018, 0x00000088, 0x0 },
142 { 0x80005012, 0x000000C0, 0x3 },
143};
144
145/* Kabylake H and S */
146static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
147 { 0x00002016, 0x000000A0, 0x0 },
148 { 0x00005012, 0x0000009B, 0x0 },
149 { 0x00007011, 0x00000088, 0x0 },
150 { 0x80009010, 0x000000C0, 0x1 },
151 { 0x00002016, 0x0000009B, 0x0 },
152 { 0x00005012, 0x00000088, 0x0 },
153 { 0x80007011, 0x000000C0, 0x1 },
154 { 0x00002016, 0x00000097, 0x0 },
155 { 0x80005012, 0x000000C0, 0x1 },
156};
157
158/* Kabylake U */
159static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
160 { 0x0000201B, 0x000000A1, 0x0 },
161 { 0x00005012, 0x00000088, 0x0 },
162 { 0x80007011, 0x000000CD, 0x3 },
163 { 0x80009010, 0x000000C0, 0x3 },
164 { 0x0000201B, 0x0000009D, 0x0 },
165 { 0x80005012, 0x000000C0, 0x3 },
166 { 0x80007011, 0x000000C0, 0x3 },
167 { 0x00002016, 0x0000004F, 0x0 },
168 { 0x80005012, 0x000000C0, 0x3 },
169};
170
171/* Kabylake Y */
172static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
173 { 0x00001017, 0x000000A1, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
175 { 0x80007011, 0x000000CD, 0x3 },
176 { 0x8000800F, 0x000000C0, 0x3 },
177 { 0x00001017, 0x0000009D, 0x0 },
178 { 0x80005012, 0x000000C0, 0x3 },
179 { 0x80007011, 0x000000C0, 0x3 },
180 { 0x00001017, 0x0000004C, 0x0 },
181 { 0x80005012, 0x000000C0, 0x3 },
182};
183
184/*
185 * Skylake/Kabylake H and S
186 * eDP 1.4 low vswing translation parameters
187 */
188static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
189 { 0x00000018, 0x000000A8, 0x0 },
190 { 0x00004013, 0x000000A9, 0x0 },
191 { 0x00007011, 0x000000A2, 0x0 },
192 { 0x00009010, 0x0000009C, 0x0 },
193 { 0x00000018, 0x000000A9, 0x0 },
194 { 0x00006013, 0x000000A2, 0x0 },
195 { 0x00007011, 0x000000A6, 0x0 },
196 { 0x00000018, 0x000000AB, 0x0 },
197 { 0x00007013, 0x0000009F, 0x0 },
198 { 0x00000018, 0x000000DF, 0x0 },
199};
200
201/*
202 * Skylake/Kabylake U
203 * eDP 1.4 low vswing translation parameters
204 */
205static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
206 { 0x00000018, 0x000000A8, 0x0 },
207 { 0x00004013, 0x000000A9, 0x0 },
208 { 0x00007011, 0x000000A2, 0x0 },
209 { 0x00009010, 0x0000009C, 0x0 },
210 { 0x00000018, 0x000000A9, 0x0 },
211 { 0x00006013, 0x000000A2, 0x0 },
212 { 0x00007011, 0x000000A6, 0x0 },
213 { 0x00002016, 0x000000AB, 0x0 },
214 { 0x00005013, 0x0000009F, 0x0 },
215 { 0x00000018, 0x000000DF, 0x0 },
216};
217
218/*
219 * Skylake/Kabylake Y
220 * eDP 1.4 low vswing translation parameters
221 */
222static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
223 { 0x00000018, 0x000000A8, 0x0 },
224 { 0x00004013, 0x000000AB, 0x0 },
225 { 0x00007011, 0x000000A4, 0x0 },
226 { 0x00009010, 0x000000DF, 0x0 },
227 { 0x00000018, 0x000000AA, 0x0 },
228 { 0x00006013, 0x000000A4, 0x0 },
229 { 0x00007011, 0x0000009D, 0x0 },
230 { 0x00000018, 0x000000A0, 0x0 },
231 { 0x00006012, 0x000000DF, 0x0 },
232 { 0x00000018, 0x0000008A, 0x0 },
233};
234
235/* Skylake/Kabylake U, H and S */
236static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
237 { 0x00000018, 0x000000AC, 0x0 },
238 { 0x00005012, 0x0000009D, 0x0 },
239 { 0x00007011, 0x00000088, 0x0 },
240 { 0x00000018, 0x000000A1, 0x0 },
241 { 0x00000018, 0x00000098, 0x0 },
242 { 0x00004013, 0x00000088, 0x0 },
243 { 0x80006012, 0x000000CD, 0x1 },
244 { 0x00000018, 0x000000DF, 0x0 },
245 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
246 { 0x80003015, 0x000000C0, 0x1 },
247 { 0x80000018, 0x000000C0, 0x1 },
248};
249
250/* Skylake/Kabylake Y */
251static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
252 { 0x00000018, 0x000000A1, 0x0 },
253 { 0x00005012, 0x000000DF, 0x0 },
254 { 0x80007011, 0x000000CB, 0x3 },
255 { 0x00000018, 0x000000A4, 0x0 },
256 { 0x00000018, 0x0000009D, 0x0 },
257 { 0x00004013, 0x00000080, 0x0 },
258 { 0x80006013, 0x000000C0, 0x3 },
259 { 0x00000018, 0x0000008A, 0x0 },
260 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
261 { 0x80003015, 0x000000C0, 0x3 },
262 { 0x80000018, 0x000000C0, 0x3 },
263};
264
265
266static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
267 /* Idx NT mV diff db */
268 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
269 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
270 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
271 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
272 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
273 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
274 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
275 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
276 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
277 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
278};
279
280static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
281 /* Idx NT mV diff db */
282 { 26, 0, 0, 128, }, /* 0: 200 0 */
283 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
284 { 48, 0, 0, 96, }, /* 2: 200 4 */
285 { 54, 0, 0, 69, }, /* 3: 200 6 */
286 { 32, 0, 0, 128, }, /* 4: 250 0 */
287 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
288 { 54, 0, 0, 85, }, /* 6: 250 4 */
289 { 43, 0, 0, 128, }, /* 7: 300 0 */
290 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
291 { 48, 0, 0, 128, }, /* 9: 300 0 */
292};
293
294/* BSpec has 2 recommended values - entries 0 and 8.
295 * Using the entry with higher vswing.
296 */
297static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
298 /* Idx NT mV diff db */
299 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
300 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
301 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
302 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
303 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
304 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
305 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
306 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
307 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
308 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
309};
310
311/* Voltage Swing Programming for VccIO 0.85V for DP */
312static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
313 /* NT mV Trans mV db */
314 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
315 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
316 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
317 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
318 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
319 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
320 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
321 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
322 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
323 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
324};
325
326/* Voltage Swing Programming for VccIO 0.85V for HDMI */
327static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
328 /* NT mV Trans mV db */
329 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
330 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
331 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
332 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
333 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
334 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
335 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
336};
337
338/* Voltage Swing Programming for VccIO 0.85V for eDP */
339static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
340 /* NT mV Trans mV db */
341 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
342 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
343 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
344 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
345 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
346 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
347 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
348 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
349 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
350};
351
352/* Voltage Swing Programming for VccIO 0.95V for DP */
353static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
354 /* NT mV Trans mV db */
355 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
356 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
357 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
358 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
359 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
360 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
361 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
362 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
363 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
364 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
365};
366
367/* Voltage Swing Programming for VccIO 0.95V for HDMI */
368static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
369 /* NT mV Trans mV db */
370 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
371 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
372 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
373 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
374 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
375 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
376 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
377 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
378 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
379 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
380 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
381};
382
383/* Voltage Swing Programming for VccIO 0.95V for eDP */
384static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
385 /* NT mV Trans mV db */
386 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
387 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
388 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
389 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
390 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
391 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
392 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
393 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
394 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
395 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
396};
397
398/* Voltage Swing Programming for VccIO 1.05V for DP */
399static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
400 /* NT mV Trans mV db */
401 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
402 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
403 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
404 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
405 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
406 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
407 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
408 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
409 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
410 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
411};
412
413/* Voltage Swing Programming for VccIO 1.05V for HDMI */
414static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
415 /* NT mV Trans mV db */
416 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
417 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
418 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
419 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
420 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
421 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
422 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
423 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
424 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
425 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
426 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
427};
428
429/* Voltage Swing Programming for VccIO 1.05V for eDP */
430static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
431 /* NT mV Trans mV db */
432 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
433 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
434 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
435 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
436 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
437 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
438 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
439 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
440 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
441};
442
443/* icl_combo_phy_ddi_translations */
444static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
445 /* NT mV Trans mV db */
446 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
447 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
448 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
449 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
450 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
451 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
452 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
453 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
454 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
455 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
456};
457
458static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
459 /* NT mV Trans mV db */
460 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
461 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
462 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
463 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
464 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
465 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
466 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
467 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
468 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
469 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
470};
471
472static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
473 /* NT mV Trans mV db */
474 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
475 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
476 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
477 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
478 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
479 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
480 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
481 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
482 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
483 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
484};
485
486static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
487 /* NT mV Trans mV db */
488 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
489 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
490 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
491 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
492 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
493 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
494 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
495};
496
497static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
498 /* NT mV Trans mV db */
499 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
500 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
501 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */
502 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */
503 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
504 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
505 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
506 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
507 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */
508 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
509};
510
511static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
512 /* NT mV Trans mV db */
513 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
514 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
515 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
516 { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */
517 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
518 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
519 { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
520 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
521 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
522 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
523};
524
525static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
526 /* NT mV Trans mV db */
527 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
528 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */
529 { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */
530 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */
531 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
532 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */
533 { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */
534 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
535 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
536 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
537};
538
539static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = {
540 /* NT mV Trans mV db */
541 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
542 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
543 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
544 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
545 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
546 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
547 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
548 { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
549 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
550 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
551};
552
553static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
554 /* NT mV Trans mV db */
555 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
556 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
557 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
558 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
559 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
560 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
561 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
562 { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
563 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
564 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
565};
566
567static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
568 /* Voltage swing pre-emphasis */
569 { 0x18, 0x00, 0x00 }, /* 0 0 */
570 { 0x1D, 0x00, 0x05 }, /* 0 1 */
571 { 0x24, 0x00, 0x0C }, /* 0 2 */
572 { 0x2B, 0x00, 0x14 }, /* 0 3 */
573 { 0x21, 0x00, 0x00 }, /* 1 0 */
574 { 0x2B, 0x00, 0x08 }, /* 1 1 */
575 { 0x30, 0x00, 0x0F }, /* 1 2 */
576 { 0x31, 0x00, 0x03 }, /* 2 0 */
577 { 0x34, 0x00, 0x0B }, /* 2 1 */
578 { 0x3F, 0x00, 0x00 }, /* 3 0 */
579};
580
581static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
582 /* Voltage swing pre-emphasis */
583 { 0x18, 0x00, 0x00 }, /* 0 0 */
584 { 0x1D, 0x00, 0x05 }, /* 0 1 */
585 { 0x24, 0x00, 0x0C }, /* 0 2 */
586 { 0x2B, 0x00, 0x14 }, /* 0 3 */
587 { 0x26, 0x00, 0x00 }, /* 1 0 */
588 { 0x2C, 0x00, 0x07 }, /* 1 1 */
589 { 0x33, 0x00, 0x0C }, /* 1 2 */
590 { 0x2E, 0x00, 0x00 }, /* 2 0 */
591 { 0x36, 0x00, 0x09 }, /* 2 1 */
592 { 0x3F, 0x00, 0x00 }, /* 3 0 */
593};
594
595static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
596 /* HDMI Preset VS Pre-emph */
597 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */
598 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */
599 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */
600 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */
601 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */
602 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
603 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
604 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
605 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
606 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
607};
608
609static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
610 /* VS pre-emp Non-trans mV Pre-emph dB */
611 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
612 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
613 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
614 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
615 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
616 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
617 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
618 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
619 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
620 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
621};
622
623static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
624 /* VS pre-emp Non-trans mV Pre-emph dB */
625 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
626 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
627 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
628 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
629 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
630 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
631 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
632 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
633 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
634 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
635};
636
637static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
638 /* HDMI Preset VS Pre-emph */
639 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */
640 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */
641 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */
642 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */
643 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */
644 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
645 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
646 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
647 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
648 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
649};
650
651static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
652 /* NT mV Trans mV db */
653 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
654 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
655 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
656 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
657 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
658 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
659 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
660 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
661 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
662 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
663};
664
665static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
666 /* NT mV Trans mV db */
667 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
668 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
669 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
670 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
671 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
672 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
673 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
674 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
675 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
676 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
677};
678
679static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
680 /* NT mV Trans mV db */
681 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
682 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
683 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
684 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
685 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
686 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
687 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
688 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
689 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
690 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
691};
692
693/*
694 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
695 * that DisplayPort specification requires
696 */
697static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
698 /* VS pre-emp */
699 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */
700 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */
701 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */
702 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */
703 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */
704 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */
705 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */
706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */
707 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */
708};
709
710static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = {
711 /* NT mV Trans mV db */
712 { 0xA, 0x2F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
713 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
714 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
715 { 0x6, 0x7D, 0x2A, 0x00, 0x15 }, /* 350 900 8.2 */
716 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
717 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
718 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
719 { 0xC, 0x6E, 0x3E, 0x00, 0x01 }, /* 650 700 0.6 */
720 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
721 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
722};
723
724static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
725 /* NT mV Trans mV db */
726 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
727 { 0xA, 0x50, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
728 { 0xC, 0x61, 0x33, 0x00, 0x0C }, /* 350 700 6.0 */
729 { 0x6, 0x7F, 0x2E, 0x00, 0x11 }, /* 350 900 8.2 */
730 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
731 { 0xC, 0x5F, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
732 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
733 { 0xC, 0x5F, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
734 { 0x6, 0x7E, 0x36, 0x00, 0x09 }, /* 600 900 3.5 */
735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
736};
737
738static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr[] = {
739 /* VS pre-emp Non-trans mV Pre-emph dB */
740 { 0x7, 0x0, 0x01 }, /* 0 0 400mV 0 dB */
741 { 0x5, 0x0, 0x06 }, /* 0 1 400mV 3.5 dB */
742 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
743 { 0x0, 0x0, 0x17 }, /* 0 3 400mV 9.5 dB */
744 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
745 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
746 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
747 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
748 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
749 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
750};
751
752static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = {
753 /* VS pre-emp Non-trans mV Pre-emph dB */
754 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
755 { 0x5, 0x0, 0x04 }, /* 0 1 400mV 3.5 dB */
756 { 0x2, 0x0, 0x0A }, /* 0 2 400mV 6 dB */
757 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
758 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
759 { 0x2, 0x0, 0x06 }, /* 1 1 600mV 3.5 dB */
760 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
761 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
762 { 0x0, 0x0, 0x09 }, /* 2 1 800mV 3.5 dB */
763 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
764};
765
766bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
767{
768 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
769}
770
771static const struct ddi_buf_trans *
772bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
773{
774 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
775
776 if (dev_priv->vbt.edp.low_vswing) {
777 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
778 return bdw_ddi_translations_edp;
779 } else {
780 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
781 return bdw_ddi_translations_dp;
782 }
783}
784
785static const struct ddi_buf_trans *
786skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
787{
788 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
789
790 if (IS_SKL_ULX(dev_priv)) {
791 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
792 return skl_y_ddi_translations_dp;
793 } else if (IS_SKL_ULT(dev_priv)) {
794 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
795 return skl_u_ddi_translations_dp;
796 } else {
797 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
798 return skl_ddi_translations_dp;
799 }
800}
801
802static const struct ddi_buf_trans *
803kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
804{
805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
806
807 if (IS_KBL_ULX(dev_priv) ||
808 IS_CFL_ULX(dev_priv) ||
809 IS_CML_ULX(dev_priv)) {
810 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
811 return kbl_y_ddi_translations_dp;
812 } else if (IS_KBL_ULT(dev_priv) ||
813 IS_CFL_ULT(dev_priv) ||
814 IS_CML_ULT(dev_priv)) {
815 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
816 return kbl_u_ddi_translations_dp;
817 } else {
818 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
819 return kbl_ddi_translations_dp;
820 }
821}
822
823static const struct ddi_buf_trans *
824skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
825{
826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
827
828 if (dev_priv->vbt.edp.low_vswing) {
829 if (IS_SKL_ULX(dev_priv) ||
830 IS_KBL_ULX(dev_priv) ||
831 IS_CFL_ULX(dev_priv) ||
832 IS_CML_ULX(dev_priv)) {
833 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
834 return skl_y_ddi_translations_edp;
835 } else if (IS_SKL_ULT(dev_priv) ||
836 IS_KBL_ULT(dev_priv) ||
837 IS_CFL_ULT(dev_priv) ||
838 IS_CML_ULT(dev_priv)) {
839 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
840 return skl_u_ddi_translations_edp;
841 } else {
842 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
843 return skl_ddi_translations_edp;
844 }
845 }
846
847 if (IS_KABYLAKE(dev_priv) ||
848 IS_COFFEELAKE(dev_priv) ||
849 IS_COMETLAKE(dev_priv))
850 return kbl_get_buf_trans_dp(encoder, n_entries);
851 else
852 return skl_get_buf_trans_dp(encoder, n_entries);
853}
854
855static const struct ddi_buf_trans *
856skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
857{
858 if (IS_SKL_ULX(dev_priv) ||
859 IS_KBL_ULX(dev_priv) ||
860 IS_CFL_ULX(dev_priv) ||
861 IS_CML_ULX(dev_priv)) {
862 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
863 return skl_y_ddi_translations_hdmi;
864 } else {
865 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
866 return skl_ddi_translations_hdmi;
867 }
868}
869
870static int skl_buf_trans_num_entries(enum port port, int n_entries)
871{
872 /* Only DDIA and DDIE can select the 10th register with DP */
873 if (port == PORT_A || port == PORT_E)
874 return min(n_entries, 10);
875 else
876 return min(n_entries, 9);
877}
878
879const struct ddi_buf_trans *
880intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
881{
882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
883
884 if (IS_KABYLAKE(dev_priv) ||
885 IS_COFFEELAKE(dev_priv) ||
886 IS_COMETLAKE(dev_priv)) {
887 const struct ddi_buf_trans *ddi_translations =
888 kbl_get_buf_trans_dp(encoder, n_entries);
889 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
890 return ddi_translations;
891 } else if (IS_SKYLAKE(dev_priv)) {
892 const struct ddi_buf_trans *ddi_translations =
893 skl_get_buf_trans_dp(encoder, n_entries);
894 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
895 return ddi_translations;
896 } else if (IS_BROADWELL(dev_priv)) {
897 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
898 return bdw_ddi_translations_dp;
899 } else if (IS_HASWELL(dev_priv)) {
900 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
901 return hsw_ddi_translations_dp;
902 }
903
904 *n_entries = 0;
905 return NULL;
906}
907
908const struct ddi_buf_trans *
909intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
910{
911 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
912
913 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
914 const struct ddi_buf_trans *ddi_translations =
915 skl_get_buf_trans_edp(encoder, n_entries);
916 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
917 return ddi_translations;
918 } else if (IS_BROADWELL(dev_priv)) {
919 return bdw_get_buf_trans_edp(encoder, n_entries);
920 } else if (IS_HASWELL(dev_priv)) {
921 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
922 return hsw_ddi_translations_dp;
923 }
924
925 *n_entries = 0;
926 return NULL;
927}
928
929const struct ddi_buf_trans *
930intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
931 int *n_entries)
932{
933 if (IS_BROADWELL(dev_priv)) {
934 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
935 return bdw_ddi_translations_fdi;
936 } else if (IS_HASWELL(dev_priv)) {
937 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
938 return hsw_ddi_translations_fdi;
939 }
940
941 *n_entries = 0;
942 return NULL;
943}
944
945const struct ddi_buf_trans *
946intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
947 int *n_entries)
948{
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
950
951 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
952 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
953 } else if (IS_BROADWELL(dev_priv)) {
954 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
955 return bdw_ddi_translations_hdmi;
956 } else if (IS_HASWELL(dev_priv)) {
957 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
958 return hsw_ddi_translations_hdmi;
959 }
960
961 *n_entries = 0;
962 return NULL;
963}
964
965static const struct bxt_ddi_buf_trans *
966bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
967{
968 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
969 return bxt_ddi_translations_dp;
970}
971
972static const struct bxt_ddi_buf_trans *
973bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
974{
975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
976
977 if (dev_priv->vbt.edp.low_vswing) {
978 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
979 return bxt_ddi_translations_edp;
980 }
981
982 return bxt_get_buf_trans_dp(encoder, n_entries);
983}
984
985static const struct bxt_ddi_buf_trans *
986bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
987{
988 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
989 return bxt_ddi_translations_hdmi;
990}
991
992const struct bxt_ddi_buf_trans *
993bxt_get_buf_trans(struct intel_encoder *encoder,
994 const struct intel_crtc_state *crtc_state,
995 int *n_entries)
996{
997 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
998 return bxt_get_buf_trans_hdmi(encoder, n_entries);
999 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1000 return bxt_get_buf_trans_edp(encoder, n_entries);
1001 return bxt_get_buf_trans_dp(encoder, n_entries);
1002}
1003
1004static const struct cnl_ddi_buf_trans *
1005cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
1006{
1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1008 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1009
1010 if (voltage == VOLTAGE_INFO_0_85V) {
1011 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1012 return cnl_ddi_translations_hdmi_0_85V;
1013 } else if (voltage == VOLTAGE_INFO_0_95V) {
1014 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1015 return cnl_ddi_translations_hdmi_0_95V;
1016 } else if (voltage == VOLTAGE_INFO_1_05V) {
1017 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1018 return cnl_ddi_translations_hdmi_1_05V;
1019 } else {
1020 *n_entries = 1; /* shut up gcc */
1021 MISSING_CASE(voltage);
1022 }
1023 return NULL;
1024}
1025
1026static const struct cnl_ddi_buf_trans *
1027cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
1028{
1029 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1030 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1031
1032 if (voltage == VOLTAGE_INFO_0_85V) {
1033 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1034 return cnl_ddi_translations_dp_0_85V;
1035 } else if (voltage == VOLTAGE_INFO_0_95V) {
1036 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1037 return cnl_ddi_translations_dp_0_95V;
1038 } else if (voltage == VOLTAGE_INFO_1_05V) {
1039 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1040 return cnl_ddi_translations_dp_1_05V;
1041 } else {
1042 *n_entries = 1; /* shut up gcc */
1043 MISSING_CASE(voltage);
1044 }
1045 return NULL;
1046}
1047
1048static const struct cnl_ddi_buf_trans *
1049cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1050{
1051 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1052 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1053
1054 if (dev_priv->vbt.edp.low_vswing) {
1055 if (voltage == VOLTAGE_INFO_0_85V) {
1056 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1057 return cnl_ddi_translations_edp_0_85V;
1058 } else if (voltage == VOLTAGE_INFO_0_95V) {
1059 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1060 return cnl_ddi_translations_edp_0_95V;
1061 } else if (voltage == VOLTAGE_INFO_1_05V) {
1062 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1063 return cnl_ddi_translations_edp_1_05V;
1064 } else {
1065 *n_entries = 1; /* shut up gcc */
1066 MISSING_CASE(voltage);
1067 }
1068 return NULL;
1069 } else {
1070 return cnl_get_buf_trans_dp(encoder, n_entries);
1071 }
1072}
1073
1074const struct cnl_ddi_buf_trans *
1075cnl_get_buf_trans(struct intel_encoder *encoder,
1076 const struct intel_crtc_state *crtc_state,
1077 int *n_entries)
1078{
1079 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1080 return cnl_get_buf_trans_hdmi(encoder, n_entries);
1081 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1082 return cnl_get_buf_trans_edp(encoder, n_entries);
1083 return cnl_get_buf_trans_dp(encoder, n_entries);
1084}
1085
1086static const struct cnl_ddi_buf_trans *
1087icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1088 const struct intel_crtc_state *crtc_state,
1089 int *n_entries)
1090{
1091 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1092 return icl_combo_phy_ddi_translations_hdmi;
1093}
1094
1095static const struct cnl_ddi_buf_trans *
1096icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1097 const struct intel_crtc_state *crtc_state,
1098 int *n_entries)
1099{
1100 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1101 return icl_combo_phy_ddi_translations_dp_hbr2;
1102}
1103
1104static const struct cnl_ddi_buf_trans *
1105icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1106 const struct intel_crtc_state *crtc_state,
1107 int *n_entries)
1108{
1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1110
1111 if (crtc_state->port_clock > 540000) {
1112 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1113 return icl_combo_phy_ddi_translations_edp_hbr3;
1114 } else if (dev_priv->vbt.edp.low_vswing) {
1115 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1116 return icl_combo_phy_ddi_translations_edp_hbr2;
1117 } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) {
1118 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3);
1119 return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3;
1120 } else if (IS_DG1(dev_priv)) {
1121 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_rbr_hbr);
1122 return dg1_combo_phy_ddi_translations_dp_rbr_hbr;
1123 }
1124
1125 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1126}
1127
1128const struct cnl_ddi_buf_trans *
1129icl_get_combo_buf_trans(struct intel_encoder *encoder,
1130 const struct intel_crtc_state *crtc_state,
1131 int *n_entries)
1132{
1133 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1134 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1135 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1136 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1137 else
1138 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1139}
1140
1141static const struct icl_mg_phy_ddi_buf_trans *
1142icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
1143 const struct intel_crtc_state *crtc_state,
1144 int *n_entries)
1145{
1146 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1147 return icl_mg_phy_ddi_translations_hdmi;
1148}
1149
1150static const struct icl_mg_phy_ddi_buf_trans *
1151icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1152 const struct intel_crtc_state *crtc_state,
1153 int *n_entries)
1154{
1155 if (crtc_state->port_clock > 270000) {
1156 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1157 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1158 } else {
1159 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1160 return icl_mg_phy_ddi_translations_rbr_hbr;
1161 }
1162}
1163
1164const struct icl_mg_phy_ddi_buf_trans *
1165icl_get_mg_buf_trans(struct intel_encoder *encoder,
1166 const struct intel_crtc_state *crtc_state,
1167 int *n_entries)
1168{
1169 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1170 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
1171 else
1172 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1173}
1174
1175static const struct cnl_ddi_buf_trans *
1176ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1177 const struct intel_crtc_state *crtc_state,
1178 int *n_entries)
1179{
1180 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1181 return icl_combo_phy_ddi_translations_hdmi;
1182}
1183
1184static const struct cnl_ddi_buf_trans *
1185ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1186 const struct intel_crtc_state *crtc_state,
1187 int *n_entries)
1188{
1189 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1190 return ehl_combo_phy_ddi_translations_dp;
1191}
1192
1193static const struct cnl_ddi_buf_trans *
1194ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1195 const struct intel_crtc_state *crtc_state,
1196 int *n_entries)
1197{
1198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1199
1200 if (dev_priv->vbt.edp.low_vswing) {
1201 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1202 return icl_combo_phy_ddi_translations_edp_hbr2;
1203 }
1204
1205 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1206}
1207
1208const struct cnl_ddi_buf_trans *
1209ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1210 const struct intel_crtc_state *crtc_state,
1211 int *n_entries)
1212{
1213 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1214 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1215 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1216 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1217 else
1218 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1219}
1220
1221static const struct cnl_ddi_buf_trans *
1222jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1223 const struct intel_crtc_state *crtc_state,
1224 int *n_entries)
1225{
1226 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1227 return icl_combo_phy_ddi_translations_hdmi;
1228}
1229
1230static const struct cnl_ddi_buf_trans *
1231jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1232 const struct intel_crtc_state *crtc_state,
1233 int *n_entries)
1234{
1235 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1236 return icl_combo_phy_ddi_translations_dp_hbr2;
1237}
1238
1239static const struct cnl_ddi_buf_trans *
1240jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1241 const struct intel_crtc_state *crtc_state,
1242 int *n_entries)
1243{
1244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1245
1246 if (dev_priv->vbt.edp.low_vswing) {
1247 if (crtc_state->port_clock > 270000) {
1248 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
1249 return jsl_combo_phy_ddi_translations_edp_hbr2;
1250 } else {
1251 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
1252 return jsl_combo_phy_ddi_translations_edp_hbr;
1253 }
1254 }
1255
1256 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1257}
1258
1259const struct cnl_ddi_buf_trans *
1260jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1261 const struct intel_crtc_state *crtc_state,
1262 int *n_entries)
1263{
1264 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1265 return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1266 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1267 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1268 else
1269 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1270}
1271
1272static const struct cnl_ddi_buf_trans *
1273tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1274 const struct intel_crtc_state *crtc_state,
1275 int *n_entries)
1276{
1277 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1278 return icl_combo_phy_ddi_translations_hdmi;
1279}
1280
1281static const struct cnl_ddi_buf_trans *
1282tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1283 const struct intel_crtc_state *crtc_state,
1284 int *n_entries)
1285{
1286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1287
1288 if (crtc_state->port_clock > 270000) {
1289 if (IS_ROCKETLAKE(dev_priv)) {
1290 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3);
1291 return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3;
1292 } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1293 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
1294 return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
1295 } else {
1296 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1297 return tgl_combo_phy_ddi_translations_dp_hbr2;
1298 }
1299 } else {
1300 if (IS_ROCKETLAKE(dev_priv)) {
1301 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr);
1302 return rkl_combo_phy_ddi_translations_dp_hbr;
1303 } else {
1304 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1305 return tgl_combo_phy_ddi_translations_dp_hbr;
1306 }
1307 }
1308}
1309
1310static const struct cnl_ddi_buf_trans *
1311tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1312 const struct intel_crtc_state *crtc_state,
1313 int *n_entries)
1314{
1315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1316 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1317
1318 if (crtc_state->port_clock > 540000) {
1319 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1320 return icl_combo_phy_ddi_translations_edp_hbr3;
1321 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
1322 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1323 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1324 } else if (dev_priv->vbt.edp.low_vswing) {
1325 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1326 return icl_combo_phy_ddi_translations_edp_hbr2;
1327 }
1328
1329 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1330}
1331
1332const struct cnl_ddi_buf_trans *
1333tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1334 const struct intel_crtc_state *crtc_state,
1335 int *n_entries)
1336{
1337 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1338 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1339 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1340 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1341 else
1342 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1343}
1344
1345static const struct tgl_dkl_phy_ddi_buf_trans *
1346tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
1347 const struct intel_crtc_state *crtc_state,
1348 int *n_entries)
1349{
1350 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1351 return tgl_dkl_phy_hdmi_ddi_trans;
1352}
1353
1354static const struct tgl_dkl_phy_ddi_buf_trans *
1355tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1356 const struct intel_crtc_state *crtc_state,
1357 int *n_entries)
1358{
1359 if (crtc_state->port_clock > 270000) {
1360 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1361 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1362 } else {
1363 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1364 return tgl_dkl_phy_dp_ddi_trans;
1365 }
1366}
1367
1368const struct tgl_dkl_phy_ddi_buf_trans *
1369tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1370 const struct intel_crtc_state *crtc_state,
1371 int *n_entries)
1372{
1373 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1374 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
1375 else
1376 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1377}
1378
1379static const struct tgl_dkl_phy_ddi_buf_trans *
1380adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1381 const struct intel_crtc_state *crtc_state,
1382 int *n_entries)
1383{
1384 if (crtc_state->port_clock > 270000) {
1385 *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3);
1386 return adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3;
1387 }
1388
1389 *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr);
1390 return adlp_dkl_phy_dp_ddi_trans_hbr;
1391}
1392
1393const struct tgl_dkl_phy_ddi_buf_trans *
1394adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1395 const struct intel_crtc_state *crtc_state,
1396 int *n_entries)
1397{
1398 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1399 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
1400 else
1401 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1402}
1403
1404int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
1405 const struct intel_crtc_state *crtc_state,
1406 int *default_entry)
1407{
1408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1409 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1410 int n_entries;
1411
1412 if (DISPLAY_VER(dev_priv) >= 12) {
1413 if (intel_phy_is_combo(dev_priv, phy))
1414 tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1415 else
1416 tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1417 *default_entry = n_entries - 1;
1418 } else if (DISPLAY_VER(dev_priv) == 11) {
1419 if (intel_phy_is_combo(dev_priv, phy))
1420 icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1421 else
1422 icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1423 *default_entry = n_entries - 1;
1424 } else if (IS_CANNONLAKE(dev_priv)) {
1425 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1426 *default_entry = n_entries - 1;
1427 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1428 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1429 *default_entry = n_entries - 1;
1430 } else if (DISPLAY_VER(dev_priv) == 9) {
1431 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1432 *default_entry = 8;
1433 } else if (IS_BROADWELL(dev_priv)) {
1434 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1435 *default_entry = 7;
1436 } else if (IS_HASWELL(dev_priv)) {
1437 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1438 *default_entry = 6;
1439 } else {
1440 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1441 return 0;
1442 }
1443
1444 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1445 return 0;
1446
1447 return n_entries;
1448}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "intel_ddi.h"
8#include "intel_ddi_buf_trans.h"
9#include "intel_de.h"
10#include "intel_display_types.h"
11#include "intel_dp.h"
12
13/* HDMI/DVI modes ignore everything but the last 2 items. So we share
14 * them for both DP and FDI transports, allowing those ports to
15 * automatically adapt to HDMI connections as well
16 */
17static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = {
18 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
19 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
20 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
21 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
22 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
23 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
24 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
25 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
26 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
27};
28
29static const struct intel_ddi_buf_trans hsw_trans_dp = {
30 .entries = _hsw_trans_dp,
31 .num_entries = ARRAY_SIZE(_hsw_trans_dp),
32};
33
34static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = {
35 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
36 { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } },
37 { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } },
38 { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } },
39 { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } },
40 { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } },
41 { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } },
42 { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } },
43 { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } },
44};
45
46static const struct intel_ddi_buf_trans hsw_trans_fdi = {
47 .entries = _hsw_trans_fdi,
48 .num_entries = ARRAY_SIZE(_hsw_trans_fdi),
49};
50
51static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = {
52 /* Idx NT mV d T mV d db */
53 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */
54 { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */
55 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, /* 2: 400 600 3.5 */
56 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, /* 3: 600 600 0 */
57 { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4: 600 750 2 */
58 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */
59 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, /* 6: 800 800 0 */
60 { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } }, /* 7: 800 1000 2 */
61 { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } }, /* 8: 850 850 0 */
62 { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } }, /* 9: 900 900 0 */
63 { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } }, /* 10: 950 950 0 */
64 { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */
65};
66
67static const struct intel_ddi_buf_trans hsw_trans_hdmi = {
68 .entries = _hsw_trans_hdmi,
69 .num_entries = ARRAY_SIZE(_hsw_trans_hdmi),
70 .hdmi_default_entry = 6,
71};
72
73static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = {
74 { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } },
75 { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } },
76 { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } },
77 { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } },
78 { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } },
79 { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } },
80 { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } },
81 { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } },
82 { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } },
83};
84
85static const struct intel_ddi_buf_trans bdw_trans_edp = {
86 .entries = _bdw_trans_edp,
87 .num_entries = ARRAY_SIZE(_bdw_trans_edp),
88};
89
90static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = {
91 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
92 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
93 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
94 { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } },
95 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
96 { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } },
97 { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } },
98 { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } },
99 { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } },
100};
101
102static const struct intel_ddi_buf_trans bdw_trans_dp = {
103 .entries = _bdw_trans_dp,
104 .num_entries = ARRAY_SIZE(_bdw_trans_dp),
105};
106
107static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = {
108 { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } },
109 { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } },
110 { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } },
111 { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } },
112 { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } },
113 { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } },
114 { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } },
115 { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } },
116 { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } },
117};
118
119static const struct intel_ddi_buf_trans bdw_trans_fdi = {
120 .entries = _bdw_trans_fdi,
121 .num_entries = ARRAY_SIZE(_bdw_trans_fdi),
122};
123
124static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = {
125 /* Idx NT mV d T mV df db */
126 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */
127 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */
128 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, /* 2: 400 800 6 */
129 { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } }, /* 3: 450 450 0 */
130 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4: 600 600 0 */
131 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */
132 { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } }, /* 6: 600 1000 4.5 */
133 { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } }, /* 7: 800 800 0 */
134 { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } }, /* 8: 800 1000 2 */
135 { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */
136};
137
138static const struct intel_ddi_buf_trans bdw_trans_hdmi = {
139 .entries = _bdw_trans_hdmi,
140 .num_entries = ARRAY_SIZE(_bdw_trans_hdmi),
141 .hdmi_default_entry = 7,
142};
143
144/* Skylake H and S */
145static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = {
146 { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
147 { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
148 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
149 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
150 { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
151 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
152 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
153 { .hsw = { 0x00002016, 0x000000DF, 0x0 } },
154 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
155};
156
157static const struct intel_ddi_buf_trans skl_trans_dp = {
158 .entries = _skl_trans_dp,
159 .num_entries = ARRAY_SIZE(_skl_trans_dp),
160};
161
162/* Skylake U */
163static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = {
164 { .hsw = { 0x0000201B, 0x000000A2, 0x0 } },
165 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
166 { .hsw = { 0x80007011, 0x000000CD, 0x1 } },
167 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
168 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
169 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
170 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
171 { .hsw = { 0x00002016, 0x00000088, 0x0 } },
172 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
173};
174
175static const struct intel_ddi_buf_trans skl_u_trans_dp = {
176 .entries = _skl_u_trans_dp,
177 .num_entries = ARRAY_SIZE(_skl_u_trans_dp),
178};
179
180/* Skylake Y */
181static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = {
182 { .hsw = { 0x00000018, 0x000000A2, 0x0 } },
183 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
184 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
185 { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
186 { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
187 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
188 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
189 { .hsw = { 0x00000018, 0x00000088, 0x0 } },
190 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
191};
192
193static const struct intel_ddi_buf_trans skl_y_trans_dp = {
194 .entries = _skl_y_trans_dp,
195 .num_entries = ARRAY_SIZE(_skl_y_trans_dp),
196};
197
198/* Kabylake H and S */
199static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = {
200 { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
201 { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
202 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
203 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
204 { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
205 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
206 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
207 { .hsw = { 0x00002016, 0x00000097, 0x0 } },
208 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
209};
210
211static const struct intel_ddi_buf_trans kbl_trans_dp = {
212 .entries = _kbl_trans_dp,
213 .num_entries = ARRAY_SIZE(_kbl_trans_dp),
214};
215
216/* Kabylake U */
217static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = {
218 { .hsw = { 0x0000201B, 0x000000A1, 0x0 } },
219 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
220 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
221 { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
222 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
223 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
224 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
225 { .hsw = { 0x00002016, 0x0000004F, 0x0 } },
226 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
227};
228
229static const struct intel_ddi_buf_trans kbl_u_trans_dp = {
230 .entries = _kbl_u_trans_dp,
231 .num_entries = ARRAY_SIZE(_kbl_u_trans_dp),
232};
233
234/* Kabylake Y */
235static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = {
236 { .hsw = { 0x00001017, 0x000000A1, 0x0 } },
237 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
238 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
239 { .hsw = { 0x8000800F, 0x000000C0, 0x3 } },
240 { .hsw = { 0x00001017, 0x0000009D, 0x0 } },
241 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
242 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
243 { .hsw = { 0x00001017, 0x0000004C, 0x0 } },
244 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
245};
246
247static const struct intel_ddi_buf_trans kbl_y_trans_dp = {
248 .entries = _kbl_y_trans_dp,
249 .num_entries = ARRAY_SIZE(_kbl_y_trans_dp),
250};
251
252/*
253 * Skylake/Kabylake H and S
254 * eDP 1.4 low vswing translation parameters
255 */
256static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = {
257 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
258 { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
259 { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
260 { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
261 { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
262 { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
263 { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
264 { .hsw = { 0x00000018, 0x000000AB, 0x0 } },
265 { .hsw = { 0x00007013, 0x0000009F, 0x0 } },
266 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
267};
268
269static const struct intel_ddi_buf_trans skl_trans_edp = {
270 .entries = _skl_trans_edp,
271 .num_entries = ARRAY_SIZE(_skl_trans_edp),
272};
273
274/*
275 * Skylake/Kabylake U
276 * eDP 1.4 low vswing translation parameters
277 */
278static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = {
279 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
280 { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
281 { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
282 { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
283 { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
284 { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
285 { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
286 { .hsw = { 0x00002016, 0x000000AB, 0x0 } },
287 { .hsw = { 0x00005013, 0x0000009F, 0x0 } },
288 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
289};
290
291static const struct intel_ddi_buf_trans skl_u_trans_edp = {
292 .entries = _skl_u_trans_edp,
293 .num_entries = ARRAY_SIZE(_skl_u_trans_edp),
294};
295
296/*
297 * Skylake/Kabylake Y
298 * eDP 1.4 low vswing translation parameters
299 */
300static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = {
301 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
302 { .hsw = { 0x00004013, 0x000000AB, 0x0 } },
303 { .hsw = { 0x00007011, 0x000000A4, 0x0 } },
304 { .hsw = { 0x00009010, 0x000000DF, 0x0 } },
305 { .hsw = { 0x00000018, 0x000000AA, 0x0 } },
306 { .hsw = { 0x00006013, 0x000000A4, 0x0 } },
307 { .hsw = { 0x00007011, 0x0000009D, 0x0 } },
308 { .hsw = { 0x00000018, 0x000000A0, 0x0 } },
309 { .hsw = { 0x00006012, 0x000000DF, 0x0 } },
310 { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
311};
312
313static const struct intel_ddi_buf_trans skl_y_trans_edp = {
314 .entries = _skl_y_trans_edp,
315 .num_entries = ARRAY_SIZE(_skl_y_trans_edp),
316};
317
318/* Skylake/Kabylake U, H and S */
319static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = {
320 { .hsw = { 0x00000018, 0x000000AC, 0x0 } },
321 { .hsw = { 0x00005012, 0x0000009D, 0x0 } },
322 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
323 { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
324 { .hsw = { 0x00000018, 0x00000098, 0x0 } },
325 { .hsw = { 0x00004013, 0x00000088, 0x0 } },
326 { .hsw = { 0x80006012, 0x000000CD, 0x1 } },
327 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
328 { .hsw = { 0x80003015, 0x000000CD, 0x1 } }, /* Default */
329 { .hsw = { 0x80003015, 0x000000C0, 0x1 } },
330 { .hsw = { 0x80000018, 0x000000C0, 0x1 } },
331};
332
333static const struct intel_ddi_buf_trans skl_trans_hdmi = {
334 .entries = _skl_trans_hdmi,
335 .num_entries = ARRAY_SIZE(_skl_trans_hdmi),
336 .hdmi_default_entry = 8,
337};
338
339/* Skylake/Kabylake Y */
340static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = {
341 { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
342 { .hsw = { 0x00005012, 0x000000DF, 0x0 } },
343 { .hsw = { 0x80007011, 0x000000CB, 0x3 } },
344 { .hsw = { 0x00000018, 0x000000A4, 0x0 } },
345 { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
346 { .hsw = { 0x00004013, 0x00000080, 0x0 } },
347 { .hsw = { 0x80006013, 0x000000C0, 0x3 } },
348 { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
349 { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, /* Default */
350 { .hsw = { 0x80003015, 0x000000C0, 0x3 } },
351 { .hsw = { 0x80000018, 0x000000C0, 0x3 } },
352};
353
354static const struct intel_ddi_buf_trans skl_y_trans_hdmi = {
355 .entries = _skl_y_trans_hdmi,
356 .num_entries = ARRAY_SIZE(_skl_y_trans_hdmi),
357 .hdmi_default_entry = 8,
358};
359
360static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = {
361 /* Idx NT mV diff db */
362 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */
363 { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */
364 { .bxt = { 104, 0x9A, 0, 64, } }, /* 2: 400 6 */
365 { .bxt = { 154, 0x9A, 0, 43, } }, /* 3: 400 9.5 */
366 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */
367 { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
368 { .bxt = { 154, 0x9A, 0, 64, } }, /* 6: 600 6 */
369 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */
370 { .bxt = { 154, 0x9A, 0, 85, } }, /* 8: 800 3.5 */
371 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */
372};
373
374static const struct intel_ddi_buf_trans bxt_trans_dp = {
375 .entries = _bxt_trans_dp,
376 .num_entries = ARRAY_SIZE(_bxt_trans_dp),
377};
378
379static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = {
380 /* Idx NT mV diff db */
381 { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */
382 { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */
383 { .bxt = { 48, 0, 0, 96, } }, /* 2: 200 4 */
384 { .bxt = { 54, 0, 0, 69, } }, /* 3: 200 6 */
385 { .bxt = { 32, 0, 0, 128, } }, /* 4: 250 0 */
386 { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */
387 { .bxt = { 54, 0, 0, 85, } }, /* 6: 250 4 */
388 { .bxt = { 43, 0, 0, 128, } }, /* 7: 300 0 */
389 { .bxt = { 54, 0, 0, 101, } }, /* 8: 300 1.5 */
390 { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */
391};
392
393static const struct intel_ddi_buf_trans bxt_trans_edp = {
394 .entries = _bxt_trans_edp,
395 .num_entries = ARRAY_SIZE(_bxt_trans_edp),
396};
397
398/* BSpec has 2 recommended values - entries 0 and 8.
399 * Using the entry with higher vswing.
400 */
401static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = {
402 /* Idx NT mV diff db */
403 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */
404 { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */
405 { .bxt = { 52, 0x9A, 0, 64, } }, /* 2: 400 6 */
406 { .bxt = { 42, 0x9A, 0, 43, } }, /* 3: 400 9.5 */
407 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */
408 { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
409 { .bxt = { 77, 0x9A, 0, 64, } }, /* 6: 600 6 */
410 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */
411 { .bxt = { 102, 0x9A, 0, 85, } }, /* 8: 800 3.5 */
412 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */
413};
414
415static const struct intel_ddi_buf_trans bxt_trans_hdmi = {
416 .entries = _bxt_trans_hdmi,
417 .num_entries = ARRAY_SIZE(_bxt_trans_hdmi),
418 .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
419};
420
421/* icl_combo_phy_trans */
422static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
423 /* NT mV Trans mV db */
424 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
425 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
426 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
427 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
428 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
429 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
430 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
431 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
432 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
433 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
434};
435
436static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = {
437 .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
438 .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
439};
440
441static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = {
442 /* NT mV Trans mV db */
443 { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
444 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
445 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
446 { .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */
447 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
448 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
449 { .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
450 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
451 { .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
452 { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
453};
454
455static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = {
456 .entries = _icl_combo_phy_trans_edp_hbr2,
457 .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2),
458};
459
460static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = {
461 /* NT mV Trans mV db */
462 { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
463 { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */
464 { .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */
465 { .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */
466 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */
467 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */
468 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
469};
470
471static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = {
472 .entries = _icl_combo_phy_trans_hdmi,
473 .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi),
474 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
475};
476
477static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = {
478 /* NT mV Trans mV db */
479 { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
480 { .icl = { 0xA, 0x47, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
481 { .icl = { 0xC, 0x64, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
482 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 350 900 8.2 */
483 { .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
484 { .icl = { 0xC, 0x64, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
485 { .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
486 { .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
487 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
488 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
489};
490
491static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = {
492 .entries = _ehl_combo_phy_trans_dp,
493 .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp),
494};
495
496static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = {
497 /* NT mV Trans mV db */
498 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
499 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
500 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
501 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */
502 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
503 { .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */
504 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */
505 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
506 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
507 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
508};
509
510static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = {
511 .entries = _ehl_combo_phy_trans_edp_hbr2,
512 .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2),
513};
514
515static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = {
516 /* NT mV Trans mV db */
517 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
518 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
519 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
520 { .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */
521 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
522 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
523 { .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
524 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
525 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
526 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
527};
528
529static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = {
530 .entries = _jsl_combo_phy_trans_edp_hbr,
531 .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr),
532};
533
534static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = {
535 /* NT mV Trans mV db */
536 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
537 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
538 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
539 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */
540 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
541 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */
542 { .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */
543 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
544 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
545 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
546};
547
548static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = {
549 .entries = _jsl_combo_phy_trans_edp_hbr2,
550 .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2),
551};
552
553static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = {
554 /* NT mV Trans mV db */
555 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
556 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
557 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
558 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
559 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
560 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
561 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
562 { .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
563 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
564 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
565};
566
567static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = {
568 .entries = _dg1_combo_phy_trans_dp_rbr_hbr,
569 .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr),
570};
571
572static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = {
573 /* NT mV Trans mV db */
574 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
575 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
576 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
577 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
578 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
579 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
580 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
581 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
582 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
583 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
584};
585
586static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = {
587 .entries = _dg1_combo_phy_trans_dp_hbr2_hbr3,
588 .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3),
589};
590
591static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = {
592 /* Voltage swing pre-emphasis */
593 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */
594 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */
595 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */
596 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */
597 { .mg = { 0x21, 0x00, 0x00 } }, /* 1 0 */
598 { .mg = { 0x2B, 0x00, 0x08 } }, /* 1 1 */
599 { .mg = { 0x30, 0x00, 0x0F } }, /* 1 2 */
600 { .mg = { 0x31, 0x00, 0x03 } }, /* 2 0 */
601 { .mg = { 0x34, 0x00, 0x0B } }, /* 2 1 */
602 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */
603};
604
605static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = {
606 .entries = _icl_mg_phy_trans_rbr_hbr,
607 .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr),
608};
609
610static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = {
611 /* Voltage swing pre-emphasis */
612 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */
613 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */
614 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */
615 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */
616 { .mg = { 0x26, 0x00, 0x00 } }, /* 1 0 */
617 { .mg = { 0x2C, 0x00, 0x07 } }, /* 1 1 */
618 { .mg = { 0x33, 0x00, 0x0C } }, /* 1 2 */
619 { .mg = { 0x2E, 0x00, 0x00 } }, /* 2 0 */
620 { .mg = { 0x36, 0x00, 0x09 } }, /* 2 1 */
621 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */
622};
623
624static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = {
625 .entries = _icl_mg_phy_trans_hbr2_hbr3,
626 .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3),
627};
628
629static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = {
630 /* HDMI Preset VS Pre-emph */
631 { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */
632 { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */
633 { .mg = { 0x29, 0x0, 0x0 } }, /* 3 650mV 0dB */
634 { .mg = { 0x32, 0x0, 0x0 } }, /* 4 800mV 0dB */
635 { .mg = { 0x3F, 0x0, 0x0 } }, /* 5 1000mV 0dB */
636 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
637 { .mg = { 0x39, 0x0, 0x6 } }, /* 7 Full -1.8 dB */
638 { .mg = { 0x38, 0x0, 0x7 } }, /* 8 Full -2 dB */
639 { .mg = { 0x37, 0x0, 0x8 } }, /* 9 Full -2.5 dB */
640 { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */
641};
642
643static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = {
644 .entries = _icl_mg_phy_trans_hdmi,
645 .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi),
646 .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1,
647};
648
649static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = {
650 /* VS pre-emp Non-trans mV Pre-emph dB */
651 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
652 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */
653 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
654 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */
655 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
656 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
657 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
658 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
659 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
660 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */
661};
662
663static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = {
664 .entries = _tgl_dkl_phy_trans_dp_hbr,
665 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr),
666};
667
668static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = {
669 /* VS pre-emp Non-trans mV Pre-emph dB */
670 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
671 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */
672 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
673 { .dkl = { 0x0, 0x0, 0x19 } }, /* 0 3 400mV 9.5 dB */
674 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
675 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
676 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
677 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
678 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
679 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */
680};
681
682static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = {
683 .entries = _tgl_dkl_phy_trans_dp_hbr2,
684 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2),
685};
686
687static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = {
688 /* HDMI Preset VS Pre-emph */
689 { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */
690 { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */
691 { .dkl = { 0x4, 0x0, 0x0 } }, /* 3 650mV 0dB */
692 { .dkl = { 0x2, 0x0, 0x0 } }, /* 4 800mV 0dB */
693 { .dkl = { 0x0, 0x0, 0x0 } }, /* 5 1000mV 0dB */
694 { .dkl = { 0x0, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
695 { .dkl = { 0x0, 0x0, 0x6 } }, /* 7 Full -1.8 dB */
696 { .dkl = { 0x0, 0x0, 0x7 } }, /* 8 Full -2 dB */
697 { .dkl = { 0x0, 0x0, 0x8 } }, /* 9 Full -2.5 dB */
698 { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */
699};
700
701static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = {
702 .entries = _tgl_dkl_phy_trans_hdmi,
703 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi),
704 .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1,
705};
706
707static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = {
708 /* NT mV Trans mV db */
709 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
710 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
711 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
712 { .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
713 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
714 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
715 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
716 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
717 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
718 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
719};
720
721static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = {
722 .entries = _tgl_combo_phy_trans_dp_hbr,
723 .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr),
724};
725
726static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = {
727 /* NT mV Trans mV db */
728 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
729 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
730 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
731 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
732 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
733 { .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
734 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
735 { .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
736 { .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
737 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
738};
739
740static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = {
741 .entries = _tgl_combo_phy_trans_dp_hbr2,
742 .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2),
743};
744
745static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = {
746 /* NT mV Trans mV db */
747 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
748 { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
749 { .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */
750 { .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */
751 { .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
752 { .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
753 { .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
754 { .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
755 { .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */
756 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
757};
758
759static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = {
760 .entries = _tgl_uy_combo_phy_trans_dp_hbr2,
761 .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2),
762};
763
764/*
765 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
766 * that DisplayPort specification requires
767 */
768static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = {
769 /* VS pre-emp */
770 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */
771 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */
772 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */
773 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */
774 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */
775 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */
776 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */
777 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */
778 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */
779};
780
781static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = {
782 .entries = _tgl_combo_phy_trans_edp_hbr2_hobl,
783 .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl),
784};
785
786static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = {
787 /* NT mV Trans mV db */
788 { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
789 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
790 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
791 { .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */
792 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
793 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
794 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
795 { .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */
796 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
797 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
798};
799
800static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = {
801 .entries = _rkl_combo_phy_trans_dp_hbr,
802 .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr),
803};
804
805static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = {
806 /* NT mV Trans mV db */
807 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
808 { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
809 { .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
810 { .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */
811 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
812 { .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
813 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
814 { .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
815 { .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */
816 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
817};
818
819static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = {
820 .entries = _rkl_combo_phy_trans_dp_hbr2_hbr3,
821 .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3),
822};
823
824static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = {
825 /* NT mV Trans mV db */
826 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
827 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
828 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
829 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
830 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
831 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
832 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
833 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
834 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
835 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
836};
837
838static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = {
839 .entries = _adls_combo_phy_trans_dp_hbr2_hbr3,
840 .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3),
841};
842
843static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = {
844 /* NT mV Trans mV db */
845 { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200 200 0.0 */
846 { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200 250 1.9 */
847 { .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } }, /* 200 300 3.5 */
848 { .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } }, /* 200 350 4.9 */
849 { .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */
850 { .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
851 { .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */
852 { .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } }, /* 300 300 0.0 */
853 { .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
854 { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */
855};
856
857static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = {
858 .entries = _adls_combo_phy_trans_edp_hbr2,
859 .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2),
860};
861
862static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = {
863 /* NT mV Trans mV db */
864 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
865 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
866 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
867 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
868 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
869 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
870 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
871 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
872 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
873 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
874};
875
876static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = {
877 .entries = _adls_combo_phy_trans_edp_hbr3,
878 .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3),
879};
880
881static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = {
882 /* NT mV Trans mV db */
883 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
884 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
885 { .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
886 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
887 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
888 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
889 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
890 { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
891 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
892 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
893};
894
895static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = {
896 .entries = _adlp_combo_phy_trans_dp_hbr,
897 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr),
898};
899
900static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = {
901 /* NT mV Trans mV db */
902 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
903 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
904 { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */
905 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
906 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
907 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
908 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
909 { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
910 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
911 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
912};
913
914static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_edp_hbr2[] = {
915 /* NT mV Trans mV db */
916 { .icl = { 0x4, 0x50, 0x38, 0x00, 0x07 } }, /* 200 200 0.0 */
917 { .icl = { 0x4, 0x58, 0x35, 0x00, 0x0A } }, /* 200 250 1.9 */
918 { .icl = { 0x4, 0x60, 0x34, 0x00, 0x0B } }, /* 200 300 3.5 */
919 { .icl = { 0x4, 0x6A, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */
920 { .icl = { 0x4, 0x5E, 0x38, 0x00, 0x07 } }, /* 250 250 0.0 */
921 { .icl = { 0x4, 0x61, 0x36, 0x00, 0x09 } }, /* 250 300 1.6 */
922 { .icl = { 0x4, 0x6B, 0x34, 0x00, 0x0B } }, /* 250 350 2.9 */
923 { .icl = { 0x4, 0x69, 0x39, 0x00, 0x06 } }, /* 300 300 0.0 */
924 { .icl = { 0x4, 0x73, 0x37, 0x00, 0x08 } }, /* 300 350 1.3 */
925 { .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } }, /* 350 350 0.0 */
926};
927
928static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
929 /* NT mV Trans mV db */
930 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
931 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
932 { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } }, /* 350 700 6.0 */
933 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
934 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
935 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
936 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
937 { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
938 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
939 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
940};
941
942static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
943 .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
944 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
945};
946
947static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
948 .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
949 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
950};
951
952static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
953 .entries = _adlp_combo_phy_trans_edp_hbr2,
954 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_edp_hbr2),
955};
956
957static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = {
958 /* VS pre-emp Non-trans mV Pre-emph dB */
959 { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */
960 { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */
961 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
962 { .dkl = { 0x0, 0x0, 0x17 } }, /* 0 3 400mV 9.5 dB */
963 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
964 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
965 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
966 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
967 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
968 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */
969};
970
971static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = {
972 .entries = _adlp_dkl_phy_trans_dp_hbr,
973 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr),
974};
975
976static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = {
977 /* VS pre-emp Non-trans mV Pre-emph dB */
978 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
979 { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */
980 { .dkl = { 0x2, 0x0, 0x0A } }, /* 0 2 400mV 6 dB */
981 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */
982 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
983 { .dkl = { 0x2, 0x0, 0x06 } }, /* 1 1 600mV 3.5 dB */
984 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
985 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
986 { .dkl = { 0x0, 0x0, 0x09 } }, /* 2 1 800mV 3.5 dB */
987 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */
988};
989
990static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = {
991 .entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3,
992 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3),
993};
994
995static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
996 { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */
997 { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */
998 { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */
999 { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */
1000 { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */
1001 { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */
1002 { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */
1003 { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */
1004 { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */
1005 { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */
1006};
1007
1008static const struct intel_ddi_buf_trans dg2_snps_trans = {
1009 .entries = _dg2_snps_trans,
1010 .num_entries = ARRAY_SIZE(_dg2_snps_trans),
1011 .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1,
1012};
1013
1014static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
1015 { .snps = { 62, 0, 0 } }, /* preset 0 */
1016 { .snps = { 55, 0, 7 } }, /* preset 1 */
1017 { .snps = { 50, 0, 12 } }, /* preset 2 */
1018 { .snps = { 44, 0, 18 } }, /* preset 3 */
1019 { .snps = { 35, 0, 21 } }, /* preset 4 */
1020 { .snps = { 59, 3, 0 } }, /* preset 5 */
1021 { .snps = { 53, 3, 6 } }, /* preset 6 */
1022 { .snps = { 48, 3, 11 } }, /* preset 7 */
1023 { .snps = { 42, 5, 15 } }, /* preset 8 */
1024 { .snps = { 37, 5, 20 } }, /* preset 9 */
1025 { .snps = { 56, 6, 0 } }, /* preset 10 */
1026 { .snps = { 48, 7, 7 } }, /* preset 11 */
1027 { .snps = { 45, 7, 10 } }, /* preset 12 */
1028 { .snps = { 39, 8, 15 } }, /* preset 13 */
1029 { .snps = { 48, 14, 0 } }, /* preset 14 */
1030 { .snps = { 45, 4, 4 } }, /* preset 15 */
1031};
1032
1033static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
1034 .entries = _dg2_snps_trans_uhbr,
1035 .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
1036};
1037
1038bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
1039{
1040 return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
1041}
1042
1043static bool use_edp_hobl(struct intel_encoder *encoder)
1044{
1045 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1046 struct intel_connector *connector = intel_dp->attached_connector;
1047
1048 return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;
1049}
1050
1051static bool use_edp_low_vswing(struct intel_encoder *encoder)
1052{
1053 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1054 struct intel_connector *connector = intel_dp->attached_connector;
1055
1056 return connector->panel.vbt.edp.low_vswing;
1057}
1058
1059static const struct intel_ddi_buf_trans *
1060intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries)
1061{
1062 *num_entries = trans->num_entries;
1063 return trans;
1064}
1065
1066static const struct intel_ddi_buf_trans *
1067hsw_get_buf_trans(struct intel_encoder *encoder,
1068 const struct intel_crtc_state *crtc_state,
1069 int *n_entries)
1070{
1071 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1072 return intel_get_buf_trans(&hsw_trans_fdi, n_entries);
1073 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1074 return intel_get_buf_trans(&hsw_trans_hdmi, n_entries);
1075 else
1076 return intel_get_buf_trans(&hsw_trans_dp, n_entries);
1077}
1078
1079static const struct intel_ddi_buf_trans *
1080bdw_get_buf_trans(struct intel_encoder *encoder,
1081 const struct intel_crtc_state *crtc_state,
1082 int *n_entries)
1083{
1084 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1085 return intel_get_buf_trans(&bdw_trans_fdi, n_entries);
1086 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1087 return intel_get_buf_trans(&bdw_trans_hdmi, n_entries);
1088 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1089 use_edp_low_vswing(encoder))
1090 return intel_get_buf_trans(&bdw_trans_edp, n_entries);
1091 else
1092 return intel_get_buf_trans(&bdw_trans_dp, n_entries);
1093}
1094
1095static int skl_buf_trans_num_entries(enum port port, int n_entries)
1096{
1097 /* Only DDIA and DDIE can select the 10th register with DP */
1098 if (port == PORT_A || port == PORT_E)
1099 return min(n_entries, 10);
1100 else
1101 return min(n_entries, 9);
1102}
1103
1104static const struct intel_ddi_buf_trans *
1105_skl_get_buf_trans_dp(struct intel_encoder *encoder,
1106 const struct intel_ddi_buf_trans *trans,
1107 int *n_entries)
1108{
1109 trans = intel_get_buf_trans(trans, n_entries);
1110 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
1111 return trans;
1112}
1113
1114static const struct intel_ddi_buf_trans *
1115skl_y_get_buf_trans(struct intel_encoder *encoder,
1116 const struct intel_crtc_state *crtc_state,
1117 int *n_entries)
1118{
1119 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1120 return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1121 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1122 use_edp_low_vswing(encoder))
1123 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1124 else
1125 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries);
1126}
1127
1128static const struct intel_ddi_buf_trans *
1129skl_u_get_buf_trans(struct intel_encoder *encoder,
1130 const struct intel_crtc_state *crtc_state,
1131 int *n_entries)
1132{
1133 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1134 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1135 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1136 use_edp_low_vswing(encoder))
1137 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1138 else
1139 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries);
1140}
1141
1142static const struct intel_ddi_buf_trans *
1143skl_get_buf_trans(struct intel_encoder *encoder,
1144 const struct intel_crtc_state *crtc_state,
1145 int *n_entries)
1146{
1147 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1148 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1149 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1150 use_edp_low_vswing(encoder))
1151 return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1152 else
1153 return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries);
1154}
1155
1156static const struct intel_ddi_buf_trans *
1157kbl_y_get_buf_trans(struct intel_encoder *encoder,
1158 const struct intel_crtc_state *crtc_state,
1159 int *n_entries)
1160{
1161 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1162 return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1163 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1164 use_edp_low_vswing(encoder))
1165 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1166 else
1167 return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries);
1168}
1169
1170static const struct intel_ddi_buf_trans *
1171kbl_u_get_buf_trans(struct intel_encoder *encoder,
1172 const struct intel_crtc_state *crtc_state,
1173 int *n_entries)
1174{
1175 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1176 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1177 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1178 use_edp_low_vswing(encoder))
1179 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1180 else
1181 return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries);
1182}
1183
1184static const struct intel_ddi_buf_trans *
1185kbl_get_buf_trans(struct intel_encoder *encoder,
1186 const struct intel_crtc_state *crtc_state,
1187 int *n_entries)
1188{
1189 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1190 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1191 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1192 use_edp_low_vswing(encoder))
1193 return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1194 else
1195 return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries);
1196}
1197
1198static const struct intel_ddi_buf_trans *
1199bxt_get_buf_trans(struct intel_encoder *encoder,
1200 const struct intel_crtc_state *crtc_state,
1201 int *n_entries)
1202{
1203 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1204 return intel_get_buf_trans(&bxt_trans_hdmi, n_entries);
1205 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1206 use_edp_low_vswing(encoder))
1207 return intel_get_buf_trans(&bxt_trans_edp, n_entries);
1208 else
1209 return intel_get_buf_trans(&bxt_trans_dp, n_entries);
1210}
1211
1212static const struct intel_ddi_buf_trans *
1213icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1214 const struct intel_crtc_state *crtc_state,
1215 int *n_entries)
1216{
1217 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1218 n_entries);
1219}
1220
1221static const struct intel_ddi_buf_trans *
1222icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1223 const struct intel_crtc_state *crtc_state,
1224 int *n_entries)
1225{
1226 if (crtc_state->port_clock > 540000) {
1227 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1228 n_entries);
1229 } else if (use_edp_low_vswing(encoder)) {
1230 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1231 n_entries);
1232 }
1233
1234 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1235}
1236
1237static const struct intel_ddi_buf_trans *
1238icl_get_combo_buf_trans(struct intel_encoder *encoder,
1239 const struct intel_crtc_state *crtc_state,
1240 int *n_entries)
1241{
1242 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1243 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1244 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1245 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1246 else
1247 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1248}
1249
1250static const struct intel_ddi_buf_trans *
1251icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1252 const struct intel_crtc_state *crtc_state,
1253 int *n_entries)
1254{
1255 if (crtc_state->port_clock > 270000) {
1256 return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3,
1257 n_entries);
1258 } else {
1259 return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr,
1260 n_entries);
1261 }
1262}
1263
1264static const struct intel_ddi_buf_trans *
1265icl_get_mg_buf_trans(struct intel_encoder *encoder,
1266 const struct intel_crtc_state *crtc_state,
1267 int *n_entries)
1268{
1269 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1270 return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries);
1271 else
1272 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1273}
1274
1275static const struct intel_ddi_buf_trans *
1276ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1277 const struct intel_crtc_state *crtc_state,
1278 int *n_entries)
1279{
1280 if (crtc_state->port_clock > 270000)
1281 return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries);
1282 else
1283 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries);
1284}
1285
1286static const struct intel_ddi_buf_trans *
1287ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1288 const struct intel_crtc_state *crtc_state,
1289 int *n_entries)
1290{
1291 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1292 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1293 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1294 use_edp_low_vswing(encoder))
1295 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1296 else
1297 return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries);
1298}
1299
1300static const struct intel_ddi_buf_trans *
1301jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1302 const struct intel_crtc_state *crtc_state,
1303 int *n_entries)
1304{
1305 if (crtc_state->port_clock > 270000)
1306 return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries);
1307 else
1308 return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries);
1309}
1310
1311static const struct intel_ddi_buf_trans *
1312jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1313 const struct intel_crtc_state *crtc_state,
1314 int *n_entries)
1315{
1316 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1317 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1318 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1319 use_edp_low_vswing(encoder))
1320 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1321 else
1322 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries);
1323}
1324
1325static const struct intel_ddi_buf_trans *
1326tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1327 const struct intel_crtc_state *crtc_state,
1328 int *n_entries)
1329{
1330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1331
1332 if (crtc_state->port_clock > 270000) {
1333 if (IS_TGL_UY(dev_priv)) {
1334 return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
1335 n_entries);
1336 } else {
1337 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2,
1338 n_entries);
1339 }
1340 } else {
1341 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr,
1342 n_entries);
1343 }
1344}
1345
1346static const struct intel_ddi_buf_trans *
1347tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1348 const struct intel_crtc_state *crtc_state,
1349 int *n_entries)
1350{
1351 if (crtc_state->port_clock > 540000) {
1352 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1353 n_entries);
1354 } else if (use_edp_hobl(encoder)) {
1355 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1356 n_entries);
1357 } else if (use_edp_low_vswing(encoder)) {
1358 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1359 n_entries);
1360 }
1361
1362 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1363}
1364
1365static const struct intel_ddi_buf_trans *
1366tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1367 const struct intel_crtc_state *crtc_state,
1368 int *n_entries)
1369{
1370 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1371 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1372 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1373 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1374 else
1375 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1376}
1377
1378static const struct intel_ddi_buf_trans *
1379dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1380 const struct intel_crtc_state *crtc_state,
1381 int *n_entries)
1382{
1383 if (crtc_state->port_clock > 270000)
1384 return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3,
1385 n_entries);
1386 else
1387 return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr,
1388 n_entries);
1389}
1390
1391static const struct intel_ddi_buf_trans *
1392dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1393 const struct intel_crtc_state *crtc_state,
1394 int *n_entries)
1395{
1396 if (crtc_state->port_clock > 540000)
1397 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1398 n_entries);
1399 else if (use_edp_hobl(encoder))
1400 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1401 n_entries);
1402 else if (use_edp_low_vswing(encoder))
1403 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1404 n_entries);
1405 else
1406 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1407}
1408
1409static const struct intel_ddi_buf_trans *
1410dg1_get_combo_buf_trans(struct intel_encoder *encoder,
1411 const struct intel_crtc_state *crtc_state,
1412 int *n_entries)
1413{
1414 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1415 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1416 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1417 return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1418 else
1419 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1420}
1421
1422static const struct intel_ddi_buf_trans *
1423rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1424 const struct intel_crtc_state *crtc_state,
1425 int *n_entries)
1426{
1427 if (crtc_state->port_clock > 270000)
1428 return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1429 else
1430 return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries);
1431}
1432
1433static const struct intel_ddi_buf_trans *
1434rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1435 const struct intel_crtc_state *crtc_state,
1436 int *n_entries)
1437{
1438 if (crtc_state->port_clock > 540000) {
1439 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1440 n_entries);
1441 } else if (use_edp_hobl(encoder)) {
1442 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1443 n_entries);
1444 } else if (use_edp_low_vswing(encoder)) {
1445 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1446 n_entries);
1447 }
1448
1449 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1450}
1451
1452static const struct intel_ddi_buf_trans *
1453rkl_get_combo_buf_trans(struct intel_encoder *encoder,
1454 const struct intel_crtc_state *crtc_state,
1455 int *n_entries)
1456{
1457 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1458 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1459 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1460 return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1461 else
1462 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1463}
1464
1465static const struct intel_ddi_buf_trans *
1466adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1467 const struct intel_crtc_state *crtc_state,
1468 int *n_entries)
1469{
1470 if (crtc_state->port_clock > 270000)
1471 return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1472 else
1473 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries);
1474}
1475
1476static const struct intel_ddi_buf_trans *
1477adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1478 const struct intel_crtc_state *crtc_state,
1479 int *n_entries)
1480{
1481 if (crtc_state->port_clock > 540000)
1482 return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries);
1483 else if (use_edp_hobl(encoder))
1484 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries);
1485 else if (use_edp_low_vswing(encoder))
1486 return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries);
1487 else
1488 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1489}
1490
1491static const struct intel_ddi_buf_trans *
1492adls_get_combo_buf_trans(struct intel_encoder *encoder,
1493 const struct intel_crtc_state *crtc_state,
1494 int *n_entries)
1495{
1496 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1497 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1498 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1499 return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1500 else
1501 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1502}
1503
1504static const struct intel_ddi_buf_trans *
1505adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1506 const struct intel_crtc_state *crtc_state,
1507 int *n_entries)
1508{
1509 if (crtc_state->port_clock > 270000)
1510 return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1511 else
1512 return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries);
1513}
1514
1515static const struct intel_ddi_buf_trans *
1516adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1517 const struct intel_crtc_state *crtc_state,
1518 int *n_entries)
1519{
1520 if (crtc_state->port_clock > 540000) {
1521 return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3,
1522 n_entries);
1523 } else if (use_edp_hobl(encoder)) {
1524 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1525 n_entries);
1526 } else if (use_edp_low_vswing(encoder)) {
1527 return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2,
1528 n_entries);
1529 }
1530
1531 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1532}
1533
1534static const struct intel_ddi_buf_trans *
1535adlp_get_combo_buf_trans(struct intel_encoder *encoder,
1536 const struct intel_crtc_state *crtc_state,
1537 int *n_entries)
1538{
1539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1540 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1541 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1542 return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1543 else
1544 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1545}
1546
1547static const struct intel_ddi_buf_trans *
1548tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1549 const struct intel_crtc_state *crtc_state,
1550 int *n_entries)
1551{
1552 if (crtc_state->port_clock > 270000) {
1553 return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2,
1554 n_entries);
1555 } else {
1556 return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr,
1557 n_entries);
1558 }
1559}
1560
1561static const struct intel_ddi_buf_trans *
1562tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1563 const struct intel_crtc_state *crtc_state,
1564 int *n_entries)
1565{
1566 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1567 return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1568 else
1569 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1570}
1571
1572static const struct intel_ddi_buf_trans *
1573adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1574 const struct intel_crtc_state *crtc_state,
1575 int *n_entries)
1576{
1577 if (crtc_state->port_clock > 270000) {
1578 return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3,
1579 n_entries);
1580 } else {
1581 return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr,
1582 n_entries);
1583 }
1584}
1585
1586static const struct intel_ddi_buf_trans *
1587adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1588 const struct intel_crtc_state *crtc_state,
1589 int *n_entries)
1590{
1591 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1592 return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1593 else
1594 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1595}
1596
1597static const struct intel_ddi_buf_trans *
1598dg2_get_snps_buf_trans(struct intel_encoder *encoder,
1599 const struct intel_crtc_state *crtc_state,
1600 int *n_entries)
1601{
1602 if (intel_crtc_has_dp_encoder(crtc_state) &&
1603 intel_dp_is_uhbr(crtc_state))
1604 return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
1605 else
1606 return intel_get_buf_trans(&dg2_snps_trans, n_entries);
1607}
1608
1609void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
1610{
1611 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1612 enum phy phy = intel_port_to_phy(i915, encoder->port);
1613
1614 if (IS_DG2(i915)) {
1615 encoder->get_buf_trans = dg2_get_snps_buf_trans;
1616 } else if (IS_ALDERLAKE_P(i915)) {
1617 if (intel_phy_is_combo(i915, phy))
1618 encoder->get_buf_trans = adlp_get_combo_buf_trans;
1619 else
1620 encoder->get_buf_trans = adlp_get_dkl_buf_trans;
1621 } else if (IS_ALDERLAKE_S(i915)) {
1622 encoder->get_buf_trans = adls_get_combo_buf_trans;
1623 } else if (IS_ROCKETLAKE(i915)) {
1624 encoder->get_buf_trans = rkl_get_combo_buf_trans;
1625 } else if (IS_DG1(i915)) {
1626 encoder->get_buf_trans = dg1_get_combo_buf_trans;
1627 } else if (DISPLAY_VER(i915) >= 12) {
1628 if (intel_phy_is_combo(i915, phy))
1629 encoder->get_buf_trans = tgl_get_combo_buf_trans;
1630 else
1631 encoder->get_buf_trans = tgl_get_dkl_buf_trans;
1632 } else if (DISPLAY_VER(i915) == 11) {
1633 if (IS_PLATFORM(i915, INTEL_JASPERLAKE))
1634 encoder->get_buf_trans = jsl_get_combo_buf_trans;
1635 else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
1636 encoder->get_buf_trans = ehl_get_combo_buf_trans;
1637 else if (intel_phy_is_combo(i915, phy))
1638 encoder->get_buf_trans = icl_get_combo_buf_trans;
1639 else
1640 encoder->get_buf_trans = icl_get_mg_buf_trans;
1641 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1642 encoder->get_buf_trans = bxt_get_buf_trans;
1643 } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
1644 encoder->get_buf_trans = kbl_y_get_buf_trans;
1645 } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
1646 encoder->get_buf_trans = kbl_u_get_buf_trans;
1647 } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
1648 encoder->get_buf_trans = kbl_get_buf_trans;
1649 } else if (IS_SKL_ULX(i915)) {
1650 encoder->get_buf_trans = skl_y_get_buf_trans;
1651 } else if (IS_SKL_ULT(i915)) {
1652 encoder->get_buf_trans = skl_u_get_buf_trans;
1653 } else if (IS_SKYLAKE(i915)) {
1654 encoder->get_buf_trans = skl_get_buf_trans;
1655 } else if (IS_BROADWELL(i915)) {
1656 encoder->get_buf_trans = bdw_get_buf_trans;
1657 } else if (IS_HASWELL(i915)) {
1658 encoder->get_buf_trans = hsw_get_buf_trans;
1659 } else {
1660 MISSING_CASE(INTEL_INFO(i915)->platform);
1661 }
1662}