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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include <linux/kernel.h>
6
7#include <drm/drm_atomic_helper.h>
8#include <drm/drm_atomic_uapi.h>
9#include <drm/drm_damage_helper.h>
10#include <drm/drm_plane_helper.h>
11#include <drm/drm_fourcc.h>
12
13#include "intel_atomic.h"
14#include "intel_atomic_plane.h"
15#include "intel_cursor.h"
16#include "intel_de.h"
17#include "intel_display_types.h"
18#include "intel_display.h"
19#include "intel_fb.h"
20
21#include "intel_frontbuffer.h"
22#include "intel_pm.h"
23#include "intel_psr.h"
24#include "intel_sprite.h"
25
26/* Cursor formats */
27static const u32 intel_cursor_formats[] = {
28 DRM_FORMAT_ARGB8888,
29};
30
31static const u64 cursor_format_modifiers[] = {
32 DRM_FORMAT_MOD_LINEAR,
33 DRM_FORMAT_MOD_INVALID
34};
35
36static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
37{
38 struct drm_i915_private *dev_priv =
39 to_i915(plane_state->uapi.plane->dev);
40 const struct drm_framebuffer *fb = plane_state->hw.fb;
41 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
42 u32 base;
43
44 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
45 base = sg_dma_address(obj->mm.pages->sgl);
46 else
47 base = intel_plane_ggtt_offset(plane_state);
48
49 return base + plane_state->view.color_plane[0].offset;
50}
51
52static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
53{
54 int x = plane_state->uapi.dst.x1;
55 int y = plane_state->uapi.dst.y1;
56 u32 pos = 0;
57
58 if (x < 0) {
59 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
60 x = -x;
61 }
62 pos |= x << CURSOR_X_SHIFT;
63
64 if (y < 0) {
65 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
66 y = -y;
67 }
68 pos |= y << CURSOR_Y_SHIFT;
69
70 return pos;
71}
72
73static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
74{
75 const struct drm_mode_config *config =
76 &plane_state->uapi.plane->dev->mode_config;
77 int width = drm_rect_width(&plane_state->uapi.dst);
78 int height = drm_rect_height(&plane_state->uapi.dst);
79
80 return width > 0 && width <= config->cursor_width &&
81 height > 0 && height <= config->cursor_height;
82}
83
84static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
85{
86 struct drm_i915_private *dev_priv =
87 to_i915(plane_state->uapi.plane->dev);
88 unsigned int rotation = plane_state->hw.rotation;
89 int src_x, src_y;
90 u32 offset;
91 int ret;
92
93 ret = intel_plane_compute_gtt(plane_state);
94 if (ret)
95 return ret;
96
97 if (!plane_state->uapi.visible)
98 return 0;
99
100 src_x = plane_state->uapi.src.x1 >> 16;
101 src_y = plane_state->uapi.src.y1 >> 16;
102
103 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
104 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
105 plane_state, 0);
106
107 if (src_x != 0 || src_y != 0) {
108 drm_dbg_kms(&dev_priv->drm,
109 "Arbitrary cursor panning not supported\n");
110 return -EINVAL;
111 }
112
113 /*
114 * Put the final coordinates back so that the src
115 * coordinate checks will see the right values.
116 */
117 drm_rect_translate_to(&plane_state->uapi.src,
118 src_x << 16, src_y << 16);
119
120 /* ILK+ do this automagically in hardware */
121 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
122 const struct drm_framebuffer *fb = plane_state->hw.fb;
123 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
124 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
125
126 offset += (src_h * src_w - 1) * fb->format->cpp[0];
127 }
128
129 plane_state->view.color_plane[0].offset = offset;
130 plane_state->view.color_plane[0].x = src_x;
131 plane_state->view.color_plane[0].y = src_y;
132
133 return 0;
134}
135
136static int intel_check_cursor(struct intel_crtc_state *crtc_state,
137 struct intel_plane_state *plane_state)
138{
139 const struct drm_framebuffer *fb = plane_state->hw.fb;
140 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
141 const struct drm_rect src = plane_state->uapi.src;
142 const struct drm_rect dst = plane_state->uapi.dst;
143 int ret;
144
145 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
146 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
147 return -EINVAL;
148 }
149
150 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
151 DRM_PLANE_HELPER_NO_SCALING,
152 DRM_PLANE_HELPER_NO_SCALING,
153 true);
154 if (ret)
155 return ret;
156
157 /* Use the unclipped src/dst rectangles, which we program to hw */
158 plane_state->uapi.src = src;
159 plane_state->uapi.dst = dst;
160
161 ret = intel_cursor_check_surface(plane_state);
162 if (ret)
163 return ret;
164
165 if (!plane_state->uapi.visible)
166 return 0;
167
168 ret = intel_plane_check_src_coordinates(plane_state);
169 if (ret)
170 return ret;
171
172 return 0;
173}
174
175static unsigned int
176i845_cursor_max_stride(struct intel_plane *plane,
177 u32 pixel_format, u64 modifier,
178 unsigned int rotation)
179{
180 return 2048;
181}
182
183static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
184{
185 u32 cntl = 0;
186
187 if (crtc_state->gamma_enable)
188 cntl |= CURSOR_GAMMA_ENABLE;
189
190 return cntl;
191}
192
193static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
194 const struct intel_plane_state *plane_state)
195{
196 return CURSOR_ENABLE |
197 CURSOR_FORMAT_ARGB |
198 CURSOR_STRIDE(plane_state->view.color_plane[0].stride);
199}
200
201static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
202{
203 int width = drm_rect_width(&plane_state->uapi.dst);
204
205 /*
206 * 845g/865g are only limited by the width of their cursors,
207 * the height is arbitrary up to the precision of the register.
208 */
209 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
210}
211
212static int i845_check_cursor(struct intel_crtc_state *crtc_state,
213 struct intel_plane_state *plane_state)
214{
215 const struct drm_framebuffer *fb = plane_state->hw.fb;
216 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
217 int ret;
218
219 ret = intel_check_cursor(crtc_state, plane_state);
220 if (ret)
221 return ret;
222
223 /* if we want to turn off the cursor ignore width and height */
224 if (!fb)
225 return 0;
226
227 /* Check for which cursor types we support */
228 if (!i845_cursor_size_ok(plane_state)) {
229 drm_dbg_kms(&i915->drm,
230 "Cursor dimension %dx%d not supported\n",
231 drm_rect_width(&plane_state->uapi.dst),
232 drm_rect_height(&plane_state->uapi.dst));
233 return -EINVAL;
234 }
235
236 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
237 plane_state->view.color_plane[0].stride != fb->pitches[0]);
238
239 switch (fb->pitches[0]) {
240 case 256:
241 case 512:
242 case 1024:
243 case 2048:
244 break;
245 default:
246 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
247 fb->pitches[0]);
248 return -EINVAL;
249 }
250
251 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
252
253 return 0;
254}
255
256static void i845_update_cursor(struct intel_plane *plane,
257 const struct intel_crtc_state *crtc_state,
258 const struct intel_plane_state *plane_state)
259{
260 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
261 u32 cntl = 0, base = 0, pos = 0, size = 0;
262 unsigned long irqflags;
263
264 if (plane_state && plane_state->uapi.visible) {
265 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
266 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
267
268 cntl = plane_state->ctl |
269 i845_cursor_ctl_crtc(crtc_state);
270
271 size = (height << 12) | width;
272
273 base = intel_cursor_base(plane_state);
274 pos = intel_cursor_position(plane_state);
275 }
276
277 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
278
279 /* On these chipsets we can only modify the base/size/stride
280 * whilst the cursor is disabled.
281 */
282 if (plane->cursor.base != base ||
283 plane->cursor.size != size ||
284 plane->cursor.cntl != cntl) {
285 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
286 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
287 intel_de_write_fw(dev_priv, CURSIZE, size);
288 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
289 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
290
291 plane->cursor.base = base;
292 plane->cursor.size = size;
293 plane->cursor.cntl = cntl;
294 } else {
295 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
296 }
297
298 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
299}
300
301static void i845_disable_cursor(struct intel_plane *plane,
302 const struct intel_crtc_state *crtc_state)
303{
304 i845_update_cursor(plane, crtc_state, NULL);
305}
306
307static bool i845_cursor_get_hw_state(struct intel_plane *plane,
308 enum pipe *pipe)
309{
310 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
311 enum intel_display_power_domain power_domain;
312 intel_wakeref_t wakeref;
313 bool ret;
314
315 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
316 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
317 if (!wakeref)
318 return false;
319
320 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
321
322 *pipe = PIPE_A;
323
324 intel_display_power_put(dev_priv, power_domain, wakeref);
325
326 return ret;
327}
328
329static unsigned int
330i9xx_cursor_max_stride(struct intel_plane *plane,
331 u32 pixel_format, u64 modifier,
332 unsigned int rotation)
333{
334 return plane->base.dev->mode_config.cursor_width * 4;
335}
336
337static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
338{
339 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
341 u32 cntl = 0;
342
343 if (DISPLAY_VER(dev_priv) >= 11)
344 return cntl;
345
346 if (crtc_state->gamma_enable)
347 cntl = MCURSOR_GAMMA_ENABLE;
348
349 if (crtc_state->csc_enable)
350 cntl |= MCURSOR_PIPE_CSC_ENABLE;
351
352 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
353 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
354
355 return cntl;
356}
357
358static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
359 const struct intel_plane_state *plane_state)
360{
361 struct drm_i915_private *dev_priv =
362 to_i915(plane_state->uapi.plane->dev);
363 u32 cntl = 0;
364
365 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
366 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
367
368 switch (drm_rect_width(&plane_state->uapi.dst)) {
369 case 64:
370 cntl |= MCURSOR_MODE_64_ARGB_AX;
371 break;
372 case 128:
373 cntl |= MCURSOR_MODE_128_ARGB_AX;
374 break;
375 case 256:
376 cntl |= MCURSOR_MODE_256_ARGB_AX;
377 break;
378 default:
379 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
380 return 0;
381 }
382
383 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
384 cntl |= MCURSOR_ROTATE_180;
385
386 /* Wa_22012358565:adlp */
387 if (DISPLAY_VER(dev_priv) == 13)
388 cntl |= MCURSOR_ARB_SLOTS(1);
389
390 return cntl;
391}
392
393static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
394{
395 struct drm_i915_private *dev_priv =
396 to_i915(plane_state->uapi.plane->dev);
397 int width = drm_rect_width(&plane_state->uapi.dst);
398 int height = drm_rect_height(&plane_state->uapi.dst);
399
400 if (!intel_cursor_size_ok(plane_state))
401 return false;
402
403 /* Cursor width is limited to a few power-of-two sizes */
404 switch (width) {
405 case 256:
406 case 128:
407 case 64:
408 break;
409 default:
410 return false;
411 }
412
413 /*
414 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
415 * height from 8 lines up to the cursor width, when the
416 * cursor is not rotated. Everything else requires square
417 * cursors.
418 */
419 if (HAS_CUR_FBC(dev_priv) &&
420 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
421 if (height < 8 || height > width)
422 return false;
423 } else {
424 if (height != width)
425 return false;
426 }
427
428 return true;
429}
430
431static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
432 struct intel_plane_state *plane_state)
433{
434 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
435 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
436 const struct drm_framebuffer *fb = plane_state->hw.fb;
437 enum pipe pipe = plane->pipe;
438 int ret;
439
440 ret = intel_check_cursor(crtc_state, plane_state);
441 if (ret)
442 return ret;
443
444 /* if we want to turn off the cursor ignore width and height */
445 if (!fb)
446 return 0;
447
448 /* Check for which cursor types we support */
449 if (!i9xx_cursor_size_ok(plane_state)) {
450 drm_dbg(&dev_priv->drm,
451 "Cursor dimension %dx%d not supported\n",
452 drm_rect_width(&plane_state->uapi.dst),
453 drm_rect_height(&plane_state->uapi.dst));
454 return -EINVAL;
455 }
456
457 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
458 plane_state->view.color_plane[0].stride != fb->pitches[0]);
459
460 if (fb->pitches[0] !=
461 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
462 drm_dbg_kms(&dev_priv->drm,
463 "Invalid cursor stride (%u) (cursor width %d)\n",
464 fb->pitches[0],
465 drm_rect_width(&plane_state->uapi.dst));
466 return -EINVAL;
467 }
468
469 /*
470 * There's something wrong with the cursor on CHV pipe C.
471 * If it straddles the left edge of the screen then
472 * moving it away from the edge or disabling it often
473 * results in a pipe underrun, and often that can lead to
474 * dead pipe (constant underrun reported, and it scans
475 * out just a solid color). To recover from that, the
476 * display power well must be turned off and on again.
477 * Refuse the put the cursor into that compromised position.
478 */
479 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
480 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
481 drm_dbg_kms(&dev_priv->drm,
482 "CHV cursor C not allowed to straddle the left screen edge\n");
483 return -EINVAL;
484 }
485
486 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
487
488 return 0;
489}
490
491static void i9xx_update_cursor(struct intel_plane *plane,
492 const struct intel_crtc_state *crtc_state,
493 const struct intel_plane_state *plane_state)
494{
495 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
496 enum pipe pipe = plane->pipe;
497 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
498 unsigned long irqflags;
499
500 if (plane_state && plane_state->uapi.visible) {
501 int width = drm_rect_width(&plane_state->uapi.dst);
502 int height = drm_rect_height(&plane_state->uapi.dst);
503
504 cntl = plane_state->ctl |
505 i9xx_cursor_ctl_crtc(crtc_state);
506
507 if (width != height)
508 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
509
510 base = intel_cursor_base(plane_state);
511 pos = intel_cursor_position(plane_state);
512 }
513
514 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
515
516 /*
517 * On some platforms writing CURCNTR first will also
518 * cause CURPOS to be armed by the CURBASE write.
519 * Without the CURCNTR write the CURPOS write would
520 * arm itself. Thus we always update CURCNTR before
521 * CURPOS.
522 *
523 * On other platforms CURPOS always requires the
524 * CURBASE write to arm the update. Additonally
525 * a write to any of the cursor register will cancel
526 * an already armed cursor update. Thus leaving out
527 * the CURBASE write after CURPOS could lead to a
528 * cursor that doesn't appear to move, or even change
529 * shape. Thus we always write CURBASE.
530 *
531 * The other registers are armed by the CURBASE write
532 * except when the plane is getting enabled at which time
533 * the CURCNTR write arms the update.
534 */
535
536 if (DISPLAY_VER(dev_priv) >= 9)
537 skl_write_cursor_wm(plane, crtc_state);
538
539 if (!intel_crtc_needs_modeset(crtc_state))
540 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
541
542 if (plane->cursor.base != base ||
543 plane->cursor.size != fbc_ctl ||
544 plane->cursor.cntl != cntl) {
545 if (HAS_CUR_FBC(dev_priv))
546 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
547 fbc_ctl);
548 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
549 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
550 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
551
552 plane->cursor.base = base;
553 plane->cursor.size = fbc_ctl;
554 plane->cursor.cntl = cntl;
555 } else {
556 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
557 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
558 }
559
560 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
561}
562
563static void i9xx_disable_cursor(struct intel_plane *plane,
564 const struct intel_crtc_state *crtc_state)
565{
566 i9xx_update_cursor(plane, crtc_state, NULL);
567}
568
569static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
570 enum pipe *pipe)
571{
572 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
573 enum intel_display_power_domain power_domain;
574 intel_wakeref_t wakeref;
575 bool ret;
576 u32 val;
577
578 /*
579 * Not 100% correct for planes that can move between pipes,
580 * but that's only the case for gen2-3 which don't have any
581 * display power wells.
582 */
583 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
584 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
585 if (!wakeref)
586 return false;
587
588 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
589
590 ret = val & MCURSOR_MODE;
591
592 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
593 *pipe = plane->pipe;
594 else
595 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
596 MCURSOR_PIPE_SELECT_SHIFT;
597
598 intel_display_power_put(dev_priv, power_domain, wakeref);
599
600 return ret;
601}
602
603static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
604 u32 format, u64 modifier)
605{
606 return modifier == DRM_FORMAT_MOD_LINEAR &&
607 format == DRM_FORMAT_ARGB8888;
608}
609
610static int
611intel_legacy_cursor_update(struct drm_plane *_plane,
612 struct drm_crtc *_crtc,
613 struct drm_framebuffer *fb,
614 int crtc_x, int crtc_y,
615 unsigned int crtc_w, unsigned int crtc_h,
616 u32 src_x, u32 src_y,
617 u32 src_w, u32 src_h,
618 struct drm_modeset_acquire_ctx *ctx)
619{
620 struct intel_plane *plane = to_intel_plane(_plane);
621 struct intel_crtc *crtc = to_intel_crtc(_crtc);
622 struct intel_plane_state *old_plane_state =
623 to_intel_plane_state(plane->base.state);
624 struct intel_plane_state *new_plane_state;
625 struct intel_crtc_state *crtc_state =
626 to_intel_crtc_state(crtc->base.state);
627 struct intel_crtc_state *new_crtc_state;
628 int ret;
629
630 /*
631 * When crtc is inactive or there is a modeset pending,
632 * wait for it to complete in the slowpath
633 *
634 * FIXME bigjoiner fastpath would be good
635 */
636 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) ||
637 crtc_state->update_pipe || crtc_state->bigjoiner)
638 goto slow;
639
640 /*
641 * Don't do an async update if there is an outstanding commit modifying
642 * the plane. This prevents our async update's changes from getting
643 * overridden by a previous synchronous update's state.
644 */
645 if (old_plane_state->uapi.commit &&
646 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
647 goto slow;
648
649 /*
650 * If any parameters change that may affect watermarks,
651 * take the slowpath. Only changing fb or position should be
652 * in the fastpath.
653 */
654 if (old_plane_state->uapi.crtc != &crtc->base ||
655 old_plane_state->uapi.src_w != src_w ||
656 old_plane_state->uapi.src_h != src_h ||
657 old_plane_state->uapi.crtc_w != crtc_w ||
658 old_plane_state->uapi.crtc_h != crtc_h ||
659 !old_plane_state->uapi.fb != !fb)
660 goto slow;
661
662 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
663 if (!new_plane_state)
664 return -ENOMEM;
665
666 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
667 if (!new_crtc_state) {
668 ret = -ENOMEM;
669 goto out_free;
670 }
671
672 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
673
674 new_plane_state->uapi.src_x = src_x;
675 new_plane_state->uapi.src_y = src_y;
676 new_plane_state->uapi.src_w = src_w;
677 new_plane_state->uapi.src_h = src_h;
678 new_plane_state->uapi.crtc_x = crtc_x;
679 new_plane_state->uapi.crtc_y = crtc_y;
680 new_plane_state->uapi.crtc_w = crtc_w;
681 new_plane_state->uapi.crtc_h = crtc_h;
682
683 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
684
685 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
686 old_plane_state, new_plane_state);
687 if (ret)
688 goto out_free;
689
690 ret = intel_plane_pin_fb(new_plane_state);
691 if (ret)
692 goto out_free;
693
694 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
695 ORIGIN_FLIP);
696 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
697 to_intel_frontbuffer(new_plane_state->hw.fb),
698 plane->frontbuffer_bit);
699
700 /* Swap plane state */
701 plane->base.state = &new_plane_state->uapi;
702
703 /*
704 * We cannot swap crtc_state as it may be in use by an atomic commit or
705 * page flip that's running simultaneously. If we swap crtc_state and
706 * destroy the old state, we will cause a use-after-free there.
707 *
708 * Only update active_planes, which is needed for our internal
709 * bookkeeping. Either value will do the right thing when updating
710 * planes atomically. If the cursor was part of the atomic update then
711 * we would have taken the slowpath.
712 */
713 crtc_state->active_planes = new_crtc_state->active_planes;
714
715 if (new_plane_state->uapi.visible)
716 intel_update_plane(plane, crtc_state, new_plane_state);
717 else
718 intel_disable_plane(plane, crtc_state);
719
720 intel_plane_unpin_fb(old_plane_state);
721
722out_free:
723 if (new_crtc_state)
724 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
725 if (ret)
726 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
727 else
728 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
729 return ret;
730
731slow:
732 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
733 crtc_x, crtc_y, crtc_w, crtc_h,
734 src_x, src_y, src_w, src_h, ctx);
735}
736
737static const struct drm_plane_funcs intel_cursor_plane_funcs = {
738 .update_plane = intel_legacy_cursor_update,
739 .disable_plane = drm_atomic_helper_disable_plane,
740 .destroy = intel_plane_destroy,
741 .atomic_duplicate_state = intel_plane_duplicate_state,
742 .atomic_destroy_state = intel_plane_destroy_state,
743 .format_mod_supported = intel_cursor_format_mod_supported,
744};
745
746struct intel_plane *
747intel_cursor_plane_create(struct drm_i915_private *dev_priv,
748 enum pipe pipe)
749{
750 struct intel_plane *cursor;
751 int ret, zpos;
752
753 cursor = intel_plane_alloc();
754 if (IS_ERR(cursor))
755 return cursor;
756
757 cursor->pipe = pipe;
758 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
759 cursor->id = PLANE_CURSOR;
760 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
761
762 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
763 cursor->max_stride = i845_cursor_max_stride;
764 cursor->update_plane = i845_update_cursor;
765 cursor->disable_plane = i845_disable_cursor;
766 cursor->get_hw_state = i845_cursor_get_hw_state;
767 cursor->check_plane = i845_check_cursor;
768 } else {
769 cursor->max_stride = i9xx_cursor_max_stride;
770 cursor->update_plane = i9xx_update_cursor;
771 cursor->disable_plane = i9xx_disable_cursor;
772 cursor->get_hw_state = i9xx_cursor_get_hw_state;
773 cursor->check_plane = i9xx_check_cursor;
774 }
775
776 cursor->cursor.base = ~0;
777 cursor->cursor.cntl = ~0;
778
779 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
780 cursor->cursor.size = ~0;
781
782 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
783 0, &intel_cursor_plane_funcs,
784 intel_cursor_formats,
785 ARRAY_SIZE(intel_cursor_formats),
786 cursor_format_modifiers,
787 DRM_PLANE_TYPE_CURSOR,
788 "cursor %c", pipe_name(pipe));
789 if (ret)
790 goto fail;
791
792 if (DISPLAY_VER(dev_priv) >= 4)
793 drm_plane_create_rotation_property(&cursor->base,
794 DRM_MODE_ROTATE_0,
795 DRM_MODE_ROTATE_0 |
796 DRM_MODE_ROTATE_180);
797
798 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
799 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
800
801 if (DISPLAY_VER(dev_priv) >= 12)
802 drm_plane_enable_fb_damage_clips(&cursor->base);
803
804 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
805
806 return cursor;
807
808fail:
809 intel_plane_free(cursor);
810
811 return ERR_PTR(ret);
812}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include <linux/kernel.h>
6
7#include <drm/drm_atomic_helper.h>
8#include <drm/drm_atomic_uapi.h>
9#include <drm/drm_blend.h>
10#include <drm/drm_damage_helper.h>
11#include <drm/drm_fourcc.h>
12
13#include "i915_reg.h"
14#include "intel_atomic.h"
15#include "intel_atomic_plane.h"
16#include "intel_cursor.h"
17#include "intel_de.h"
18#include "intel_display.h"
19#include "intel_display_types.h"
20#include "intel_fb.h"
21#include "intel_fb_pin.h"
22#include "intel_frontbuffer.h"
23#include "intel_psr.h"
24#include "intel_sprite.h"
25#include "skl_watermark.h"
26
27/* Cursor formats */
28static const u32 intel_cursor_formats[] = {
29 DRM_FORMAT_ARGB8888,
30};
31
32static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
33{
34 struct drm_i915_private *dev_priv =
35 to_i915(plane_state->uapi.plane->dev);
36 const struct drm_framebuffer *fb = plane_state->hw.fb;
37 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
38 u32 base;
39
40 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
41 base = sg_dma_address(obj->mm.pages->sgl);
42 else
43 base = intel_plane_ggtt_offset(plane_state);
44
45 return base + plane_state->view.color_plane[0].offset;
46}
47
48static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
49{
50 int x = plane_state->uapi.dst.x1;
51 int y = plane_state->uapi.dst.y1;
52 u32 pos = 0;
53
54 if (x < 0) {
55 pos |= CURSOR_POS_X_SIGN;
56 x = -x;
57 }
58 pos |= CURSOR_POS_X(x);
59
60 if (y < 0) {
61 pos |= CURSOR_POS_Y_SIGN;
62 y = -y;
63 }
64 pos |= CURSOR_POS_Y(y);
65
66 return pos;
67}
68
69static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
70{
71 const struct drm_mode_config *config =
72 &plane_state->uapi.plane->dev->mode_config;
73 int width = drm_rect_width(&plane_state->uapi.dst);
74 int height = drm_rect_height(&plane_state->uapi.dst);
75
76 return width > 0 && width <= config->cursor_width &&
77 height > 0 && height <= config->cursor_height;
78}
79
80static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
81{
82 struct drm_i915_private *dev_priv =
83 to_i915(plane_state->uapi.plane->dev);
84 unsigned int rotation = plane_state->hw.rotation;
85 int src_x, src_y;
86 u32 offset;
87 int ret;
88
89 ret = intel_plane_compute_gtt(plane_state);
90 if (ret)
91 return ret;
92
93 if (!plane_state->uapi.visible)
94 return 0;
95
96 src_x = plane_state->uapi.src.x1 >> 16;
97 src_y = plane_state->uapi.src.y1 >> 16;
98
99 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
100 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
101 plane_state, 0);
102
103 if (src_x != 0 || src_y != 0) {
104 drm_dbg_kms(&dev_priv->drm,
105 "Arbitrary cursor panning not supported\n");
106 return -EINVAL;
107 }
108
109 /*
110 * Put the final coordinates back so that the src
111 * coordinate checks will see the right values.
112 */
113 drm_rect_translate_to(&plane_state->uapi.src,
114 src_x << 16, src_y << 16);
115
116 /* ILK+ do this automagically in hardware */
117 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
118 const struct drm_framebuffer *fb = plane_state->hw.fb;
119 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
120 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
121
122 offset += (src_h * src_w - 1) * fb->format->cpp[0];
123 }
124
125 plane_state->view.color_plane[0].offset = offset;
126 plane_state->view.color_plane[0].x = src_x;
127 plane_state->view.color_plane[0].y = src_y;
128
129 return 0;
130}
131
132static int intel_check_cursor(struct intel_crtc_state *crtc_state,
133 struct intel_plane_state *plane_state)
134{
135 const struct drm_framebuffer *fb = plane_state->hw.fb;
136 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
137 const struct drm_rect src = plane_state->uapi.src;
138 const struct drm_rect dst = plane_state->uapi.dst;
139 int ret;
140
141 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
142 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
143 return -EINVAL;
144 }
145
146 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
147 DRM_PLANE_NO_SCALING,
148 DRM_PLANE_NO_SCALING,
149 true);
150 if (ret)
151 return ret;
152
153 /* Use the unclipped src/dst rectangles, which we program to hw */
154 plane_state->uapi.src = src;
155 plane_state->uapi.dst = dst;
156
157 /* final plane coordinates will be relative to the plane's pipe */
158 drm_rect_translate(&plane_state->uapi.dst,
159 -crtc_state->pipe_src.x1,
160 -crtc_state->pipe_src.y1);
161
162 ret = intel_cursor_check_surface(plane_state);
163 if (ret)
164 return ret;
165
166 if (!plane_state->uapi.visible)
167 return 0;
168
169 ret = intel_plane_check_src_coordinates(plane_state);
170 if (ret)
171 return ret;
172
173 return 0;
174}
175
176static unsigned int
177i845_cursor_max_stride(struct intel_plane *plane,
178 u32 pixel_format, u64 modifier,
179 unsigned int rotation)
180{
181 return 2048;
182}
183
184static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
185{
186 u32 cntl = 0;
187
188 if (crtc_state->gamma_enable)
189 cntl |= CURSOR_PIPE_GAMMA_ENABLE;
190
191 return cntl;
192}
193
194static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
195 const struct intel_plane_state *plane_state)
196{
197 return CURSOR_ENABLE |
198 CURSOR_FORMAT_ARGB |
199 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
200}
201
202static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
203{
204 int width = drm_rect_width(&plane_state->uapi.dst);
205
206 /*
207 * 845g/865g are only limited by the width of their cursors,
208 * the height is arbitrary up to the precision of the register.
209 */
210 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
211}
212
213static int i845_check_cursor(struct intel_crtc_state *crtc_state,
214 struct intel_plane_state *plane_state)
215{
216 const struct drm_framebuffer *fb = plane_state->hw.fb;
217 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
218 int ret;
219
220 ret = intel_check_cursor(crtc_state, plane_state);
221 if (ret)
222 return ret;
223
224 /* if we want to turn off the cursor ignore width and height */
225 if (!fb)
226 return 0;
227
228 /* Check for which cursor types we support */
229 if (!i845_cursor_size_ok(plane_state)) {
230 drm_dbg_kms(&i915->drm,
231 "Cursor dimension %dx%d not supported\n",
232 drm_rect_width(&plane_state->uapi.dst),
233 drm_rect_height(&plane_state->uapi.dst));
234 return -EINVAL;
235 }
236
237 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
238 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
239
240 switch (fb->pitches[0]) {
241 case 256:
242 case 512:
243 case 1024:
244 case 2048:
245 break;
246 default:
247 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
248 fb->pitches[0]);
249 return -EINVAL;
250 }
251
252 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
253
254 return 0;
255}
256
257/* TODO: split into noarm+arm pair */
258static void i845_cursor_update_arm(struct intel_plane *plane,
259 const struct intel_crtc_state *crtc_state,
260 const struct intel_plane_state *plane_state)
261{
262 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
263 u32 cntl = 0, base = 0, pos = 0, size = 0;
264
265 if (plane_state && plane_state->uapi.visible) {
266 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
267 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
268
269 cntl = plane_state->ctl |
270 i845_cursor_ctl_crtc(crtc_state);
271
272 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
273
274 base = intel_cursor_base(plane_state);
275 pos = intel_cursor_position(plane_state);
276 }
277
278 /* On these chipsets we can only modify the base/size/stride
279 * whilst the cursor is disabled.
280 */
281 if (plane->cursor.base != base ||
282 plane->cursor.size != size ||
283 plane->cursor.cntl != cntl) {
284 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
285 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
286 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
287 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
288 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
289
290 plane->cursor.base = base;
291 plane->cursor.size = size;
292 plane->cursor.cntl = cntl;
293 } else {
294 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
295 }
296}
297
298static void i845_cursor_disable_arm(struct intel_plane *plane,
299 const struct intel_crtc_state *crtc_state)
300{
301 i845_cursor_update_arm(plane, crtc_state, NULL);
302}
303
304static bool i845_cursor_get_hw_state(struct intel_plane *plane,
305 enum pipe *pipe)
306{
307 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
308 enum intel_display_power_domain power_domain;
309 intel_wakeref_t wakeref;
310 bool ret;
311
312 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
313 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
314 if (!wakeref)
315 return false;
316
317 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
318
319 *pipe = PIPE_A;
320
321 intel_display_power_put(dev_priv, power_domain, wakeref);
322
323 return ret;
324}
325
326static unsigned int
327i9xx_cursor_max_stride(struct intel_plane *plane,
328 u32 pixel_format, u64 modifier,
329 unsigned int rotation)
330{
331 return plane->base.dev->mode_config.cursor_width * 4;
332}
333
334static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
335{
336 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
337 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
338 u32 cntl = 0;
339
340 if (DISPLAY_VER(dev_priv) >= 11)
341 return cntl;
342
343 if (crtc_state->gamma_enable)
344 cntl = MCURSOR_PIPE_GAMMA_ENABLE;
345
346 if (crtc_state->csc_enable)
347 cntl |= MCURSOR_PIPE_CSC_ENABLE;
348
349 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
350 cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
351
352 return cntl;
353}
354
355static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
356 const struct intel_plane_state *plane_state)
357{
358 struct drm_i915_private *dev_priv =
359 to_i915(plane_state->uapi.plane->dev);
360 u32 cntl = 0;
361
362 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
363 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
364
365 switch (drm_rect_width(&plane_state->uapi.dst)) {
366 case 64:
367 cntl |= MCURSOR_MODE_64_ARGB_AX;
368 break;
369 case 128:
370 cntl |= MCURSOR_MODE_128_ARGB_AX;
371 break;
372 case 256:
373 cntl |= MCURSOR_MODE_256_ARGB_AX;
374 break;
375 default:
376 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
377 return 0;
378 }
379
380 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
381 cntl |= MCURSOR_ROTATE_180;
382
383 /* Wa_22012358565:adl-p */
384 if (DISPLAY_VER(dev_priv) == 13)
385 cntl |= MCURSOR_ARB_SLOTS(1);
386
387 return cntl;
388}
389
390static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
391{
392 struct drm_i915_private *dev_priv =
393 to_i915(plane_state->uapi.plane->dev);
394 int width = drm_rect_width(&plane_state->uapi.dst);
395 int height = drm_rect_height(&plane_state->uapi.dst);
396
397 if (!intel_cursor_size_ok(plane_state))
398 return false;
399
400 /* Cursor width is limited to a few power-of-two sizes */
401 switch (width) {
402 case 256:
403 case 128:
404 case 64:
405 break;
406 default:
407 return false;
408 }
409
410 /*
411 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
412 * height from 8 lines up to the cursor width, when the
413 * cursor is not rotated. Everything else requires square
414 * cursors.
415 */
416 if (HAS_CUR_FBC(dev_priv) &&
417 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
418 if (height < 8 || height > width)
419 return false;
420 } else {
421 if (height != width)
422 return false;
423 }
424
425 return true;
426}
427
428static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
429 struct intel_plane_state *plane_state)
430{
431 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
432 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
433 const struct drm_framebuffer *fb = plane_state->hw.fb;
434 enum pipe pipe = plane->pipe;
435 int ret;
436
437 ret = intel_check_cursor(crtc_state, plane_state);
438 if (ret)
439 return ret;
440
441 /* if we want to turn off the cursor ignore width and height */
442 if (!fb)
443 return 0;
444
445 /* Check for which cursor types we support */
446 if (!i9xx_cursor_size_ok(plane_state)) {
447 drm_dbg(&dev_priv->drm,
448 "Cursor dimension %dx%d not supported\n",
449 drm_rect_width(&plane_state->uapi.dst),
450 drm_rect_height(&plane_state->uapi.dst));
451 return -EINVAL;
452 }
453
454 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
455 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
456
457 if (fb->pitches[0] !=
458 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
459 drm_dbg_kms(&dev_priv->drm,
460 "Invalid cursor stride (%u) (cursor width %d)\n",
461 fb->pitches[0],
462 drm_rect_width(&plane_state->uapi.dst));
463 return -EINVAL;
464 }
465
466 /*
467 * There's something wrong with the cursor on CHV pipe C.
468 * If it straddles the left edge of the screen then
469 * moving it away from the edge or disabling it often
470 * results in a pipe underrun, and often that can lead to
471 * dead pipe (constant underrun reported, and it scans
472 * out just a solid color). To recover from that, the
473 * display power well must be turned off and on again.
474 * Refuse the put the cursor into that compromised position.
475 */
476 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
477 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
478 drm_dbg_kms(&dev_priv->drm,
479 "CHV cursor C not allowed to straddle the left screen edge\n");
480 return -EINVAL;
481 }
482
483 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
484
485 return 0;
486}
487
488/* TODO: split into noarm+arm pair */
489static void i9xx_cursor_update_arm(struct intel_plane *plane,
490 const struct intel_crtc_state *crtc_state,
491 const struct intel_plane_state *plane_state)
492{
493 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
494 enum pipe pipe = plane->pipe;
495 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
496
497 if (plane_state && plane_state->uapi.visible) {
498 int width = drm_rect_width(&plane_state->uapi.dst);
499 int height = drm_rect_height(&plane_state->uapi.dst);
500
501 cntl = plane_state->ctl |
502 i9xx_cursor_ctl_crtc(crtc_state);
503
504 if (width != height)
505 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
506
507 base = intel_cursor_base(plane_state);
508 pos = intel_cursor_position(plane_state);
509 }
510
511 /*
512 * On some platforms writing CURCNTR first will also
513 * cause CURPOS to be armed by the CURBASE write.
514 * Without the CURCNTR write the CURPOS write would
515 * arm itself. Thus we always update CURCNTR before
516 * CURPOS.
517 *
518 * On other platforms CURPOS always requires the
519 * CURBASE write to arm the update. Additonally
520 * a write to any of the cursor register will cancel
521 * an already armed cursor update. Thus leaving out
522 * the CURBASE write after CURPOS could lead to a
523 * cursor that doesn't appear to move, or even change
524 * shape. Thus we always write CURBASE.
525 *
526 * The other registers are armed by the CURBASE write
527 * except when the plane is getting enabled at which time
528 * the CURCNTR write arms the update.
529 */
530
531 if (DISPLAY_VER(dev_priv) >= 9)
532 skl_write_cursor_wm(plane, crtc_state);
533
534 if (plane_state)
535 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
536 else
537 intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
538
539 if (plane->cursor.base != base ||
540 plane->cursor.size != fbc_ctl ||
541 plane->cursor.cntl != cntl) {
542 if (HAS_CUR_FBC(dev_priv))
543 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
544 fbc_ctl);
545 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
546 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
547 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
548
549 plane->cursor.base = base;
550 plane->cursor.size = fbc_ctl;
551 plane->cursor.cntl = cntl;
552 } else {
553 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
554 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
555 }
556}
557
558static void i9xx_cursor_disable_arm(struct intel_plane *plane,
559 const struct intel_crtc_state *crtc_state)
560{
561 i9xx_cursor_update_arm(plane, crtc_state, NULL);
562}
563
564static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
565 enum pipe *pipe)
566{
567 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
568 enum intel_display_power_domain power_domain;
569 intel_wakeref_t wakeref;
570 bool ret;
571 u32 val;
572
573 /*
574 * Not 100% correct for planes that can move between pipes,
575 * but that's only the case for gen2-3 which don't have any
576 * display power wells.
577 */
578 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
579 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
580 if (!wakeref)
581 return false;
582
583 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
584
585 ret = val & MCURSOR_MODE_MASK;
586
587 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
588 *pipe = plane->pipe;
589 else
590 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
591
592 intel_display_power_put(dev_priv, power_domain, wakeref);
593
594 return ret;
595}
596
597static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
598 u32 format, u64 modifier)
599{
600 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
601 return false;
602
603 return format == DRM_FORMAT_ARGB8888;
604}
605
606static int
607intel_legacy_cursor_update(struct drm_plane *_plane,
608 struct drm_crtc *_crtc,
609 struct drm_framebuffer *fb,
610 int crtc_x, int crtc_y,
611 unsigned int crtc_w, unsigned int crtc_h,
612 u32 src_x, u32 src_y,
613 u32 src_w, u32 src_h,
614 struct drm_modeset_acquire_ctx *ctx)
615{
616 struct intel_plane *plane = to_intel_plane(_plane);
617 struct intel_crtc *crtc = to_intel_crtc(_crtc);
618 struct intel_plane_state *old_plane_state =
619 to_intel_plane_state(plane->base.state);
620 struct intel_plane_state *new_plane_state;
621 struct intel_crtc_state *crtc_state =
622 to_intel_crtc_state(crtc->base.state);
623 struct intel_crtc_state *new_crtc_state;
624 int ret;
625
626 /*
627 * When crtc is inactive or there is a modeset pending,
628 * wait for it to complete in the slowpath.
629 * PSR2 selective fetch also requires the slow path as
630 * PSR2 plane and transcoder registers can only be updated during
631 * vblank.
632 *
633 * FIXME bigjoiner fastpath would be good
634 */
635 if (!crtc_state->hw.active ||
636 intel_crtc_needs_modeset(crtc_state) ||
637 intel_crtc_needs_fastset(crtc_state) ||
638 crtc_state->bigjoiner_pipes)
639 goto slow;
640
641 /*
642 * Don't do an async update if there is an outstanding commit modifying
643 * the plane. This prevents our async update's changes from getting
644 * overridden by a previous synchronous update's state.
645 */
646 if (old_plane_state->uapi.commit &&
647 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
648 goto slow;
649
650 /*
651 * If any parameters change that may affect watermarks,
652 * take the slowpath. Only changing fb or position should be
653 * in the fastpath.
654 */
655 if (old_plane_state->uapi.crtc != &crtc->base ||
656 old_plane_state->uapi.src_w != src_w ||
657 old_plane_state->uapi.src_h != src_h ||
658 old_plane_state->uapi.crtc_w != crtc_w ||
659 old_plane_state->uapi.crtc_h != crtc_h ||
660 !old_plane_state->uapi.fb != !fb)
661 goto slow;
662
663 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
664 if (!new_plane_state)
665 return -ENOMEM;
666
667 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
668 if (!new_crtc_state) {
669 ret = -ENOMEM;
670 goto out_free;
671 }
672
673 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
674
675 new_plane_state->uapi.src_x = src_x;
676 new_plane_state->uapi.src_y = src_y;
677 new_plane_state->uapi.src_w = src_w;
678 new_plane_state->uapi.src_h = src_h;
679 new_plane_state->uapi.crtc_x = crtc_x;
680 new_plane_state->uapi.crtc_y = crtc_y;
681 new_plane_state->uapi.crtc_w = crtc_w;
682 new_plane_state->uapi.crtc_h = crtc_h;
683
684 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
685
686 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
687 old_plane_state, new_plane_state);
688 if (ret)
689 goto out_free;
690
691 ret = intel_plane_pin_fb(new_plane_state);
692 if (ret)
693 goto out_free;
694
695 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
696 ORIGIN_CURSOR_UPDATE);
697 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
698 to_intel_frontbuffer(new_plane_state->hw.fb),
699 plane->frontbuffer_bit);
700
701 /* Swap plane state */
702 plane->base.state = &new_plane_state->uapi;
703
704 /*
705 * We cannot swap crtc_state as it may be in use by an atomic commit or
706 * page flip that's running simultaneously. If we swap crtc_state and
707 * destroy the old state, we will cause a use-after-free there.
708 *
709 * Only update active_planes, which is needed for our internal
710 * bookkeeping. Either value will do the right thing when updating
711 * planes atomically. If the cursor was part of the atomic update then
712 * we would have taken the slowpath.
713 */
714 crtc_state->active_planes = new_crtc_state->active_planes;
715
716 /*
717 * Technically we should do a vblank evasion here to make
718 * sure all the cursor registers update on the same frame.
719 * For now just make sure the register writes happen as
720 * quickly as possible to minimize the race window.
721 */
722 local_irq_disable();
723
724 if (new_plane_state->uapi.visible) {
725 intel_plane_update_noarm(plane, crtc_state, new_plane_state);
726 intel_plane_update_arm(plane, crtc_state, new_plane_state);
727 } else {
728 intel_plane_disable_arm(plane, crtc_state);
729 }
730
731 local_irq_enable();
732
733 intel_plane_unpin_fb(old_plane_state);
734
735out_free:
736 if (new_crtc_state)
737 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
738 if (ret)
739 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
740 else
741 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
742 return ret;
743
744slow:
745 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
746 crtc_x, crtc_y, crtc_w, crtc_h,
747 src_x, src_y, src_w, src_h, ctx);
748}
749
750static const struct drm_plane_funcs intel_cursor_plane_funcs = {
751 .update_plane = intel_legacy_cursor_update,
752 .disable_plane = drm_atomic_helper_disable_plane,
753 .destroy = intel_plane_destroy,
754 .atomic_duplicate_state = intel_plane_duplicate_state,
755 .atomic_destroy_state = intel_plane_destroy_state,
756 .format_mod_supported = intel_cursor_format_mod_supported,
757};
758
759struct intel_plane *
760intel_cursor_plane_create(struct drm_i915_private *dev_priv,
761 enum pipe pipe)
762{
763 struct intel_plane *cursor;
764 int ret, zpos;
765 u64 *modifiers;
766
767 cursor = intel_plane_alloc();
768 if (IS_ERR(cursor))
769 return cursor;
770
771 cursor->pipe = pipe;
772 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
773 cursor->id = PLANE_CURSOR;
774 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
775
776 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
777 cursor->max_stride = i845_cursor_max_stride;
778 cursor->update_arm = i845_cursor_update_arm;
779 cursor->disable_arm = i845_cursor_disable_arm;
780 cursor->get_hw_state = i845_cursor_get_hw_state;
781 cursor->check_plane = i845_check_cursor;
782 } else {
783 cursor->max_stride = i9xx_cursor_max_stride;
784 cursor->update_arm = i9xx_cursor_update_arm;
785 cursor->disable_arm = i9xx_cursor_disable_arm;
786 cursor->get_hw_state = i9xx_cursor_get_hw_state;
787 cursor->check_plane = i9xx_check_cursor;
788 }
789
790 cursor->cursor.base = ~0;
791 cursor->cursor.cntl = ~0;
792
793 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
794 cursor->cursor.size = ~0;
795
796 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
797
798 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
799 0, &intel_cursor_plane_funcs,
800 intel_cursor_formats,
801 ARRAY_SIZE(intel_cursor_formats),
802 modifiers,
803 DRM_PLANE_TYPE_CURSOR,
804 "cursor %c", pipe_name(pipe));
805
806 kfree(modifiers);
807
808 if (ret)
809 goto fail;
810
811 if (DISPLAY_VER(dev_priv) >= 4)
812 drm_plane_create_rotation_property(&cursor->base,
813 DRM_MODE_ROTATE_0,
814 DRM_MODE_ROTATE_0 |
815 DRM_MODE_ROTATE_180);
816
817 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
818 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
819
820 if (DISPLAY_VER(dev_priv) >= 12)
821 drm_plane_enable_fb_damage_clips(&cursor->base);
822
823 intel_plane_helper_add(cursor);
824
825 return cursor;
826
827fail:
828 intel_plane_free(cursor);
829
830 return ERR_PTR(ret);
831}