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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "gc/gc_10_1_0_offset.h"
41#include "gc/gc_10_1_0_sh_mask.h"
42#include "mp/mp_11_0_offset.h"
43
44#include "soc15.h"
45#include "soc15_common.h"
46#include "gmc_v10_0.h"
47#include "gfxhub_v2_0.h"
48#include "mmhub_v2_0.h"
49#include "nbio_v2_3.h"
50#include "nbio_v7_2.h"
51#include "hdp_v5_0.h"
52#include "nv.h"
53#include "navi10_ih.h"
54#include "gfx_v10_0.h"
55#include "sdma_v5_0.h"
56#include "sdma_v5_2.h"
57#include "vcn_v2_0.h"
58#include "jpeg_v2_0.h"
59#include "vcn_v3_0.h"
60#include "jpeg_v3_0.h"
61#include "dce_virtual.h"
62#include "mes_v10_1.h"
63#include "mxgpu_nv.h"
64#include "smuio_v11_0.h"
65#include "smuio_v11_0_6.h"
66
67static const struct amd_ip_funcs nv_common_ip_funcs;
68
69/* Navi */
70static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
71{
72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
74};
75
76static const struct amdgpu_video_codecs nv_video_codecs_encode =
77{
78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
79 .codec_array = nv_video_codecs_encode_array,
80};
81
82/* Navi1x */
83static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
84{
85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
92};
93
94static const struct amdgpu_video_codecs nv_video_codecs_decode =
95{
96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
97 .codec_array = nv_video_codecs_decode_array,
98};
99
100/* Sienna Cichlid */
101static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
102{
103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
111};
112
113static const struct amdgpu_video_codecs sc_video_codecs_decode =
114{
115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
116 .codec_array = sc_video_codecs_decode_array,
117};
118
119/* SRIOV Sienna Cichlid, not const since data is controlled by host */
120static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
121{
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
124};
125
126static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
127{
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
136};
137
138static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
139{
140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
141 .codec_array = sriov_sc_video_codecs_encode_array,
142};
143
144static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
145{
146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
147 .codec_array = sriov_sc_video_codecs_decode_array,
148};
149
150/* Beige Goby*/
151static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
155};
156
157static const struct amdgpu_video_codecs bg_video_codecs_decode = {
158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
159 .codec_array = bg_video_codecs_decode_array,
160};
161
162static const struct amdgpu_video_codecs bg_video_codecs_encode = {
163 .codec_count = 0,
164 .codec_array = NULL,
165};
166
167/* Yellow Carp*/
168static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
173};
174
175static const struct amdgpu_video_codecs yc_video_codecs_decode = {
176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
177 .codec_array = yc_video_codecs_decode_array,
178};
179
180static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
181 const struct amdgpu_video_codecs **codecs)
182{
183 switch (adev->asic_type) {
184 case CHIP_SIENNA_CICHLID:
185 if (amdgpu_sriov_vf(adev)) {
186 if (encode)
187 *codecs = &sriov_sc_video_codecs_encode;
188 else
189 *codecs = &sriov_sc_video_codecs_decode;
190 } else {
191 if (encode)
192 *codecs = &nv_video_codecs_encode;
193 else
194 *codecs = &sc_video_codecs_decode;
195 }
196 return 0;
197 case CHIP_NAVY_FLOUNDER:
198 case CHIP_DIMGREY_CAVEFISH:
199 case CHIP_VANGOGH:
200 if (encode)
201 *codecs = &nv_video_codecs_encode;
202 else
203 *codecs = &sc_video_codecs_decode;
204 return 0;
205 case CHIP_YELLOW_CARP:
206 if (encode)
207 *codecs = &nv_video_codecs_encode;
208 else
209 *codecs = &yc_video_codecs_decode;
210 return 0;
211 case CHIP_BEIGE_GOBY:
212 if (encode)
213 *codecs = &bg_video_codecs_encode;
214 else
215 *codecs = &bg_video_codecs_decode;
216 return 0;
217 case CHIP_NAVI10:
218 case CHIP_NAVI14:
219 case CHIP_NAVI12:
220 if (encode)
221 *codecs = &nv_video_codecs_encode;
222 else
223 *codecs = &nv_video_codecs_decode;
224 return 0;
225 default:
226 return -EINVAL;
227 }
228}
229
230/*
231 * Indirect registers accessor
232 */
233static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
234{
235 unsigned long address, data;
236 address = adev->nbio.funcs->get_pcie_index_offset(adev);
237 data = adev->nbio.funcs->get_pcie_data_offset(adev);
238
239 return amdgpu_device_indirect_rreg(adev, address, data, reg);
240}
241
242static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
243{
244 unsigned long address, data;
245
246 address = adev->nbio.funcs->get_pcie_index_offset(adev);
247 data = adev->nbio.funcs->get_pcie_data_offset(adev);
248
249 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
250}
251
252static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
253{
254 unsigned long address, data;
255 address = adev->nbio.funcs->get_pcie_index_offset(adev);
256 data = adev->nbio.funcs->get_pcie_data_offset(adev);
257
258 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
259}
260
261static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
262{
263 unsigned long flags, address, data;
264 u32 r;
265 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
266 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
267
268 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
269 WREG32(address, reg * 4);
270 (void)RREG32(address);
271 r = RREG32(data);
272 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
273 return r;
274}
275
276static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
277{
278 unsigned long address, data;
279
280 address = adev->nbio.funcs->get_pcie_index_offset(adev);
281 data = adev->nbio.funcs->get_pcie_data_offset(adev);
282
283 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
284}
285
286static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
287{
288 unsigned long flags, address, data;
289
290 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
291 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
292
293 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
294 WREG32(address, reg * 4);
295 (void)RREG32(address);
296 WREG32(data, v);
297 (void)RREG32(data);
298 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
299}
300
301static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
302{
303 unsigned long flags, address, data;
304 u32 r;
305
306 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
307 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
308
309 spin_lock_irqsave(&adev->didt_idx_lock, flags);
310 WREG32(address, (reg));
311 r = RREG32(data);
312 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
313 return r;
314}
315
316static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
317{
318 unsigned long flags, address, data;
319
320 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
321 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
322
323 spin_lock_irqsave(&adev->didt_idx_lock, flags);
324 WREG32(address, (reg));
325 WREG32(data, (v));
326 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
327}
328
329static u32 nv_get_config_memsize(struct amdgpu_device *adev)
330{
331 return adev->nbio.funcs->get_memsize(adev);
332}
333
334static u32 nv_get_xclk(struct amdgpu_device *adev)
335{
336 return adev->clock.spll.reference_freq;
337}
338
339
340void nv_grbm_select(struct amdgpu_device *adev,
341 u32 me, u32 pipe, u32 queue, u32 vmid)
342{
343 u32 grbm_gfx_cntl = 0;
344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
346 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
347 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
348
349 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
350}
351
352static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
353{
354 /* todo */
355}
356
357static bool nv_read_disabled_bios(struct amdgpu_device *adev)
358{
359 /* todo */
360 return false;
361}
362
363static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
364 u8 *bios, u32 length_bytes)
365{
366 u32 *dw_ptr;
367 u32 i, length_dw;
368 u32 rom_index_offset, rom_data_offset;
369
370 if (bios == NULL)
371 return false;
372 if (length_bytes == 0)
373 return false;
374 /* APU vbios image is part of sbios image */
375 if (adev->flags & AMD_IS_APU)
376 return false;
377
378 dw_ptr = (u32 *)bios;
379 length_dw = ALIGN(length_bytes, 4) / 4;
380
381 rom_index_offset =
382 adev->smuio.funcs->get_rom_index_offset(adev);
383 rom_data_offset =
384 adev->smuio.funcs->get_rom_data_offset(adev);
385
386 /* set rom index to 0 */
387 WREG32(rom_index_offset, 0);
388 /* read out the rom data */
389 for (i = 0; i < length_dw; i++)
390 dw_ptr[i] = RREG32(rom_data_offset);
391
392 return true;
393}
394
395static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
396 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
397 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
398 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
399 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
400 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
401 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
402 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
403 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
404 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
405 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
406 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
407 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
408 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
409 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
410 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
411 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
412 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
413 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
414 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
415};
416
417static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
418 u32 sh_num, u32 reg_offset)
419{
420 uint32_t val;
421
422 mutex_lock(&adev->grbm_idx_mutex);
423 if (se_num != 0xffffffff || sh_num != 0xffffffff)
424 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
425
426 val = RREG32(reg_offset);
427
428 if (se_num != 0xffffffff || sh_num != 0xffffffff)
429 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
430 mutex_unlock(&adev->grbm_idx_mutex);
431 return val;
432}
433
434static uint32_t nv_get_register_value(struct amdgpu_device *adev,
435 bool indexed, u32 se_num,
436 u32 sh_num, u32 reg_offset)
437{
438 if (indexed) {
439 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
440 } else {
441 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
442 return adev->gfx.config.gb_addr_config;
443 return RREG32(reg_offset);
444 }
445}
446
447static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
448 u32 sh_num, u32 reg_offset, u32 *value)
449{
450 uint32_t i;
451 struct soc15_allowed_register_entry *en;
452
453 *value = 0;
454 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
455 en = &nv_allowed_read_registers[i];
456 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
457 reg_offset !=
458 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
459 continue;
460
461 *value = nv_get_register_value(adev,
462 nv_allowed_read_registers[i].grbm_indexed,
463 se_num, sh_num, reg_offset);
464 return 0;
465 }
466 return -EINVAL;
467}
468
469static int nv_asic_mode2_reset(struct amdgpu_device *adev)
470{
471 u32 i;
472 int ret = 0;
473
474 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
475
476 /* disable BM */
477 pci_clear_master(adev->pdev);
478
479 amdgpu_device_cache_pci_state(adev->pdev);
480
481 ret = amdgpu_dpm_mode2_reset(adev);
482 if (ret)
483 dev_err(adev->dev, "GPU mode2 reset failed\n");
484
485 amdgpu_device_load_pci_state(adev->pdev);
486
487 /* wait for asic to come out of reset */
488 for (i = 0; i < adev->usec_timeout; i++) {
489 u32 memsize = adev->nbio.funcs->get_memsize(adev);
490
491 if (memsize != 0xffffffff)
492 break;
493 udelay(1);
494 }
495
496 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
497
498 return ret;
499}
500
501static enum amd_reset_method
502nv_asic_reset_method(struct amdgpu_device *adev)
503{
504 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
505 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
506 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
507 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
508 return amdgpu_reset_method;
509
510 if (amdgpu_reset_method != -1)
511 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
512 amdgpu_reset_method);
513
514 switch (adev->asic_type) {
515 case CHIP_VANGOGH:
516 case CHIP_YELLOW_CARP:
517 return AMD_RESET_METHOD_MODE2;
518 case CHIP_SIENNA_CICHLID:
519 case CHIP_NAVY_FLOUNDER:
520 case CHIP_DIMGREY_CAVEFISH:
521 case CHIP_BEIGE_GOBY:
522 return AMD_RESET_METHOD_MODE1;
523 default:
524 if (amdgpu_dpm_is_baco_supported(adev))
525 return AMD_RESET_METHOD_BACO;
526 else
527 return AMD_RESET_METHOD_MODE1;
528 }
529}
530
531static int nv_asic_reset(struct amdgpu_device *adev)
532{
533 int ret = 0;
534
535 switch (nv_asic_reset_method(adev)) {
536 case AMD_RESET_METHOD_PCI:
537 dev_info(adev->dev, "PCI reset\n");
538 ret = amdgpu_device_pci_reset(adev);
539 break;
540 case AMD_RESET_METHOD_BACO:
541 dev_info(adev->dev, "BACO reset\n");
542 ret = amdgpu_dpm_baco_reset(adev);
543 break;
544 case AMD_RESET_METHOD_MODE2:
545 dev_info(adev->dev, "MODE2 reset\n");
546 ret = nv_asic_mode2_reset(adev);
547 break;
548 default:
549 dev_info(adev->dev, "MODE1 reset\n");
550 ret = amdgpu_device_mode1_reset(adev);
551 break;
552 }
553
554 return ret;
555}
556
557static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
558{
559 /* todo */
560 return 0;
561}
562
563static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
564{
565 /* todo */
566 return 0;
567}
568
569static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
570{
571 if (pci_is_root_bus(adev->pdev->bus))
572 return;
573
574 if (amdgpu_pcie_gen2 == 0)
575 return;
576
577 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
578 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
579 return;
580
581 /* todo */
582}
583
584static void nv_program_aspm(struct amdgpu_device *adev)
585{
586 if (!amdgpu_aspm)
587 return;
588
589 if (!(adev->flags & AMD_IS_APU) &&
590 (adev->nbio.funcs->program_aspm))
591 adev->nbio.funcs->program_aspm(adev);
592
593}
594
595static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
596 bool enable)
597{
598 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
599 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
600}
601
602static const struct amdgpu_ip_block_version nv_common_ip_block =
603{
604 .type = AMD_IP_BLOCK_TYPE_COMMON,
605 .major = 1,
606 .minor = 0,
607 .rev = 0,
608 .funcs = &nv_common_ip_funcs,
609};
610
611static bool nv_is_headless_sku(struct pci_dev *pdev)
612{
613 if ((pdev->device == 0x731E &&
614 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
615 (pdev->device == 0x7340 && pdev->revision == 0xC9) ||
616 (pdev->device == 0x7360 && pdev->revision == 0xC7))
617 return true;
618 return false;
619}
620
621static int nv_reg_base_init(struct amdgpu_device *adev)
622{
623 int r;
624
625 if (amdgpu_discovery) {
626 r = amdgpu_discovery_reg_base_init(adev);
627 if (r) {
628 DRM_WARN("failed to init reg base from ip discovery table, "
629 "fallback to legacy init method\n");
630 goto legacy_init;
631 }
632
633 amdgpu_discovery_harvest_ip(adev);
634 if (nv_is_headless_sku(adev->pdev)) {
635 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
636 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
637 }
638
639 return 0;
640 }
641
642legacy_init:
643 switch (adev->asic_type) {
644 case CHIP_NAVI10:
645 navi10_reg_base_init(adev);
646 break;
647 case CHIP_NAVI14:
648 navi14_reg_base_init(adev);
649 break;
650 case CHIP_NAVI12:
651 navi12_reg_base_init(adev);
652 break;
653 case CHIP_SIENNA_CICHLID:
654 case CHIP_NAVY_FLOUNDER:
655 sienna_cichlid_reg_base_init(adev);
656 break;
657 case CHIP_VANGOGH:
658 vangogh_reg_base_init(adev);
659 break;
660 case CHIP_DIMGREY_CAVEFISH:
661 dimgrey_cavefish_reg_base_init(adev);
662 break;
663 case CHIP_BEIGE_GOBY:
664 beige_goby_reg_base_init(adev);
665 break;
666 case CHIP_YELLOW_CARP:
667 yellow_carp_reg_base_init(adev);
668 break;
669 default:
670 return -EINVAL;
671 }
672
673 return 0;
674}
675
676void nv_set_virt_ops(struct amdgpu_device *adev)
677{
678 adev->virt.ops = &xgpu_nv_virt_ops;
679}
680
681int nv_set_ip_blocks(struct amdgpu_device *adev)
682{
683 int r;
684
685 if (adev->flags & AMD_IS_APU) {
686 adev->nbio.funcs = &nbio_v7_2_funcs;
687 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
688 } else {
689 adev->nbio.funcs = &nbio_v2_3_funcs;
690 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
691 }
692 adev->hdp.funcs = &hdp_v5_0_funcs;
693
694 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
695 adev->smuio.funcs = &smuio_v11_0_6_funcs;
696 else
697 adev->smuio.funcs = &smuio_v11_0_funcs;
698
699 if (adev->asic_type == CHIP_SIENNA_CICHLID)
700 adev->gmc.xgmi.supported = true;
701
702 /* Set IP register base before any HW register access */
703 r = nv_reg_base_init(adev);
704 if (r)
705 return r;
706
707 switch (adev->asic_type) {
708 case CHIP_NAVI10:
709 case CHIP_NAVI14:
710 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
711 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
712 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
713 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
714 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
715 !amdgpu_sriov_vf(adev))
716 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
717 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
718 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
719#if defined(CONFIG_DRM_AMD_DC)
720 else if (amdgpu_device_has_dc_support(adev))
721 amdgpu_device_ip_block_add(adev, &dm_ip_block);
722#endif
723 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
724 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
725 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
726 !amdgpu_sriov_vf(adev))
727 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
728 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
729 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
730 if (adev->enable_mes)
731 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
732 break;
733 case CHIP_NAVI12:
734 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
735 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
736 if (!amdgpu_sriov_vf(adev)) {
737 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
738 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
739 } else {
740 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
741 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
742 }
743 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
744 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
745 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
746 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
747#if defined(CONFIG_DRM_AMD_DC)
748 else if (amdgpu_device_has_dc_support(adev))
749 amdgpu_device_ip_block_add(adev, &dm_ip_block);
750#endif
751 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
752 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
753 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
754 !amdgpu_sriov_vf(adev))
755 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
756 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
757 if (!amdgpu_sriov_vf(adev))
758 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
759 break;
760 case CHIP_SIENNA_CICHLID:
761 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
762 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
763 if (!amdgpu_sriov_vf(adev)) {
764 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
765 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
766 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
767 } else {
768 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
769 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
770 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
771 }
772 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
773 is_support_sw_smu(adev))
774 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
775 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
776 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
777#if defined(CONFIG_DRM_AMD_DC)
778 else if (amdgpu_device_has_dc_support(adev))
779 amdgpu_device_ip_block_add(adev, &dm_ip_block);
780#endif
781 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
782 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
783 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
784 if (!amdgpu_sriov_vf(adev))
785 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
786 if (adev->enable_mes)
787 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
788 break;
789 case CHIP_NAVY_FLOUNDER:
790 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
791 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
792 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
793 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
794 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
795 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
796 is_support_sw_smu(adev))
797 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
798 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
799 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
800#if defined(CONFIG_DRM_AMD_DC)
801 else if (amdgpu_device_has_dc_support(adev))
802 amdgpu_device_ip_block_add(adev, &dm_ip_block);
803#endif
804 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
805 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
806 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
807 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
808 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
809 is_support_sw_smu(adev))
810 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
811 break;
812 case CHIP_VANGOGH:
813 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
814 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
815 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
816 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
817 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
818 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
819 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
820 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
821#if defined(CONFIG_DRM_AMD_DC)
822 else if (amdgpu_device_has_dc_support(adev))
823 amdgpu_device_ip_block_add(adev, &dm_ip_block);
824#endif
825 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
826 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
827 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
828 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
829 break;
830 case CHIP_DIMGREY_CAVEFISH:
831 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
832 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
833 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
834 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
835 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
836 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
837 is_support_sw_smu(adev))
838 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
839 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
840 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
841#if defined(CONFIG_DRM_AMD_DC)
842 else if (amdgpu_device_has_dc_support(adev))
843 amdgpu_device_ip_block_add(adev, &dm_ip_block);
844#endif
845 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
846 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
847 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
848 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
849 break;
850 case CHIP_BEIGE_GOBY:
851 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
852 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
853 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
854 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
855 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
856 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
857 is_support_sw_smu(adev))
858 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
859 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
860 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
861 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
862 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
863#if defined(CONFIG_DRM_AMD_DC)
864 else if (amdgpu_device_has_dc_support(adev))
865 amdgpu_device_ip_block_add(adev, &dm_ip_block);
866#endif
867 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
868 is_support_sw_smu(adev))
869 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
870 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
871 break;
872 case CHIP_YELLOW_CARP:
873 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
874 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
875 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
876 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
877 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
878 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
879 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
880 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
881 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
882 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
883 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
884 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
885#if defined(CONFIG_DRM_AMD_DC)
886 else if (amdgpu_device_has_dc_support(adev))
887 amdgpu_device_ip_block_add(adev, &dm_ip_block);
888#endif
889 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
890 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
891 break;
892 default:
893 return -EINVAL;
894 }
895
896 return 0;
897}
898
899static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
900{
901 return adev->nbio.funcs->get_rev_id(adev);
902}
903
904static bool nv_need_full_reset(struct amdgpu_device *adev)
905{
906 return true;
907}
908
909static bool nv_need_reset_on_init(struct amdgpu_device *adev)
910{
911 u32 sol_reg;
912
913 if (adev->flags & AMD_IS_APU)
914 return false;
915
916 /* Check sOS sign of life register to confirm sys driver and sOS
917 * are already been loaded.
918 */
919 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
920 if (sol_reg)
921 return true;
922
923 return false;
924}
925
926static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
927{
928
929 /* TODO
930 * dummy implement for pcie_replay_count sysfs interface
931 * */
932
933 return 0;
934}
935
936static void nv_init_doorbell_index(struct amdgpu_device *adev)
937{
938 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
939 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
940 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
941 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
942 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
943 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
944 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
945 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
946 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
947 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
948 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
949 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
950 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
951 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
952 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
953 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
954 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
955 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
956 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
957 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
958 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
959 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
960 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
961 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
962 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
963
964 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
965 adev->doorbell_index.sdma_doorbell_range = 20;
966}
967
968static void nv_pre_asic_init(struct amdgpu_device *adev)
969{
970}
971
972static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
973 bool enter)
974{
975 if (enter)
976 amdgpu_gfx_rlc_enter_safe_mode(adev);
977 else
978 amdgpu_gfx_rlc_exit_safe_mode(adev);
979
980 if (adev->gfx.funcs->update_perfmon_mgcg)
981 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
982
983 if (!(adev->flags & AMD_IS_APU) &&
984 (adev->nbio.funcs->enable_aspm))
985 adev->nbio.funcs->enable_aspm(adev, !enter);
986
987 return 0;
988}
989
990static const struct amdgpu_asic_funcs nv_asic_funcs =
991{
992 .read_disabled_bios = &nv_read_disabled_bios,
993 .read_bios_from_rom = &nv_read_bios_from_rom,
994 .read_register = &nv_read_register,
995 .reset = &nv_asic_reset,
996 .reset_method = &nv_asic_reset_method,
997 .set_vga_state = &nv_vga_set_state,
998 .get_xclk = &nv_get_xclk,
999 .set_uvd_clocks = &nv_set_uvd_clocks,
1000 .set_vce_clocks = &nv_set_vce_clocks,
1001 .get_config_memsize = &nv_get_config_memsize,
1002 .init_doorbell_index = &nv_init_doorbell_index,
1003 .need_full_reset = &nv_need_full_reset,
1004 .need_reset_on_init = &nv_need_reset_on_init,
1005 .get_pcie_replay_count = &nv_get_pcie_replay_count,
1006 .supports_baco = &amdgpu_dpm_is_baco_supported,
1007 .pre_asic_init = &nv_pre_asic_init,
1008 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
1009 .query_video_codecs = &nv_query_video_codecs,
1010};
1011
1012static int nv_common_early_init(void *handle)
1013{
1014#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016
1017 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1018 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1019 adev->smc_rreg = NULL;
1020 adev->smc_wreg = NULL;
1021 adev->pcie_rreg = &nv_pcie_rreg;
1022 adev->pcie_wreg = &nv_pcie_wreg;
1023 adev->pcie_rreg64 = &nv_pcie_rreg64;
1024 adev->pcie_wreg64 = &nv_pcie_wreg64;
1025 adev->pciep_rreg = &nv_pcie_port_rreg;
1026 adev->pciep_wreg = &nv_pcie_port_wreg;
1027
1028 /* TODO: will add them during VCN v2 implementation */
1029 adev->uvd_ctx_rreg = NULL;
1030 adev->uvd_ctx_wreg = NULL;
1031
1032 adev->didt_rreg = &nv_didt_rreg;
1033 adev->didt_wreg = &nv_didt_wreg;
1034
1035 adev->asic_funcs = &nv_asic_funcs;
1036
1037 adev->rev_id = nv_get_rev_id(adev);
1038 adev->external_rev_id = 0xff;
1039 switch (adev->asic_type) {
1040 case CHIP_NAVI10:
1041 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1042 AMD_CG_SUPPORT_GFX_CGCG |
1043 AMD_CG_SUPPORT_IH_CG |
1044 AMD_CG_SUPPORT_HDP_MGCG |
1045 AMD_CG_SUPPORT_HDP_LS |
1046 AMD_CG_SUPPORT_SDMA_MGCG |
1047 AMD_CG_SUPPORT_SDMA_LS |
1048 AMD_CG_SUPPORT_MC_MGCG |
1049 AMD_CG_SUPPORT_MC_LS |
1050 AMD_CG_SUPPORT_ATHUB_MGCG |
1051 AMD_CG_SUPPORT_ATHUB_LS |
1052 AMD_CG_SUPPORT_VCN_MGCG |
1053 AMD_CG_SUPPORT_JPEG_MGCG |
1054 AMD_CG_SUPPORT_BIF_MGCG |
1055 AMD_CG_SUPPORT_BIF_LS;
1056 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1057 AMD_PG_SUPPORT_VCN_DPG |
1058 AMD_PG_SUPPORT_JPEG |
1059 AMD_PG_SUPPORT_ATHUB;
1060 adev->external_rev_id = adev->rev_id + 0x1;
1061 break;
1062 case CHIP_NAVI14:
1063 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1064 AMD_CG_SUPPORT_GFX_CGCG |
1065 AMD_CG_SUPPORT_IH_CG |
1066 AMD_CG_SUPPORT_HDP_MGCG |
1067 AMD_CG_SUPPORT_HDP_LS |
1068 AMD_CG_SUPPORT_SDMA_MGCG |
1069 AMD_CG_SUPPORT_SDMA_LS |
1070 AMD_CG_SUPPORT_MC_MGCG |
1071 AMD_CG_SUPPORT_MC_LS |
1072 AMD_CG_SUPPORT_ATHUB_MGCG |
1073 AMD_CG_SUPPORT_ATHUB_LS |
1074 AMD_CG_SUPPORT_VCN_MGCG |
1075 AMD_CG_SUPPORT_JPEG_MGCG |
1076 AMD_CG_SUPPORT_BIF_MGCG |
1077 AMD_CG_SUPPORT_BIF_LS;
1078 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1079 AMD_PG_SUPPORT_JPEG |
1080 AMD_PG_SUPPORT_VCN_DPG;
1081 adev->external_rev_id = adev->rev_id + 20;
1082 break;
1083 case CHIP_NAVI12:
1084 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1085 AMD_CG_SUPPORT_GFX_MGLS |
1086 AMD_CG_SUPPORT_GFX_CGCG |
1087 AMD_CG_SUPPORT_GFX_CP_LS |
1088 AMD_CG_SUPPORT_GFX_RLC_LS |
1089 AMD_CG_SUPPORT_IH_CG |
1090 AMD_CG_SUPPORT_HDP_MGCG |
1091 AMD_CG_SUPPORT_HDP_LS |
1092 AMD_CG_SUPPORT_SDMA_MGCG |
1093 AMD_CG_SUPPORT_SDMA_LS |
1094 AMD_CG_SUPPORT_MC_MGCG |
1095 AMD_CG_SUPPORT_MC_LS |
1096 AMD_CG_SUPPORT_ATHUB_MGCG |
1097 AMD_CG_SUPPORT_ATHUB_LS |
1098 AMD_CG_SUPPORT_VCN_MGCG |
1099 AMD_CG_SUPPORT_JPEG_MGCG;
1100 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1101 AMD_PG_SUPPORT_VCN_DPG |
1102 AMD_PG_SUPPORT_JPEG |
1103 AMD_PG_SUPPORT_ATHUB;
1104 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1105 * as a consequence, the rev_id and external_rev_id are wrong.
1106 * workaround it by hardcoding rev_id to 0 (default value).
1107 */
1108 if (amdgpu_sriov_vf(adev))
1109 adev->rev_id = 0;
1110 adev->external_rev_id = adev->rev_id + 0xa;
1111 break;
1112 case CHIP_SIENNA_CICHLID:
1113 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1114 AMD_CG_SUPPORT_GFX_CGCG |
1115 AMD_CG_SUPPORT_GFX_CGLS |
1116 AMD_CG_SUPPORT_GFX_3D_CGCG |
1117 AMD_CG_SUPPORT_MC_MGCG |
1118 AMD_CG_SUPPORT_VCN_MGCG |
1119 AMD_CG_SUPPORT_JPEG_MGCG |
1120 AMD_CG_SUPPORT_HDP_MGCG |
1121 AMD_CG_SUPPORT_HDP_LS |
1122 AMD_CG_SUPPORT_IH_CG |
1123 AMD_CG_SUPPORT_MC_LS;
1124 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1125 AMD_PG_SUPPORT_VCN_DPG |
1126 AMD_PG_SUPPORT_JPEG |
1127 AMD_PG_SUPPORT_ATHUB |
1128 AMD_PG_SUPPORT_MMHUB;
1129 if (amdgpu_sriov_vf(adev)) {
1130 /* hypervisor control CG and PG enablement */
1131 adev->cg_flags = 0;
1132 adev->pg_flags = 0;
1133 }
1134 adev->external_rev_id = adev->rev_id + 0x28;
1135 break;
1136 case CHIP_NAVY_FLOUNDER:
1137 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1138 AMD_CG_SUPPORT_GFX_CGCG |
1139 AMD_CG_SUPPORT_GFX_CGLS |
1140 AMD_CG_SUPPORT_GFX_3D_CGCG |
1141 AMD_CG_SUPPORT_VCN_MGCG |
1142 AMD_CG_SUPPORT_JPEG_MGCG |
1143 AMD_CG_SUPPORT_MC_MGCG |
1144 AMD_CG_SUPPORT_MC_LS |
1145 AMD_CG_SUPPORT_HDP_MGCG |
1146 AMD_CG_SUPPORT_HDP_LS |
1147 AMD_CG_SUPPORT_IH_CG;
1148 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1149 AMD_PG_SUPPORT_VCN_DPG |
1150 AMD_PG_SUPPORT_JPEG |
1151 AMD_PG_SUPPORT_ATHUB |
1152 AMD_PG_SUPPORT_MMHUB;
1153 adev->external_rev_id = adev->rev_id + 0x32;
1154 break;
1155
1156 case CHIP_VANGOGH:
1157 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1158 AMD_CG_SUPPORT_GFX_MGLS |
1159 AMD_CG_SUPPORT_GFX_CP_LS |
1160 AMD_CG_SUPPORT_GFX_RLC_LS |
1161 AMD_CG_SUPPORT_GFX_CGCG |
1162 AMD_CG_SUPPORT_GFX_CGLS |
1163 AMD_CG_SUPPORT_GFX_3D_CGCG |
1164 AMD_CG_SUPPORT_GFX_3D_CGLS |
1165 AMD_CG_SUPPORT_MC_MGCG |
1166 AMD_CG_SUPPORT_MC_LS |
1167 AMD_CG_SUPPORT_GFX_FGCG |
1168 AMD_CG_SUPPORT_VCN_MGCG |
1169 AMD_CG_SUPPORT_SDMA_MGCG |
1170 AMD_CG_SUPPORT_SDMA_LS |
1171 AMD_CG_SUPPORT_JPEG_MGCG;
1172 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1173 AMD_PG_SUPPORT_VCN |
1174 AMD_PG_SUPPORT_VCN_DPG |
1175 AMD_PG_SUPPORT_JPEG;
1176 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1177 adev->external_rev_id = adev->rev_id + 0x01;
1178 break;
1179 case CHIP_DIMGREY_CAVEFISH:
1180 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1181 AMD_CG_SUPPORT_GFX_CGCG |
1182 AMD_CG_SUPPORT_GFX_CGLS |
1183 AMD_CG_SUPPORT_GFX_3D_CGCG |
1184 AMD_CG_SUPPORT_VCN_MGCG |
1185 AMD_CG_SUPPORT_JPEG_MGCG |
1186 AMD_CG_SUPPORT_MC_MGCG |
1187 AMD_CG_SUPPORT_MC_LS |
1188 AMD_CG_SUPPORT_HDP_MGCG |
1189 AMD_CG_SUPPORT_HDP_LS |
1190 AMD_CG_SUPPORT_IH_CG;
1191 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1192 AMD_PG_SUPPORT_VCN_DPG |
1193 AMD_PG_SUPPORT_JPEG |
1194 AMD_PG_SUPPORT_ATHUB |
1195 AMD_PG_SUPPORT_MMHUB;
1196 adev->external_rev_id = adev->rev_id + 0x3c;
1197 break;
1198 case CHIP_BEIGE_GOBY:
1199 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1200 AMD_CG_SUPPORT_GFX_CGCG |
1201 AMD_CG_SUPPORT_GFX_CGLS |
1202 AMD_CG_SUPPORT_GFX_3D_CGCG |
1203 AMD_CG_SUPPORT_MC_MGCG |
1204 AMD_CG_SUPPORT_MC_LS |
1205 AMD_CG_SUPPORT_HDP_MGCG |
1206 AMD_CG_SUPPORT_HDP_LS |
1207 AMD_CG_SUPPORT_IH_CG |
1208 AMD_CG_SUPPORT_VCN_MGCG;
1209 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1210 AMD_PG_SUPPORT_VCN_DPG |
1211 AMD_PG_SUPPORT_ATHUB |
1212 AMD_PG_SUPPORT_MMHUB;
1213 adev->external_rev_id = adev->rev_id + 0x46;
1214 break;
1215 case CHIP_YELLOW_CARP:
1216 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1217 AMD_CG_SUPPORT_GFX_MGLS |
1218 AMD_CG_SUPPORT_GFX_CGCG |
1219 AMD_CG_SUPPORT_GFX_CGLS |
1220 AMD_CG_SUPPORT_GFX_3D_CGCG |
1221 AMD_CG_SUPPORT_GFX_3D_CGLS |
1222 AMD_CG_SUPPORT_GFX_RLC_LS |
1223 AMD_CG_SUPPORT_GFX_CP_LS |
1224 AMD_CG_SUPPORT_GFX_FGCG |
1225 AMD_CG_SUPPORT_MC_MGCG |
1226 AMD_CG_SUPPORT_MC_LS |
1227 AMD_CG_SUPPORT_SDMA_LS |
1228 AMD_CG_SUPPORT_HDP_MGCG |
1229 AMD_CG_SUPPORT_HDP_LS |
1230 AMD_CG_SUPPORT_ATHUB_MGCG |
1231 AMD_CG_SUPPORT_ATHUB_LS |
1232 AMD_CG_SUPPORT_IH_CG |
1233 AMD_CG_SUPPORT_VCN_MGCG |
1234 AMD_CG_SUPPORT_JPEG_MGCG;
1235 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1236 AMD_PG_SUPPORT_VCN |
1237 AMD_PG_SUPPORT_VCN_DPG |
1238 AMD_PG_SUPPORT_JPEG;
1239 if (adev->pdev->device == 0x1681)
1240 adev->external_rev_id = adev->rev_id + 0x19;
1241 else
1242 adev->external_rev_id = adev->rev_id + 0x01;
1243 break;
1244 default:
1245 /* FIXME: not supported yet */
1246 return -EINVAL;
1247 }
1248
1249 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1250 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1251 AMD_PG_SUPPORT_VCN_DPG |
1252 AMD_PG_SUPPORT_JPEG);
1253
1254 if (amdgpu_sriov_vf(adev)) {
1255 amdgpu_virt_init_setting(adev);
1256 xgpu_nv_mailbox_set_irq_funcs(adev);
1257 }
1258
1259 return 0;
1260}
1261
1262static int nv_common_late_init(void *handle)
1263{
1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265
1266 if (amdgpu_sriov_vf(adev)) {
1267 xgpu_nv_mailbox_get_irq(adev);
1268 amdgpu_virt_update_sriov_video_codec(adev,
1269 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1270 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
1271 }
1272
1273 return 0;
1274}
1275
1276static int nv_common_sw_init(void *handle)
1277{
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280 if (amdgpu_sriov_vf(adev))
1281 xgpu_nv_mailbox_add_irq_id(adev);
1282
1283 return 0;
1284}
1285
1286static int nv_common_sw_fini(void *handle)
1287{
1288 return 0;
1289}
1290
1291static int nv_common_hw_init(void *handle)
1292{
1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294
1295 if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1296 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1297
1298 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1299 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1300
1301 /* enable pcie gen2/3 link */
1302 nv_pcie_gen3_enable(adev);
1303 /* enable aspm */
1304 nv_program_aspm(adev);
1305 /* setup nbio registers */
1306 adev->nbio.funcs->init_registers(adev);
1307 /* remap HDP registers to a hole in mmio space,
1308 * for the purpose of expose those registers
1309 * to process space
1310 */
1311 if (adev->nbio.funcs->remap_hdp_registers)
1312 adev->nbio.funcs->remap_hdp_registers(adev);
1313 /* enable the doorbell aperture */
1314 nv_enable_doorbell_aperture(adev, true);
1315
1316 return 0;
1317}
1318
1319static int nv_common_hw_fini(void *handle)
1320{
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322
1323 /* disable the doorbell aperture */
1324 nv_enable_doorbell_aperture(adev, false);
1325
1326 return 0;
1327}
1328
1329static int nv_common_suspend(void *handle)
1330{
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332
1333 return nv_common_hw_fini(adev);
1334}
1335
1336static int nv_common_resume(void *handle)
1337{
1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340 return nv_common_hw_init(adev);
1341}
1342
1343static bool nv_common_is_idle(void *handle)
1344{
1345 return true;
1346}
1347
1348static int nv_common_wait_for_idle(void *handle)
1349{
1350 return 0;
1351}
1352
1353static int nv_common_soft_reset(void *handle)
1354{
1355 return 0;
1356}
1357
1358static int nv_common_set_clockgating_state(void *handle,
1359 enum amd_clockgating_state state)
1360{
1361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362
1363 if (amdgpu_sriov_vf(adev))
1364 return 0;
1365
1366 switch (adev->asic_type) {
1367 case CHIP_NAVI10:
1368 case CHIP_NAVI14:
1369 case CHIP_NAVI12:
1370 case CHIP_SIENNA_CICHLID:
1371 case CHIP_NAVY_FLOUNDER:
1372 case CHIP_DIMGREY_CAVEFISH:
1373 case CHIP_BEIGE_GOBY:
1374 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1375 state == AMD_CG_STATE_GATE);
1376 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1377 state == AMD_CG_STATE_GATE);
1378 adev->hdp.funcs->update_clock_gating(adev,
1379 state == AMD_CG_STATE_GATE);
1380 adev->smuio.funcs->update_rom_clock_gating(adev,
1381 state == AMD_CG_STATE_GATE);
1382 break;
1383 default:
1384 break;
1385 }
1386 return 0;
1387}
1388
1389static int nv_common_set_powergating_state(void *handle,
1390 enum amd_powergating_state state)
1391{
1392 /* TODO */
1393 return 0;
1394}
1395
1396static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1397{
1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1399
1400 if (amdgpu_sriov_vf(adev))
1401 *flags = 0;
1402
1403 adev->nbio.funcs->get_clockgating_state(adev, flags);
1404
1405 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1406
1407 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1408
1409 return;
1410}
1411
1412static const struct amd_ip_funcs nv_common_ip_funcs = {
1413 .name = "nv_common",
1414 .early_init = nv_common_early_init,
1415 .late_init = nv_common_late_init,
1416 .sw_init = nv_common_sw_init,
1417 .sw_fini = nv_common_sw_fini,
1418 .hw_init = nv_common_hw_init,
1419 .hw_fini = nv_common_hw_fini,
1420 .suspend = nv_common_suspend,
1421 .resume = nv_common_resume,
1422 .is_idle = nv_common_is_idle,
1423 .wait_for_idle = nv_common_wait_for_idle,
1424 .soft_reset = nv_common_soft_reset,
1425 .set_clockgating_state = nv_common_set_clockgating_state,
1426 .set_powergating_state = nv_common_set_powergating_state,
1427 .get_clockgating_state = nv_common_get_clockgating_state,
1428};
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "gc/gc_10_1_0_offset.h"
41#include "gc/gc_10_1_0_sh_mask.h"
42#include "mp/mp_11_0_offset.h"
43
44#include "soc15.h"
45#include "soc15_common.h"
46#include "gmc_v10_0.h"
47#include "gfxhub_v2_0.h"
48#include "mmhub_v2_0.h"
49#include "nbio_v2_3.h"
50#include "nbio_v7_2.h"
51#include "hdp_v5_0.h"
52#include "nv.h"
53#include "navi10_ih.h"
54#include "gfx_v10_0.h"
55#include "sdma_v5_0.h"
56#include "sdma_v5_2.h"
57#include "vcn_v2_0.h"
58#include "jpeg_v2_0.h"
59#include "vcn_v3_0.h"
60#include "jpeg_v3_0.h"
61#include "amdgpu_vkms.h"
62#include "mes_v10_1.h"
63#include "mxgpu_nv.h"
64#include "smuio_v11_0.h"
65#include "smuio_v11_0_6.h"
66
67static const struct amd_ip_funcs nv_common_ip_funcs;
68
69/* Navi */
70static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
71{
72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
74};
75
76static const struct amdgpu_video_codecs nv_video_codecs_encode =
77{
78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
79 .codec_array = nv_video_codecs_encode_array,
80};
81
82/* Navi1x */
83static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
84{
85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
92};
93
94static const struct amdgpu_video_codecs nv_video_codecs_decode =
95{
96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
97 .codec_array = nv_video_codecs_decode_array,
98};
99
100/* Sienna Cichlid */
101static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
102{
103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
111};
112
113static const struct amdgpu_video_codecs sc_video_codecs_decode =
114{
115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
116 .codec_array = sc_video_codecs_decode_array,
117};
118
119/* SRIOV Sienna Cichlid, not const since data is controlled by host */
120static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
121{
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
124};
125
126static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
127{
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
136};
137
138static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
139{
140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
141 .codec_array = sriov_sc_video_codecs_encode_array,
142};
143
144static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
145{
146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
147 .codec_array = sriov_sc_video_codecs_decode_array,
148};
149
150/* Beige Goby*/
151static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
155};
156
157static const struct amdgpu_video_codecs bg_video_codecs_decode = {
158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
159 .codec_array = bg_video_codecs_decode_array,
160};
161
162static const struct amdgpu_video_codecs bg_video_codecs_encode = {
163 .codec_count = 0,
164 .codec_array = NULL,
165};
166
167/* Yellow Carp*/
168static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
173 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
174};
175
176static const struct amdgpu_video_codecs yc_video_codecs_decode = {
177 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
178 .codec_array = yc_video_codecs_decode_array,
179};
180
181static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
182 const struct amdgpu_video_codecs **codecs)
183{
184 switch (adev->ip_versions[UVD_HWIP][0]) {
185 case IP_VERSION(3, 0, 0):
186 case IP_VERSION(3, 0, 64):
187 case IP_VERSION(3, 0, 192):
188 if (amdgpu_sriov_vf(adev)) {
189 if (encode)
190 *codecs = &sriov_sc_video_codecs_encode;
191 else
192 *codecs = &sriov_sc_video_codecs_decode;
193 } else {
194 if (encode)
195 *codecs = &nv_video_codecs_encode;
196 else
197 *codecs = &sc_video_codecs_decode;
198 }
199 return 0;
200 case IP_VERSION(3, 0, 16):
201 case IP_VERSION(3, 0, 2):
202 if (encode)
203 *codecs = &nv_video_codecs_encode;
204 else
205 *codecs = &sc_video_codecs_decode;
206 return 0;
207 case IP_VERSION(3, 1, 1):
208 case IP_VERSION(3, 1, 2):
209 if (encode)
210 *codecs = &nv_video_codecs_encode;
211 else
212 *codecs = &yc_video_codecs_decode;
213 return 0;
214 case IP_VERSION(3, 0, 33):
215 if (encode)
216 *codecs = &bg_video_codecs_encode;
217 else
218 *codecs = &bg_video_codecs_decode;
219 return 0;
220 case IP_VERSION(2, 0, 0):
221 case IP_VERSION(2, 0, 2):
222 if (encode)
223 *codecs = &nv_video_codecs_encode;
224 else
225 *codecs = &nv_video_codecs_decode;
226 return 0;
227 default:
228 return -EINVAL;
229 }
230}
231
232/*
233 * Indirect registers accessor
234 */
235static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
236{
237 unsigned long address, data;
238 address = adev->nbio.funcs->get_pcie_index_offset(adev);
239 data = adev->nbio.funcs->get_pcie_data_offset(adev);
240
241 return amdgpu_device_indirect_rreg(adev, address, data, reg);
242}
243
244static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
245{
246 unsigned long address, data;
247
248 address = adev->nbio.funcs->get_pcie_index_offset(adev);
249 data = adev->nbio.funcs->get_pcie_data_offset(adev);
250
251 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
252}
253
254static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
255{
256 unsigned long address, data;
257 address = adev->nbio.funcs->get_pcie_index_offset(adev);
258 data = adev->nbio.funcs->get_pcie_data_offset(adev);
259
260 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
261}
262
263static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
264{
265 unsigned long address, data;
266
267 address = adev->nbio.funcs->get_pcie_index_offset(adev);
268 data = adev->nbio.funcs->get_pcie_data_offset(adev);
269
270 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
271}
272
273static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
274{
275 unsigned long flags, address, data;
276 u32 r;
277
278 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
279 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
280
281 spin_lock_irqsave(&adev->didt_idx_lock, flags);
282 WREG32(address, (reg));
283 r = RREG32(data);
284 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
285 return r;
286}
287
288static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
289{
290 unsigned long flags, address, data;
291
292 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
293 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
294
295 spin_lock_irqsave(&adev->didt_idx_lock, flags);
296 WREG32(address, (reg));
297 WREG32(data, (v));
298 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
299}
300
301static u32 nv_get_config_memsize(struct amdgpu_device *adev)
302{
303 return adev->nbio.funcs->get_memsize(adev);
304}
305
306static u32 nv_get_xclk(struct amdgpu_device *adev)
307{
308 return adev->clock.spll.reference_freq;
309}
310
311
312void nv_grbm_select(struct amdgpu_device *adev,
313 u32 me, u32 pipe, u32 queue, u32 vmid)
314{
315 u32 grbm_gfx_cntl = 0;
316 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
318 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
319 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
320
321 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
322}
323
324static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
325{
326 /* todo */
327}
328
329static bool nv_read_disabled_bios(struct amdgpu_device *adev)
330{
331 /* todo */
332 return false;
333}
334
335static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
343 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
344 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
354 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
355};
356
357static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
358 u32 sh_num, u32 reg_offset)
359{
360 uint32_t val;
361
362 mutex_lock(&adev->grbm_idx_mutex);
363 if (se_num != 0xffffffff || sh_num != 0xffffffff)
364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
365
366 val = RREG32(reg_offset);
367
368 if (se_num != 0xffffffff || sh_num != 0xffffffff)
369 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
370 mutex_unlock(&adev->grbm_idx_mutex);
371 return val;
372}
373
374static uint32_t nv_get_register_value(struct amdgpu_device *adev,
375 bool indexed, u32 se_num,
376 u32 sh_num, u32 reg_offset)
377{
378 if (indexed) {
379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
380 } else {
381 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
382 return adev->gfx.config.gb_addr_config;
383 return RREG32(reg_offset);
384 }
385}
386
387static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
388 u32 sh_num, u32 reg_offset, u32 *value)
389{
390 uint32_t i;
391 struct soc15_allowed_register_entry *en;
392
393 *value = 0;
394 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
395 en = &nv_allowed_read_registers[i];
396 if (adev->reg_offset[en->hwip][en->inst] &&
397 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
398 + en->reg_offset))
399 continue;
400
401 *value = nv_get_register_value(adev,
402 nv_allowed_read_registers[i].grbm_indexed,
403 se_num, sh_num, reg_offset);
404 return 0;
405 }
406 return -EINVAL;
407}
408
409static int nv_asic_mode2_reset(struct amdgpu_device *adev)
410{
411 u32 i;
412 int ret = 0;
413
414 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
415
416 /* disable BM */
417 pci_clear_master(adev->pdev);
418
419 amdgpu_device_cache_pci_state(adev->pdev);
420
421 ret = amdgpu_dpm_mode2_reset(adev);
422 if (ret)
423 dev_err(adev->dev, "GPU mode2 reset failed\n");
424
425 amdgpu_device_load_pci_state(adev->pdev);
426
427 /* wait for asic to come out of reset */
428 for (i = 0; i < adev->usec_timeout; i++) {
429 u32 memsize = adev->nbio.funcs->get_memsize(adev);
430
431 if (memsize != 0xffffffff)
432 break;
433 udelay(1);
434 }
435
436 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
437
438 return ret;
439}
440
441static enum amd_reset_method
442nv_asic_reset_method(struct amdgpu_device *adev)
443{
444 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
445 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
446 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
447 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
448 return amdgpu_reset_method;
449
450 if (amdgpu_reset_method != -1)
451 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
452 amdgpu_reset_method);
453
454 switch (adev->ip_versions[MP1_HWIP][0]) {
455 case IP_VERSION(11, 5, 0):
456 case IP_VERSION(13, 0, 1):
457 case IP_VERSION(13, 0, 3):
458 case IP_VERSION(13, 0, 5):
459 case IP_VERSION(13, 0, 8):
460 return AMD_RESET_METHOD_MODE2;
461 case IP_VERSION(11, 0, 7):
462 case IP_VERSION(11, 0, 11):
463 case IP_VERSION(11, 0, 12):
464 case IP_VERSION(11, 0, 13):
465 return AMD_RESET_METHOD_MODE1;
466 default:
467 if (amdgpu_dpm_is_baco_supported(adev))
468 return AMD_RESET_METHOD_BACO;
469 else
470 return AMD_RESET_METHOD_MODE1;
471 }
472}
473
474static int nv_asic_reset(struct amdgpu_device *adev)
475{
476 int ret = 0;
477
478 switch (nv_asic_reset_method(adev)) {
479 case AMD_RESET_METHOD_PCI:
480 dev_info(adev->dev, "PCI reset\n");
481 ret = amdgpu_device_pci_reset(adev);
482 break;
483 case AMD_RESET_METHOD_BACO:
484 dev_info(adev->dev, "BACO reset\n");
485 ret = amdgpu_dpm_baco_reset(adev);
486 break;
487 case AMD_RESET_METHOD_MODE2:
488 dev_info(adev->dev, "MODE2 reset\n");
489 ret = nv_asic_mode2_reset(adev);
490 break;
491 default:
492 dev_info(adev->dev, "MODE1 reset\n");
493 ret = amdgpu_device_mode1_reset(adev);
494 break;
495 }
496
497 return ret;
498}
499
500static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
501{
502 /* todo */
503 return 0;
504}
505
506static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
507{
508 /* todo */
509 return 0;
510}
511
512static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
513{
514 if (pci_is_root_bus(adev->pdev->bus))
515 return;
516
517 if (amdgpu_pcie_gen2 == 0)
518 return;
519
520 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
521 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
522 return;
523
524 /* todo */
525}
526
527static void nv_program_aspm(struct amdgpu_device *adev)
528{
529 if (!amdgpu_device_should_use_aspm(adev))
530 return;
531
532 if (!(adev->flags & AMD_IS_APU) &&
533 (adev->nbio.funcs->program_aspm))
534 adev->nbio.funcs->program_aspm(adev);
535
536}
537
538static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
539 bool enable)
540{
541 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
542 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
543}
544
545const struct amdgpu_ip_block_version nv_common_ip_block =
546{
547 .type = AMD_IP_BLOCK_TYPE_COMMON,
548 .major = 1,
549 .minor = 0,
550 .rev = 0,
551 .funcs = &nv_common_ip_funcs,
552};
553
554void nv_set_virt_ops(struct amdgpu_device *adev)
555{
556 adev->virt.ops = &xgpu_nv_virt_ops;
557}
558
559static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
560{
561 return adev->nbio.funcs->get_rev_id(adev);
562}
563
564static bool nv_need_full_reset(struct amdgpu_device *adev)
565{
566 return true;
567}
568
569static bool nv_need_reset_on_init(struct amdgpu_device *adev)
570{
571 u32 sol_reg;
572
573 if (adev->flags & AMD_IS_APU)
574 return false;
575
576 /* Check sOS sign of life register to confirm sys driver and sOS
577 * are already been loaded.
578 */
579 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
580 if (sol_reg)
581 return true;
582
583 return false;
584}
585
586static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
587{
588
589 /* TODO
590 * dummy implement for pcie_replay_count sysfs interface
591 * */
592
593 return 0;
594}
595
596static void nv_init_doorbell_index(struct amdgpu_device *adev)
597{
598 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
599 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
600 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
601 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
602 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
603 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
604 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
605 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
606 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
607 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
608 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
609 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
610 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
611 adev->doorbell_index.gfx_userqueue_start =
612 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
613 adev->doorbell_index.gfx_userqueue_end =
614 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
615 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
616 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
617 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
618 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
619 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
620 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
621 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
622 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
623 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
624 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
625 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
626 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
627 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
628
629 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
630 adev->doorbell_index.sdma_doorbell_range = 20;
631}
632
633static void nv_pre_asic_init(struct amdgpu_device *adev)
634{
635}
636
637static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
638 bool enter)
639{
640 if (enter)
641 amdgpu_gfx_rlc_enter_safe_mode(adev);
642 else
643 amdgpu_gfx_rlc_exit_safe_mode(adev);
644
645 if (adev->gfx.funcs->update_perfmon_mgcg)
646 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
647
648 if (!(adev->flags & AMD_IS_APU) &&
649 (adev->nbio.funcs->enable_aspm) &&
650 amdgpu_device_should_use_aspm(adev))
651 adev->nbio.funcs->enable_aspm(adev, !enter);
652
653 return 0;
654}
655
656static const struct amdgpu_asic_funcs nv_asic_funcs =
657{
658 .read_disabled_bios = &nv_read_disabled_bios,
659 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
660 .read_register = &nv_read_register,
661 .reset = &nv_asic_reset,
662 .reset_method = &nv_asic_reset_method,
663 .set_vga_state = &nv_vga_set_state,
664 .get_xclk = &nv_get_xclk,
665 .set_uvd_clocks = &nv_set_uvd_clocks,
666 .set_vce_clocks = &nv_set_vce_clocks,
667 .get_config_memsize = &nv_get_config_memsize,
668 .init_doorbell_index = &nv_init_doorbell_index,
669 .need_full_reset = &nv_need_full_reset,
670 .need_reset_on_init = &nv_need_reset_on_init,
671 .get_pcie_replay_count = &nv_get_pcie_replay_count,
672 .supports_baco = &amdgpu_dpm_is_baco_supported,
673 .pre_asic_init = &nv_pre_asic_init,
674 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
675 .query_video_codecs = &nv_query_video_codecs,
676};
677
678static int nv_common_early_init(void *handle)
679{
680#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
681 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
682
683 if (!amdgpu_sriov_vf(adev)) {
684 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
685 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
686 }
687 adev->smc_rreg = NULL;
688 adev->smc_wreg = NULL;
689 adev->pcie_rreg = &nv_pcie_rreg;
690 adev->pcie_wreg = &nv_pcie_wreg;
691 adev->pcie_rreg64 = &nv_pcie_rreg64;
692 adev->pcie_wreg64 = &nv_pcie_wreg64;
693 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
694 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
695
696 /* TODO: will add them during VCN v2 implementation */
697 adev->uvd_ctx_rreg = NULL;
698 adev->uvd_ctx_wreg = NULL;
699
700 adev->didt_rreg = &nv_didt_rreg;
701 adev->didt_wreg = &nv_didt_wreg;
702
703 adev->asic_funcs = &nv_asic_funcs;
704
705 adev->rev_id = nv_get_rev_id(adev);
706 adev->external_rev_id = 0xff;
707 /* TODO: split the GC and PG flags based on the relevant IP version for which
708 * they are relevant.
709 */
710 switch (adev->ip_versions[GC_HWIP][0]) {
711 case IP_VERSION(10, 1, 10):
712 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
713 AMD_CG_SUPPORT_GFX_CGCG |
714 AMD_CG_SUPPORT_IH_CG |
715 AMD_CG_SUPPORT_HDP_MGCG |
716 AMD_CG_SUPPORT_HDP_LS |
717 AMD_CG_SUPPORT_SDMA_MGCG |
718 AMD_CG_SUPPORT_SDMA_LS |
719 AMD_CG_SUPPORT_MC_MGCG |
720 AMD_CG_SUPPORT_MC_LS |
721 AMD_CG_SUPPORT_ATHUB_MGCG |
722 AMD_CG_SUPPORT_ATHUB_LS |
723 AMD_CG_SUPPORT_VCN_MGCG |
724 AMD_CG_SUPPORT_JPEG_MGCG |
725 AMD_CG_SUPPORT_BIF_MGCG |
726 AMD_CG_SUPPORT_BIF_LS;
727 adev->pg_flags = AMD_PG_SUPPORT_VCN |
728 AMD_PG_SUPPORT_VCN_DPG |
729 AMD_PG_SUPPORT_JPEG |
730 AMD_PG_SUPPORT_ATHUB;
731 adev->external_rev_id = adev->rev_id + 0x1;
732 break;
733 case IP_VERSION(10, 1, 1):
734 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
735 AMD_CG_SUPPORT_GFX_CGCG |
736 AMD_CG_SUPPORT_IH_CG |
737 AMD_CG_SUPPORT_HDP_MGCG |
738 AMD_CG_SUPPORT_HDP_LS |
739 AMD_CG_SUPPORT_SDMA_MGCG |
740 AMD_CG_SUPPORT_SDMA_LS |
741 AMD_CG_SUPPORT_MC_MGCG |
742 AMD_CG_SUPPORT_MC_LS |
743 AMD_CG_SUPPORT_ATHUB_MGCG |
744 AMD_CG_SUPPORT_ATHUB_LS |
745 AMD_CG_SUPPORT_VCN_MGCG |
746 AMD_CG_SUPPORT_JPEG_MGCG |
747 AMD_CG_SUPPORT_BIF_MGCG |
748 AMD_CG_SUPPORT_BIF_LS;
749 adev->pg_flags = AMD_PG_SUPPORT_VCN |
750 AMD_PG_SUPPORT_JPEG |
751 AMD_PG_SUPPORT_VCN_DPG;
752 adev->external_rev_id = adev->rev_id + 20;
753 break;
754 case IP_VERSION(10, 1, 2):
755 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
756 AMD_CG_SUPPORT_GFX_MGLS |
757 AMD_CG_SUPPORT_GFX_CGCG |
758 AMD_CG_SUPPORT_GFX_CP_LS |
759 AMD_CG_SUPPORT_GFX_RLC_LS |
760 AMD_CG_SUPPORT_IH_CG |
761 AMD_CG_SUPPORT_HDP_MGCG |
762 AMD_CG_SUPPORT_HDP_LS |
763 AMD_CG_SUPPORT_SDMA_MGCG |
764 AMD_CG_SUPPORT_SDMA_LS |
765 AMD_CG_SUPPORT_MC_MGCG |
766 AMD_CG_SUPPORT_MC_LS |
767 AMD_CG_SUPPORT_ATHUB_MGCG |
768 AMD_CG_SUPPORT_ATHUB_LS |
769 AMD_CG_SUPPORT_VCN_MGCG |
770 AMD_CG_SUPPORT_JPEG_MGCG;
771 adev->pg_flags = AMD_PG_SUPPORT_VCN |
772 AMD_PG_SUPPORT_VCN_DPG |
773 AMD_PG_SUPPORT_JPEG |
774 AMD_PG_SUPPORT_ATHUB;
775 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
776 * as a consequence, the rev_id and external_rev_id are wrong.
777 * workaround it by hardcoding rev_id to 0 (default value).
778 */
779 if (amdgpu_sriov_vf(adev))
780 adev->rev_id = 0;
781 adev->external_rev_id = adev->rev_id + 0xa;
782 break;
783 case IP_VERSION(10, 3, 0):
784 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
785 AMD_CG_SUPPORT_GFX_CGCG |
786 AMD_CG_SUPPORT_GFX_CGLS |
787 AMD_CG_SUPPORT_GFX_3D_CGCG |
788 AMD_CG_SUPPORT_MC_MGCG |
789 AMD_CG_SUPPORT_VCN_MGCG |
790 AMD_CG_SUPPORT_JPEG_MGCG |
791 AMD_CG_SUPPORT_HDP_MGCG |
792 AMD_CG_SUPPORT_HDP_LS |
793 AMD_CG_SUPPORT_IH_CG |
794 AMD_CG_SUPPORT_MC_LS;
795 adev->pg_flags = AMD_PG_SUPPORT_VCN |
796 AMD_PG_SUPPORT_VCN_DPG |
797 AMD_PG_SUPPORT_JPEG |
798 AMD_PG_SUPPORT_ATHUB |
799 AMD_PG_SUPPORT_MMHUB;
800 if (amdgpu_sriov_vf(adev)) {
801 /* hypervisor control CG and PG enablement */
802 adev->cg_flags = 0;
803 adev->pg_flags = 0;
804 }
805 adev->external_rev_id = adev->rev_id + 0x28;
806 break;
807 case IP_VERSION(10, 3, 2):
808 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
809 AMD_CG_SUPPORT_GFX_CGCG |
810 AMD_CG_SUPPORT_GFX_CGLS |
811 AMD_CG_SUPPORT_GFX_3D_CGCG |
812 AMD_CG_SUPPORT_VCN_MGCG |
813 AMD_CG_SUPPORT_JPEG_MGCG |
814 AMD_CG_SUPPORT_MC_MGCG |
815 AMD_CG_SUPPORT_MC_LS |
816 AMD_CG_SUPPORT_HDP_MGCG |
817 AMD_CG_SUPPORT_HDP_LS |
818 AMD_CG_SUPPORT_IH_CG;
819 adev->pg_flags = AMD_PG_SUPPORT_VCN |
820 AMD_PG_SUPPORT_VCN_DPG |
821 AMD_PG_SUPPORT_JPEG |
822 AMD_PG_SUPPORT_ATHUB |
823 AMD_PG_SUPPORT_MMHUB;
824 adev->external_rev_id = adev->rev_id + 0x32;
825 break;
826 case IP_VERSION(10, 3, 1):
827 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
828 AMD_CG_SUPPORT_GFX_MGLS |
829 AMD_CG_SUPPORT_GFX_CP_LS |
830 AMD_CG_SUPPORT_GFX_RLC_LS |
831 AMD_CG_SUPPORT_GFX_CGCG |
832 AMD_CG_SUPPORT_GFX_CGLS |
833 AMD_CG_SUPPORT_GFX_3D_CGCG |
834 AMD_CG_SUPPORT_GFX_3D_CGLS |
835 AMD_CG_SUPPORT_MC_MGCG |
836 AMD_CG_SUPPORT_MC_LS |
837 AMD_CG_SUPPORT_GFX_FGCG |
838 AMD_CG_SUPPORT_VCN_MGCG |
839 AMD_CG_SUPPORT_SDMA_MGCG |
840 AMD_CG_SUPPORT_SDMA_LS |
841 AMD_CG_SUPPORT_JPEG_MGCG;
842 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
843 AMD_PG_SUPPORT_VCN |
844 AMD_PG_SUPPORT_VCN_DPG |
845 AMD_PG_SUPPORT_JPEG;
846 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
847 adev->external_rev_id = adev->rev_id + 0x01;
848 break;
849 case IP_VERSION(10, 3, 4):
850 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
851 AMD_CG_SUPPORT_GFX_CGCG |
852 AMD_CG_SUPPORT_GFX_CGLS |
853 AMD_CG_SUPPORT_GFX_3D_CGCG |
854 AMD_CG_SUPPORT_VCN_MGCG |
855 AMD_CG_SUPPORT_JPEG_MGCG |
856 AMD_CG_SUPPORT_MC_MGCG |
857 AMD_CG_SUPPORT_MC_LS |
858 AMD_CG_SUPPORT_HDP_MGCG |
859 AMD_CG_SUPPORT_HDP_LS |
860 AMD_CG_SUPPORT_IH_CG;
861 adev->pg_flags = AMD_PG_SUPPORT_VCN |
862 AMD_PG_SUPPORT_VCN_DPG |
863 AMD_PG_SUPPORT_JPEG |
864 AMD_PG_SUPPORT_ATHUB |
865 AMD_PG_SUPPORT_MMHUB;
866 adev->external_rev_id = adev->rev_id + 0x3c;
867 break;
868 case IP_VERSION(10, 3, 5):
869 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
870 AMD_CG_SUPPORT_GFX_CGCG |
871 AMD_CG_SUPPORT_GFX_CGLS |
872 AMD_CG_SUPPORT_GFX_3D_CGCG |
873 AMD_CG_SUPPORT_MC_MGCG |
874 AMD_CG_SUPPORT_MC_LS |
875 AMD_CG_SUPPORT_HDP_MGCG |
876 AMD_CG_SUPPORT_HDP_LS |
877 AMD_CG_SUPPORT_IH_CG |
878 AMD_CG_SUPPORT_VCN_MGCG;
879 adev->pg_flags = AMD_PG_SUPPORT_VCN |
880 AMD_PG_SUPPORT_VCN_DPG |
881 AMD_PG_SUPPORT_ATHUB |
882 AMD_PG_SUPPORT_MMHUB;
883 adev->external_rev_id = adev->rev_id + 0x46;
884 break;
885 case IP_VERSION(10, 3, 3):
886 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
887 AMD_CG_SUPPORT_GFX_MGLS |
888 AMD_CG_SUPPORT_GFX_CGCG |
889 AMD_CG_SUPPORT_GFX_CGLS |
890 AMD_CG_SUPPORT_GFX_3D_CGCG |
891 AMD_CG_SUPPORT_GFX_3D_CGLS |
892 AMD_CG_SUPPORT_GFX_RLC_LS |
893 AMD_CG_SUPPORT_GFX_CP_LS |
894 AMD_CG_SUPPORT_GFX_FGCG |
895 AMD_CG_SUPPORT_MC_MGCG |
896 AMD_CG_SUPPORT_MC_LS |
897 AMD_CG_SUPPORT_SDMA_LS |
898 AMD_CG_SUPPORT_HDP_MGCG |
899 AMD_CG_SUPPORT_HDP_LS |
900 AMD_CG_SUPPORT_ATHUB_MGCG |
901 AMD_CG_SUPPORT_ATHUB_LS |
902 AMD_CG_SUPPORT_IH_CG |
903 AMD_CG_SUPPORT_VCN_MGCG |
904 AMD_CG_SUPPORT_JPEG_MGCG;
905 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
906 AMD_PG_SUPPORT_VCN |
907 AMD_PG_SUPPORT_VCN_DPG |
908 AMD_PG_SUPPORT_JPEG;
909 if (adev->pdev->device == 0x1681)
910 adev->external_rev_id = 0x20;
911 else
912 adev->external_rev_id = adev->rev_id + 0x01;
913 break;
914 case IP_VERSION(10, 1, 3):
915 case IP_VERSION(10, 1, 4):
916 adev->cg_flags = 0;
917 adev->pg_flags = 0;
918 adev->external_rev_id = adev->rev_id + 0x82;
919 break;
920 case IP_VERSION(10, 3, 6):
921 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
922 AMD_CG_SUPPORT_GFX_MGLS |
923 AMD_CG_SUPPORT_GFX_CGCG |
924 AMD_CG_SUPPORT_GFX_CGLS |
925 AMD_CG_SUPPORT_GFX_3D_CGCG |
926 AMD_CG_SUPPORT_GFX_3D_CGLS |
927 AMD_CG_SUPPORT_GFX_RLC_LS |
928 AMD_CG_SUPPORT_GFX_CP_LS |
929 AMD_CG_SUPPORT_GFX_FGCG |
930 AMD_CG_SUPPORT_MC_MGCG |
931 AMD_CG_SUPPORT_MC_LS |
932 AMD_CG_SUPPORT_SDMA_LS |
933 AMD_CG_SUPPORT_HDP_MGCG |
934 AMD_CG_SUPPORT_HDP_LS |
935 AMD_CG_SUPPORT_ATHUB_MGCG |
936 AMD_CG_SUPPORT_ATHUB_LS |
937 AMD_CG_SUPPORT_IH_CG |
938 AMD_CG_SUPPORT_VCN_MGCG |
939 AMD_CG_SUPPORT_JPEG_MGCG;
940 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
941 AMD_PG_SUPPORT_VCN |
942 AMD_PG_SUPPORT_VCN_DPG |
943 AMD_PG_SUPPORT_JPEG;
944 adev->external_rev_id = adev->rev_id + 0x01;
945 break;
946 case IP_VERSION(10, 3, 7):
947 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
948 AMD_CG_SUPPORT_GFX_MGLS |
949 AMD_CG_SUPPORT_GFX_CGCG |
950 AMD_CG_SUPPORT_GFX_CGLS |
951 AMD_CG_SUPPORT_GFX_3D_CGCG |
952 AMD_CG_SUPPORT_GFX_3D_CGLS |
953 AMD_CG_SUPPORT_GFX_RLC_LS |
954 AMD_CG_SUPPORT_GFX_CP_LS |
955 AMD_CG_SUPPORT_GFX_FGCG |
956 AMD_CG_SUPPORT_MC_MGCG |
957 AMD_CG_SUPPORT_MC_LS |
958 AMD_CG_SUPPORT_SDMA_LS |
959 AMD_CG_SUPPORT_HDP_MGCG |
960 AMD_CG_SUPPORT_HDP_LS |
961 AMD_CG_SUPPORT_ATHUB_MGCG |
962 AMD_CG_SUPPORT_ATHUB_LS |
963 AMD_CG_SUPPORT_IH_CG |
964 AMD_CG_SUPPORT_VCN_MGCG |
965 AMD_CG_SUPPORT_JPEG_MGCG;
966 adev->pg_flags = AMD_PG_SUPPORT_VCN |
967 AMD_PG_SUPPORT_VCN_DPG |
968 AMD_PG_SUPPORT_JPEG |
969 AMD_PG_SUPPORT_GFX_PG;
970 adev->external_rev_id = adev->rev_id + 0x01;
971 break;
972 default:
973 /* FIXME: not supported yet */
974 return -EINVAL;
975 }
976
977 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
978 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
979 AMD_PG_SUPPORT_VCN_DPG |
980 AMD_PG_SUPPORT_JPEG);
981
982 if (amdgpu_sriov_vf(adev)) {
983 amdgpu_virt_init_setting(adev);
984 xgpu_nv_mailbox_set_irq_funcs(adev);
985 }
986
987 return 0;
988}
989
990static int nv_common_late_init(void *handle)
991{
992 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
993
994 if (amdgpu_sriov_vf(adev)) {
995 xgpu_nv_mailbox_get_irq(adev);
996 amdgpu_virt_update_sriov_video_codec(adev,
997 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
998 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
999 }
1000
1001 return 0;
1002}
1003
1004static int nv_common_sw_init(void *handle)
1005{
1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008 if (amdgpu_sriov_vf(adev))
1009 xgpu_nv_mailbox_add_irq_id(adev);
1010
1011 return 0;
1012}
1013
1014static int nv_common_sw_fini(void *handle)
1015{
1016 return 0;
1017}
1018
1019static int nv_common_hw_init(void *handle)
1020{
1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022
1023 if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1024 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1025
1026 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1027 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1028
1029 /* enable pcie gen2/3 link */
1030 nv_pcie_gen3_enable(adev);
1031 /* enable aspm */
1032 nv_program_aspm(adev);
1033 /* setup nbio registers */
1034 adev->nbio.funcs->init_registers(adev);
1035 /* remap HDP registers to a hole in mmio space,
1036 * for the purpose of expose those registers
1037 * to process space
1038 */
1039 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1040 adev->nbio.funcs->remap_hdp_registers(adev);
1041 /* enable the doorbell aperture */
1042 nv_enable_doorbell_aperture(adev, true);
1043
1044 return 0;
1045}
1046
1047static int nv_common_hw_fini(void *handle)
1048{
1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050
1051 /* disable the doorbell aperture */
1052 nv_enable_doorbell_aperture(adev, false);
1053
1054 return 0;
1055}
1056
1057static int nv_common_suspend(void *handle)
1058{
1059 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1060
1061 return nv_common_hw_fini(adev);
1062}
1063
1064static int nv_common_resume(void *handle)
1065{
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067
1068 return nv_common_hw_init(adev);
1069}
1070
1071static bool nv_common_is_idle(void *handle)
1072{
1073 return true;
1074}
1075
1076static int nv_common_wait_for_idle(void *handle)
1077{
1078 return 0;
1079}
1080
1081static int nv_common_soft_reset(void *handle)
1082{
1083 return 0;
1084}
1085
1086static int nv_common_set_clockgating_state(void *handle,
1087 enum amd_clockgating_state state)
1088{
1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090
1091 if (amdgpu_sriov_vf(adev))
1092 return 0;
1093
1094 switch (adev->ip_versions[NBIO_HWIP][0]) {
1095 case IP_VERSION(2, 3, 0):
1096 case IP_VERSION(2, 3, 1):
1097 case IP_VERSION(2, 3, 2):
1098 case IP_VERSION(3, 3, 0):
1099 case IP_VERSION(3, 3, 1):
1100 case IP_VERSION(3, 3, 2):
1101 case IP_VERSION(3, 3, 3):
1102 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1103 state == AMD_CG_STATE_GATE);
1104 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1105 state == AMD_CG_STATE_GATE);
1106 adev->hdp.funcs->update_clock_gating(adev,
1107 state == AMD_CG_STATE_GATE);
1108 adev->smuio.funcs->update_rom_clock_gating(adev,
1109 state == AMD_CG_STATE_GATE);
1110 break;
1111 default:
1112 break;
1113 }
1114 return 0;
1115}
1116
1117static int nv_common_set_powergating_state(void *handle,
1118 enum amd_powergating_state state)
1119{
1120 /* TODO */
1121 return 0;
1122}
1123
1124static void nv_common_get_clockgating_state(void *handle, u64 *flags)
1125{
1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1127
1128 if (amdgpu_sriov_vf(adev))
1129 *flags = 0;
1130
1131 adev->nbio.funcs->get_clockgating_state(adev, flags);
1132
1133 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1134
1135 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1136
1137 return;
1138}
1139
1140static const struct amd_ip_funcs nv_common_ip_funcs = {
1141 .name = "nv_common",
1142 .early_init = nv_common_early_init,
1143 .late_init = nv_common_late_init,
1144 .sw_init = nv_common_sw_init,
1145 .sw_fini = nv_common_sw_fini,
1146 .hw_init = nv_common_hw_init,
1147 .hw_fini = nv_common_hw_fini,
1148 .suspend = nv_common_suspend,
1149 .resume = nv_common_resume,
1150 .is_idle = nv_common_is_idle,
1151 .wait_for_idle = nv_common_wait_for_idle,
1152 .soft_reset = nv_common_soft_reset,
1153 .set_clockgating_state = nv_common_set_clockgating_state,
1154 .set_powergating_state = nv_common_set_powergating_state,
1155 .get_clockgating_state = nv_common_get_clockgating_state,
1156};