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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2010 John Crispin <john@phrozen.org>
5 */
6
7#include <linux/export.h>
8#include <linux/clk.h>
9#include <linux/memblock.h>
10#include <linux/of_fdt.h>
11
12#include <asm/bootinfo.h>
13#include <asm/time.h>
14#include <asm/prom.h>
15
16#include <lantiq.h>
17
18#include "prom.h"
19#include "clk.h"
20
21/* access to the ebu needs to be locked between different drivers */
22DEFINE_SPINLOCK(ebu_lock);
23EXPORT_SYMBOL_GPL(ebu_lock);
24
25/*
26 * This is needed by the VPE loader code, just set it to 0 and assume
27 * that the firmware hardcodes this value to something useful.
28 */
29unsigned long physical_memsize = 0L;
30
31/*
32 * this struct is filled by the soc specific detection code and holds
33 * information about the specific soc type, revision and name
34 */
35static struct ltq_soc_info soc_info;
36
37const char *get_system_type(void)
38{
39 return soc_info.sys_type;
40}
41
42int ltq_soc_type(void)
43{
44 return soc_info.type;
45}
46
47static void __init prom_init_cmdline(void)
48{
49 int argc = fw_arg0;
50 char **argv = (char **) KSEG1ADDR(fw_arg1);
51 int i;
52
53 arcs_cmdline[0] = '\0';
54
55 for (i = 0; i < argc; i++) {
56 char *p = (char *) KSEG1ADDR(argv[i]);
57
58 if (CPHYSADDR(p) && *p) {
59 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
60 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
61 }
62 }
63}
64
65void __init plat_mem_setup(void)
66{
67 void *dtb;
68
69 ioport_resource.start = IOPORT_RESOURCE_START;
70 ioport_resource.end = IOPORT_RESOURCE_END;
71 iomem_resource.start = IOMEM_RESOURCE_START;
72 iomem_resource.end = IOMEM_RESOURCE_END;
73
74 set_io_port_base((unsigned long) KSEG1);
75
76 dtb = get_fdt();
77 if (dtb == NULL)
78 panic("no dtb found");
79
80 /*
81 * Load the devicetree. This causes the chosen node to be
82 * parsed resulting in our memory appearing
83 */
84 __dt_setup_arch(dtb);
85}
86
87void __init device_tree_init(void)
88{
89 unflatten_and_copy_device_tree();
90}
91
92void __init prom_init(void)
93{
94 /* call the soc specific detetcion code and get it to fill soc_info */
95 ltq_soc_detect(&soc_info);
96 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
97 soc_info.name, soc_info.rev_type);
98 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
99 pr_info("SoC: %s\n", soc_info.sys_type);
100 prom_init_cmdline();
101
102#if defined(CONFIG_MIPS_MT_SMP)
103 if (register_vsmp_smp_ops())
104 panic("failed to register_vsmp_smp_ops()");
105#endif
106}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2010 John Crispin <john@phrozen.org>
5 */
6
7#include <linux/export.h>
8#include <linux/clk.h>
9#include <linux/memblock.h>
10#include <linux/of_fdt.h>
11
12#include <asm/bootinfo.h>
13#include <asm/time.h>
14#include <asm/prom.h>
15
16#include <lantiq.h>
17
18#include "prom.h"
19#include "clk.h"
20
21/* access to the ebu needs to be locked between different drivers */
22DEFINE_SPINLOCK(ebu_lock);
23EXPORT_SYMBOL_GPL(ebu_lock);
24
25/*
26 * This is needed by the VPE loader code, just set it to 0 and assume
27 * that the firmware hardcodes this value to something useful.
28 */
29unsigned long physical_memsize = 0L;
30
31/*
32 * this struct is filled by the soc specific detection code and holds
33 * information about the specific soc type, revision and name
34 */
35static struct ltq_soc_info soc_info;
36
37/*
38 * These structs are used to override vsmp_init_secondary()
39 */
40#if defined(CONFIG_MIPS_MT_SMP)
41extern const struct plat_smp_ops vsmp_smp_ops;
42static struct plat_smp_ops lantiq_smp_ops;
43#endif
44
45const char *get_system_type(void)
46{
47 return soc_info.sys_type;
48}
49
50int ltq_soc_type(void)
51{
52 return soc_info.type;
53}
54
55static void __init prom_init_cmdline(void)
56{
57 int argc = fw_arg0;
58 char **argv = (char **) KSEG1ADDR(fw_arg1);
59 int i;
60
61 arcs_cmdline[0] = '\0';
62
63 for (i = 0; i < argc; i++) {
64 char *p = (char *) KSEG1ADDR(argv[i]);
65
66 if (CPHYSADDR(p) && *p) {
67 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
68 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
69 }
70 }
71}
72
73void __init plat_mem_setup(void)
74{
75 void *dtb;
76
77 ioport_resource.start = IOPORT_RESOURCE_START;
78 ioport_resource.end = IOPORT_RESOURCE_END;
79 iomem_resource.start = IOMEM_RESOURCE_START;
80 iomem_resource.end = IOMEM_RESOURCE_END;
81
82 set_io_port_base((unsigned long) KSEG1);
83
84 dtb = get_fdt();
85 if (dtb == NULL)
86 panic("no dtb found");
87
88 /*
89 * Load the devicetree. This causes the chosen node to be
90 * parsed resulting in our memory appearing
91 */
92 __dt_setup_arch(dtb);
93}
94
95#if defined(CONFIG_MIPS_MT_SMP)
96static void lantiq_init_secondary(void)
97{
98 /*
99 * MIPS CPU startup function vsmp_init_secondary() will only
100 * enable some of the interrupts for the second CPU/VPE.
101 */
102 set_c0_status(ST0_IM);
103}
104#endif
105
106void __init prom_init(void)
107{
108 /* call the soc specific detetcion code and get it to fill soc_info */
109 ltq_soc_detect(&soc_info);
110 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
111 soc_info.name, soc_info.rev_type);
112 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
113 pr_info("SoC: %s\n", soc_info.sys_type);
114 prom_init_cmdline();
115
116#if defined(CONFIG_MIPS_MT_SMP)
117 if (cpu_has_mipsmt) {
118 lantiq_smp_ops = vsmp_smp_ops;
119 lantiq_smp_ops.init_secondary = lantiq_init_secondary;
120 register_smp_ops(&lantiq_smp_ops);
121 }
122#endif
123}