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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <joerg.roedel@amd.com>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#ifndef _ASM_X86_AMD_IOMMU_H
9#define _ASM_X86_AMD_IOMMU_H
10
11#include <linux/types.h>
12
13struct amd_iommu;
14
15/*
16 * This is mainly used to communicate information back-and-forth
17 * between SVM and IOMMU for setting up and tearing down posted
18 * interrupt
19 */
20struct amd_iommu_pi_data {
21 u32 ga_tag;
22 u32 prev_ga_tag;
23 u64 base;
24 bool is_guest_mode;
25 struct vcpu_data *vcpu_data;
26 void *ir_data;
27};
28
29#ifdef CONFIG_AMD_IOMMU
30
31struct task_struct;
32struct pci_dev;
33
34extern int amd_iommu_detect(void);
35extern int amd_iommu_init_hardware(void);
36
37/**
38 * amd_iommu_init_device() - Init device for use with IOMMUv2 driver
39 * @pdev: The PCI device to initialize
40 * @pasids: Number of PASIDs to support for this device
41 *
42 * This function does all setup for the device pdev so that it can be
43 * used with IOMMUv2.
44 * Returns 0 on success or negative value on error.
45 */
46extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
47
48/**
49 * amd_iommu_free_device() - Free all IOMMUv2 related device resources
50 * and disable IOMMUv2 usage for this device
51 * @pdev: The PCI device to disable IOMMUv2 usage for'
52 */
53extern void amd_iommu_free_device(struct pci_dev *pdev);
54
55/**
56 * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
57 * @pdev: The PCI device to bind the task to
58 * @pasid: The PASID on the device the task should be bound to
59 * @task: the task to bind
60 *
61 * The function returns 0 on success or a negative value on error.
62 */
63extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
64 struct task_struct *task);
65
66/**
67 * amd_iommu_unbind_pasid() - Unbind a PASID from its task on
68 * a device
69 * @pdev: The device of the PASID
70 * @pasid: The PASID to unbind
71 *
72 * When this function returns the device is no longer using the PASID
73 * and the PASID is no longer bound to its task.
74 */
75extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);
76
77/**
78 * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
79 * PRI requests
80 * @pdev: The PCI device the call-back should be registered for
81 * @cb: The call-back function
82 *
83 * The IOMMUv2 driver invokes this call-back when it is unable to
84 * successfully handle a PRI request. The device driver can then decide
85 * which PRI response the device should see. Possible return values for
86 * the call-back are:
87 *
88 * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
89 * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
90 * - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
91 * the device is required to disable
92 * PRI when it receives this response
93 *
94 * The function returns 0 on success or negative value on error.
95 */
96#define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
97#define AMD_IOMMU_INV_PRI_RSP_INVALID 1
98#define AMD_IOMMU_INV_PRI_RSP_FAIL 2
99
100typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
101 u32 pasid,
102 unsigned long address,
103 u16);
104
105extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
106 amd_iommu_invalid_ppr_cb cb);
107
108#define PPR_FAULT_EXEC (1 << 1)
109#define PPR_FAULT_READ (1 << 2)
110#define PPR_FAULT_WRITE (1 << 5)
111#define PPR_FAULT_USER (1 << 6)
112#define PPR_FAULT_RSVD (1 << 7)
113#define PPR_FAULT_GN (1 << 8)
114
115/**
116 * amd_iommu_device_info() - Get information about IOMMUv2 support of a
117 * PCI device
118 * @pdev: PCI device to query information from
119 * @info: A pointer to an amd_iommu_device_info structure which will contain
120 * the information about the PCI device
121 *
122 * Returns 0 on success, negative value on error
123 */
124
125#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
126#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
127#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
128#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
129 on memory pages */
130#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
131 super-user privileges */
132
133struct amd_iommu_device_info {
134 int max_pasids;
135 u32 flags;
136};
137
138extern int amd_iommu_device_info(struct pci_dev *pdev,
139 struct amd_iommu_device_info *info);
140
141/**
142 * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
143 * a pasid context. This call-back is
144 * invoked when the IOMMUv2 driver needs to
145 * invalidate a PASID context, for example
146 * because the task that is bound to that
147 * context is about to exit.
148 *
149 * @pdev: The PCI device the call-back should be registered for
150 * @cb: The call-back function
151 */
152
153typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid);
154
155extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
156 amd_iommu_invalidate_ctx cb);
157#else /* CONFIG_AMD_IOMMU */
158
159static inline int amd_iommu_detect(void) { return -ENODEV; }
160
161#endif /* CONFIG_AMD_IOMMU */
162
163#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
164
165/* IOMMU AVIC Function */
166extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
167
168extern int
169amd_iommu_update_ga(int cpu, bool is_run, void *data);
170
171extern int amd_iommu_activate_guest_mode(void *data);
172extern int amd_iommu_deactivate_guest_mode(void *data);
173
174#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
175
176static inline int
177amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
178{
179 return 0;
180}
181
182static inline int
183amd_iommu_update_ga(int cpu, bool is_run, void *data)
184{
185 return 0;
186}
187
188static inline int amd_iommu_activate_guest_mode(void *data)
189{
190 return 0;
191}
192
193static inline int amd_iommu_deactivate_guest_mode(void *data)
194{
195 return 0;
196}
197#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
198
199int amd_iommu_get_num_iommus(void);
200bool amd_iommu_pc_supported(void);
201u8 amd_iommu_pc_get_max_banks(unsigned int idx);
202u8 amd_iommu_pc_get_max_counters(unsigned int idx);
203int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
204 u64 *value);
205int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
206 u64 *value);
207struct amd_iommu *get_amd_iommu(unsigned int idx);
208
209#endif /* _ASM_X86_AMD_IOMMU_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <joerg.roedel@amd.com>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#ifndef _ASM_X86_AMD_IOMMU_H
9#define _ASM_X86_AMD_IOMMU_H
10
11#include <linux/types.h>
12
13struct amd_iommu;
14
15/*
16 * This is mainly used to communicate information back-and-forth
17 * between SVM and IOMMU for setting up and tearing down posted
18 * interrupt
19 */
20struct amd_iommu_pi_data {
21 u32 ga_tag;
22 u32 prev_ga_tag;
23 u64 base;
24 bool is_guest_mode;
25 struct vcpu_data *vcpu_data;
26 void *ir_data;
27};
28
29#ifdef CONFIG_AMD_IOMMU
30
31struct task_struct;
32struct pci_dev;
33
34extern int amd_iommu_detect(void);
35
36#else /* CONFIG_AMD_IOMMU */
37
38static inline int amd_iommu_detect(void) { return -ENODEV; }
39
40#endif /* CONFIG_AMD_IOMMU */
41
42#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
43
44/* IOMMU AVIC Function */
45extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
46
47extern int
48amd_iommu_update_ga(int cpu, bool is_run, void *data);
49
50extern int amd_iommu_activate_guest_mode(void *data);
51extern int amd_iommu_deactivate_guest_mode(void *data);
52
53#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
54
55static inline int
56amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
57{
58 return 0;
59}
60
61static inline int
62amd_iommu_update_ga(int cpu, bool is_run, void *data)
63{
64 return 0;
65}
66
67static inline int amd_iommu_activate_guest_mode(void *data)
68{
69 return 0;
70}
71
72static inline int amd_iommu_deactivate_guest_mode(void *data)
73{
74 return 0;
75}
76#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
77
78int amd_iommu_get_num_iommus(void);
79bool amd_iommu_pc_supported(void);
80u8 amd_iommu_pc_get_max_banks(unsigned int idx);
81u8 amd_iommu_pc_get_max_counters(unsigned int idx);
82int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
83 u64 *value);
84int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
85 u64 *value);
86struct amd_iommu *get_amd_iommu(unsigned int idx);
87
88#ifdef CONFIG_KVM_AMD_SEV
89int amd_iommu_snp_disable(void);
90#else
91static inline int amd_iommu_snp_disable(void) { return 0; }
92#endif
93
94#endif /* _ASM_X86_AMD_IOMMU_H */