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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <linux/math.h>
7
8#include "i915_reg.h"
9#include "intel_ddi.h"
10#include "intel_ddi_buf_trans.h"
11#include "intel_de.h"
12#include "intel_display_types.h"
13#include "intel_snps_phy.h"
14#include "intel_snps_phy_regs.h"
15
16/**
17 * DOC: Synopsis PHY support
18 *
19 * Synopsis PHYs are primarily programmed by looking up magic register values
20 * in tables rather than calculating the necessary values at runtime.
21 *
22 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
23 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other
24 * platforms and must be programming directly during the modeset sequence
25 * since it is not handled by the shared DPLL framework as on other platforms.
26 */
27
28void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
29{
30 enum phy phy;
31
32 for_each_phy_masked(phy, ~0) {
33 if (!intel_phy_is_snps(i915, phy))
34 continue;
35
36 /*
37 * If calibration does not complete successfully, we'll remember
38 * which phy was affected and skip setup of the corresponding
39 * output later.
40 */
41 if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
42 DG2_PHY_DP_TX_ACK_MASK, 25))
43 i915->display.snps.phy_failed_calibration |= BIT(phy);
44 }
45}
46
47void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
48 bool enable)
49{
50 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
51 enum phy phy = intel_encoder_to_phy(encoder);
52 u32 val;
53
54 if (!intel_encoder_is_snps(encoder))
55 return;
56
57 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
58 enable ? 2 : 3);
59 intel_de_rmw(i915, SNPS_PHY_TX_REQ(phy),
60 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
61}
62
63void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
64 const struct intel_crtc_state *crtc_state)
65{
66 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
67 const struct intel_ddi_buf_trans *trans;
68 enum phy phy = intel_encoder_to_phy(encoder);
69 int n_entries, ln;
70
71 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
72 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
73 return;
74
75 for (ln = 0; ln < 4; ln++) {
76 int level = intel_ddi_level(encoder, crtc_state, ln);
77 u32 val = 0;
78
79 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
80 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
81 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
82
83 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
84 }
85}
86
87/*
88 * Basic DP link rates with 100 MHz reference clock.
89 */
90
91static const struct intel_mpllb_state dg2_dp_rbr_100 = {
92 .clock = 162000,
93 .ref_control =
94 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
95 .mpllb_cp =
96 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
97 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
98 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
99 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
100 .mpllb_div =
101 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
102 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
103 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
104 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
105 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
106 .mpllb_div2 =
107 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
108 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
109 .mpllb_fracn1 =
110 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
111 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
112 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
113 .mpllb_fracn2 =
114 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
115 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
116};
117
118static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
119 .clock = 270000,
120 .ref_control =
121 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
122 .mpllb_cp =
123 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
124 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
125 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
126 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
127 .mpllb_div =
128 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
129 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
130 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
131 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
132 .mpllb_div2 =
133 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
134 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
135 .mpllb_fracn1 =
136 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
137 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
138};
139
140static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
141 .clock = 540000,
142 .ref_control =
143 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
144 .mpllb_cp =
145 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
146 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
147 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
148 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
149 .mpllb_div =
150 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
151 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
152 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
153 .mpllb_div2 =
154 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
155 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
156 .mpllb_fracn1 =
157 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
158 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
159};
160
161static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
162 .clock = 810000,
163 .ref_control =
164 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
165 .mpllb_cp =
166 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
167 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
168 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
169 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
170 .mpllb_div =
171 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
172 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
173 .mpllb_div2 =
174 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
175 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
176 .mpllb_fracn1 =
177 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
178 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
179};
180
181static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
182 .clock = 1000000,
183 .ref_control =
184 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
185 .mpllb_cp =
186 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
187 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |
188 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
189 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
190 .mpllb_div =
191 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
192 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
193 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
194 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
195 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
196 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
197 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
198 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
199 .mpllb_div2 =
200 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
201 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),
202 .mpllb_fracn1 =
203 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
204 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
205
206 /*
207 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
208 */
209 .mpllb_sscen =
210 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
211 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),
212 .mpllb_sscstep =
213 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
214};
215
216static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
217 .clock = 1350000,
218 .ref_control =
219 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
220 .mpllb_cp =
221 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
222 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
223 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
224 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
225 .mpllb_div =
226 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
227 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
228 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
229 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
230 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
231 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
232 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
233 .mpllb_div2 =
234 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
235 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
236 .mpllb_fracn1 =
237 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
238 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
239
240 /*
241 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
242 */
243 .mpllb_sscen =
244 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
245 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
246 .mpllb_sscstep =
247 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
248};
249
250static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
251 &dg2_dp_rbr_100,
252 &dg2_dp_hbr1_100,
253 &dg2_dp_hbr2_100,
254 &dg2_dp_hbr3_100,
255 &dg2_dp_uhbr10_100,
256 &dg2_dp_uhbr13_100,
257 NULL,
258};
259
260/*
261 * eDP link rates with 100 MHz reference clock.
262 */
263
264static const struct intel_mpllb_state dg2_edp_r216 = {
265 .clock = 216000,
266 .ref_control =
267 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
268 .mpllb_cp =
269 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
270 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
271 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
272 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
273 .mpllb_div =
274 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
275 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
276 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
277 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
278 .mpllb_div2 =
279 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
280 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
281 .mpllb_fracn1 =
282 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
283 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
284 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
285 .mpllb_fracn2 =
286 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
287 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
288 .mpllb_sscen =
289 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
290 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
291 .mpllb_sscstep =
292 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
293};
294
295static const struct intel_mpllb_state dg2_edp_r243 = {
296 .clock = 243000,
297 .ref_control =
298 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
299 .mpllb_cp =
300 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
301 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
302 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
303 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
304 .mpllb_div =
305 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
306 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
307 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
308 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
309 .mpllb_div2 =
310 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
311 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
312 .mpllb_fracn1 =
313 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
314 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
315 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
316 .mpllb_fracn2 =
317 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
318 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
319 .mpllb_sscen =
320 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
321 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
322 .mpllb_sscstep =
323 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
324};
325
326static const struct intel_mpllb_state dg2_edp_r324 = {
327 .clock = 324000,
328 .ref_control =
329 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
330 .mpllb_cp =
331 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
332 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
333 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
334 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
335 .mpllb_div =
336 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
337 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
338 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
339 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
340 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
341 .mpllb_div2 =
342 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
343 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
344 .mpllb_fracn1 =
345 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
346 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
347 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
348 .mpllb_fracn2 =
349 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
350 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
351 .mpllb_sscen =
352 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
353 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
354 .mpllb_sscstep =
355 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
356};
357
358static const struct intel_mpllb_state dg2_edp_r432 = {
359 .clock = 432000,
360 .ref_control =
361 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
362 .mpllb_cp =
363 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
364 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
365 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
366 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
367 .mpllb_div =
368 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
369 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
370 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
371 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
372 .mpllb_div2 =
373 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
374 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
375 .mpllb_fracn1 =
376 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
377 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
378 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
379 .mpllb_fracn2 =
380 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
381 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
382 .mpllb_sscen =
383 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
384 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
385 .mpllb_sscstep =
386 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
387};
388
389static const struct intel_mpllb_state * const dg2_edp_tables[] = {
390 &dg2_dp_rbr_100,
391 &dg2_edp_r216,
392 &dg2_edp_r243,
393 &dg2_dp_hbr1_100,
394 &dg2_edp_r324,
395 &dg2_edp_r432,
396 &dg2_dp_hbr2_100,
397 &dg2_dp_hbr3_100,
398 NULL,
399};
400
401/*
402 * HDMI link rates with 100 MHz reference clock.
403 */
404
405static const struct intel_mpllb_state dg2_hdmi_25_175 = {
406 .clock = 25175,
407 .ref_control =
408 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
409 .mpllb_cp =
410 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
411 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
412 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
413 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
414 .mpllb_div =
415 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
416 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
417 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
418 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
419 .mpllb_div2 =
420 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
421 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
422 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
423 .mpllb_fracn1 =
424 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
425 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
426 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
427 .mpllb_fracn2 =
428 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
429 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
430 .mpllb_sscen =
431 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
432};
433
434static const struct intel_mpllb_state dg2_hdmi_27_0 = {
435 .clock = 27000,
436 .ref_control =
437 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
438 .mpllb_cp =
439 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
440 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
441 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
442 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
443 .mpllb_div =
444 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
445 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
446 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
447 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
448 .mpllb_div2 =
449 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
450 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
451 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
452 .mpllb_fracn1 =
453 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
454 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
455 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
456 .mpllb_fracn2 =
457 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
458 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
459 .mpllb_sscen =
460 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
461};
462
463static const struct intel_mpllb_state dg2_hdmi_74_25 = {
464 .clock = 74250,
465 .ref_control =
466 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
467 .mpllb_cp =
468 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
469 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
470 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
471 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
472 .mpllb_div =
473 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
474 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
475 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
476 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
477 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
478 .mpllb_div2 =
479 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
480 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
481 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
482 .mpllb_fracn1 =
483 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
484 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
485 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
486 .mpllb_fracn2 =
487 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
488 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
489 .mpllb_sscen =
490 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
491};
492
493static const struct intel_mpllb_state dg2_hdmi_148_5 = {
494 .clock = 148500,
495 .ref_control =
496 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
497 .mpllb_cp =
498 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
499 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
500 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
501 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
502 .mpllb_div =
503 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
504 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
505 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
506 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
507 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
508 .mpllb_div2 =
509 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
510 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
511 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
512 .mpllb_fracn1 =
513 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
514 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
515 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
516 .mpllb_fracn2 =
517 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
518 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
519 .mpllb_sscen =
520 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
521};
522
523/* values in the below table are calculted using the algo */
524static const struct intel_mpllb_state dg2_hdmi_25200 = {
525 .clock = 25200,
526 .ref_control =
527 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
528 .mpllb_cp =
529 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
530 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
531 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
532 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
533 .mpllb_div =
534 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
535 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
536 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
537 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
538 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
539 .mpllb_div2 =
540 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
541 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
542 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
543 .mpllb_fracn1 =
544 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
545 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
546 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
547 .mpllb_fracn2 =
548 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |
549 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),
550 .mpllb_sscen =
551 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
552};
553
554static const struct intel_mpllb_state dg2_hdmi_27027 = {
555 .clock = 27027,
556 .ref_control =
557 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
558 .mpllb_cp =
559 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
560 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
561 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
562 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
563 .mpllb_div =
564 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
565 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
566 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
567 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
568 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
569 .mpllb_div2 =
570 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
571 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
572 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
573 .mpllb_fracn1 =
574 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
575 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
576 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
577 .mpllb_fracn2 =
578 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |
579 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),
580 .mpllb_sscen =
581 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
582};
583
584static const struct intel_mpllb_state dg2_hdmi_28320 = {
585 .clock = 28320,
586 .ref_control =
587 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
588 .mpllb_cp =
589 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
590 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
591 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
592 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
593 .mpllb_div =
594 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
595 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
596 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
597 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
598 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
599 .mpllb_div2 =
600 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
601 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |
602 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
603 .mpllb_fracn1 =
604 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
605 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
606 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
607 .mpllb_fracn2 =
608 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) |
609 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408),
610 .mpllb_sscen =
611 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
612};
613
614static const struct intel_mpllb_state dg2_hdmi_30240 = {
615 .clock = 30240,
616 .ref_control =
617 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
618 .mpllb_cp =
619 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
620 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
621 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
622 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
623 .mpllb_div =
624 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
625 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
626 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
627 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
628 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
629 .mpllb_div2 =
630 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
631 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
632 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
633 .mpllb_fracn1 =
634 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
635 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
636 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
637 .mpllb_fracn2 =
638 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) |
639 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466),
640 .mpllb_sscen =
641 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
642};
643
644static const struct intel_mpllb_state dg2_hdmi_31500 = {
645 .clock = 31500,
646 .ref_control =
647 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
648 .mpllb_cp =
649 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
650 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
651 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
652 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
653 .mpllb_div =
654 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
655 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
656 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
657 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
658 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
659 .mpllb_div2 =
660 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
661 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) |
662 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
663 .mpllb_fracn1 =
664 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
665 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
666 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
667 .mpllb_fracn2 =
668 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
669 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
670 .mpllb_sscen =
671 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
672};
673
674static const struct intel_mpllb_state dg2_hdmi_36000 = {
675 .clock = 36000,
676 .ref_control =
677 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
678 .mpllb_cp =
679 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
680 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
681 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
682 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
683 .mpllb_div =
684 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
685 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
686 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
687 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
688 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
689 .mpllb_div2 =
690 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
691 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) |
692 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
693 .mpllb_fracn1 =
694 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
695 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
696 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
697 .mpllb_fracn2 =
698 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
699 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
700 .mpllb_sscen =
701 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
702};
703
704static const struct intel_mpllb_state dg2_hdmi_40000 = {
705 .clock = 40000,
706 .ref_control =
707 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
708 .mpllb_cp =
709 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
710 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
711 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
712 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
713 .mpllb_div =
714 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
715 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
716 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
717 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
718 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
719 .mpllb_div2 =
720 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
721 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
722 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
723 .mpllb_fracn1 =
724 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
725 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
726 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
727 .mpllb_fracn2 =
728 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
729 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
730 .mpllb_sscen =
731 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
732};
733
734static const struct intel_mpllb_state dg2_hdmi_49500 = {
735 .clock = 49500,
736 .ref_control =
737 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
738 .mpllb_cp =
739 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
740 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
741 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
742 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
743 .mpllb_div =
744 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
745 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
746 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
747 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
748 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
749 .mpllb_div2 =
750 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
751 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) |
752 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
753 .mpllb_fracn1 =
754 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
755 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
756 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
757 .mpllb_fracn2 =
758 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
759 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
760 .mpllb_sscen =
761 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
762};
763
764static const struct intel_mpllb_state dg2_hdmi_50000 = {
765 .clock = 50000,
766 .ref_control =
767 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
768 .mpllb_cp =
769 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
770 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
771 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
772 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
773 .mpllb_div =
774 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
775 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
776 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
777 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
778 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
779 .mpllb_div2 =
780 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
781 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
782 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
783 .mpllb_fracn1 =
784 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
785 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
786 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
787 .mpllb_fracn2 =
788 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
789 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
790 .mpllb_sscen =
791 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
792};
793
794static const struct intel_mpllb_state dg2_hdmi_57284 = {
795 .clock = 57284,
796 .ref_control =
797 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
798 .mpllb_cp =
799 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
800 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
801 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
802 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
803 .mpllb_div =
804 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
805 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
806 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
807 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
808 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
809 .mpllb_div2 =
810 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
811 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) |
812 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
813 .mpllb_fracn1 =
814 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
815 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
816 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
817 .mpllb_fracn2 =
818 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) |
819 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701),
820 .mpllb_sscen =
821 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
822};
823
824static const struct intel_mpllb_state dg2_hdmi_58000 = {
825 .clock = 58000,
826 .ref_control =
827 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
828 .mpllb_cp =
829 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
830 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
831 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
832 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
833 .mpllb_div =
834 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
835 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
836 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
837 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
838 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
839 .mpllb_div2 =
840 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
841 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
842 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
843 .mpllb_fracn1 =
844 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
845 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
846 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
847 .mpllb_fracn2 =
848 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
849 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
850 .mpllb_sscen =
851 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
852};
853
854static const struct intel_mpllb_state dg2_hdmi_65000 = {
855 .clock = 65000,
856 .ref_control =
857 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
858 .mpllb_cp =
859 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
860 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
861 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
862 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
863 .mpllb_div =
864 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
865 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
866 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
867 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
868 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
869 .mpllb_div2 =
870 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
871 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
872 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
873 .mpllb_fracn1 =
874 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
875 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
876 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
877 .mpllb_fracn2 =
878 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
879 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
880 .mpllb_sscen =
881 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
882};
883
884static const struct intel_mpllb_state dg2_hdmi_71000 = {
885 .clock = 71000,
886 .ref_control =
887 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
888 .mpllb_cp =
889 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
890 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
891 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
892 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
893 .mpllb_div =
894 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
895 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
896 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
897 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
898 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
899 .mpllb_div2 =
900 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
901 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) |
902 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
903 .mpllb_fracn1 =
904 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
905 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
906 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
907 .mpllb_fracn2 =
908 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
909 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
910 .mpllb_sscen =
911 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
912};
913
914static const struct intel_mpllb_state dg2_hdmi_74176 = {
915 .clock = 74176,
916 .ref_control =
917 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
918 .mpllb_cp =
919 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
920 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
921 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
922 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
923 .mpllb_div =
924 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
925 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
926 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
927 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
928 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
929 .mpllb_div2 =
930 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
931 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
932 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
933 .mpllb_fracn1 =
934 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
935 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
936 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
937 .mpllb_fracn2 =
938 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
939 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
940 .mpllb_sscen =
941 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
942};
943
944static const struct intel_mpllb_state dg2_hdmi_75000 = {
945 .clock = 75000,
946 .ref_control =
947 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
948 .mpllb_cp =
949 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
950 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
951 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
952 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
953 .mpllb_div =
954 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
955 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
956 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
957 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
958 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
959 .mpllb_div2 =
960 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
961 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) |
962 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
963 .mpllb_fracn1 =
964 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
965 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
966 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
967 .mpllb_fracn2 =
968 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
969 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
970 .mpllb_sscen =
971 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
972};
973
974static const struct intel_mpllb_state dg2_hdmi_78750 = {
975 .clock = 78750,
976 .ref_control =
977 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
978 .mpllb_cp =
979 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
980 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
981 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
982 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
983 .mpllb_div =
984 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
985 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
986 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
987 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
988 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
989 .mpllb_div2 =
990 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
991 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
992 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
993 .mpllb_fracn1 =
994 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
995 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
996 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
997 .mpllb_fracn2 =
998 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
999 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1000 .mpllb_sscen =
1001 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1002};
1003
1004static const struct intel_mpllb_state dg2_hdmi_85500 = {
1005 .clock = 85500,
1006 .ref_control =
1007 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1008 .mpllb_cp =
1009 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1010 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1011 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1012 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1013 .mpllb_div =
1014 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1015 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1016 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1017 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1018 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1019 .mpllb_div2 =
1020 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1021 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) |
1022 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1023 .mpllb_fracn1 =
1024 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1025 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1026 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1027 .mpllb_fracn2 =
1028 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1029 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1030 .mpllb_sscen =
1031 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1032};
1033
1034static const struct intel_mpllb_state dg2_hdmi_88750 = {
1035 .clock = 88750,
1036 .ref_control =
1037 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1038 .mpllb_cp =
1039 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1040 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1041 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1042 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1043 .mpllb_div =
1044 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1045 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1046 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
1047 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1048 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
1049 .mpllb_div2 =
1050 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1051 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) |
1052 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1053 .mpllb_fracn1 =
1054 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1055 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1056 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1057 .mpllb_fracn2 =
1058 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1059 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1060 .mpllb_sscen =
1061 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1062};
1063
1064static const struct intel_mpllb_state dg2_hdmi_106500 = {
1065 .clock = 106500,
1066 .ref_control =
1067 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1068 .mpllb_cp =
1069 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1070 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1071 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1072 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1073 .mpllb_div =
1074 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1075 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1076 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1077 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1078 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1079 .mpllb_div2 =
1080 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1081 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) |
1082 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1083 .mpllb_fracn1 =
1084 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1085 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1086 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1087 .mpllb_fracn2 =
1088 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1089 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1090 .mpllb_sscen =
1091 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1092};
1093
1094static const struct intel_mpllb_state dg2_hdmi_108000 = {
1095 .clock = 108000,
1096 .ref_control =
1097 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1098 .mpllb_cp =
1099 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1100 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1101 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1102 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1103 .mpllb_div =
1104 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1105 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1106 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1107 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1108 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1109 .mpllb_div2 =
1110 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1111 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
1112 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1113 .mpllb_fracn1 =
1114 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1115 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1116 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1117 .mpllb_fracn2 =
1118 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1119 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1120 .mpllb_sscen =
1121 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1122};
1123
1124static const struct intel_mpllb_state dg2_hdmi_115500 = {
1125 .clock = 115500,
1126 .ref_control =
1127 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1128 .mpllb_cp =
1129 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1130 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1131 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1132 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1133 .mpllb_div =
1134 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1135 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1136 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1137 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1138 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1139 .mpllb_div2 =
1140 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1141 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
1142 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1143 .mpllb_fracn1 =
1144 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1145 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1146 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1147 .mpllb_fracn2 =
1148 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1149 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1150 .mpllb_sscen =
1151 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1152};
1153
1154static const struct intel_mpllb_state dg2_hdmi_119000 = {
1155 .clock = 119000,
1156 .ref_control =
1157 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1158 .mpllb_cp =
1159 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1160 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1162 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1163 .mpllb_div =
1164 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1165 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1166 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1167 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1168 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1169 .mpllb_div2 =
1170 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1171 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) |
1172 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1173 .mpllb_fracn1 =
1174 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1175 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1176 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1177 .mpllb_fracn2 =
1178 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1179 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1180 .mpllb_sscen =
1181 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1182};
1183
1184static const struct intel_mpllb_state dg2_hdmi_135000 = {
1185 .clock = 135000,
1186 .ref_control =
1187 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1188 .mpllb_cp =
1189 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1190 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1191 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1192 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1193 .mpllb_div =
1194 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1195 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1196 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
1197 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1198 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1199 .mpllb_div2 =
1200 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1201 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) |
1202 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1203 .mpllb_fracn1 =
1204 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1205 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1206 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1207 .mpllb_fracn2 =
1208 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1209 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1210 .mpllb_sscen =
1211 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1212};
1213
1214static const struct intel_mpllb_state dg2_hdmi_138500 = {
1215 .clock = 138500,
1216 .ref_control =
1217 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1218 .mpllb_cp =
1219 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1220 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1221 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1222 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1223 .mpllb_div =
1224 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1225 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1226 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1227 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1228 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1229 .mpllb_div2 =
1230 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1231 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) |
1232 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1233 .mpllb_fracn1 =
1234 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1235 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1236 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1237 .mpllb_fracn2 =
1238 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1239 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1240 .mpllb_sscen =
1241 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1242};
1243
1244static const struct intel_mpllb_state dg2_hdmi_147160 = {
1245 .clock = 147160,
1246 .ref_control =
1247 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1248 .mpllb_cp =
1249 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1250 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1251 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1252 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1253 .mpllb_div =
1254 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1255 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1256 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1257 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1258 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1259 .mpllb_div2 =
1260 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1261 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) |
1262 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1263 .mpllb_fracn1 =
1264 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1265 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1266 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1267 .mpllb_fracn2 =
1268 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) |
1269 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815),
1270 .mpllb_sscen =
1271 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1272};
1273
1274static const struct intel_mpllb_state dg2_hdmi_148352 = {
1275 .clock = 148352,
1276 .ref_control =
1277 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1278 .mpllb_cp =
1279 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1280 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1281 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1282 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1283 .mpllb_div =
1284 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1285 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1286 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1287 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1288 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1289 .mpllb_div2 =
1290 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1291 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1292 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1293 .mpllb_fracn1 =
1294 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1295 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1296 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1297 .mpllb_fracn2 =
1298 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
1299 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
1300 .mpllb_sscen =
1301 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1302};
1303
1304static const struct intel_mpllb_state dg2_hdmi_154000 = {
1305 .clock = 154000,
1306 .ref_control =
1307 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1308 .mpllb_cp =
1309 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1310 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) |
1311 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1312 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1313 .mpllb_div =
1314 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1315 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1316 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1317 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1318 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1319 .mpllb_div2 =
1320 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1321 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) |
1322 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1323 .mpllb_fracn1 =
1324 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1325 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1326 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1327 .mpllb_fracn2 =
1328 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
1329 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
1330 .mpllb_sscen =
1331 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1332};
1333
1334static const struct intel_mpllb_state dg2_hdmi_162000 = {
1335 .clock = 162000,
1336 .ref_control =
1337 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1338 .mpllb_cp =
1339 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1340 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1341 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1342 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1343 .mpllb_div =
1344 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1345 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1346 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1347 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1348 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1349 .mpllb_div2 =
1350 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1351 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
1352 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1353 .mpllb_fracn1 =
1354 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1355 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1356 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1357 .mpllb_fracn2 =
1358 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
1359 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1360 .mpllb_sscen =
1361 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1362};
1363
1364static const struct intel_mpllb_state dg2_hdmi_209800 = {
1365 .clock = 209800,
1366 .ref_control =
1367 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1368 .mpllb_cp =
1369 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1370 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1371 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1372 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1373 .mpllb_div =
1374 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1375 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1376 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1377 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1378 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1379 .mpllb_div2 =
1380 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1381 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) |
1382 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1383 .mpllb_fracn1 =
1384 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1385 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1386 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1387 .mpllb_fracn2 =
1388 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) |
1389 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864),
1390 .mpllb_sscen =
1391 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1392};
1393
1394static const struct intel_mpllb_state dg2_hdmi_262750 = {
1395 .clock = 262750,
1396 .ref_control =
1397 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1398 .mpllb_cp =
1399 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1400 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1401 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1402 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1403 .mpllb_div =
1404 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1405 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1406 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1407 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1408 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1409 .mpllb_div2 =
1410 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1411 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
1412 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1413 .mpllb_fracn1 =
1414 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1415 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1416 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1417 .mpllb_fracn2 =
1418 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
1419 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1420 .mpllb_sscen =
1421 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1422};
1423
1424static const struct intel_mpllb_state dg2_hdmi_267300 = {
1425 .clock = 267300,
1426 .ref_control =
1427 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1428 .mpllb_cp =
1429 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1430 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1431 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1432 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1433 .mpllb_div =
1434 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1435 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1436 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1437 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1438 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1439 .mpllb_div2 =
1440 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1441 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
1442 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1443 .mpllb_fracn1 =
1444 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1445 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1446 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1447 .mpllb_fracn2 =
1448 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) |
1449 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699),
1450 .mpllb_sscen =
1451 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1452};
1453
1454static const struct intel_mpllb_state dg2_hdmi_268500 = {
1455 .clock = 268500,
1456 .ref_control =
1457 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1458 .mpllb_cp =
1459 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1460 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1461 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1462 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1463 .mpllb_div =
1464 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1465 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1466 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1467 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1468 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1469 .mpllb_div2 =
1470 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1471 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
1472 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1473 .mpllb_fracn1 =
1474 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1475 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1476 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1477 .mpllb_fracn2 =
1478 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) |
1479 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1480 .mpllb_sscen =
1481 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1482};
1483
1484static const struct intel_mpllb_state dg2_hdmi_296703 = {
1485 .clock = 296703,
1486 .ref_control =
1487 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1488 .mpllb_cp =
1489 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1490 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1491 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1492 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1493 .mpllb_div =
1494 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1495 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1496 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1497 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1498 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1499 .mpllb_div2 =
1500 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1501 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1502 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1503 .mpllb_fracn1 =
1504 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1505 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1506 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1507 .mpllb_fracn2 =
1508 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) |
1509 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804),
1510 .mpllb_sscen =
1511 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1512};
1513
1514static const struct intel_mpllb_state dg2_hdmi_241500 = {
1515 .clock = 241500,
1516 .ref_control =
1517 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1518 .mpllb_cp =
1519 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1520 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1521 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1522 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1523 .mpllb_div =
1524 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1525 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1526 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1527 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1528 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1529 .mpllb_div2 =
1530 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1531 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
1532 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1533 .mpllb_fracn1 =
1534 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1535 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1536 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1537 .mpllb_fracn2 =
1538 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
1539 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
1540 .mpllb_sscen =
1541 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1542};
1543
1544static const struct intel_mpllb_state dg2_hdmi_319890 = {
1545 .clock = 319890,
1546 .ref_control =
1547 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1548 .mpllb_cp =
1549 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1550 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1551 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1552 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1553 .mpllb_div =
1554 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1555 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1556 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1557 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1558 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1559 .mpllb_div2 =
1560 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1561 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
1562 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1563 .mpllb_fracn1 =
1564 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1565 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1566 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1567 .mpllb_fracn2 =
1568 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) |
1569 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631),
1570 .mpllb_sscen =
1571 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1572};
1573
1574static const struct intel_mpllb_state dg2_hdmi_497750 = {
1575 .clock = 497750,
1576 .ref_control =
1577 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1578 .mpllb_cp =
1579 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1580 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1581 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1582 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1583 .mpllb_div =
1584 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1585 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1586 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1587 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1588 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1589 .mpllb_div2 =
1590 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1591 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) |
1592 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1593 .mpllb_fracn1 =
1594 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1595 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1596 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1597 .mpllb_fracn2 =
1598 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
1599 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1600 .mpllb_sscen =
1601 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1602};
1603
1604static const struct intel_mpllb_state dg2_hdmi_592000 = {
1605 .clock = 592000,
1606 .ref_control =
1607 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1608 .mpllb_cp =
1609 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1610 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1611 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1612 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1613 .mpllb_div =
1614 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1615 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
1616 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1617 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1618 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1619 .mpllb_div2 =
1620 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1621 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1622 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1623 .mpllb_fracn1 =
1624 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1625 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1626 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1627 .mpllb_fracn2 =
1628 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1629 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1630 .mpllb_sscen =
1631 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1632};
1633
1634static const struct intel_mpllb_state dg2_hdmi_593407 = {
1635 .clock = 593407,
1636 .ref_control =
1637 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1638 .mpllb_cp =
1639 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1640 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1641 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1642 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1643 .mpllb_div =
1644 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1645 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
1646 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1647 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1648 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1649 .mpllb_div2 =
1650 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1651 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1652 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1653 .mpllb_fracn1 =
1654 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1655 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1656 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1657 .mpllb_fracn2 =
1658 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) |
1659 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549),
1660 .mpllb_sscen =
1661 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1662};
1663
1664static const struct intel_mpllb_state dg2_hdmi_297 = {
1665 .clock = 297000,
1666 .ref_control =
1667 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1668 .mpllb_cp =
1669 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1670 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1671 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1672 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1673 .mpllb_div =
1674 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1675 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1676 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1677 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1678 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1679 .mpllb_div2 =
1680 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1681 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1682 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1683 .mpllb_fracn1 =
1684 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1685 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1686 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1687 .mpllb_fracn2 =
1688 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1689 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1690 .mpllb_sscen =
1691 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1692};
1693
1694static const struct intel_mpllb_state dg2_hdmi_594 = {
1695 .clock = 594000,
1696 .ref_control =
1697 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1698 .mpllb_cp =
1699 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
1700 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1701 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1702 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1703 .mpllb_div =
1704 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1705 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1706 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1707 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1708 .mpllb_div2 =
1709 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1710 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1711 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1712 .mpllb_fracn1 =
1713 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1714 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1715 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
1716 .mpllb_fracn2 =
1717 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1718 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
1719 .mpllb_sscen =
1720 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1721};
1722
1723static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
1724 &dg2_hdmi_25_175,
1725 &dg2_hdmi_27_0,
1726 &dg2_hdmi_74_25,
1727 &dg2_hdmi_148_5,
1728 &dg2_hdmi_297,
1729 &dg2_hdmi_594,
1730 &dg2_hdmi_25200,
1731 &dg2_hdmi_27027,
1732 &dg2_hdmi_28320,
1733 &dg2_hdmi_30240,
1734 &dg2_hdmi_31500,
1735 &dg2_hdmi_36000,
1736 &dg2_hdmi_40000,
1737 &dg2_hdmi_49500,
1738 &dg2_hdmi_50000,
1739 &dg2_hdmi_57284,
1740 &dg2_hdmi_58000,
1741 &dg2_hdmi_65000,
1742 &dg2_hdmi_71000,
1743 &dg2_hdmi_74176,
1744 &dg2_hdmi_75000,
1745 &dg2_hdmi_78750,
1746 &dg2_hdmi_85500,
1747 &dg2_hdmi_88750,
1748 &dg2_hdmi_106500,
1749 &dg2_hdmi_108000,
1750 &dg2_hdmi_115500,
1751 &dg2_hdmi_119000,
1752 &dg2_hdmi_135000,
1753 &dg2_hdmi_138500,
1754 &dg2_hdmi_147160,
1755 &dg2_hdmi_148352,
1756 &dg2_hdmi_154000,
1757 &dg2_hdmi_162000,
1758 &dg2_hdmi_209800,
1759 &dg2_hdmi_241500,
1760 &dg2_hdmi_262750,
1761 &dg2_hdmi_267300,
1762 &dg2_hdmi_268500,
1763 &dg2_hdmi_296703,
1764 &dg2_hdmi_319890,
1765 &dg2_hdmi_497750,
1766 &dg2_hdmi_592000,
1767 &dg2_hdmi_593407,
1768 NULL,
1769};
1770
1771static const struct intel_mpllb_state * const *
1772intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
1773 struct intel_encoder *encoder)
1774{
1775 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1776 return dg2_edp_tables;
1777 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1778 return dg2_dp_100_tables;
1779 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1780 return dg2_hdmi_tables;
1781 }
1782
1783 MISSING_CASE(encoder->type);
1784 return NULL;
1785}
1786
1787int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
1788 struct intel_encoder *encoder)
1789{
1790 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1791 const struct intel_mpllb_state * const *tables;
1792 int i;
1793
1794 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1795 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
1796 != MODE_OK) {
1797 /*
1798 * FIXME: Can only support fixed HDMI frequencies
1799 * until we have a proper algorithm under a valid
1800 * license.
1801 */
1802 drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
1803 crtc_state->port_clock);
1804 return -EINVAL;
1805 }
1806 }
1807
1808 tables = intel_mpllb_tables_get(crtc_state, encoder);
1809 if (!tables)
1810 return -EINVAL;
1811
1812 for (i = 0; tables[i]; i++) {
1813 if (crtc_state->port_clock == tables[i]->clock) {
1814 crtc_state->dpll_hw_state.mpllb = *tables[i];
1815 return 0;
1816 }
1817 }
1818
1819 return -EINVAL;
1820}
1821
1822void intel_mpllb_enable(struct intel_encoder *encoder,
1823 const struct intel_crtc_state *crtc_state)
1824{
1825 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1826 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
1827 enum phy phy = intel_encoder_to_phy(encoder);
1828 i915_reg_t enable_reg = (phy <= PHY_D ?
1829 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
1830
1831 /*
1832 * 3. Software programs the following PLL registers for the desired
1833 * frequency.
1834 */
1835 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
1836 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
1837 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
1838 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
1839 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
1840 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
1841 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
1842
1843 /*
1844 * 4. If the frequency will result in a change to the voltage
1845 * requirement, follow the Display Voltage Frequency Switching -
1846 * Sequence Before Frequency Change.
1847 *
1848 * We handle this step in bxt_set_cdclk().
1849 */
1850
1851 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
1852 intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE);
1853
1854 /*
1855 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
1856 * will keep the PLL running during the DDI lane programming and any
1857 * typeC DP cable disconnect. Do not set the force before enabling the
1858 * PLL because that will start the PLL before it has sampled the
1859 * divider values.
1860 */
1861 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
1862 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
1863
1864 /*
1865 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
1866 * is locked at new settings. This register bit is sampling PHY
1867 * dp_mpllb_state interface signal.
1868 */
1869 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
1870 drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
1871
1872 /*
1873 * 11. If the frequency will result in a change to the voltage
1874 * requirement, follow the Display Voltage Frequency Switching -
1875 * Sequence After Frequency Change.
1876 *
1877 * We handle this step in bxt_set_cdclk().
1878 */
1879}
1880
1881void intel_mpllb_disable(struct intel_encoder *encoder)
1882{
1883 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1884 enum phy phy = intel_encoder_to_phy(encoder);
1885 i915_reg_t enable_reg = (phy <= PHY_D ?
1886 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
1887
1888 /*
1889 * 1. If the frequency will result in a change to the voltage
1890 * requirement, follow the Display Voltage Frequency Switching -
1891 * Sequence Before Frequency Change.
1892 *
1893 * We handle this step in bxt_set_cdclk().
1894 */
1895
1896 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
1897 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
1898
1899 /*
1900 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
1901 * This will allow the PLL to stop running.
1902 */
1903 intel_de_rmw(i915, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);
1904
1905 /*
1906 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
1907 * (dp_txX_ack) that the new transmitter setting request is completed.
1908 */
1909 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
1910 drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
1911
1912 /*
1913 * 6. If the frequency will result in a change to the voltage
1914 * requirement, follow the Display Voltage Frequency Switching -
1915 * Sequence After Frequency Change.
1916 *
1917 * We handle this step in bxt_set_cdclk().
1918 */
1919}
1920
1921int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
1922 const struct intel_mpllb_state *pll_state)
1923{
1924 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
1925 unsigned int multiplier, tx_clk_div, refclk;
1926 bool frac_en;
1927
1928 if (0)
1929 refclk = 38400;
1930 else
1931 refclk = 100000;
1932
1933 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
1934
1935 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
1936
1937 if (frac_en) {
1938 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
1939 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
1940 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
1941 }
1942
1943 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
1944
1945 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
1946
1947 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
1948 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
1949 10 << (tx_clk_div + 16));
1950}
1951
1952void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
1953 struct intel_mpllb_state *pll_state)
1954{
1955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1956 enum phy phy = intel_encoder_to_phy(encoder);
1957
1958 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy));
1959 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy));
1960 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy));
1961 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy));
1962 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy));
1963 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy));
1964 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy));
1965
1966 /*
1967 * REF_CONTROL is under firmware control and never programmed by the
1968 * driver; we read it only for sanity checking purposes. The bspec
1969 * only tells us the expected value for one field in this register,
1970 * so we'll only read out those specific bits here.
1971 */
1972 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) &
1973 SNPS_PHY_REF_CONTROL_REF_RANGE;
1974
1975 /*
1976 * MPLLB_DIV is programmed twice, once with the software-computed
1977 * state, then again with the MPLLB_FORCE_EN bit added. Drop that
1978 * extra bit during readout so that we return the actual expected
1979 * software state.
1980 */
1981 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
1982}
1983
1984int intel_snps_phy_check_hdmi_link_rate(int clock)
1985{
1986 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables;
1987 int i;
1988
1989 for (i = 0; tables[i]; i++) {
1990 if (clock == tables[i]->clock)
1991 return MODE_OK;
1992 }
1993
1994 return MODE_CLOCK_RANGE;
1995}
1996
1997void intel_mpllb_state_verify(struct intel_atomic_state *state,
1998 struct intel_crtc *crtc)
1999{
2000 struct intel_display *display = to_intel_display(state);
2001 struct drm_i915_private *i915 = to_i915(state->base.dev);
2002 const struct intel_crtc_state *new_crtc_state =
2003 intel_atomic_get_new_crtc_state(state, crtc);
2004 struct intel_mpllb_state mpllb_hw_state = {};
2005 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb;
2006 struct intel_encoder *encoder;
2007
2008 if (!IS_DG2(i915))
2009 return;
2010
2011 if (!new_crtc_state->hw.active)
2012 return;
2013
2014 /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
2015 if (!intel_crtc_needs_modeset(new_crtc_state) &&
2016 !intel_crtc_needs_fastset(new_crtc_state))
2017 return;
2018
2019 encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
2020 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
2021
2022#define MPLLB_CHECK(__name) \
2023 INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \
2024 "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
2025 crtc->base.base.id, crtc->base.name, \
2026 __stringify(__name), \
2027 mpllb_sw_state->__name, mpllb_hw_state.__name)
2028
2029 MPLLB_CHECK(mpllb_cp);
2030 MPLLB_CHECK(mpllb_div);
2031 MPLLB_CHECK(mpllb_div2);
2032 MPLLB_CHECK(mpllb_fracn1);
2033 MPLLB_CHECK(mpllb_fracn2);
2034 MPLLB_CHECK(mpllb_sscen);
2035 MPLLB_CHECK(mpllb_sscstep);
2036
2037 /*
2038 * ref_control is handled by the hardware/firemware and never
2039 * programmed by the software, but the proper values are supplied
2040 * in the bspec for verification purposes.
2041 */
2042 MPLLB_CHECK(ref_control);
2043
2044#undef MPLLB_CHECK
2045}