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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
37#include <drm/drm_hdcp.h>
38#include <drm/drm_scdc_helper.h>
39#include <drm/intel_lpe_audio.h>
40
41#include "i915_debugfs.h"
42#include "i915_drv.h"
43#include "intel_atomic.h"
44#include "intel_connector.h"
45#include "intel_ddi.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_dp.h"
49#include "intel_gmbus.h"
50#include "intel_hdcp.h"
51#include "intel_hdmi.h"
52#include "intel_lspcon.h"
53#include "intel_panel.h"
54
55static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
56{
57 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
58}
59
60static void
61assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
62{
63 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
64 struct drm_i915_private *dev_priv = to_i915(dev);
65 u32 enabled_bits;
66
67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
68
69 drm_WARN(dev,
70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
71 "HDMI port enabled, expecting disabled\n");
72}
73
74static void
75assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
76 enum transcoder cpu_transcoder)
77{
78 drm_WARN(&dev_priv->drm,
79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
80 TRANS_DDI_FUNC_ENABLE,
81 "HDMI transcoder function enabled, expecting disabled\n");
82}
83
84static u32 g4x_infoframe_index(unsigned int type)
85{
86 switch (type) {
87 case HDMI_PACKET_TYPE_GAMUT_METADATA:
88 return VIDEO_DIP_SELECT_GAMUT;
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_SELECT_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_SELECT_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_SELECT_VENDOR;
95 default:
96 MISSING_CASE(type);
97 return 0;
98 }
99}
100
101static u32 g4x_infoframe_enable(unsigned int type)
102{
103 switch (type) {
104 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
105 return VIDEO_DIP_ENABLE_GCP;
106 case HDMI_PACKET_TYPE_GAMUT_METADATA:
107 return VIDEO_DIP_ENABLE_GAMUT;
108 case DP_SDP_VSC:
109 return 0;
110 case HDMI_INFOFRAME_TYPE_AVI:
111 return VIDEO_DIP_ENABLE_AVI;
112 case HDMI_INFOFRAME_TYPE_SPD:
113 return VIDEO_DIP_ENABLE_SPD;
114 case HDMI_INFOFRAME_TYPE_VENDOR:
115 return VIDEO_DIP_ENABLE_VENDOR;
116 case HDMI_INFOFRAME_TYPE_DRM:
117 return 0;
118 default:
119 MISSING_CASE(type);
120 return 0;
121 }
122}
123
124static u32 hsw_infoframe_enable(unsigned int type)
125{
126 switch (type) {
127 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
128 return VIDEO_DIP_ENABLE_GCP_HSW;
129 case HDMI_PACKET_TYPE_GAMUT_METADATA:
130 return VIDEO_DIP_ENABLE_GMP_HSW;
131 case DP_SDP_VSC:
132 return VIDEO_DIP_ENABLE_VSC_HSW;
133 case DP_SDP_PPS:
134 return VDIP_ENABLE_PPS;
135 case HDMI_INFOFRAME_TYPE_AVI:
136 return VIDEO_DIP_ENABLE_AVI_HSW;
137 case HDMI_INFOFRAME_TYPE_SPD:
138 return VIDEO_DIP_ENABLE_SPD_HSW;
139 case HDMI_INFOFRAME_TYPE_VENDOR:
140 return VIDEO_DIP_ENABLE_VS_HSW;
141 case HDMI_INFOFRAME_TYPE_DRM:
142 return VIDEO_DIP_ENABLE_DRM_GLK;
143 default:
144 MISSING_CASE(type);
145 return 0;
146 }
147}
148
149static i915_reg_t
150hsw_dip_data_reg(struct drm_i915_private *dev_priv,
151 enum transcoder cpu_transcoder,
152 unsigned int type,
153 int i)
154{
155 switch (type) {
156 case HDMI_PACKET_TYPE_GAMUT_METADATA:
157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
158 case DP_SDP_VSC:
159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
160 case DP_SDP_PPS:
161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
162 case HDMI_INFOFRAME_TYPE_AVI:
163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
164 case HDMI_INFOFRAME_TYPE_SPD:
165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_VENDOR:
167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_DRM:
169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
170 default:
171 MISSING_CASE(type);
172 return INVALID_MMIO_REG;
173 }
174}
175
176static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
177 unsigned int type)
178{
179 switch (type) {
180 case DP_SDP_VSC:
181 return VIDEO_DIP_VSC_DATA_SIZE;
182 case DP_SDP_PPS:
183 return VIDEO_DIP_PPS_DATA_SIZE;
184 case HDMI_PACKET_TYPE_GAMUT_METADATA:
185 if (DISPLAY_VER(dev_priv) >= 11)
186 return VIDEO_DIP_GMP_DATA_SIZE;
187 else
188 return VIDEO_DIP_DATA_SIZE;
189 default:
190 return VIDEO_DIP_DATA_SIZE;
191 }
192}
193
194static void g4x_write_infoframe(struct intel_encoder *encoder,
195 const struct intel_crtc_state *crtc_state,
196 unsigned int type,
197 const void *frame, ssize_t len)
198{
199 const u32 *data = frame;
200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
202 int i;
203
204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
205 "Writing DIP with CTL reg disabled\n");
206
207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
208 val |= g4x_infoframe_index(type);
209
210 val &= ~g4x_infoframe_enable(type);
211
212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
213
214 for (i = 0; i < len; i += 4) {
215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
216 data++;
217 }
218 /* Write every possible data byte to force correct ECC calculation. */
219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
221
222 val |= g4x_infoframe_enable(type);
223 val &= ~VIDEO_DIP_FREQ_MASK;
224 val |= VIDEO_DIP_FREQ_VSYNC;
225
226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
228}
229
230static void g4x_read_infoframe(struct intel_encoder *encoder,
231 const struct intel_crtc_state *crtc_state,
232 unsigned int type,
233 void *frame, ssize_t len)
234{
235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
236 u32 val, *data = frame;
237 int i;
238
239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
240
241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
242 val |= g4x_infoframe_index(type);
243
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
245
246 for (i = 0; i < len; i += 4)
247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
248}
249
250static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
251 const struct intel_crtc_state *pipe_config)
252{
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
255
256 if ((val & VIDEO_DIP_ENABLE) == 0)
257 return 0;
258
259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
260 return 0;
261
262 return val & (VIDEO_DIP_ENABLE_AVI |
263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
264}
265
266static void ibx_write_infoframe(struct intel_encoder *encoder,
267 const struct intel_crtc_state *crtc_state,
268 unsigned int type,
269 const void *frame, ssize_t len)
270{
271 const u32 *data = frame;
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
274 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
275 u32 val = intel_de_read(dev_priv, reg);
276 int i;
277
278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
279 "Writing DIP with CTL reg disabled\n");
280
281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
282 val |= g4x_infoframe_index(type);
283
284 val &= ~g4x_infoframe_enable(type);
285
286 intel_de_write(dev_priv, reg, val);
287
288 for (i = 0; i < len; i += 4) {
289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
290 *data);
291 data++;
292 }
293 /* Write every possible data byte to force correct ECC calculation. */
294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
296
297 val |= g4x_infoframe_enable(type);
298 val &= ~VIDEO_DIP_FREQ_MASK;
299 val |= VIDEO_DIP_FREQ_VSYNC;
300
301 intel_de_write(dev_priv, reg, val);
302 intel_de_posting_read(dev_priv, reg);
303}
304
305static void ibx_read_infoframe(struct intel_encoder *encoder,
306 const struct intel_crtc_state *crtc_state,
307 unsigned int type,
308 void *frame, ssize_t len)
309{
310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
312 u32 val, *data = frame;
313 int i;
314
315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
316
317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
318 val |= g4x_infoframe_index(type);
319
320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
321
322 for (i = 0; i < len; i += 4)
323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
324}
325
326static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
327 const struct intel_crtc_state *pipe_config)
328{
329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
332 u32 val = intel_de_read(dev_priv, reg);
333
334 if ((val & VIDEO_DIP_ENABLE) == 0)
335 return 0;
336
337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
338 return 0;
339
340 return val & (VIDEO_DIP_ENABLE_AVI |
341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
343}
344
345static void cpt_write_infoframe(struct intel_encoder *encoder,
346 const struct intel_crtc_state *crtc_state,
347 unsigned int type,
348 const void *frame, ssize_t len)
349{
350 const u32 *data = frame;
351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
353 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
354 u32 val = intel_de_read(dev_priv, reg);
355 int i;
356
357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
358 "Writing DIP with CTL reg disabled\n");
359
360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
361 val |= g4x_infoframe_index(type);
362
363 /* The DIP control register spec says that we need to update the AVI
364 * infoframe without clearing its enable bit */
365 if (type != HDMI_INFOFRAME_TYPE_AVI)
366 val &= ~g4x_infoframe_enable(type);
367
368 intel_de_write(dev_priv, reg, val);
369
370 for (i = 0; i < len; i += 4) {
371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
372 *data);
373 data++;
374 }
375 /* Write every possible data byte to force correct ECC calculation. */
376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
378
379 val |= g4x_infoframe_enable(type);
380 val &= ~VIDEO_DIP_FREQ_MASK;
381 val |= VIDEO_DIP_FREQ_VSYNC;
382
383 intel_de_write(dev_priv, reg, val);
384 intel_de_posting_read(dev_priv, reg);
385}
386
387static void cpt_read_infoframe(struct intel_encoder *encoder,
388 const struct intel_crtc_state *crtc_state,
389 unsigned int type,
390 void *frame, ssize_t len)
391{
392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
394 u32 val, *data = frame;
395 int i;
396
397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
398
399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
400 val |= g4x_infoframe_index(type);
401
402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
403
404 for (i = 0; i < len; i += 4)
405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
406}
407
408static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
409 const struct intel_crtc_state *pipe_config)
410{
411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
414
415 if ((val & VIDEO_DIP_ENABLE) == 0)
416 return 0;
417
418 return val & (VIDEO_DIP_ENABLE_AVI |
419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
421}
422
423static void vlv_write_infoframe(struct intel_encoder *encoder,
424 const struct intel_crtc_state *crtc_state,
425 unsigned int type,
426 const void *frame, ssize_t len)
427{
428 const u32 *data = frame;
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
432 u32 val = intel_de_read(dev_priv, reg);
433 int i;
434
435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
436 "Writing DIP with CTL reg disabled\n");
437
438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
439 val |= g4x_infoframe_index(type);
440
441 val &= ~g4x_infoframe_enable(type);
442
443 intel_de_write(dev_priv, reg, val);
444
445 for (i = 0; i < len; i += 4) {
446 intel_de_write(dev_priv,
447 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
448 data++;
449 }
450 /* Write every possible data byte to force correct ECC calculation. */
451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
452 intel_de_write(dev_priv,
453 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
454
455 val |= g4x_infoframe_enable(type);
456 val &= ~VIDEO_DIP_FREQ_MASK;
457 val |= VIDEO_DIP_FREQ_VSYNC;
458
459 intel_de_write(dev_priv, reg, val);
460 intel_de_posting_read(dev_priv, reg);
461}
462
463static void vlv_read_infoframe(struct intel_encoder *encoder,
464 const struct intel_crtc_state *crtc_state,
465 unsigned int type,
466 void *frame, ssize_t len)
467{
468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
470 u32 val, *data = frame;
471 int i;
472
473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
474
475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
476 val |= g4x_infoframe_index(type);
477
478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
479
480 for (i = 0; i < len; i += 4)
481 *data++ = intel_de_read(dev_priv,
482 VLV_TVIDEO_DIP_DATA(crtc->pipe));
483}
484
485static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
486 const struct intel_crtc_state *pipe_config)
487{
488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
491
492 if ((val & VIDEO_DIP_ENABLE) == 0)
493 return 0;
494
495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
496 return 0;
497
498 return val & (VIDEO_DIP_ENABLE_AVI |
499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
501}
502
503void hsw_write_infoframe(struct intel_encoder *encoder,
504 const struct intel_crtc_state *crtc_state,
505 unsigned int type,
506 const void *frame, ssize_t len)
507{
508 const u32 *data = frame;
509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
512 int data_size;
513 int i;
514 u32 val = intel_de_read(dev_priv, ctl_reg);
515
516 data_size = hsw_dip_data_size(dev_priv, type);
517
518 drm_WARN_ON(&dev_priv->drm, len > data_size);
519
520 val &= ~hsw_infoframe_enable(type);
521 intel_de_write(dev_priv, ctl_reg, val);
522
523 for (i = 0; i < len; i += 4) {
524 intel_de_write(dev_priv,
525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
526 *data);
527 data++;
528 }
529 /* Write every possible data byte to force correct ECC calculation. */
530 for (; i < data_size; i += 4)
531 intel_de_write(dev_priv,
532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
533 0);
534
535 /* Wa_14013475917 */
536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
537 type == DP_SDP_VSC)
538 return;
539
540 val |= hsw_infoframe_enable(type);
541 intel_de_write(dev_priv, ctl_reg, val);
542 intel_de_posting_read(dev_priv, ctl_reg);
543}
544
545void hsw_read_infoframe(struct intel_encoder *encoder,
546 const struct intel_crtc_state *crtc_state,
547 unsigned int type, void *frame, ssize_t len)
548{
549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
551 u32 *data = frame;
552 int i;
553
554 for (i = 0; i < len; i += 4)
555 *data++ = intel_de_read(dev_priv,
556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
557}
558
559static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
560 const struct intel_crtc_state *pipe_config)
561{
562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 u32 val = intel_de_read(dev_priv,
564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
565 u32 mask;
566
567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
570
571 if (DISPLAY_VER(dev_priv) >= 10)
572 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
573
574 return val & mask;
575}
576
577static const u8 infoframe_type_to_idx[] = {
578 HDMI_PACKET_TYPE_GENERAL_CONTROL,
579 HDMI_PACKET_TYPE_GAMUT_METADATA,
580 DP_SDP_VSC,
581 HDMI_INFOFRAME_TYPE_AVI,
582 HDMI_INFOFRAME_TYPE_SPD,
583 HDMI_INFOFRAME_TYPE_VENDOR,
584 HDMI_INFOFRAME_TYPE_DRM,
585};
586
587u32 intel_hdmi_infoframe_enable(unsigned int type)
588{
589 int i;
590
591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
592 if (infoframe_type_to_idx[i] == type)
593 return BIT(i);
594 }
595
596 return 0;
597}
598
599u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
600 const struct intel_crtc_state *crtc_state)
601{
602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
604 u32 val, ret = 0;
605 int i;
606
607 val = dig_port->infoframes_enabled(encoder, crtc_state);
608
609 /* map from hardware bits to dip idx */
610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
611 unsigned int type = infoframe_type_to_idx[i];
612
613 if (HAS_DDI(dev_priv)) {
614 if (val & hsw_infoframe_enable(type))
615 ret |= BIT(i);
616 } else {
617 if (val & g4x_infoframe_enable(type))
618 ret |= BIT(i);
619 }
620 }
621
622 return ret;
623}
624
625/*
626 * The data we write to the DIP data buffer registers is 1 byte bigger than the
627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
629 * used for both technologies.
630 *
631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
632 * DW1: DB3 | DB2 | DB1 | DB0
633 * DW2: DB7 | DB6 | DB5 | DB4
634 * DW3: ...
635 *
636 * (HB is Header Byte, DB is Data Byte)
637 *
638 * The hdmi pack() functions don't know about that hardware specific hole so we
639 * trick them by giving an offset into the buffer and moving back the header
640 * bytes by one.
641 */
642static void intel_write_infoframe(struct intel_encoder *encoder,
643 const struct intel_crtc_state *crtc_state,
644 enum hdmi_infoframe_type type,
645 const union hdmi_infoframe *frame)
646{
647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
648 u8 buffer[VIDEO_DIP_DATA_SIZE];
649 ssize_t len;
650
651 if ((crtc_state->infoframes.enable &
652 intel_hdmi_infoframe_enable(type)) == 0)
653 return;
654
655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
656 return;
657
658 /* see comment above for the reason for this offset */
659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
660 if (drm_WARN_ON(encoder->base.dev, len < 0))
661 return;
662
663 /* Insert the 'hole' (see big comment above) at position 3 */
664 memmove(&buffer[0], &buffer[1], 3);
665 buffer[3] = 0;
666 len++;
667
668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
669}
670
671void intel_read_infoframe(struct intel_encoder *encoder,
672 const struct intel_crtc_state *crtc_state,
673 enum hdmi_infoframe_type type,
674 union hdmi_infoframe *frame)
675{
676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
677 u8 buffer[VIDEO_DIP_DATA_SIZE];
678 int ret;
679
680 if ((crtc_state->infoframes.enable &
681 intel_hdmi_infoframe_enable(type)) == 0)
682 return;
683
684 dig_port->read_infoframe(encoder, crtc_state,
685 type, buffer, sizeof(buffer));
686
687 /* Fill the 'hole' (see big comment above) at position 3 */
688 memmove(&buffer[1], &buffer[0], 3);
689
690 /* see comment above for the reason for this offset */
691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
692 if (ret) {
693 drm_dbg_kms(encoder->base.dev,
694 "Failed to unpack infoframe type 0x%02x\n", type);
695 return;
696 }
697
698 if (frame->any.type != type)
699 drm_dbg_kms(encoder->base.dev,
700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
701 frame->any.type, type);
702}
703
704static bool
705intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
706 struct intel_crtc_state *crtc_state,
707 struct drm_connector_state *conn_state)
708{
709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
710 const struct drm_display_mode *adjusted_mode =
711 &crtc_state->hw.adjusted_mode;
712 struct drm_connector *connector = conn_state->connector;
713 int ret;
714
715 if (!crtc_state->has_infoframe)
716 return true;
717
718 crtc_state->infoframes.enable |=
719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
720
721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
722 adjusted_mode);
723 if (ret)
724 return false;
725
726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
727 frame->colorspace = HDMI_COLORSPACE_YUV420;
728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
729 frame->colorspace = HDMI_COLORSPACE_YUV444;
730 else
731 frame->colorspace = HDMI_COLORSPACE_RGB;
732
733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
734
735 /* nonsense combination */
736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
738
739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
740 drm_hdmi_avi_infoframe_quant_range(frame, connector,
741 adjusted_mode,
742 crtc_state->limited_color_range ?
743 HDMI_QUANTIZATION_RANGE_LIMITED :
744 HDMI_QUANTIZATION_RANGE_FULL);
745 } else {
746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
748 }
749
750 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
751
752 /* TODO: handle pixel repetition for YCBCR420 outputs */
753
754 ret = hdmi_avi_infoframe_check(frame);
755 if (drm_WARN_ON(encoder->base.dev, ret))
756 return false;
757
758 return true;
759}
760
761static bool
762intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
763 struct intel_crtc_state *crtc_state,
764 struct drm_connector_state *conn_state)
765{
766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
767 int ret;
768
769 if (!crtc_state->has_infoframe)
770 return true;
771
772 crtc_state->infoframes.enable |=
773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
774
775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
776 if (drm_WARN_ON(encoder->base.dev, ret))
777 return false;
778
779 frame->sdi = HDMI_SPD_SDI_PC;
780
781 ret = hdmi_spd_infoframe_check(frame);
782 if (drm_WARN_ON(encoder->base.dev, ret))
783 return false;
784
785 return true;
786}
787
788static bool
789intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
790 struct intel_crtc_state *crtc_state,
791 struct drm_connector_state *conn_state)
792{
793 struct hdmi_vendor_infoframe *frame =
794 &crtc_state->infoframes.hdmi.vendor.hdmi;
795 const struct drm_display_info *info =
796 &conn_state->connector->display_info;
797 int ret;
798
799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
800 return true;
801
802 crtc_state->infoframes.enable |=
803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
804
805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
806 conn_state->connector,
807 &crtc_state->hw.adjusted_mode);
808 if (drm_WARN_ON(encoder->base.dev, ret))
809 return false;
810
811 ret = hdmi_vendor_infoframe_check(frame);
812 if (drm_WARN_ON(encoder->base.dev, ret))
813 return false;
814
815 return true;
816}
817
818static bool
819intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
820 struct intel_crtc_state *crtc_state,
821 struct drm_connector_state *conn_state)
822{
823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
825 int ret;
826
827 if (DISPLAY_VER(dev_priv) < 10)
828 return true;
829
830 if (!crtc_state->has_infoframe)
831 return true;
832
833 if (!conn_state->hdr_output_metadata)
834 return true;
835
836 crtc_state->infoframes.enable |=
837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
838
839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
840 if (ret < 0) {
841 drm_dbg_kms(&dev_priv->drm,
842 "couldn't set HDR metadata in infoframe\n");
843 return false;
844 }
845
846 ret = hdmi_drm_infoframe_check(frame);
847 if (drm_WARN_ON(&dev_priv->drm, ret))
848 return false;
849
850 return true;
851}
852
853static void g4x_set_infoframes(struct intel_encoder *encoder,
854 bool enable,
855 const struct intel_crtc_state *crtc_state,
856 const struct drm_connector_state *conn_state)
857{
858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
861 i915_reg_t reg = VIDEO_DIP_CTL;
862 u32 val = intel_de_read(dev_priv, reg);
863 u32 port = VIDEO_DIP_PORT(encoder->port);
864
865 assert_hdmi_port_disabled(intel_hdmi);
866
867 /* If the registers were not initialized yet, they might be zeroes,
868 * which means we're selecting the AVI DIP and we're setting its
869 * frequency to once. This seems to really confuse the HW and make
870 * things stop working (the register spec says the AVI always needs to
871 * be sent every VSync). So here we avoid writing to the register more
872 * than we need and also explicitly select the AVI DIP and explicitly
873 * set its frequency to every VSync. Avoiding to write it twice seems to
874 * be enough to solve the problem, but being defensive shouldn't hurt us
875 * either. */
876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
877
878 if (!enable) {
879 if (!(val & VIDEO_DIP_ENABLE))
880 return;
881 if (port != (val & VIDEO_DIP_PORT_MASK)) {
882 drm_dbg_kms(&dev_priv->drm,
883 "video DIP still enabled on port %c\n",
884 (val & VIDEO_DIP_PORT_MASK) >> 29);
885 return;
886 }
887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
889 intel_de_write(dev_priv, reg, val);
890 intel_de_posting_read(dev_priv, reg);
891 return;
892 }
893
894 if (port != (val & VIDEO_DIP_PORT_MASK)) {
895 if (val & VIDEO_DIP_ENABLE) {
896 drm_dbg_kms(&dev_priv->drm,
897 "video DIP already enabled on port %c\n",
898 (val & VIDEO_DIP_PORT_MASK) >> 29);
899 return;
900 }
901 val &= ~VIDEO_DIP_PORT_MASK;
902 val |= port;
903 }
904
905 val |= VIDEO_DIP_ENABLE;
906 val &= ~(VIDEO_DIP_ENABLE_AVI |
907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
908
909 intel_de_write(dev_priv, reg, val);
910 intel_de_posting_read(dev_priv, reg);
911
912 intel_write_infoframe(encoder, crtc_state,
913 HDMI_INFOFRAME_TYPE_AVI,
914 &crtc_state->infoframes.avi);
915 intel_write_infoframe(encoder, crtc_state,
916 HDMI_INFOFRAME_TYPE_SPD,
917 &crtc_state->infoframes.spd);
918 intel_write_infoframe(encoder, crtc_state,
919 HDMI_INFOFRAME_TYPE_VENDOR,
920 &crtc_state->infoframes.hdmi);
921}
922
923/*
924 * Determine if default_phase=1 can be indicated in the GCP infoframe.
925 *
926 * From HDMI specification 1.4a:
927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
931 * phase of 0
932 */
933static bool gcp_default_phase_possible(int pipe_bpp,
934 const struct drm_display_mode *mode)
935{
936 unsigned int pixels_per_group;
937
938 switch (pipe_bpp) {
939 case 30:
940 /* 4 pixels in 5 clocks */
941 pixels_per_group = 4;
942 break;
943 case 36:
944 /* 2 pixels in 3 clocks */
945 pixels_per_group = 2;
946 break;
947 case 48:
948 /* 1 pixel in 2 clocks */
949 pixels_per_group = 1;
950 break;
951 default:
952 /* phase information not relevant for 8bpc */
953 return false;
954 }
955
956 return mode->crtc_hdisplay % pixels_per_group == 0 &&
957 mode->crtc_htotal % pixels_per_group == 0 &&
958 mode->crtc_hblank_start % pixels_per_group == 0 &&
959 mode->crtc_hblank_end % pixels_per_group == 0 &&
960 mode->crtc_hsync_start % pixels_per_group == 0 &&
961 mode->crtc_hsync_end % pixels_per_group == 0 &&
962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
963 mode->crtc_htotal/2 % pixels_per_group == 0);
964}
965
966static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
967 const struct intel_crtc_state *crtc_state,
968 const struct drm_connector_state *conn_state)
969{
970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
972 i915_reg_t reg;
973
974 if ((crtc_state->infoframes.enable &
975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
976 return false;
977
978 if (HAS_DDI(dev_priv))
979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
982 else if (HAS_PCH_SPLIT(dev_priv))
983 reg = TVIDEO_DIP_GCP(crtc->pipe);
984 else
985 return false;
986
987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
988
989 return true;
990}
991
992void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
993 struct intel_crtc_state *crtc_state)
994{
995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
997 i915_reg_t reg;
998
999 if ((crtc_state->infoframes.enable &
1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1001 return;
1002
1003 if (HAS_DDI(dev_priv))
1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1007 else if (HAS_PCH_SPLIT(dev_priv))
1008 reg = TVIDEO_DIP_GCP(crtc->pipe);
1009 else
1010 return;
1011
1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1013}
1014
1015static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1016 struct intel_crtc_state *crtc_state,
1017 struct drm_connector_state *conn_state)
1018{
1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1020
1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1022 return;
1023
1024 crtc_state->infoframes.enable |=
1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1026
1027 /* Indicate color indication for deep color mode */
1028 if (crtc_state->pipe_bpp > 24)
1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1030
1031 /* Enable default_phase whenever the display mode is suitably aligned */
1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1033 &crtc_state->hw.adjusted_mode))
1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1035}
1036
1037static void ibx_set_infoframes(struct intel_encoder *encoder,
1038 bool enable,
1039 const struct intel_crtc_state *crtc_state,
1040 const struct drm_connector_state *conn_state)
1041{
1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1046 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1047 u32 val = intel_de_read(dev_priv, reg);
1048 u32 port = VIDEO_DIP_PORT(encoder->port);
1049
1050 assert_hdmi_port_disabled(intel_hdmi);
1051
1052 /* See the big comment in g4x_set_infoframes() */
1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1054
1055 if (!enable) {
1056 if (!(val & VIDEO_DIP_ENABLE))
1057 return;
1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1061 intel_de_write(dev_priv, reg, val);
1062 intel_de_posting_read(dev_priv, reg);
1063 return;
1064 }
1065
1066 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1068 "DIP already enabled on port %c\n",
1069 (val & VIDEO_DIP_PORT_MASK) >> 29);
1070 val &= ~VIDEO_DIP_PORT_MASK;
1071 val |= port;
1072 }
1073
1074 val |= VIDEO_DIP_ENABLE;
1075 val &= ~(VIDEO_DIP_ENABLE_AVI |
1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1078
1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1080 val |= VIDEO_DIP_ENABLE_GCP;
1081
1082 intel_de_write(dev_priv, reg, val);
1083 intel_de_posting_read(dev_priv, reg);
1084
1085 intel_write_infoframe(encoder, crtc_state,
1086 HDMI_INFOFRAME_TYPE_AVI,
1087 &crtc_state->infoframes.avi);
1088 intel_write_infoframe(encoder, crtc_state,
1089 HDMI_INFOFRAME_TYPE_SPD,
1090 &crtc_state->infoframes.spd);
1091 intel_write_infoframe(encoder, crtc_state,
1092 HDMI_INFOFRAME_TYPE_VENDOR,
1093 &crtc_state->infoframes.hdmi);
1094}
1095
1096static void cpt_set_infoframes(struct intel_encoder *encoder,
1097 bool enable,
1098 const struct intel_crtc_state *crtc_state,
1099 const struct drm_connector_state *conn_state)
1100{
1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1104 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1105 u32 val = intel_de_read(dev_priv, reg);
1106
1107 assert_hdmi_port_disabled(intel_hdmi);
1108
1109 /* See the big comment in g4x_set_infoframes() */
1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1111
1112 if (!enable) {
1113 if (!(val & VIDEO_DIP_ENABLE))
1114 return;
1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1118 intel_de_write(dev_priv, reg, val);
1119 intel_de_posting_read(dev_priv, reg);
1120 return;
1121 }
1122
1123 /* Set both together, unset both together: see the spec. */
1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1127
1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1129 val |= VIDEO_DIP_ENABLE_GCP;
1130
1131 intel_de_write(dev_priv, reg, val);
1132 intel_de_posting_read(dev_priv, reg);
1133
1134 intel_write_infoframe(encoder, crtc_state,
1135 HDMI_INFOFRAME_TYPE_AVI,
1136 &crtc_state->infoframes.avi);
1137 intel_write_infoframe(encoder, crtc_state,
1138 HDMI_INFOFRAME_TYPE_SPD,
1139 &crtc_state->infoframes.spd);
1140 intel_write_infoframe(encoder, crtc_state,
1141 HDMI_INFOFRAME_TYPE_VENDOR,
1142 &crtc_state->infoframes.hdmi);
1143}
1144
1145static void vlv_set_infoframes(struct intel_encoder *encoder,
1146 bool enable,
1147 const struct intel_crtc_state *crtc_state,
1148 const struct drm_connector_state *conn_state)
1149{
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1154 u32 val = intel_de_read(dev_priv, reg);
1155 u32 port = VIDEO_DIP_PORT(encoder->port);
1156
1157 assert_hdmi_port_disabled(intel_hdmi);
1158
1159 /* See the big comment in g4x_set_infoframes() */
1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1161
1162 if (!enable) {
1163 if (!(val & VIDEO_DIP_ENABLE))
1164 return;
1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1168 intel_de_write(dev_priv, reg, val);
1169 intel_de_posting_read(dev_priv, reg);
1170 return;
1171 }
1172
1173 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1175 "DIP already enabled on port %c\n",
1176 (val & VIDEO_DIP_PORT_MASK) >> 29);
1177 val &= ~VIDEO_DIP_PORT_MASK;
1178 val |= port;
1179 }
1180
1181 val |= VIDEO_DIP_ENABLE;
1182 val &= ~(VIDEO_DIP_ENABLE_AVI |
1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1185
1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1187 val |= VIDEO_DIP_ENABLE_GCP;
1188
1189 intel_de_write(dev_priv, reg, val);
1190 intel_de_posting_read(dev_priv, reg);
1191
1192 intel_write_infoframe(encoder, crtc_state,
1193 HDMI_INFOFRAME_TYPE_AVI,
1194 &crtc_state->infoframes.avi);
1195 intel_write_infoframe(encoder, crtc_state,
1196 HDMI_INFOFRAME_TYPE_SPD,
1197 &crtc_state->infoframes.spd);
1198 intel_write_infoframe(encoder, crtc_state,
1199 HDMI_INFOFRAME_TYPE_VENDOR,
1200 &crtc_state->infoframes.hdmi);
1201}
1202
1203static void hsw_set_infoframes(struct intel_encoder *encoder,
1204 bool enable,
1205 const struct intel_crtc_state *crtc_state,
1206 const struct drm_connector_state *conn_state)
1207{
1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1210 u32 val = intel_de_read(dev_priv, reg);
1211
1212 assert_hdmi_transcoder_func_disabled(dev_priv,
1213 crtc_state->cpu_transcoder);
1214
1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1218 VIDEO_DIP_ENABLE_DRM_GLK);
1219
1220 if (!enable) {
1221 intel_de_write(dev_priv, reg, val);
1222 intel_de_posting_read(dev_priv, reg);
1223 return;
1224 }
1225
1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1227 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1228
1229 intel_de_write(dev_priv, reg, val);
1230 intel_de_posting_read(dev_priv, reg);
1231
1232 intel_write_infoframe(encoder, crtc_state,
1233 HDMI_INFOFRAME_TYPE_AVI,
1234 &crtc_state->infoframes.avi);
1235 intel_write_infoframe(encoder, crtc_state,
1236 HDMI_INFOFRAME_TYPE_SPD,
1237 &crtc_state->infoframes.spd);
1238 intel_write_infoframe(encoder, crtc_state,
1239 HDMI_INFOFRAME_TYPE_VENDOR,
1240 &crtc_state->infoframes.hdmi);
1241 intel_write_infoframe(encoder, crtc_state,
1242 HDMI_INFOFRAME_TYPE_DRM,
1243 &crtc_state->infoframes.drm);
1244}
1245
1246void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1247{
1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1249 struct i2c_adapter *adapter =
1250 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1251
1252 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1253 return;
1254
1255 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1256 enable ? "Enabling" : "Disabling");
1257
1258 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1259}
1260
1261static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1262 unsigned int offset, void *buffer, size_t size)
1263{
1264 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1265 struct intel_hdmi *hdmi = &dig_port->hdmi;
1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1267 hdmi->ddc_bus);
1268 int ret;
1269 u8 start = offset & 0xff;
1270 struct i2c_msg msgs[] = {
1271 {
1272 .addr = DRM_HDCP_DDC_ADDR,
1273 .flags = 0,
1274 .len = 1,
1275 .buf = &start,
1276 },
1277 {
1278 .addr = DRM_HDCP_DDC_ADDR,
1279 .flags = I2C_M_RD,
1280 .len = size,
1281 .buf = buffer
1282 }
1283 };
1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1285 if (ret == ARRAY_SIZE(msgs))
1286 return 0;
1287 return ret >= 0 ? -EIO : ret;
1288}
1289
1290static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1291 unsigned int offset, void *buffer, size_t size)
1292{
1293 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1294 struct intel_hdmi *hdmi = &dig_port->hdmi;
1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1296 hdmi->ddc_bus);
1297 int ret;
1298 u8 *write_buf;
1299 struct i2c_msg msg;
1300
1301 write_buf = kzalloc(size + 1, GFP_KERNEL);
1302 if (!write_buf)
1303 return -ENOMEM;
1304
1305 write_buf[0] = offset & 0xff;
1306 memcpy(&write_buf[1], buffer, size);
1307
1308 msg.addr = DRM_HDCP_DDC_ADDR;
1309 msg.flags = 0,
1310 msg.len = size + 1,
1311 msg.buf = write_buf;
1312
1313 ret = i2c_transfer(adapter, &msg, 1);
1314 if (ret == 1)
1315 ret = 0;
1316 else if (ret >= 0)
1317 ret = -EIO;
1318
1319 kfree(write_buf);
1320 return ret;
1321}
1322
1323static
1324int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1325 u8 *an)
1326{
1327 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1328 struct intel_hdmi *hdmi = &dig_port->hdmi;
1329 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1330 hdmi->ddc_bus);
1331 int ret;
1332
1333 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1334 DRM_HDCP_AN_LEN);
1335 if (ret) {
1336 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1337 ret);
1338 return ret;
1339 }
1340
1341 ret = intel_gmbus_output_aksv(adapter);
1342 if (ret < 0) {
1343 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1344 return ret;
1345 }
1346 return 0;
1347}
1348
1349static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1350 u8 *bksv)
1351{
1352 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1353
1354 int ret;
1355 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1356 DRM_HDCP_KSV_LEN);
1357 if (ret)
1358 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1359 ret);
1360 return ret;
1361}
1362
1363static
1364int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1365 u8 *bstatus)
1366{
1367 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1368
1369 int ret;
1370 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1371 bstatus, DRM_HDCP_BSTATUS_LEN);
1372 if (ret)
1373 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1374 ret);
1375 return ret;
1376}
1377
1378static
1379int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1380 bool *repeater_present)
1381{
1382 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1383 int ret;
1384 u8 val;
1385
1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1387 if (ret) {
1388 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1389 ret);
1390 return ret;
1391 }
1392 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1393 return 0;
1394}
1395
1396static
1397int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1398 u8 *ri_prime)
1399{
1400 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1401
1402 int ret;
1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1404 ri_prime, DRM_HDCP_RI_LEN);
1405 if (ret)
1406 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1407 ret);
1408 return ret;
1409}
1410
1411static
1412int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1413 bool *ksv_ready)
1414{
1415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1416 int ret;
1417 u8 val;
1418
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1420 if (ret) {
1421 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1422 ret);
1423 return ret;
1424 }
1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1426 return 0;
1427}
1428
1429static
1430int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1431 int num_downstream, u8 *ksv_fifo)
1432{
1433 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1434 int ret;
1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1436 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1437 if (ret) {
1438 drm_dbg_kms(&i915->drm,
1439 "Read ksv fifo over DDC failed (%d)\n", ret);
1440 return ret;
1441 }
1442 return 0;
1443}
1444
1445static
1446int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1447 int i, u32 *part)
1448{
1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1450 int ret;
1451
1452 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1453 return -EINVAL;
1454
1455 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1456 part, DRM_HDCP_V_PRIME_PART_LEN);
1457 if (ret)
1458 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1459 i, ret);
1460 return ret;
1461}
1462
1463static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1464 enum transcoder cpu_transcoder)
1465{
1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1468 struct drm_crtc *crtc = connector->base.state->crtc;
1469 struct intel_crtc *intel_crtc = container_of(crtc,
1470 struct intel_crtc, base);
1471 u32 scanline;
1472 int ret;
1473
1474 for (;;) {
1475 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1476 if (scanline > 100 && scanline < 200)
1477 break;
1478 usleep_range(25, 50);
1479 }
1480
1481 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1482 false, TRANS_DDI_HDCP_SIGNALLING);
1483 if (ret) {
1484 drm_err(&dev_priv->drm,
1485 "Disable HDCP signalling failed (%d)\n", ret);
1486 return ret;
1487 }
1488
1489 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1490 true, TRANS_DDI_HDCP_SIGNALLING);
1491 if (ret) {
1492 drm_err(&dev_priv->drm,
1493 "Enable HDCP signalling failed (%d)\n", ret);
1494 return ret;
1495 }
1496
1497 return 0;
1498}
1499
1500static
1501int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1502 enum transcoder cpu_transcoder,
1503 bool enable)
1504{
1505 struct intel_hdmi *hdmi = &dig_port->hdmi;
1506 struct intel_connector *connector = hdmi->attached_connector;
1507 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1508 int ret;
1509
1510 if (!enable)
1511 usleep_range(6, 60); /* Bspec says >= 6us */
1512
1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1514 cpu_transcoder, enable,
1515 TRANS_DDI_HDCP_SIGNALLING);
1516 if (ret) {
1517 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1518 enable ? "Enable" : "Disable", ret);
1519 return ret;
1520 }
1521
1522 /*
1523 * WA: To fix incorrect positioning of the window of
1524 * opportunity and enc_en signalling in KABYLAKE.
1525 */
1526 if (IS_KABYLAKE(dev_priv) && enable)
1527 return kbl_repositioning_enc_en_signal(connector,
1528 cpu_transcoder);
1529
1530 return 0;
1531}
1532
1533static
1534bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1535 struct intel_connector *connector)
1536{
1537 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1538 enum port port = dig_port->base.port;
1539 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1540 int ret;
1541 union {
1542 u32 reg;
1543 u8 shim[DRM_HDCP_RI_LEN];
1544 } ri;
1545
1546 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1547 if (ret)
1548 return false;
1549
1550 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1551
1552 /* Wait for Ri prime match */
1553 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1554 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1556 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1557 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1558 port)));
1559 return false;
1560 }
1561 return true;
1562}
1563
1564static
1565bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1566 struct intel_connector *connector)
1567{
1568 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1569 int retry;
1570
1571 for (retry = 0; retry < 3; retry++)
1572 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1573 return true;
1574
1575 drm_err(&i915->drm, "Link check failed\n");
1576 return false;
1577}
1578
1579struct hdcp2_hdmi_msg_timeout {
1580 u8 msg_id;
1581 u16 timeout;
1582};
1583
1584static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1585 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1586 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1587 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1588 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1589 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1590};
1591
1592static
1593int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1594 u8 *rx_status)
1595{
1596 return intel_hdmi_hdcp_read(dig_port,
1597 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1598 rx_status,
1599 HDCP_2_2_HDMI_RXSTATUS_LEN);
1600}
1601
1602static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1603{
1604 int i;
1605
1606 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1607 if (is_paired)
1608 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1609 else
1610 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1611 }
1612
1613 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1614 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1615 return hdcp2_msg_timeout[i].timeout;
1616 }
1617
1618 return -EINVAL;
1619}
1620
1621static int
1622hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1623 u8 msg_id, bool *msg_ready,
1624 ssize_t *msg_sz)
1625{
1626 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1627 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1628 int ret;
1629
1630 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1631 if (ret < 0) {
1632 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1633 ret);
1634 return ret;
1635 }
1636
1637 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1638 rx_status[0]);
1639
1640 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1641 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1642 *msg_sz);
1643 else
1644 *msg_ready = *msg_sz;
1645
1646 return 0;
1647}
1648
1649static ssize_t
1650intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1651 u8 msg_id, bool paired)
1652{
1653 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1654 bool msg_ready = false;
1655 int timeout, ret;
1656 ssize_t msg_sz = 0;
1657
1658 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1659 if (timeout < 0)
1660 return timeout;
1661
1662 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1663 msg_id, &msg_ready,
1664 &msg_sz),
1665 !ret && msg_ready && msg_sz, timeout * 1000,
1666 1000, 5 * 1000);
1667 if (ret)
1668 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1669 msg_id, ret, timeout);
1670
1671 return ret ? ret : msg_sz;
1672}
1673
1674static
1675int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1676 void *buf, size_t size)
1677{
1678 unsigned int offset;
1679
1680 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1681 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1682}
1683
1684static
1685int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1686 u8 msg_id, void *buf, size_t size)
1687{
1688 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1689 struct intel_hdmi *hdmi = &dig_port->hdmi;
1690 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1691 unsigned int offset;
1692 ssize_t ret;
1693
1694 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1695 hdcp->is_paired);
1696 if (ret < 0)
1697 return ret;
1698
1699 /*
1700 * Available msg size should be equal to or lesser than the
1701 * available buffer.
1702 */
1703 if (ret > size) {
1704 drm_dbg_kms(&i915->drm,
1705 "msg_sz(%zd) is more than exp size(%zu)\n",
1706 ret, size);
1707 return -1;
1708 }
1709
1710 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1711 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1712 if (ret)
1713 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1714 msg_id, ret);
1715
1716 return ret;
1717}
1718
1719static
1720int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1721 struct intel_connector *connector)
1722{
1723 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1724 int ret;
1725
1726 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1727 if (ret)
1728 return ret;
1729
1730 /*
1731 * Re-auth request and Link Integrity Failures are represented by
1732 * same bit. i.e reauth_req.
1733 */
1734 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1735 ret = HDCP_REAUTH_REQUEST;
1736 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1737 ret = HDCP_TOPOLOGY_CHANGE;
1738
1739 return ret;
1740}
1741
1742static
1743int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1744 bool *capable)
1745{
1746 u8 hdcp2_version;
1747 int ret;
1748
1749 *capable = false;
1750 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1751 &hdcp2_version, sizeof(hdcp2_version));
1752 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1753 *capable = true;
1754
1755 return ret;
1756}
1757
1758static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1759 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1760 .read_bksv = intel_hdmi_hdcp_read_bksv,
1761 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1762 .repeater_present = intel_hdmi_hdcp_repeater_present,
1763 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1764 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1765 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1766 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1767 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1768 .check_link = intel_hdmi_hdcp_check_link,
1769 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1770 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1771 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1772 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1773 .protocol = HDCP_PROTOCOL_HDMI,
1774};
1775
1776static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1777{
1778 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1779 int max_tmds_clock, vbt_max_tmds_clock;
1780
1781 if (DISPLAY_VER(dev_priv) >= 10)
1782 max_tmds_clock = 594000;
1783 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1784 max_tmds_clock = 300000;
1785 else if (DISPLAY_VER(dev_priv) >= 5)
1786 max_tmds_clock = 225000;
1787 else
1788 max_tmds_clock = 165000;
1789
1790 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1791 if (vbt_max_tmds_clock)
1792 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1793
1794 return max_tmds_clock;
1795}
1796
1797static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1798 const struct drm_connector_state *conn_state)
1799{
1800 return hdmi->has_hdmi_sink &&
1801 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1802}
1803
1804static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1805 bool respect_downstream_limits,
1806 bool has_hdmi_sink)
1807{
1808 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1809 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1810
1811 if (respect_downstream_limits) {
1812 struct intel_connector *connector = hdmi->attached_connector;
1813 const struct drm_display_info *info = &connector->base.display_info;
1814
1815 if (hdmi->dp_dual_mode.max_tmds_clock)
1816 max_tmds_clock = min(max_tmds_clock,
1817 hdmi->dp_dual_mode.max_tmds_clock);
1818
1819 if (info->max_tmds_clock)
1820 max_tmds_clock = min(max_tmds_clock,
1821 info->max_tmds_clock);
1822 else if (!has_hdmi_sink)
1823 max_tmds_clock = min(max_tmds_clock, 165000);
1824 }
1825
1826 return max_tmds_clock;
1827}
1828
1829static enum drm_mode_status
1830hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1831 int clock, bool respect_downstream_limits,
1832 bool has_hdmi_sink)
1833{
1834 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1835
1836 if (clock < 25000)
1837 return MODE_CLOCK_LOW;
1838 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1839 has_hdmi_sink))
1840 return MODE_CLOCK_HIGH;
1841
1842 /* GLK DPLL can't generate 446-480 MHz */
1843 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1844 return MODE_CLOCK_RANGE;
1845
1846 /* BXT/GLK DPLL can't generate 223-240 MHz */
1847 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1848 clock > 223333 && clock < 240000)
1849 return MODE_CLOCK_RANGE;
1850
1851 /* CHV DPLL can't generate 216-240 MHz */
1852 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1853 return MODE_CLOCK_RANGE;
1854
1855 return MODE_OK;
1856}
1857
1858static int intel_hdmi_port_clock(int clock, int bpc)
1859{
1860 /*
1861 * Need to adjust the port link by:
1862 * 1.5x for 12bpc
1863 * 1.25x for 10bpc
1864 */
1865 return clock * bpc / 8;
1866}
1867
1868static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
1869 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1870{
1871 struct drm_i915_private *i915 = to_i915(connector->dev);
1872 const struct drm_display_info *info = &connector->display_info;
1873 const struct drm_hdmi_info *hdmi = &info->hdmi;
1874
1875 switch (bpc) {
1876 case 12:
1877 if (HAS_GMCH(i915))
1878 return false;
1879
1880 if (!has_hdmi_sink)
1881 return false;
1882
1883 if (ycbcr420_output)
1884 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1885 else
1886 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36;
1887 case 10:
1888 if (DISPLAY_VER(i915) < 11)
1889 return false;
1890
1891 if (!has_hdmi_sink)
1892 return false;
1893
1894 if (ycbcr420_output)
1895 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1896 else
1897 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30;
1898 case 8:
1899 return true;
1900 default:
1901 MISSING_CASE(bpc);
1902 return false;
1903 }
1904}
1905
1906static enum drm_mode_status
1907intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1908 bool has_hdmi_sink, bool ycbcr420_output)
1909{
1910 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1911 enum drm_mode_status status;
1912
1913 if (ycbcr420_output)
1914 clock /= 2;
1915
1916 /* check if we can do 8bpc */
1917 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
1918 true, has_hdmi_sink);
1919
1920 /* if we can't do 8bpc we may still be able to do 12bpc */
1921 if (status != MODE_OK &&
1922 intel_hdmi_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
1923 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
1924 true, has_hdmi_sink);
1925
1926 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1927 if (status != MODE_OK &&
1928 intel_hdmi_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
1929 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
1930 true, has_hdmi_sink);
1931
1932 return status;
1933}
1934
1935static enum drm_mode_status
1936intel_hdmi_mode_valid(struct drm_connector *connector,
1937 struct drm_display_mode *mode)
1938{
1939 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1940 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1941 struct drm_i915_private *dev_priv = to_i915(dev);
1942 enum drm_mode_status status;
1943 int clock = mode->clock;
1944 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1945 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1946 bool ycbcr_420_only;
1947
1948 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1949 return MODE_NO_DBLESCAN;
1950
1951 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1952 clock *= 2;
1953
1954 if (clock > max_dotclk)
1955 return MODE_CLOCK_HIGH;
1956
1957 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1958 if (!has_hdmi_sink)
1959 return MODE_CLOCK_LOW;
1960 clock *= 2;
1961 }
1962
1963 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
1964
1965 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
1966 if (status != MODE_OK) {
1967 if (ycbcr_420_only ||
1968 !connector->ycbcr_420_allowed ||
1969 !drm_mode_is_420_also(&connector->display_info, mode))
1970 return status;
1971
1972 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
1973 if (status != MODE_OK)
1974 return status;
1975 }
1976
1977 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
1978}
1979
1980bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1981 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1982{
1983 struct drm_atomic_state *state = crtc_state->uapi.state;
1984 struct drm_connector_state *connector_state;
1985 struct drm_connector *connector;
1986 int i;
1987
1988 if (crtc_state->pipe_bpp < bpc * 3)
1989 return false;
1990
1991 for_each_new_connector_in_state(state, connector, connector_state, i) {
1992 if (connector_state->crtc != crtc_state->uapi.crtc)
1993 continue;
1994
1995 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1996 return false;
1997 }
1998
1999 return true;
2000}
2001
2002static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2003 int bpc)
2004{
2005 struct drm_i915_private *dev_priv =
2006 to_i915(crtc_state->uapi.crtc->dev);
2007 const struct drm_display_mode *adjusted_mode =
2008 &crtc_state->hw.adjusted_mode;
2009
2010 /*
2011 * HDMI deep color affects the clocks, so it's only possible
2012 * when not cloning with other encoder types.
2013 */
2014 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2015 return false;
2016
2017 /* Display Wa_1405510057:icl,ehl */
2018 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2019 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2020 (adjusted_mode->crtc_hblank_end -
2021 adjusted_mode->crtc_hblank_start) % 8 == 2)
2022 return false;
2023
2024 return intel_hdmi_deep_color_possible(crtc_state, bpc,
2025 crtc_state->has_hdmi_sink,
2026 crtc_state->output_format ==
2027 INTEL_OUTPUT_FORMAT_YCBCR420);
2028}
2029
2030static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2031 struct intel_crtc_state *crtc_state,
2032 int clock)
2033{
2034 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2035 int bpc;
2036
2037 for (bpc = 12; bpc >= 10; bpc -= 2) {
2038 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2039 hdmi_port_clock_valid(intel_hdmi,
2040 intel_hdmi_port_clock(clock, bpc),
2041 true, crtc_state->has_hdmi_sink) == MODE_OK)
2042 return bpc;
2043 }
2044
2045 return 8;
2046}
2047
2048static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2049 struct intel_crtc_state *crtc_state)
2050{
2051 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2052 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2053 const struct drm_display_mode *adjusted_mode =
2054 &crtc_state->hw.adjusted_mode;
2055 int bpc, clock = adjusted_mode->crtc_clock;
2056
2057 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2058 clock *= 2;
2059
2060 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2061 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2062 clock /= 2;
2063
2064 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2065
2066 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2067
2068 /*
2069 * pipe_bpp could already be below 8bpc due to
2070 * FDI bandwidth constraints. We shouldn't bump it
2071 * back up to 8bpc in that case.
2072 */
2073 if (crtc_state->pipe_bpp > bpc * 3)
2074 crtc_state->pipe_bpp = bpc * 3;
2075
2076 drm_dbg_kms(&i915->drm,
2077 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2078 bpc, crtc_state->pipe_bpp);
2079
2080 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2081 false, crtc_state->has_hdmi_sink) != MODE_OK) {
2082 drm_dbg_kms(&i915->drm,
2083 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2084 crtc_state->port_clock);
2085 return -EINVAL;
2086 }
2087
2088 return 0;
2089}
2090
2091bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2092 const struct drm_connector_state *conn_state)
2093{
2094 const struct intel_digital_connector_state *intel_conn_state =
2095 to_intel_digital_connector_state(conn_state);
2096 const struct drm_display_mode *adjusted_mode =
2097 &crtc_state->hw.adjusted_mode;
2098
2099 /*
2100 * Our YCbCr output is always limited range.
2101 * crtc_state->limited_color_range only applies to RGB,
2102 * and it must never be set for YCbCr or we risk setting
2103 * some conflicting bits in PIPECONF which will mess up
2104 * the colors on the monitor.
2105 */
2106 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2107 return false;
2108
2109 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2110 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2111 return crtc_state->has_hdmi_sink &&
2112 drm_default_rgb_quant_range(adjusted_mode) ==
2113 HDMI_QUANTIZATION_RANGE_LIMITED;
2114 } else {
2115 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2116 }
2117}
2118
2119static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2120 const struct intel_crtc_state *crtc_state,
2121 const struct drm_connector_state *conn_state)
2122{
2123 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2124 const struct intel_digital_connector_state *intel_conn_state =
2125 to_intel_digital_connector_state(conn_state);
2126
2127 if (!crtc_state->has_hdmi_sink)
2128 return false;
2129
2130 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2131 return intel_hdmi->has_audio;
2132 else
2133 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2134}
2135
2136static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2137 struct intel_crtc_state *crtc_state,
2138 const struct drm_connector_state *conn_state)
2139{
2140 struct drm_connector *connector = conn_state->connector;
2141 struct drm_i915_private *i915 = to_i915(connector->dev);
2142 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2143 int ret;
2144 bool ycbcr_420_only;
2145
2146 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
2147 if (connector->ycbcr_420_allowed && ycbcr_420_only) {
2148 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2149 } else {
2150 if (!connector->ycbcr_420_allowed && ycbcr_420_only)
2151 drm_dbg_kms(&i915->drm,
2152 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2153 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2154 }
2155
2156 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2157 if (ret) {
2158 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
2159 connector->ycbcr_420_allowed &&
2160 drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
2161 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2162 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2163 }
2164 }
2165
2166 return ret;
2167}
2168
2169int intel_hdmi_compute_config(struct intel_encoder *encoder,
2170 struct intel_crtc_state *pipe_config,
2171 struct drm_connector_state *conn_state)
2172{
2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2175 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2176 struct drm_connector *connector = conn_state->connector;
2177 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2178 int ret;
2179
2180 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2181 return -EINVAL;
2182
2183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2184 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2185 conn_state);
2186
2187 if (pipe_config->has_hdmi_sink)
2188 pipe_config->has_infoframe = true;
2189
2190 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2191 pipe_config->pixel_multiplier = 2;
2192
2193 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2194 pipe_config->has_pch_encoder = true;
2195
2196 pipe_config->has_audio =
2197 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2198
2199 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
2200 if (ret)
2201 return ret;
2202
2203 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2204 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2205 if (ret)
2206 return ret;
2207 }
2208
2209 pipe_config->limited_color_range =
2210 intel_hdmi_limited_color_range(pipe_config, conn_state);
2211
2212 if (conn_state->picture_aspect_ratio)
2213 adjusted_mode->picture_aspect_ratio =
2214 conn_state->picture_aspect_ratio;
2215
2216 pipe_config->lane_count = 4;
2217
2218 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2219 if (scdc->scrambling.low_rates)
2220 pipe_config->hdmi_scrambling = true;
2221
2222 if (pipe_config->port_clock > 340000) {
2223 pipe_config->hdmi_scrambling = true;
2224 pipe_config->hdmi_high_tmds_clock_ratio = true;
2225 }
2226 }
2227
2228 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2229 conn_state);
2230
2231 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2232 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2233 return -EINVAL;
2234 }
2235
2236 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2237 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2238 return -EINVAL;
2239 }
2240
2241 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2242 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2243 return -EINVAL;
2244 }
2245
2246 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2247 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2248 return -EINVAL;
2249 }
2250
2251 return 0;
2252}
2253
2254static void
2255intel_hdmi_unset_edid(struct drm_connector *connector)
2256{
2257 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2258
2259 intel_hdmi->has_hdmi_sink = false;
2260 intel_hdmi->has_audio = false;
2261
2262 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2263 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2264
2265 kfree(to_intel_connector(connector)->detect_edid);
2266 to_intel_connector(connector)->detect_edid = NULL;
2267}
2268
2269static void
2270intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2271{
2272 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2273 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2274 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2275 struct i2c_adapter *adapter =
2276 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2277 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2278
2279 /*
2280 * Type 1 DVI adaptors are not required to implement any
2281 * registers, so we can't always detect their presence.
2282 * Ideally we should be able to check the state of the
2283 * CONFIG1 pin, but no such luck on our hardware.
2284 *
2285 * The only method left to us is to check the VBT to see
2286 * if the port is a dual mode capable DP port. But let's
2287 * only do that when we sucesfully read the EDID, to avoid
2288 * confusing log messages about DP dual mode adaptors when
2289 * there's nothing connected to the port.
2290 */
2291 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2292 /* An overridden EDID imply that we want this port for testing.
2293 * Make sure not to set limits for that port.
2294 */
2295 if (has_edid && !connector->override_edid &&
2296 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2297 drm_dbg_kms(&dev_priv->drm,
2298 "Assuming DP dual mode adaptor presence based on VBT\n");
2299 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2300 } else {
2301 type = DRM_DP_DUAL_MODE_NONE;
2302 }
2303 }
2304
2305 if (type == DRM_DP_DUAL_MODE_NONE)
2306 return;
2307
2308 hdmi->dp_dual_mode.type = type;
2309 hdmi->dp_dual_mode.max_tmds_clock =
2310 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2311
2312 drm_dbg_kms(&dev_priv->drm,
2313 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2314 drm_dp_get_dual_mode_type_name(type),
2315 hdmi->dp_dual_mode.max_tmds_clock);
2316}
2317
2318static bool
2319intel_hdmi_set_edid(struct drm_connector *connector)
2320{
2321 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2322 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2323 intel_wakeref_t wakeref;
2324 struct edid *edid;
2325 bool connected = false;
2326 struct i2c_adapter *i2c;
2327
2328 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2329
2330 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2331
2332 edid = drm_get_edid(connector, i2c);
2333
2334 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2335 drm_dbg_kms(&dev_priv->drm,
2336 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2337 intel_gmbus_force_bit(i2c, true);
2338 edid = drm_get_edid(connector, i2c);
2339 intel_gmbus_force_bit(i2c, false);
2340 }
2341
2342 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2343
2344 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2345
2346 to_intel_connector(connector)->detect_edid = edid;
2347 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2348 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2349 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2350
2351 connected = true;
2352 }
2353
2354 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2355
2356 return connected;
2357}
2358
2359static enum drm_connector_status
2360intel_hdmi_detect(struct drm_connector *connector, bool force)
2361{
2362 enum drm_connector_status status = connector_status_disconnected;
2363 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2364 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2365 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2366 intel_wakeref_t wakeref;
2367
2368 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2369 connector->base.id, connector->name);
2370
2371 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2372 return connector_status_disconnected;
2373
2374 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2375
2376 if (DISPLAY_VER(dev_priv) >= 11 &&
2377 !intel_digital_port_connected(encoder))
2378 goto out;
2379
2380 intel_hdmi_unset_edid(connector);
2381
2382 if (intel_hdmi_set_edid(connector))
2383 status = connector_status_connected;
2384
2385out:
2386 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2387
2388 if (status != connector_status_connected)
2389 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2390
2391 /*
2392 * Make sure the refs for power wells enabled during detect are
2393 * dropped to avoid a new detect cycle triggered by HPD polling.
2394 */
2395 intel_display_power_flush_work(dev_priv);
2396
2397 return status;
2398}
2399
2400static void
2401intel_hdmi_force(struct drm_connector *connector)
2402{
2403 struct drm_i915_private *i915 = to_i915(connector->dev);
2404
2405 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2406 connector->base.id, connector->name);
2407
2408 intel_hdmi_unset_edid(connector);
2409
2410 if (connector->status != connector_status_connected)
2411 return;
2412
2413 intel_hdmi_set_edid(connector);
2414}
2415
2416static int intel_hdmi_get_modes(struct drm_connector *connector)
2417{
2418 struct edid *edid;
2419
2420 edid = to_intel_connector(connector)->detect_edid;
2421 if (edid == NULL)
2422 return 0;
2423
2424 return intel_connector_update_modes(connector, edid);
2425}
2426
2427static struct i2c_adapter *
2428intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2429{
2430 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2431 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2432
2433 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2434}
2435
2436static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2437{
2438 struct drm_i915_private *i915 = to_i915(connector->dev);
2439 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2440 struct kobject *i2c_kobj = &adapter->dev.kobj;
2441 struct kobject *connector_kobj = &connector->kdev->kobj;
2442 int ret;
2443
2444 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2445 if (ret)
2446 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2447}
2448
2449static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2450{
2451 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2452 struct kobject *i2c_kobj = &adapter->dev.kobj;
2453 struct kobject *connector_kobj = &connector->kdev->kobj;
2454
2455 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2456}
2457
2458static int
2459intel_hdmi_connector_register(struct drm_connector *connector)
2460{
2461 int ret;
2462
2463 ret = intel_connector_register(connector);
2464 if (ret)
2465 return ret;
2466
2467 intel_hdmi_create_i2c_symlink(connector);
2468
2469 return ret;
2470}
2471
2472static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2473{
2474 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2475
2476 cec_notifier_conn_unregister(n);
2477
2478 intel_hdmi_remove_i2c_symlink(connector);
2479 intel_connector_unregister(connector);
2480}
2481
2482static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2483 .detect = intel_hdmi_detect,
2484 .force = intel_hdmi_force,
2485 .fill_modes = drm_helper_probe_single_connector_modes,
2486 .atomic_get_property = intel_digital_connector_atomic_get_property,
2487 .atomic_set_property = intel_digital_connector_atomic_set_property,
2488 .late_register = intel_hdmi_connector_register,
2489 .early_unregister = intel_hdmi_connector_unregister,
2490 .destroy = intel_connector_destroy,
2491 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2492 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2493};
2494
2495static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2496 .get_modes = intel_hdmi_get_modes,
2497 .mode_valid = intel_hdmi_mode_valid,
2498 .atomic_check = intel_digital_connector_atomic_check,
2499};
2500
2501static void
2502intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2503{
2504 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2505
2506 intel_attach_force_audio_property(connector);
2507 intel_attach_broadcast_rgb_property(connector);
2508 intel_attach_aspect_ratio_property(connector);
2509
2510 intel_attach_hdmi_colorspace_property(connector);
2511 drm_connector_attach_content_type_property(connector);
2512
2513 if (DISPLAY_VER(dev_priv) >= 10)
2514 drm_connector_attach_hdr_output_metadata_property(connector);
2515
2516 if (!HAS_GMCH(dev_priv))
2517 drm_connector_attach_max_bpc_property(connector, 8, 12);
2518}
2519
2520/*
2521 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2522 * @encoder: intel_encoder
2523 * @connector: drm_connector
2524 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2525 * or reset the high tmds clock ratio for scrambling
2526 * @scrambling: bool to Indicate if the function needs to set or reset
2527 * sink scrambling
2528 *
2529 * This function handles scrambling on HDMI 2.0 capable sinks.
2530 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2531 * it enables scrambling. This should be called before enabling the HDMI
2532 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2533 * detect a scrambled clock within 100 ms.
2534 *
2535 * Returns:
2536 * True on success, false on failure.
2537 */
2538bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2539 struct drm_connector *connector,
2540 bool high_tmds_clock_ratio,
2541 bool scrambling)
2542{
2543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2545 struct drm_scrambling *sink_scrambling =
2546 &connector->display_info.hdmi.scdc.scrambling;
2547 struct i2c_adapter *adapter =
2548 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2549
2550 if (!sink_scrambling->supported)
2551 return true;
2552
2553 drm_dbg_kms(&dev_priv->drm,
2554 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2555 connector->base.id, connector->name,
2556 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2557
2558 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2559 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2560 high_tmds_clock_ratio) &&
2561 drm_scdc_set_scrambling(adapter, scrambling);
2562}
2563
2564static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2565{
2566 u8 ddc_pin;
2567
2568 switch (port) {
2569 case PORT_B:
2570 ddc_pin = GMBUS_PIN_DPB;
2571 break;
2572 case PORT_C:
2573 ddc_pin = GMBUS_PIN_DPC;
2574 break;
2575 case PORT_D:
2576 ddc_pin = GMBUS_PIN_DPD_CHV;
2577 break;
2578 default:
2579 MISSING_CASE(port);
2580 ddc_pin = GMBUS_PIN_DPB;
2581 break;
2582 }
2583 return ddc_pin;
2584}
2585
2586static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2587{
2588 u8 ddc_pin;
2589
2590 switch (port) {
2591 case PORT_B:
2592 ddc_pin = GMBUS_PIN_1_BXT;
2593 break;
2594 case PORT_C:
2595 ddc_pin = GMBUS_PIN_2_BXT;
2596 break;
2597 default:
2598 MISSING_CASE(port);
2599 ddc_pin = GMBUS_PIN_1_BXT;
2600 break;
2601 }
2602 return ddc_pin;
2603}
2604
2605static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2606 enum port port)
2607{
2608 u8 ddc_pin;
2609
2610 switch (port) {
2611 case PORT_B:
2612 ddc_pin = GMBUS_PIN_1_BXT;
2613 break;
2614 case PORT_C:
2615 ddc_pin = GMBUS_PIN_2_BXT;
2616 break;
2617 case PORT_D:
2618 ddc_pin = GMBUS_PIN_4_CNP;
2619 break;
2620 case PORT_F:
2621 ddc_pin = GMBUS_PIN_3_BXT;
2622 break;
2623 default:
2624 MISSING_CASE(port);
2625 ddc_pin = GMBUS_PIN_1_BXT;
2626 break;
2627 }
2628 return ddc_pin;
2629}
2630
2631static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2632{
2633 enum phy phy = intel_port_to_phy(dev_priv, port);
2634
2635 if (intel_phy_is_combo(dev_priv, phy))
2636 return GMBUS_PIN_1_BXT + port;
2637 else if (intel_phy_is_tc(dev_priv, phy))
2638 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2639
2640 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2641 return GMBUS_PIN_2_BXT;
2642}
2643
2644static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2645{
2646 enum phy phy = intel_port_to_phy(dev_priv, port);
2647 u8 ddc_pin;
2648
2649 switch (phy) {
2650 case PHY_A:
2651 ddc_pin = GMBUS_PIN_1_BXT;
2652 break;
2653 case PHY_B:
2654 ddc_pin = GMBUS_PIN_2_BXT;
2655 break;
2656 case PHY_C:
2657 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2658 break;
2659 default:
2660 MISSING_CASE(phy);
2661 ddc_pin = GMBUS_PIN_1_BXT;
2662 break;
2663 }
2664 return ddc_pin;
2665}
2666
2667static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2668{
2669 enum phy phy = intel_port_to_phy(dev_priv, port);
2670
2671 WARN_ON(port == PORT_C);
2672
2673 /*
2674 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2675 * final two outputs use type-c pins, even though they're actually
2676 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2677 * all outputs.
2678 */
2679 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2680 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2681
2682 return GMBUS_PIN_1_BXT + phy;
2683}
2684
2685static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2686{
2687 enum phy phy = intel_port_to_phy(i915, port);
2688
2689 drm_WARN_ON(&i915->drm, port == PORT_A);
2690
2691 /*
2692 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2693 * final two outputs use type-c pins, even though they're actually
2694 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2695 * all outputs.
2696 */
2697 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2698 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2699
2700 return GMBUS_PIN_1_BXT + phy;
2701}
2702
2703static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2704{
2705 return intel_port_to_phy(dev_priv, port) + 1;
2706}
2707
2708static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2709{
2710 enum phy phy = intel_port_to_phy(dev_priv, port);
2711
2712 WARN_ON(port == PORT_B || port == PORT_C);
2713
2714 /*
2715 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2716 * except first combo output.
2717 */
2718 if (phy == PHY_A)
2719 return GMBUS_PIN_1_BXT;
2720
2721 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2722}
2723
2724static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2725 enum port port)
2726{
2727 u8 ddc_pin;
2728
2729 switch (port) {
2730 case PORT_B:
2731 ddc_pin = GMBUS_PIN_DPB;
2732 break;
2733 case PORT_C:
2734 ddc_pin = GMBUS_PIN_DPC;
2735 break;
2736 case PORT_D:
2737 ddc_pin = GMBUS_PIN_DPD;
2738 break;
2739 default:
2740 MISSING_CASE(port);
2741 ddc_pin = GMBUS_PIN_DPB;
2742 break;
2743 }
2744 return ddc_pin;
2745}
2746
2747static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2748{
2749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750 enum port port = encoder->port;
2751 u8 ddc_pin;
2752
2753 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2754 if (ddc_pin) {
2755 drm_dbg_kms(&dev_priv->drm,
2756 "Using DDC pin 0x%x for port %c (VBT)\n",
2757 ddc_pin, port_name(port));
2758 return ddc_pin;
2759 }
2760
2761 if (IS_ALDERLAKE_S(dev_priv))
2762 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2763 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2764 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2765 else if (IS_ROCKETLAKE(dev_priv))
2766 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2767 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2768 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2769 else if (HAS_PCH_MCC(dev_priv))
2770 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2771 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2772 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2773 else if (HAS_PCH_CNP(dev_priv))
2774 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2775 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2776 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2777 else if (IS_CHERRYVIEW(dev_priv))
2778 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2779 else
2780 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2781
2782 drm_dbg_kms(&dev_priv->drm,
2783 "Using DDC pin 0x%x for port %c (platform default)\n",
2784 ddc_pin, port_name(port));
2785
2786 return ddc_pin;
2787}
2788
2789void intel_infoframe_init(struct intel_digital_port *dig_port)
2790{
2791 struct drm_i915_private *dev_priv =
2792 to_i915(dig_port->base.base.dev);
2793
2794 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2795 dig_port->write_infoframe = vlv_write_infoframe;
2796 dig_port->read_infoframe = vlv_read_infoframe;
2797 dig_port->set_infoframes = vlv_set_infoframes;
2798 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2799 } else if (IS_G4X(dev_priv)) {
2800 dig_port->write_infoframe = g4x_write_infoframe;
2801 dig_port->read_infoframe = g4x_read_infoframe;
2802 dig_port->set_infoframes = g4x_set_infoframes;
2803 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2804 } else if (HAS_DDI(dev_priv)) {
2805 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2806 dig_port->write_infoframe = lspcon_write_infoframe;
2807 dig_port->read_infoframe = lspcon_read_infoframe;
2808 dig_port->set_infoframes = lspcon_set_infoframes;
2809 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2810 } else {
2811 dig_port->write_infoframe = hsw_write_infoframe;
2812 dig_port->read_infoframe = hsw_read_infoframe;
2813 dig_port->set_infoframes = hsw_set_infoframes;
2814 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2815 }
2816 } else if (HAS_PCH_IBX(dev_priv)) {
2817 dig_port->write_infoframe = ibx_write_infoframe;
2818 dig_port->read_infoframe = ibx_read_infoframe;
2819 dig_port->set_infoframes = ibx_set_infoframes;
2820 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2821 } else {
2822 dig_port->write_infoframe = cpt_write_infoframe;
2823 dig_port->read_infoframe = cpt_read_infoframe;
2824 dig_port->set_infoframes = cpt_set_infoframes;
2825 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2826 }
2827}
2828
2829void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2830 struct intel_connector *intel_connector)
2831{
2832 struct drm_connector *connector = &intel_connector->base;
2833 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2834 struct intel_encoder *intel_encoder = &dig_port->base;
2835 struct drm_device *dev = intel_encoder->base.dev;
2836 struct drm_i915_private *dev_priv = to_i915(dev);
2837 struct i2c_adapter *ddc;
2838 enum port port = intel_encoder->port;
2839 struct cec_connector_info conn_info;
2840
2841 drm_dbg_kms(&dev_priv->drm,
2842 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2843 intel_encoder->base.base.id, intel_encoder->base.name);
2844
2845 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2846 return;
2847
2848 if (drm_WARN(dev, dig_port->max_lanes < 4,
2849 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2850 dig_port->max_lanes, intel_encoder->base.base.id,
2851 intel_encoder->base.name))
2852 return;
2853
2854 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2855 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2856
2857 drm_connector_init_with_ddc(dev, connector,
2858 &intel_hdmi_connector_funcs,
2859 DRM_MODE_CONNECTOR_HDMIA,
2860 ddc);
2861 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2862
2863 connector->interlace_allowed = 1;
2864 connector->doublescan_allowed = 0;
2865 connector->stereo_allowed = 1;
2866
2867 if (DISPLAY_VER(dev_priv) >= 10)
2868 connector->ycbcr_420_allowed = true;
2869
2870 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2871
2872 if (HAS_DDI(dev_priv))
2873 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2874 else
2875 intel_connector->get_hw_state = intel_connector_get_hw_state;
2876
2877 intel_hdmi_add_properties(intel_hdmi, connector);
2878
2879 intel_connector_attach_encoder(intel_connector, intel_encoder);
2880 intel_hdmi->attached_connector = intel_connector;
2881
2882 if (is_hdcp_supported(dev_priv, port)) {
2883 int ret = intel_hdcp_init(intel_connector, dig_port,
2884 &intel_hdmi_hdcp_shim);
2885 if (ret)
2886 drm_dbg_kms(&dev_priv->drm,
2887 "HDCP init failed, skipping.\n");
2888 }
2889
2890 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2891 * 0xd. Failure to do so will result in spurious interrupts being
2892 * generated on the port when a cable is not attached.
2893 */
2894 if (IS_G45(dev_priv)) {
2895 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2896 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2897 (temp & ~0xf) | 0xd);
2898 }
2899
2900 cec_fill_conn_info_from_drm(&conn_info, connector);
2901
2902 intel_hdmi->cec_notifier =
2903 cec_notifier_conn_register(dev->dev, port_identifier(port),
2904 &conn_info);
2905 if (!intel_hdmi->cec_notifier)
2906 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2907}
2908
2909/*
2910 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2911 * @vactive: Vactive of a display mode
2912 *
2913 * @return: appropriate dsc slice height for a given mode.
2914 */
2915int intel_hdmi_dsc_get_slice_height(int vactive)
2916{
2917 int slice_height;
2918
2919 /*
2920 * Slice Height determination : HDMI2.1 Section 7.7.5.2
2921 * Select smallest slice height >=96, that results in a valid PPS and
2922 * requires minimum padding lines required for final slice.
2923 *
2924 * Assumption : Vactive is even.
2925 */
2926 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
2927 if (vactive % slice_height == 0)
2928 return slice_height;
2929
2930 return 0;
2931}
2932
2933/*
2934 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
2935 * and dsc decoder capabilities
2936 *
2937 * @crtc_state: intel crtc_state
2938 * @src_max_slices: maximum slices supported by the DSC encoder
2939 * @src_max_slice_width: maximum slice width supported by DSC encoder
2940 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
2941 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
2942 *
2943 * @return: num of dsc slices that can be supported by the dsc encoder
2944 * and decoder.
2945 */
2946int
2947intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
2948 int src_max_slices, int src_max_slice_width,
2949 int hdmi_max_slices, int hdmi_throughput)
2950{
2951/* Pixel rates in KPixels/sec */
2952#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
2953/*
2954 * Rates at which the source and sink are required to process pixels in each
2955 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
2956 */
2957#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
2958#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
2959
2960/* Spec limits the slice width to 2720 pixels */
2961#define MAX_HDMI_SLICE_WIDTH 2720
2962 int kslice_adjust;
2963 int adjusted_clk_khz;
2964 int min_slices;
2965 int target_slices;
2966 int max_throughput; /* max clock freq. in khz per slice */
2967 int max_slice_width;
2968 int slice_width;
2969 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
2970
2971 if (!hdmi_throughput)
2972 return 0;
2973
2974 /*
2975 * Slice Width determination : HDMI2.1 Section 7.7.5.1
2976 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
2977 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
2978 * dividing adjusted clock value by 10.
2979 */
2980 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
2981 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2982 kslice_adjust = 10;
2983 else
2984 kslice_adjust = 5;
2985
2986 /*
2987 * As per spec, the rate at which the source and the sink process
2988 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
2989 * This depends upon the pixel clock rate and output formats
2990 * (kslice adjust).
2991 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
2992 * at max 340MHz, otherwise they can be processed at max 400MHz.
2993 */
2994
2995 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
2996
2997 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
2998 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
2999 else
3000 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3001
3002 /*
3003 * Taking into account the sink's capability for maximum
3004 * clock per slice (in MHz) as read from HF-VSDB.
3005 */
3006 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3007
3008 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3009 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3010
3011 /*
3012 * Keep on increasing the num of slices/line, starting from min_slices
3013 * per line till we get such a number, for which the slice_width is
3014 * just less than max_slice_width. The slices/line selected should be
3015 * less than or equal to the max horizontal slices that the combination
3016 * of PCON encoder and HDMI decoder can support.
3017 */
3018 slice_width = max_slice_width;
3019
3020 do {
3021 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3022 target_slices = 1;
3023 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3024 target_slices = 2;
3025 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3026 target_slices = 4;
3027 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3028 target_slices = 8;
3029 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3030 target_slices = 12;
3031 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3032 target_slices = 16;
3033 else
3034 return 0;
3035
3036 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3037 if (slice_width >= max_slice_width)
3038 min_slices = target_slices + 1;
3039 } while (slice_width >= max_slice_width);
3040
3041 return target_slices;
3042}
3043
3044/*
3045 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3046 * source and sink capabilities.
3047 *
3048 * @src_fraction_bpp: fractional bpp supported by the source
3049 * @slice_width: dsc slice width supported by the source and sink
3050 * @num_slices: num of slices supported by the source and sink
3051 * @output_format: video output format
3052 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3053 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3054 *
3055 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3056 */
3057int
3058intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3059 int output_format, bool hdmi_all_bpp,
3060 int hdmi_max_chunk_bytes)
3061{
3062 int max_dsc_bpp, min_dsc_bpp;
3063 int target_bytes;
3064 bool bpp_found = false;
3065 int bpp_decrement_x16;
3066 int bpp_target;
3067 int bpp_target_x16;
3068
3069 /*
3070 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3071 * Start with the max bpp and keep on decrementing with
3072 * fractional bpp, if supported by PCON DSC encoder
3073 *
3074 * for each bpp we check if no of bytes can be supported by HDMI sink
3075 */
3076
3077 /* Assuming: bpc as 8*/
3078 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3079 min_dsc_bpp = 6;
3080 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3081 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3082 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3083 min_dsc_bpp = 8;
3084 max_dsc_bpp = 3 * 8; /* 3*bpc */
3085 } else {
3086 /* Assuming 4:2:2 encoding */
3087 min_dsc_bpp = 7;
3088 max_dsc_bpp = 2 * 8; /* 2*bpc */
3089 }
3090
3091 /*
3092 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3093 * Section 7.7.34 : Source shall not enable compressed Video
3094 * Transport with bpp_target settings above 12 bpp unless
3095 * DSC_all_bpp is set to 1.
3096 */
3097 if (!hdmi_all_bpp)
3098 max_dsc_bpp = min(max_dsc_bpp, 12);
3099
3100 /*
3101 * The Sink has a limit of compressed data in bytes for a scanline,
3102 * as described in max_chunk_bytes field in HFVSDB block of edid.
3103 * The no. of bytes depend on the target bits per pixel that the
3104 * source configures. So we start with the max_bpp and calculate
3105 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3106 * till we get the target_chunk_bytes just less than what the sink's
3107 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3108 *
3109 * The decrement is according to the fractional support from PCON DSC
3110 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3111 *
3112 * bpp_target_x16 = bpp_target * 16
3113 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3114 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3115 */
3116
3117 bpp_target = max_dsc_bpp;
3118
3119 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3120 if (!src_fractional_bpp)
3121 src_fractional_bpp = 1;
3122 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3123 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3124
3125 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3126 int bpp;
3127
3128 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3129 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3130 if (target_bytes <= hdmi_max_chunk_bytes) {
3131 bpp_found = true;
3132 break;
3133 }
3134 bpp_target_x16 -= bpp_decrement_x16;
3135 }
3136 if (bpp_found)
3137 return bpp_target_x16;
3138
3139 return 0;
3140}
1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/hdmi.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/string_helpers.h>
34
35#include <drm/display/drm_hdcp_helper.h>
36#include <drm/display/drm_hdmi_helper.h>
37#include <drm/display/drm_scdc_helper.h>
38#include <drm/drm_atomic_helper.h>
39#include <drm/drm_crtc.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/intel/intel_lpe_audio.h>
43
44#include <media/cec-notifier.h>
45
46#include "g4x_hdmi.h"
47#include "i915_drv.h"
48#include "i915_reg.h"
49#include "intel_atomic.h"
50#include "intel_audio.h"
51#include "intel_connector.h"
52#include "intel_cx0_phy.h"
53#include "intel_ddi.h"
54#include "intel_de.h"
55#include "intel_display_driver.h"
56#include "intel_display_types.h"
57#include "intel_dp.h"
58#include "intel_gmbus.h"
59#include "intel_hdcp.h"
60#include "intel_hdcp_regs.h"
61#include "intel_hdcp_shim.h"
62#include "intel_hdmi.h"
63#include "intel_lspcon.h"
64#include "intel_panel.h"
65#include "intel_pfit.h"
66#include "intel_snps_phy.h"
67
68static void
69assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
70{
71 struct intel_display *display = to_intel_display(intel_hdmi);
72 u32 enabled_bits;
73
74 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75
76 drm_WARN(display->drm,
77 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,
78 "HDMI port enabled, expecting disabled\n");
79}
80
81static void
82assert_hdmi_transcoder_func_disabled(struct intel_display *display,
83 enum transcoder cpu_transcoder)
84{
85 drm_WARN(display->drm,
86 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
87 TRANS_DDI_FUNC_ENABLE,
88 "HDMI transcoder function enabled, expecting disabled\n");
89}
90
91static u32 g4x_infoframe_index(unsigned int type)
92{
93 switch (type) {
94 case HDMI_PACKET_TYPE_GAMUT_METADATA:
95 return VIDEO_DIP_SELECT_GAMUT;
96 case HDMI_INFOFRAME_TYPE_AVI:
97 return VIDEO_DIP_SELECT_AVI;
98 case HDMI_INFOFRAME_TYPE_SPD:
99 return VIDEO_DIP_SELECT_SPD;
100 case HDMI_INFOFRAME_TYPE_VENDOR:
101 return VIDEO_DIP_SELECT_VENDOR;
102 default:
103 MISSING_CASE(type);
104 return 0;
105 }
106}
107
108static u32 g4x_infoframe_enable(unsigned int type)
109{
110 switch (type) {
111 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
112 return VIDEO_DIP_ENABLE_GCP;
113 case HDMI_PACKET_TYPE_GAMUT_METADATA:
114 return VIDEO_DIP_ENABLE_GAMUT;
115 case DP_SDP_VSC:
116 return 0;
117 case DP_SDP_ADAPTIVE_SYNC:
118 return 0;
119 case HDMI_INFOFRAME_TYPE_AVI:
120 return VIDEO_DIP_ENABLE_AVI;
121 case HDMI_INFOFRAME_TYPE_SPD:
122 return VIDEO_DIP_ENABLE_SPD;
123 case HDMI_INFOFRAME_TYPE_VENDOR:
124 return VIDEO_DIP_ENABLE_VENDOR;
125 case HDMI_INFOFRAME_TYPE_DRM:
126 return 0;
127 default:
128 MISSING_CASE(type);
129 return 0;
130 }
131}
132
133static u32 hsw_infoframe_enable(unsigned int type)
134{
135 switch (type) {
136 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
137 return VIDEO_DIP_ENABLE_GCP_HSW;
138 case HDMI_PACKET_TYPE_GAMUT_METADATA:
139 return VIDEO_DIP_ENABLE_GMP_HSW;
140 case DP_SDP_VSC:
141 return VIDEO_DIP_ENABLE_VSC_HSW;
142 case DP_SDP_ADAPTIVE_SYNC:
143 return VIDEO_DIP_ENABLE_AS_ADL;
144 case DP_SDP_PPS:
145 return VDIP_ENABLE_PPS;
146 case HDMI_INFOFRAME_TYPE_AVI:
147 return VIDEO_DIP_ENABLE_AVI_HSW;
148 case HDMI_INFOFRAME_TYPE_SPD:
149 return VIDEO_DIP_ENABLE_SPD_HSW;
150 case HDMI_INFOFRAME_TYPE_VENDOR:
151 return VIDEO_DIP_ENABLE_VS_HSW;
152 case HDMI_INFOFRAME_TYPE_DRM:
153 return VIDEO_DIP_ENABLE_DRM_GLK;
154 default:
155 MISSING_CASE(type);
156 return 0;
157 }
158}
159
160static i915_reg_t
161hsw_dip_data_reg(struct intel_display *display,
162 enum transcoder cpu_transcoder,
163 unsigned int type,
164 int i)
165{
166 switch (type) {
167 case HDMI_PACKET_TYPE_GAMUT_METADATA:
168 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i);
169 case DP_SDP_VSC:
170 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i);
171 case DP_SDP_ADAPTIVE_SYNC:
172 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i);
173 case DP_SDP_PPS:
174 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i);
175 case HDMI_INFOFRAME_TYPE_AVI:
176 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i);
177 case HDMI_INFOFRAME_TYPE_SPD:
178 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i);
179 case HDMI_INFOFRAME_TYPE_VENDOR:
180 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i);
181 case HDMI_INFOFRAME_TYPE_DRM:
182 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i);
183 default:
184 MISSING_CASE(type);
185 return INVALID_MMIO_REG;
186 }
187}
188
189static int hsw_dip_data_size(struct intel_display *display,
190 unsigned int type)
191{
192 switch (type) {
193 case DP_SDP_VSC:
194 return VIDEO_DIP_VSC_DATA_SIZE;
195 case DP_SDP_ADAPTIVE_SYNC:
196 return VIDEO_DIP_ASYNC_DATA_SIZE;
197 case DP_SDP_PPS:
198 return VIDEO_DIP_PPS_DATA_SIZE;
199 case HDMI_PACKET_TYPE_GAMUT_METADATA:
200 if (DISPLAY_VER(display) >= 11)
201 return VIDEO_DIP_GMP_DATA_SIZE;
202 else
203 return VIDEO_DIP_DATA_SIZE;
204 default:
205 return VIDEO_DIP_DATA_SIZE;
206 }
207}
208
209static void g4x_write_infoframe(struct intel_encoder *encoder,
210 const struct intel_crtc_state *crtc_state,
211 unsigned int type,
212 const void *frame, ssize_t len)
213{
214 struct intel_display *display = to_intel_display(encoder);
215 const u32 *data = frame;
216 u32 val = intel_de_read(display, VIDEO_DIP_CTL);
217 int i;
218
219 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
220 "Writing DIP with CTL reg disabled\n");
221
222 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
223 val |= g4x_infoframe_index(type);
224
225 val &= ~g4x_infoframe_enable(type);
226
227 intel_de_write(display, VIDEO_DIP_CTL, val);
228
229 for (i = 0; i < len; i += 4) {
230 intel_de_write(display, VIDEO_DIP_DATA, *data);
231 data++;
232 }
233 /* Write every possible data byte to force correct ECC calculation. */
234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
235 intel_de_write(display, VIDEO_DIP_DATA, 0);
236
237 val |= g4x_infoframe_enable(type);
238 val &= ~VIDEO_DIP_FREQ_MASK;
239 val |= VIDEO_DIP_FREQ_VSYNC;
240
241 intel_de_write(display, VIDEO_DIP_CTL, val);
242 intel_de_posting_read(display, VIDEO_DIP_CTL);
243}
244
245static void g4x_read_infoframe(struct intel_encoder *encoder,
246 const struct intel_crtc_state *crtc_state,
247 unsigned int type,
248 void *frame, ssize_t len)
249{
250 struct intel_display *display = to_intel_display(encoder);
251 u32 *data = frame;
252 int i;
253
254 intel_de_rmw(display, VIDEO_DIP_CTL,
255 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
256
257 for (i = 0; i < len; i += 4)
258 *data++ = intel_de_read(display, VIDEO_DIP_DATA);
259}
260
261static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
262 const struct intel_crtc_state *pipe_config)
263{
264 struct intel_display *display = to_intel_display(encoder);
265 u32 val = intel_de_read(display, VIDEO_DIP_CTL);
266
267 if ((val & VIDEO_DIP_ENABLE) == 0)
268 return 0;
269
270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
271 return 0;
272
273 return val & (VIDEO_DIP_ENABLE_AVI |
274 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
275}
276
277static void ibx_write_infoframe(struct intel_encoder *encoder,
278 const struct intel_crtc_state *crtc_state,
279 unsigned int type,
280 const void *frame, ssize_t len)
281{
282 struct intel_display *display = to_intel_display(encoder);
283 const u32 *data = frame;
284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
285 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
286 u32 val = intel_de_read(display, reg);
287 int i;
288
289 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
290 "Writing DIP with CTL reg disabled\n");
291
292 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
293 val |= g4x_infoframe_index(type);
294
295 val &= ~g4x_infoframe_enable(type);
296
297 intel_de_write(display, reg, val);
298
299 for (i = 0; i < len; i += 4) {
300 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
301 *data);
302 data++;
303 }
304 /* Write every possible data byte to force correct ECC calculation. */
305 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
306 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
307
308 val |= g4x_infoframe_enable(type);
309 val &= ~VIDEO_DIP_FREQ_MASK;
310 val |= VIDEO_DIP_FREQ_VSYNC;
311
312 intel_de_write(display, reg, val);
313 intel_de_posting_read(display, reg);
314}
315
316static void ibx_read_infoframe(struct intel_encoder *encoder,
317 const struct intel_crtc_state *crtc_state,
318 unsigned int type,
319 void *frame, ssize_t len)
320{
321 struct intel_display *display = to_intel_display(encoder);
322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
323 u32 *data = frame;
324 int i;
325
326 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
327 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
328
329 for (i = 0; i < len; i += 4)
330 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
331}
332
333static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
334 const struct intel_crtc_state *pipe_config)
335{
336 struct intel_display *display = to_intel_display(encoder);
337 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
339 u32 val = intel_de_read(display, reg);
340
341 if ((val & VIDEO_DIP_ENABLE) == 0)
342 return 0;
343
344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
345 return 0;
346
347 return val & (VIDEO_DIP_ENABLE_AVI |
348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
350}
351
352static void cpt_write_infoframe(struct intel_encoder *encoder,
353 const struct intel_crtc_state *crtc_state,
354 unsigned int type,
355 const void *frame, ssize_t len)
356{
357 struct intel_display *display = to_intel_display(encoder);
358 const u32 *data = frame;
359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
360 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
361 u32 val = intel_de_read(display, reg);
362 int i;
363
364 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
365 "Writing DIP with CTL reg disabled\n");
366
367 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
368 val |= g4x_infoframe_index(type);
369
370 /* The DIP control register spec says that we need to update the AVI
371 * infoframe without clearing its enable bit */
372 if (type != HDMI_INFOFRAME_TYPE_AVI)
373 val &= ~g4x_infoframe_enable(type);
374
375 intel_de_write(display, reg, val);
376
377 for (i = 0; i < len; i += 4) {
378 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
379 *data);
380 data++;
381 }
382 /* Write every possible data byte to force correct ECC calculation. */
383 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
384 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
385
386 val |= g4x_infoframe_enable(type);
387 val &= ~VIDEO_DIP_FREQ_MASK;
388 val |= VIDEO_DIP_FREQ_VSYNC;
389
390 intel_de_write(display, reg, val);
391 intel_de_posting_read(display, reg);
392}
393
394static void cpt_read_infoframe(struct intel_encoder *encoder,
395 const struct intel_crtc_state *crtc_state,
396 unsigned int type,
397 void *frame, ssize_t len)
398{
399 struct intel_display *display = to_intel_display(encoder);
400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
401 u32 *data = frame;
402 int i;
403
404 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
405 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
406
407 for (i = 0; i < len; i += 4)
408 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
409}
410
411static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
412 const struct intel_crtc_state *pipe_config)
413{
414 struct intel_display *display = to_intel_display(encoder);
415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
416 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));
417
418 if ((val & VIDEO_DIP_ENABLE) == 0)
419 return 0;
420
421 return val & (VIDEO_DIP_ENABLE_AVI |
422 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
423 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
424}
425
426static void vlv_write_infoframe(struct intel_encoder *encoder,
427 const struct intel_crtc_state *crtc_state,
428 unsigned int type,
429 const void *frame, ssize_t len)
430{
431 struct intel_display *display = to_intel_display(encoder);
432 const u32 *data = frame;
433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
434 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
435 u32 val = intel_de_read(display, reg);
436 int i;
437
438 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
439 "Writing DIP with CTL reg disabled\n");
440
441 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
442 val |= g4x_infoframe_index(type);
443
444 val &= ~g4x_infoframe_enable(type);
445
446 intel_de_write(display, reg, val);
447
448 for (i = 0; i < len; i += 4) {
449 intel_de_write(display,
450 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
451 data++;
452 }
453 /* Write every possible data byte to force correct ECC calculation. */
454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
455 intel_de_write(display,
456 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
457
458 val |= g4x_infoframe_enable(type);
459 val &= ~VIDEO_DIP_FREQ_MASK;
460 val |= VIDEO_DIP_FREQ_VSYNC;
461
462 intel_de_write(display, reg, val);
463 intel_de_posting_read(display, reg);
464}
465
466static void vlv_read_infoframe(struct intel_encoder *encoder,
467 const struct intel_crtc_state *crtc_state,
468 unsigned int type,
469 void *frame, ssize_t len)
470{
471 struct intel_display *display = to_intel_display(encoder);
472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
473 u32 *data = frame;
474 int i;
475
476 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),
477 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
478
479 for (i = 0; i < len; i += 4)
480 *data++ = intel_de_read(display,
481 VLV_TVIDEO_DIP_DATA(crtc->pipe));
482}
483
484static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
485 const struct intel_crtc_state *pipe_config)
486{
487 struct intel_display *display = to_intel_display(encoder);
488 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
489 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));
490
491 if ((val & VIDEO_DIP_ENABLE) == 0)
492 return 0;
493
494 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
495 return 0;
496
497 return val & (VIDEO_DIP_ENABLE_AVI |
498 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
499 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
500}
501
502void hsw_write_infoframe(struct intel_encoder *encoder,
503 const struct intel_crtc_state *crtc_state,
504 unsigned int type,
505 const void *frame, ssize_t len)
506{
507 struct intel_display *display = to_intel_display(encoder);
508 const u32 *data = frame;
509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
510 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
511 int data_size;
512 int i;
513 u32 val = intel_de_read(display, ctl_reg);
514
515 data_size = hsw_dip_data_size(display, type);
516
517 drm_WARN_ON(display->drm, len > data_size);
518
519 val &= ~hsw_infoframe_enable(type);
520 intel_de_write(display, ctl_reg, val);
521
522 for (i = 0; i < len; i += 4) {
523 intel_de_write(display,
524 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
525 *data);
526 data++;
527 }
528 /* Write every possible data byte to force correct ECC calculation. */
529 for (; i < data_size; i += 4)
530 intel_de_write(display,
531 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
532 0);
533
534 /* Wa_14013475917 */
535 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
536 !crtc_state->has_panel_replay && type == DP_SDP_VSC))
537 val |= hsw_infoframe_enable(type);
538
539 if (type == DP_SDP_VSC)
540 val |= VSC_DIP_HW_DATA_SW_HEA;
541
542 intel_de_write(display, ctl_reg, val);
543 intel_de_posting_read(display, ctl_reg);
544}
545
546void hsw_read_infoframe(struct intel_encoder *encoder,
547 const struct intel_crtc_state *crtc_state,
548 unsigned int type, void *frame, ssize_t len)
549{
550 struct intel_display *display = to_intel_display(encoder);
551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
552 u32 *data = frame;
553 int i;
554
555 for (i = 0; i < len; i += 4)
556 *data++ = intel_de_read(display,
557 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2));
558}
559
560static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
561 const struct intel_crtc_state *pipe_config)
562{
563 struct intel_display *display = to_intel_display(encoder);
564 u32 val = intel_de_read(display,
565 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
566 u32 mask;
567
568 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
569 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
570 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
571
572 if (DISPLAY_VER(display) >= 10)
573 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
574
575 if (HAS_AS_SDP(display))
576 mask |= VIDEO_DIP_ENABLE_AS_ADL;
577
578 return val & mask;
579}
580
581static const u8 infoframe_type_to_idx[] = {
582 HDMI_PACKET_TYPE_GENERAL_CONTROL,
583 HDMI_PACKET_TYPE_GAMUT_METADATA,
584 DP_SDP_VSC,
585 DP_SDP_ADAPTIVE_SYNC,
586 HDMI_INFOFRAME_TYPE_AVI,
587 HDMI_INFOFRAME_TYPE_SPD,
588 HDMI_INFOFRAME_TYPE_VENDOR,
589 HDMI_INFOFRAME_TYPE_DRM,
590};
591
592u32 intel_hdmi_infoframe_enable(unsigned int type)
593{
594 int i;
595
596 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
597 if (infoframe_type_to_idx[i] == type)
598 return BIT(i);
599 }
600
601 return 0;
602}
603
604u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
605 const struct intel_crtc_state *crtc_state)
606{
607 struct intel_display *display = to_intel_display(encoder);
608 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
609 u32 val, ret = 0;
610 int i;
611
612 val = dig_port->infoframes_enabled(encoder, crtc_state);
613
614 /* map from hardware bits to dip idx */
615 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
616 unsigned int type = infoframe_type_to_idx[i];
617
618 if (HAS_DDI(display)) {
619 if (val & hsw_infoframe_enable(type))
620 ret |= BIT(i);
621 } else {
622 if (val & g4x_infoframe_enable(type))
623 ret |= BIT(i);
624 }
625 }
626
627 return ret;
628}
629
630/*
631 * The data we write to the DIP data buffer registers is 1 byte bigger than the
632 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
633 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
634 * used for both technologies.
635 *
636 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
637 * DW1: DB3 | DB2 | DB1 | DB0
638 * DW2: DB7 | DB6 | DB5 | DB4
639 * DW3: ...
640 *
641 * (HB is Header Byte, DB is Data Byte)
642 *
643 * The hdmi pack() functions don't know about that hardware specific hole so we
644 * trick them by giving an offset into the buffer and moving back the header
645 * bytes by one.
646 */
647static void intel_write_infoframe(struct intel_encoder *encoder,
648 const struct intel_crtc_state *crtc_state,
649 enum hdmi_infoframe_type type,
650 const union hdmi_infoframe *frame)
651{
652 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
653 u8 buffer[VIDEO_DIP_DATA_SIZE];
654 ssize_t len;
655
656 if ((crtc_state->infoframes.enable &
657 intel_hdmi_infoframe_enable(type)) == 0)
658 return;
659
660 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
661 return;
662
663 /* see comment above for the reason for this offset */
664 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
665 if (drm_WARN_ON(encoder->base.dev, len < 0))
666 return;
667
668 /* Insert the 'hole' (see big comment above) at position 3 */
669 memmove(&buffer[0], &buffer[1], 3);
670 buffer[3] = 0;
671 len++;
672
673 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
674}
675
676void intel_read_infoframe(struct intel_encoder *encoder,
677 const struct intel_crtc_state *crtc_state,
678 enum hdmi_infoframe_type type,
679 union hdmi_infoframe *frame)
680{
681 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
682 u8 buffer[VIDEO_DIP_DATA_SIZE];
683 int ret;
684
685 if ((crtc_state->infoframes.enable &
686 intel_hdmi_infoframe_enable(type)) == 0)
687 return;
688
689 dig_port->read_infoframe(encoder, crtc_state,
690 type, buffer, sizeof(buffer));
691
692 /* Fill the 'hole' (see big comment above) at position 3 */
693 memmove(&buffer[1], &buffer[0], 3);
694
695 /* see comment above for the reason for this offset */
696 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
697 if (ret) {
698 drm_dbg_kms(encoder->base.dev,
699 "Failed to unpack infoframe type 0x%02x\n", type);
700 return;
701 }
702
703 if (frame->any.type != type)
704 drm_dbg_kms(encoder->base.dev,
705 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
706 frame->any.type, type);
707}
708
709static bool
710intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
711 struct intel_crtc_state *crtc_state,
712 struct drm_connector_state *conn_state)
713{
714 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
715 const struct drm_display_mode *adjusted_mode =
716 &crtc_state->hw.adjusted_mode;
717 struct drm_connector *connector = conn_state->connector;
718 int ret;
719
720 if (!crtc_state->has_infoframe)
721 return true;
722
723 crtc_state->infoframes.enable |=
724 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
725
726 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
727 adjusted_mode);
728 if (ret)
729 return false;
730
731 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
732 frame->colorspace = HDMI_COLORSPACE_YUV420;
733 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
734 frame->colorspace = HDMI_COLORSPACE_YUV444;
735 else
736 frame->colorspace = HDMI_COLORSPACE_RGB;
737
738 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
739
740 /* nonsense combination */
741 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
742 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
743
744 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
745 drm_hdmi_avi_infoframe_quant_range(frame, connector,
746 adjusted_mode,
747 crtc_state->limited_color_range ?
748 HDMI_QUANTIZATION_RANGE_LIMITED :
749 HDMI_QUANTIZATION_RANGE_FULL);
750 } else {
751 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
752 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
753 }
754
755 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
756
757 /* TODO: handle pixel repetition for YCBCR420 outputs */
758
759 ret = hdmi_avi_infoframe_check(frame);
760 if (drm_WARN_ON(encoder->base.dev, ret))
761 return false;
762
763 return true;
764}
765
766static bool
767intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
768 struct intel_crtc_state *crtc_state,
769 struct drm_connector_state *conn_state)
770{
771 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
772 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
773 int ret;
774
775 if (!crtc_state->has_infoframe)
776 return true;
777
778 crtc_state->infoframes.enable |=
779 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
780
781 if (IS_DGFX(i915))
782 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
783 else
784 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
785
786 if (drm_WARN_ON(encoder->base.dev, ret))
787 return false;
788
789 frame->sdi = HDMI_SPD_SDI_PC;
790
791 ret = hdmi_spd_infoframe_check(frame);
792 if (drm_WARN_ON(encoder->base.dev, ret))
793 return false;
794
795 return true;
796}
797
798static bool
799intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
800 struct intel_crtc_state *crtc_state,
801 struct drm_connector_state *conn_state)
802{
803 struct hdmi_vendor_infoframe *frame =
804 &crtc_state->infoframes.hdmi.vendor.hdmi;
805 const struct drm_display_info *info =
806 &conn_state->connector->display_info;
807 int ret;
808
809 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
810 return true;
811
812 crtc_state->infoframes.enable |=
813 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
814
815 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
816 conn_state->connector,
817 &crtc_state->hw.adjusted_mode);
818 if (drm_WARN_ON(encoder->base.dev, ret))
819 return false;
820
821 ret = hdmi_vendor_infoframe_check(frame);
822 if (drm_WARN_ON(encoder->base.dev, ret))
823 return false;
824
825 return true;
826}
827
828static bool
829intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
830 struct intel_crtc_state *crtc_state,
831 struct drm_connector_state *conn_state)
832{
833 struct intel_display *display = to_intel_display(encoder);
834 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
835 int ret;
836
837 if (DISPLAY_VER(display) < 10)
838 return true;
839
840 if (!crtc_state->has_infoframe)
841 return true;
842
843 if (!conn_state->hdr_output_metadata)
844 return true;
845
846 crtc_state->infoframes.enable |=
847 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
848
849 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
850 if (ret < 0) {
851 drm_dbg_kms(display->drm,
852 "couldn't set HDR metadata in infoframe\n");
853 return false;
854 }
855
856 ret = hdmi_drm_infoframe_check(frame);
857 if (drm_WARN_ON(display->drm, ret))
858 return false;
859
860 return true;
861}
862
863static void g4x_set_infoframes(struct intel_encoder *encoder,
864 bool enable,
865 const struct intel_crtc_state *crtc_state,
866 const struct drm_connector_state *conn_state)
867{
868 struct intel_display *display = to_intel_display(encoder);
869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
870 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
871 i915_reg_t reg = VIDEO_DIP_CTL;
872 u32 val = intel_de_read(display, reg);
873 u32 port = VIDEO_DIP_PORT(encoder->port);
874
875 assert_hdmi_port_disabled(intel_hdmi);
876
877 /* If the registers were not initialized yet, they might be zeroes,
878 * which means we're selecting the AVI DIP and we're setting its
879 * frequency to once. This seems to really confuse the HW and make
880 * things stop working (the register spec says the AVI always needs to
881 * be sent every VSync). So here we avoid writing to the register more
882 * than we need and also explicitly select the AVI DIP and explicitly
883 * set its frequency to every VSync. Avoiding to write it twice seems to
884 * be enough to solve the problem, but being defensive shouldn't hurt us
885 * either. */
886 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
887
888 if (!enable) {
889 if (!(val & VIDEO_DIP_ENABLE))
890 return;
891 if (port != (val & VIDEO_DIP_PORT_MASK)) {
892 drm_dbg_kms(display->drm,
893 "video DIP still enabled on port %c\n",
894 (val & VIDEO_DIP_PORT_MASK) >> 29);
895 return;
896 }
897 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
898 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
899 intel_de_write(display, reg, val);
900 intel_de_posting_read(display, reg);
901 return;
902 }
903
904 if (port != (val & VIDEO_DIP_PORT_MASK)) {
905 if (val & VIDEO_DIP_ENABLE) {
906 drm_dbg_kms(display->drm,
907 "video DIP already enabled on port %c\n",
908 (val & VIDEO_DIP_PORT_MASK) >> 29);
909 return;
910 }
911 val &= ~VIDEO_DIP_PORT_MASK;
912 val |= port;
913 }
914
915 val |= VIDEO_DIP_ENABLE;
916 val &= ~(VIDEO_DIP_ENABLE_AVI |
917 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
918
919 intel_de_write(display, reg, val);
920 intel_de_posting_read(display, reg);
921
922 intel_write_infoframe(encoder, crtc_state,
923 HDMI_INFOFRAME_TYPE_AVI,
924 &crtc_state->infoframes.avi);
925 intel_write_infoframe(encoder, crtc_state,
926 HDMI_INFOFRAME_TYPE_SPD,
927 &crtc_state->infoframes.spd);
928 intel_write_infoframe(encoder, crtc_state,
929 HDMI_INFOFRAME_TYPE_VENDOR,
930 &crtc_state->infoframes.hdmi);
931}
932
933/*
934 * Determine if default_phase=1 can be indicated in the GCP infoframe.
935 *
936 * From HDMI specification 1.4a:
937 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
938 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
939 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
940 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
941 * phase of 0
942 */
943static bool gcp_default_phase_possible(int pipe_bpp,
944 const struct drm_display_mode *mode)
945{
946 unsigned int pixels_per_group;
947
948 switch (pipe_bpp) {
949 case 30:
950 /* 4 pixels in 5 clocks */
951 pixels_per_group = 4;
952 break;
953 case 36:
954 /* 2 pixels in 3 clocks */
955 pixels_per_group = 2;
956 break;
957 case 48:
958 /* 1 pixel in 2 clocks */
959 pixels_per_group = 1;
960 break;
961 default:
962 /* phase information not relevant for 8bpc */
963 return false;
964 }
965
966 return mode->crtc_hdisplay % pixels_per_group == 0 &&
967 mode->crtc_htotal % pixels_per_group == 0 &&
968 mode->crtc_hblank_start % pixels_per_group == 0 &&
969 mode->crtc_hblank_end % pixels_per_group == 0 &&
970 mode->crtc_hsync_start % pixels_per_group == 0 &&
971 mode->crtc_hsync_end % pixels_per_group == 0 &&
972 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
973 mode->crtc_htotal/2 % pixels_per_group == 0);
974}
975
976static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
977 const struct intel_crtc_state *crtc_state,
978 const struct drm_connector_state *conn_state)
979{
980 struct intel_display *display = to_intel_display(encoder);
981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 i915_reg_t reg;
984
985 if ((crtc_state->infoframes.enable &
986 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
987 return false;
988
989 if (HAS_DDI(display))
990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
991 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
992 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
993 else if (HAS_PCH_SPLIT(dev_priv))
994 reg = TVIDEO_DIP_GCP(crtc->pipe);
995 else
996 return false;
997
998 intel_de_write(display, reg, crtc_state->infoframes.gcp);
999
1000 return true;
1001}
1002
1003void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1004 struct intel_crtc_state *crtc_state)
1005{
1006 struct intel_display *display = to_intel_display(encoder);
1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1009 i915_reg_t reg;
1010
1011 if ((crtc_state->infoframes.enable &
1012 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1013 return;
1014
1015 if (HAS_DDI(display))
1016 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
1017 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1018 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1019 else if (HAS_PCH_SPLIT(dev_priv))
1020 reg = TVIDEO_DIP_GCP(crtc->pipe);
1021 else
1022 return;
1023
1024 crtc_state->infoframes.gcp = intel_de_read(display, reg);
1025}
1026
1027static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1028 struct intel_crtc_state *crtc_state,
1029 struct drm_connector_state *conn_state)
1030{
1031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1032
1033 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1034 return;
1035
1036 crtc_state->infoframes.enable |=
1037 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1038
1039 /* Indicate color indication for deep color mode */
1040 if (crtc_state->pipe_bpp > 24)
1041 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1042
1043 /* Enable default_phase whenever the display mode is suitably aligned */
1044 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1045 &crtc_state->hw.adjusted_mode))
1046 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1047}
1048
1049static void ibx_set_infoframes(struct intel_encoder *encoder,
1050 bool enable,
1051 const struct intel_crtc_state *crtc_state,
1052 const struct drm_connector_state *conn_state)
1053{
1054 struct intel_display *display = to_intel_display(encoder);
1055 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1056 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1057 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1058 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1059 u32 val = intel_de_read(display, reg);
1060 u32 port = VIDEO_DIP_PORT(encoder->port);
1061
1062 assert_hdmi_port_disabled(intel_hdmi);
1063
1064 /* See the big comment in g4x_set_infoframes() */
1065 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1066
1067 if (!enable) {
1068 if (!(val & VIDEO_DIP_ENABLE))
1069 return;
1070 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1071 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1072 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1073 intel_de_write(display, reg, val);
1074 intel_de_posting_read(display, reg);
1075 return;
1076 }
1077
1078 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1079 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
1080 "DIP already enabled on port %c\n",
1081 (val & VIDEO_DIP_PORT_MASK) >> 29);
1082 val &= ~VIDEO_DIP_PORT_MASK;
1083 val |= port;
1084 }
1085
1086 val |= VIDEO_DIP_ENABLE;
1087 val &= ~(VIDEO_DIP_ENABLE_AVI |
1088 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1089 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1090
1091 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1092 val |= VIDEO_DIP_ENABLE_GCP;
1093
1094 intel_de_write(display, reg, val);
1095 intel_de_posting_read(display, reg);
1096
1097 intel_write_infoframe(encoder, crtc_state,
1098 HDMI_INFOFRAME_TYPE_AVI,
1099 &crtc_state->infoframes.avi);
1100 intel_write_infoframe(encoder, crtc_state,
1101 HDMI_INFOFRAME_TYPE_SPD,
1102 &crtc_state->infoframes.spd);
1103 intel_write_infoframe(encoder, crtc_state,
1104 HDMI_INFOFRAME_TYPE_VENDOR,
1105 &crtc_state->infoframes.hdmi);
1106}
1107
1108static void cpt_set_infoframes(struct intel_encoder *encoder,
1109 bool enable,
1110 const struct intel_crtc_state *crtc_state,
1111 const struct drm_connector_state *conn_state)
1112{
1113 struct intel_display *display = to_intel_display(encoder);
1114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1115 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1116 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1117 u32 val = intel_de_read(display, reg);
1118
1119 assert_hdmi_port_disabled(intel_hdmi);
1120
1121 /* See the big comment in g4x_set_infoframes() */
1122 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1123
1124 if (!enable) {
1125 if (!(val & VIDEO_DIP_ENABLE))
1126 return;
1127 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1128 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1129 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1130 intel_de_write(display, reg, val);
1131 intel_de_posting_read(display, reg);
1132 return;
1133 }
1134
1135 /* Set both together, unset both together: see the spec. */
1136 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1137 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1138 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1139
1140 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1141 val |= VIDEO_DIP_ENABLE_GCP;
1142
1143 intel_de_write(display, reg, val);
1144 intel_de_posting_read(display, reg);
1145
1146 intel_write_infoframe(encoder, crtc_state,
1147 HDMI_INFOFRAME_TYPE_AVI,
1148 &crtc_state->infoframes.avi);
1149 intel_write_infoframe(encoder, crtc_state,
1150 HDMI_INFOFRAME_TYPE_SPD,
1151 &crtc_state->infoframes.spd);
1152 intel_write_infoframe(encoder, crtc_state,
1153 HDMI_INFOFRAME_TYPE_VENDOR,
1154 &crtc_state->infoframes.hdmi);
1155}
1156
1157static void vlv_set_infoframes(struct intel_encoder *encoder,
1158 bool enable,
1159 const struct intel_crtc_state *crtc_state,
1160 const struct drm_connector_state *conn_state)
1161{
1162 struct intel_display *display = to_intel_display(encoder);
1163 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1164 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1165 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1166 u32 val = intel_de_read(display, reg);
1167 u32 port = VIDEO_DIP_PORT(encoder->port);
1168
1169 assert_hdmi_port_disabled(intel_hdmi);
1170
1171 /* See the big comment in g4x_set_infoframes() */
1172 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1173
1174 if (!enable) {
1175 if (!(val & VIDEO_DIP_ENABLE))
1176 return;
1177 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1178 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1179 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1180 intel_de_write(display, reg, val);
1181 intel_de_posting_read(display, reg);
1182 return;
1183 }
1184
1185 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1186 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
1187 "DIP already enabled on port %c\n",
1188 (val & VIDEO_DIP_PORT_MASK) >> 29);
1189 val &= ~VIDEO_DIP_PORT_MASK;
1190 val |= port;
1191 }
1192
1193 val |= VIDEO_DIP_ENABLE;
1194 val &= ~(VIDEO_DIP_ENABLE_AVI |
1195 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1196 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1197
1198 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1199 val |= VIDEO_DIP_ENABLE_GCP;
1200
1201 intel_de_write(display, reg, val);
1202 intel_de_posting_read(display, reg);
1203
1204 intel_write_infoframe(encoder, crtc_state,
1205 HDMI_INFOFRAME_TYPE_AVI,
1206 &crtc_state->infoframes.avi);
1207 intel_write_infoframe(encoder, crtc_state,
1208 HDMI_INFOFRAME_TYPE_SPD,
1209 &crtc_state->infoframes.spd);
1210 intel_write_infoframe(encoder, crtc_state,
1211 HDMI_INFOFRAME_TYPE_VENDOR,
1212 &crtc_state->infoframes.hdmi);
1213}
1214
1215void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
1216 const struct intel_crtc_state *crtc_state,
1217 const struct drm_connector_state *conn_state)
1218{
1219 struct intel_display *display = to_intel_display(encoder);
1220 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
1221 crtc_state->cpu_transcoder);
1222 u32 val = intel_de_read(display, reg);
1223
1224 if ((crtc_state->infoframes.enable &
1225 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 &&
1226 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0)
1227 return;
1228
1229 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK);
1230
1231 intel_de_write(display, reg, val);
1232 intel_de_posting_read(display, reg);
1233
1234 intel_write_infoframe(encoder, crtc_state,
1235 HDMI_INFOFRAME_TYPE_DRM,
1236 &crtc_state->infoframes.drm);
1237}
1238
1239static void hsw_set_infoframes(struct intel_encoder *encoder,
1240 bool enable,
1241 const struct intel_crtc_state *crtc_state,
1242 const struct drm_connector_state *conn_state)
1243{
1244 struct intel_display *display = to_intel_display(encoder);
1245 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
1246 crtc_state->cpu_transcoder);
1247 u32 val = intel_de_read(display, reg);
1248
1249 assert_hdmi_transcoder_func_disabled(display,
1250 crtc_state->cpu_transcoder);
1251
1252 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1253 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1254 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1255 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL);
1256
1257 if (!enable) {
1258 intel_de_write(display, reg, val);
1259 intel_de_posting_read(display, reg);
1260 return;
1261 }
1262
1263 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1264 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1265
1266 intel_de_write(display, reg, val);
1267 intel_de_posting_read(display, reg);
1268
1269 intel_write_infoframe(encoder, crtc_state,
1270 HDMI_INFOFRAME_TYPE_AVI,
1271 &crtc_state->infoframes.avi);
1272 intel_write_infoframe(encoder, crtc_state,
1273 HDMI_INFOFRAME_TYPE_SPD,
1274 &crtc_state->infoframes.spd);
1275 intel_write_infoframe(encoder, crtc_state,
1276 HDMI_INFOFRAME_TYPE_VENDOR,
1277 &crtc_state->infoframes.hdmi);
1278 intel_write_infoframe(encoder, crtc_state,
1279 HDMI_INFOFRAME_TYPE_DRM,
1280 &crtc_state->infoframes.drm);
1281}
1282
1283void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1284{
1285 struct intel_display *display = to_intel_display(hdmi);
1286 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1287
1288 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1289 return;
1290
1291 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",
1292 enable ? "Enabling" : "Disabling");
1293
1294 drm_dp_dual_mode_set_tmds_output(display->drm,
1295 hdmi->dp_dual_mode.type, ddc, enable);
1296}
1297
1298static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1299 unsigned int offset, void *buffer, size_t size)
1300{
1301 struct intel_hdmi *hdmi = &dig_port->hdmi;
1302 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1303 int ret;
1304 u8 start = offset & 0xff;
1305 struct i2c_msg msgs[] = {
1306 {
1307 .addr = DRM_HDCP_DDC_ADDR,
1308 .flags = 0,
1309 .len = 1,
1310 .buf = &start,
1311 },
1312 {
1313 .addr = DRM_HDCP_DDC_ADDR,
1314 .flags = I2C_M_RD,
1315 .len = size,
1316 .buf = buffer
1317 }
1318 };
1319 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));
1320 if (ret == ARRAY_SIZE(msgs))
1321 return 0;
1322 return ret >= 0 ? -EIO : ret;
1323}
1324
1325static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1326 unsigned int offset, void *buffer, size_t size)
1327{
1328 struct intel_hdmi *hdmi = &dig_port->hdmi;
1329 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1330 int ret;
1331 u8 *write_buf;
1332 struct i2c_msg msg;
1333
1334 write_buf = kzalloc(size + 1, GFP_KERNEL);
1335 if (!write_buf)
1336 return -ENOMEM;
1337
1338 write_buf[0] = offset & 0xff;
1339 memcpy(&write_buf[1], buffer, size);
1340
1341 msg.addr = DRM_HDCP_DDC_ADDR;
1342 msg.flags = 0;
1343 msg.len = size + 1;
1344 msg.buf = write_buf;
1345
1346 ret = i2c_transfer(ddc, &msg, 1);
1347 if (ret == 1)
1348 ret = 0;
1349 else if (ret >= 0)
1350 ret = -EIO;
1351
1352 kfree(write_buf);
1353 return ret;
1354}
1355
1356static
1357int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1358 u8 *an)
1359{
1360 struct intel_display *display = to_intel_display(dig_port);
1361 struct intel_hdmi *hdmi = &dig_port->hdmi;
1362 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1363 int ret;
1364
1365 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1366 DRM_HDCP_AN_LEN);
1367 if (ret) {
1368 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",
1369 ret);
1370 return ret;
1371 }
1372
1373 ret = intel_gmbus_output_aksv(ddc);
1374 if (ret < 0) {
1375 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);
1376 return ret;
1377 }
1378 return 0;
1379}
1380
1381static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1382 u8 *bksv)
1383{
1384 struct intel_display *display = to_intel_display(dig_port);
1385
1386 int ret;
1387 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1388 DRM_HDCP_KSV_LEN);
1389 if (ret)
1390 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",
1391 ret);
1392 return ret;
1393}
1394
1395static
1396int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1397 u8 *bstatus)
1398{
1399 struct intel_display *display = to_intel_display(dig_port);
1400
1401 int ret;
1402 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1403 bstatus, DRM_HDCP_BSTATUS_LEN);
1404 if (ret)
1405 drm_dbg_kms(display->drm,
1406 "Read bstatus over DDC failed (%d)\n",
1407 ret);
1408 return ret;
1409}
1410
1411static
1412int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1413 bool *repeater_present)
1414{
1415 struct intel_display *display = to_intel_display(dig_port);
1416 int ret;
1417 u8 val;
1418
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1420 if (ret) {
1421 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
1422 ret);
1423 return ret;
1424 }
1425 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1426 return 0;
1427}
1428
1429static
1430int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1431 u8 *ri_prime)
1432{
1433 struct intel_display *display = to_intel_display(dig_port);
1434
1435 int ret;
1436 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1437 ri_prime, DRM_HDCP_RI_LEN);
1438 if (ret)
1439 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",
1440 ret);
1441 return ret;
1442}
1443
1444static
1445int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1446 bool *ksv_ready)
1447{
1448 struct intel_display *display = to_intel_display(dig_port);
1449 int ret;
1450 u8 val;
1451
1452 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1453 if (ret) {
1454 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
1455 ret);
1456 return ret;
1457 }
1458 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1459 return 0;
1460}
1461
1462static
1463int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1464 int num_downstream, u8 *ksv_fifo)
1465{
1466 struct intel_display *display = to_intel_display(dig_port);
1467 int ret;
1468 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1469 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1470 if (ret) {
1471 drm_dbg_kms(display->drm,
1472 "Read ksv fifo over DDC failed (%d)\n", ret);
1473 return ret;
1474 }
1475 return 0;
1476}
1477
1478static
1479int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1480 int i, u32 *part)
1481{
1482 struct intel_display *display = to_intel_display(dig_port);
1483 int ret;
1484
1485 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1486 return -EINVAL;
1487
1488 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1489 part, DRM_HDCP_V_PRIME_PART_LEN);
1490 if (ret)
1491 drm_dbg_kms(display->drm,
1492 "Read V'[%d] over DDC failed (%d)\n",
1493 i, ret);
1494 return ret;
1495}
1496
1497static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1498 enum transcoder cpu_transcoder)
1499{
1500 struct intel_display *display = to_intel_display(connector);
1501 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1502 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1503 u32 scanline;
1504 int ret;
1505
1506 for (;;) {
1507 scanline = intel_de_read(display,
1508 PIPEDSL(display, crtc->pipe));
1509 if (scanline > 100 && scanline < 200)
1510 break;
1511 usleep_range(25, 50);
1512 }
1513
1514 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1515 false, TRANS_DDI_HDCP_SIGNALLING);
1516 if (ret) {
1517 drm_err(display->drm,
1518 "Disable HDCP signalling failed (%d)\n", ret);
1519 return ret;
1520 }
1521
1522 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1523 true, TRANS_DDI_HDCP_SIGNALLING);
1524 if (ret) {
1525 drm_err(display->drm,
1526 "Enable HDCP signalling failed (%d)\n", ret);
1527 return ret;
1528 }
1529
1530 return 0;
1531}
1532
1533static
1534int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1535 enum transcoder cpu_transcoder,
1536 bool enable)
1537{
1538 struct intel_display *display = to_intel_display(dig_port);
1539 struct intel_hdmi *hdmi = &dig_port->hdmi;
1540 struct intel_connector *connector = hdmi->attached_connector;
1541 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1542 int ret;
1543
1544 if (!enable)
1545 usleep_range(6, 60); /* Bspec says >= 6us */
1546
1547 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1548 cpu_transcoder, enable,
1549 TRANS_DDI_HDCP_SIGNALLING);
1550 if (ret) {
1551 drm_err(display->drm, "%s HDCP signalling failed (%d)\n",
1552 enable ? "Enable" : "Disable", ret);
1553 return ret;
1554 }
1555
1556 /*
1557 * WA: To fix incorrect positioning of the window of
1558 * opportunity and enc_en signalling in KABYLAKE.
1559 */
1560 if (IS_KABYLAKE(dev_priv) && enable)
1561 return kbl_repositioning_enc_en_signal(connector,
1562 cpu_transcoder);
1563
1564 return 0;
1565}
1566
1567static
1568bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1569 struct intel_connector *connector)
1570{
1571 struct intel_display *display = to_intel_display(dig_port);
1572 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1573 enum port port = dig_port->base.port;
1574 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1575 int ret;
1576 union {
1577 u32 reg;
1578 u8 shim[DRM_HDCP_RI_LEN];
1579 } ri;
1580
1581 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1582 if (ret)
1583 return false;
1584
1585 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1586
1587 /* Wait for Ri prime match */
1588 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1589 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1590 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1591 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
1592 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1593 port)));
1594 return false;
1595 }
1596 return true;
1597}
1598
1599static
1600bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1601 struct intel_connector *connector)
1602{
1603 struct intel_display *display = to_intel_display(dig_port);
1604 int retry;
1605
1606 for (retry = 0; retry < 3; retry++)
1607 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1608 return true;
1609
1610 drm_err(display->drm, "Link check failed\n");
1611 return false;
1612}
1613
1614struct hdcp2_hdmi_msg_timeout {
1615 u8 msg_id;
1616 u16 timeout;
1617};
1618
1619static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1620 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1621 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1622 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1623 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1624 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1625};
1626
1627static
1628int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1629 u8 *rx_status)
1630{
1631 return intel_hdmi_hdcp_read(dig_port,
1632 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1633 rx_status,
1634 HDCP_2_2_HDMI_RXSTATUS_LEN);
1635}
1636
1637static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1638{
1639 int i;
1640
1641 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1642 if (is_paired)
1643 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1644 else
1645 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1646 }
1647
1648 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1649 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1650 return hdcp2_msg_timeout[i].timeout;
1651 }
1652
1653 return -EINVAL;
1654}
1655
1656static int
1657hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1658 u8 msg_id, bool *msg_ready,
1659 ssize_t *msg_sz)
1660{
1661 struct intel_display *display = to_intel_display(dig_port);
1662 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1663 int ret;
1664
1665 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1666 if (ret < 0) {
1667 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",
1668 ret);
1669 return ret;
1670 }
1671
1672 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1673 rx_status[0]);
1674
1675 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1676 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1677 *msg_sz);
1678 else
1679 *msg_ready = *msg_sz;
1680
1681 return 0;
1682}
1683
1684static ssize_t
1685intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1686 u8 msg_id, bool paired)
1687{
1688 struct intel_display *display = to_intel_display(dig_port);
1689 bool msg_ready = false;
1690 int timeout, ret;
1691 ssize_t msg_sz = 0;
1692
1693 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1694 if (timeout < 0)
1695 return timeout;
1696
1697 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1698 msg_id, &msg_ready,
1699 &msg_sz),
1700 !ret && msg_ready && msg_sz, timeout * 1000,
1701 1000, 5 * 1000);
1702 if (ret)
1703 drm_dbg_kms(display->drm,
1704 "msg_id: %d, ret: %d, timeout: %d\n",
1705 msg_id, ret, timeout);
1706
1707 return ret ? ret : msg_sz;
1708}
1709
1710static
1711int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector,
1712 void *buf, size_t size)
1713{
1714 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1715 unsigned int offset;
1716
1717 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1718 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1719}
1720
1721static
1722int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector,
1723 u8 msg_id, void *buf, size_t size)
1724{
1725 struct intel_display *display = to_intel_display(connector);
1726 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1727 struct intel_hdmi *hdmi = &dig_port->hdmi;
1728 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1729 unsigned int offset;
1730 ssize_t ret;
1731
1732 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1733 hdcp->is_paired);
1734 if (ret < 0)
1735 return ret;
1736
1737 /*
1738 * Available msg size should be equal to or lesser than the
1739 * available buffer.
1740 */
1741 if (ret > size) {
1742 drm_dbg_kms(display->drm,
1743 "msg_sz(%zd) is more than exp size(%zu)\n",
1744 ret, size);
1745 return -EINVAL;
1746 }
1747
1748 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1749 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1750 if (ret)
1751 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",
1752 msg_id, ret);
1753
1754 return ret;
1755}
1756
1757static
1758int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1759 struct intel_connector *connector)
1760{
1761 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1762 int ret;
1763
1764 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1765 if (ret)
1766 return ret;
1767
1768 /*
1769 * Re-auth request and Link Integrity Failures are represented by
1770 * same bit. i.e reauth_req.
1771 */
1772 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1773 ret = HDCP_REAUTH_REQUEST;
1774 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1775 ret = HDCP_TOPOLOGY_CHANGE;
1776
1777 return ret;
1778}
1779
1780static
1781int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector,
1782 bool *capable)
1783{
1784 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1785 u8 hdcp2_version;
1786 int ret;
1787
1788 *capable = false;
1789 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1790 &hdcp2_version, sizeof(hdcp2_version));
1791 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1792 *capable = true;
1793
1794 return ret;
1795}
1796
1797static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1798 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1799 .read_bksv = intel_hdmi_hdcp_read_bksv,
1800 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1801 .repeater_present = intel_hdmi_hdcp_repeater_present,
1802 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1803 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1804 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1805 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1806 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1807 .check_link = intel_hdmi_hdcp_check_link,
1808 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1809 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1810 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1811 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability,
1812 .protocol = HDCP_PROTOCOL_HDMI,
1813};
1814
1815static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1816{
1817 struct intel_display *display = to_intel_display(encoder);
1818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1819 int max_tmds_clock, vbt_max_tmds_clock;
1820
1821 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv))
1822 max_tmds_clock = 600000;
1823 else if (DISPLAY_VER(display) >= 10)
1824 max_tmds_clock = 594000;
1825 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv))
1826 max_tmds_clock = 300000;
1827 else if (DISPLAY_VER(display) >= 5)
1828 max_tmds_clock = 225000;
1829 else
1830 max_tmds_clock = 165000;
1831
1832 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1833 if (vbt_max_tmds_clock)
1834 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1835
1836 return max_tmds_clock;
1837}
1838
1839static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1840 const struct drm_connector_state *conn_state)
1841{
1842 struct intel_connector *connector = hdmi->attached_connector;
1843
1844 return connector->base.display_info.is_hdmi &&
1845 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1846}
1847
1848static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1849{
1850 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1851}
1852
1853static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1854 bool respect_downstream_limits,
1855 bool has_hdmi_sink)
1856{
1857 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1858 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1859
1860 if (respect_downstream_limits) {
1861 struct intel_connector *connector = hdmi->attached_connector;
1862 const struct drm_display_info *info = &connector->base.display_info;
1863
1864 if (hdmi->dp_dual_mode.max_tmds_clock)
1865 max_tmds_clock = min(max_tmds_clock,
1866 hdmi->dp_dual_mode.max_tmds_clock);
1867
1868 if (info->max_tmds_clock)
1869 max_tmds_clock = min(max_tmds_clock,
1870 info->max_tmds_clock);
1871 else if (!has_hdmi_sink)
1872 max_tmds_clock = min(max_tmds_clock, 165000);
1873 }
1874
1875 return max_tmds_clock;
1876}
1877
1878static enum drm_mode_status
1879hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1880 int clock, bool respect_downstream_limits,
1881 bool has_hdmi_sink)
1882{
1883 struct intel_display *display = to_intel_display(hdmi);
1884 struct drm_i915_private *dev_priv = to_i915(display->drm);
1885 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1886
1887 if (clock < 25000)
1888 return MODE_CLOCK_LOW;
1889 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1890 has_hdmi_sink))
1891 return MODE_CLOCK_HIGH;
1892
1893 /* GLK DPLL can't generate 446-480 MHz */
1894 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1895 return MODE_CLOCK_RANGE;
1896
1897 /* BXT/GLK DPLL can't generate 223-240 MHz */
1898 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1899 clock > 223333 && clock < 240000)
1900 return MODE_CLOCK_RANGE;
1901
1902 /* CHV DPLL can't generate 216-240 MHz */
1903 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1904 return MODE_CLOCK_RANGE;
1905
1906 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1907 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200)
1908 return MODE_CLOCK_RANGE;
1909
1910 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1911 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)
1912 return MODE_CLOCK_RANGE;
1913
1914 /*
1915 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1916 * set of link rates.
1917 *
1918 * FIXME: We will hopefully get an algorithmic way of programming
1919 * the MPLLB for HDMI in the future.
1920 */
1921 if (DISPLAY_VER(display) >= 14)
1922 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
1923 else if (IS_DG2(dev_priv))
1924 return intel_snps_phy_check_hdmi_link_rate(clock);
1925
1926 return MODE_OK;
1927}
1928
1929int intel_hdmi_tmds_clock(int clock, int bpc,
1930 enum intel_output_format sink_format)
1931{
1932 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1933 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1934 clock /= 2;
1935
1936 /*
1937 * Need to adjust the port link by:
1938 * 1.5x for 12bpc
1939 * 1.25x for 10bpc
1940 */
1941 return DIV_ROUND_CLOSEST(clock * bpc, 8);
1942}
1943
1944static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)
1945{
1946 switch (bpc) {
1947 case 12:
1948 return !HAS_GMCH(display);
1949 case 10:
1950 return DISPLAY_VER(display) >= 11;
1951 case 8:
1952 return true;
1953 default:
1954 MISSING_CASE(bpc);
1955 return false;
1956 }
1957}
1958
1959static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1960 int bpc, bool has_hdmi_sink,
1961 enum intel_output_format sink_format)
1962{
1963 const struct drm_display_info *info = &connector->display_info;
1964 const struct drm_hdmi_info *hdmi = &info->hdmi;
1965
1966 switch (bpc) {
1967 case 12:
1968 if (!has_hdmi_sink)
1969 return false;
1970
1971 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1972 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1973 else
1974 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1975 case 10:
1976 if (!has_hdmi_sink)
1977 return false;
1978
1979 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1980 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1981 else
1982 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1983 case 8:
1984 return true;
1985 default:
1986 MISSING_CASE(bpc);
1987 return false;
1988 }
1989}
1990
1991static enum drm_mode_status
1992intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1993 bool has_hdmi_sink,
1994 enum intel_output_format sink_format)
1995{
1996 struct intel_display *display = to_intel_display(connector->dev);
1997 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1998 enum drm_mode_status status = MODE_OK;
1999 int bpc;
2000
2001 /*
2002 * Try all color depths since valid port clock range
2003 * can have holes. Any mode that can be used with at
2004 * least one color depth is accepted.
2005 */
2006 for (bpc = 12; bpc >= 8; bpc -= 2) {
2007 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
2008
2009 if (!intel_hdmi_source_bpc_possible(display, bpc))
2010 continue;
2011
2012 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format))
2013 continue;
2014
2015 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
2016 if (status == MODE_OK)
2017 return MODE_OK;
2018 }
2019
2020 /* can never happen */
2021 drm_WARN_ON(display->drm, status == MODE_OK);
2022
2023 return status;
2024}
2025
2026static enum drm_mode_status
2027intel_hdmi_mode_valid(struct drm_connector *connector,
2028 struct drm_display_mode *mode)
2029{
2030 struct intel_display *display = to_intel_display(connector->dev);
2031 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2032 struct drm_i915_private *dev_priv = to_i915(display->drm);
2033 enum drm_mode_status status;
2034 int clock = mode->clock;
2035 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
2036 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
2037 bool ycbcr_420_only;
2038 enum intel_output_format sink_format;
2039
2040 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
2041 if (status != MODE_OK)
2042 return status;
2043
2044 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2045 clock *= 2;
2046
2047 if (clock > max_dotclk)
2048 return MODE_CLOCK_HIGH;
2049
2050 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2051 if (!has_hdmi_sink)
2052 return MODE_CLOCK_LOW;
2053 clock *= 2;
2054 }
2055
2056 /*
2057 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2058 * enumerated only if FRL is supported. Current platforms do not support
2059 * FRL so prune the higher resolution modes that require doctclock more
2060 * than 600MHz.
2061 */
2062 if (clock > 600000)
2063 return MODE_CLOCK_HIGH;
2064
2065 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2066
2067 if (ycbcr_420_only)
2068 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2069 else
2070 sink_format = INTEL_OUTPUT_FORMAT_RGB;
2071
2072 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2073 if (status != MODE_OK) {
2074 if (ycbcr_420_only ||
2075 !connector->ycbcr_420_allowed ||
2076 !drm_mode_is_420_also(&connector->display_info, mode))
2077 return status;
2078
2079 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2080 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2081 if (status != MODE_OK)
2082 return status;
2083 }
2084
2085 return intel_mode_valid_max_plane_size(dev_priv, mode, 1);
2086}
2087
2088bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2089 int bpc, bool has_hdmi_sink)
2090{
2091 struct drm_atomic_state *state = crtc_state->uapi.state;
2092 struct drm_connector_state *connector_state;
2093 struct drm_connector *connector;
2094 int i;
2095
2096 for_each_new_connector_in_state(state, connector, connector_state, i) {
2097 if (connector_state->crtc != crtc_state->uapi.crtc)
2098 continue;
2099
2100 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink,
2101 crtc_state->sink_format))
2102 return false;
2103 }
2104
2105 return true;
2106}
2107
2108static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2109{
2110 struct intel_display *display = to_intel_display(crtc_state);
2111 const struct drm_display_mode *adjusted_mode =
2112 &crtc_state->hw.adjusted_mode;
2113
2114 if (!intel_hdmi_source_bpc_possible(display, bpc))
2115 return false;
2116
2117 /* Display Wa_1405510057:icl,ehl */
2118 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2119 bpc == 10 && DISPLAY_VER(display) == 11 &&
2120 (adjusted_mode->crtc_hblank_end -
2121 adjusted_mode->crtc_hblank_start) % 8 == 2)
2122 return false;
2123
2124 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2125}
2126
2127static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2128 struct intel_crtc_state *crtc_state,
2129 int clock, bool respect_downstream_limits)
2130{
2131 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2132 int bpc;
2133
2134 /*
2135 * pipe_bpp could already be below 8bpc due to FDI
2136 * bandwidth constraints. HDMI minimum is 8bpc however.
2137 */
2138 bpc = max(crtc_state->pipe_bpp / 3, 8);
2139
2140 /*
2141 * We will never exceed downstream TMDS clock limits while
2142 * attempting deep color. If the user insists on forcing an
2143 * out of spec mode they will have to be satisfied with 8bpc.
2144 */
2145 if (!respect_downstream_limits)
2146 bpc = 8;
2147
2148 for (; bpc >= 8; bpc -= 2) {
2149 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
2150 crtc_state->sink_format);
2151
2152 if (hdmi_bpc_possible(crtc_state, bpc) &&
2153 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2154 respect_downstream_limits,
2155 crtc_state->has_hdmi_sink) == MODE_OK)
2156 return bpc;
2157 }
2158
2159 return -EINVAL;
2160}
2161
2162static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2163 struct intel_crtc_state *crtc_state,
2164 bool respect_downstream_limits)
2165{
2166 struct intel_display *display = to_intel_display(encoder);
2167 const struct drm_display_mode *adjusted_mode =
2168 &crtc_state->hw.adjusted_mode;
2169 int bpc, clock = adjusted_mode->crtc_clock;
2170
2171 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2172 clock *= 2;
2173
2174 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2175 respect_downstream_limits);
2176 if (bpc < 0)
2177 return bpc;
2178
2179 crtc_state->port_clock =
2180 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2181
2182 /*
2183 * pipe_bpp could already be below 8bpc due to
2184 * FDI bandwidth constraints. We shouldn't bump it
2185 * back up to the HDMI minimum 8bpc in that case.
2186 */
2187 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2188
2189 drm_dbg_kms(display->drm,
2190 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2191 bpc, crtc_state->pipe_bpp);
2192
2193 return 0;
2194}
2195
2196bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2197 const struct drm_connector_state *conn_state)
2198{
2199 const struct intel_digital_connector_state *intel_conn_state =
2200 to_intel_digital_connector_state(conn_state);
2201 const struct drm_display_mode *adjusted_mode =
2202 &crtc_state->hw.adjusted_mode;
2203
2204 /*
2205 * Our YCbCr output is always limited range.
2206 * crtc_state->limited_color_range only applies to RGB,
2207 * and it must never be set for YCbCr or we risk setting
2208 * some conflicting bits in TRANSCONF which will mess up
2209 * the colors on the monitor.
2210 */
2211 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2212 return false;
2213
2214 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2215 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2216 return crtc_state->has_hdmi_sink &&
2217 drm_default_rgb_quant_range(adjusted_mode) ==
2218 HDMI_QUANTIZATION_RANGE_LIMITED;
2219 } else {
2220 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2221 }
2222}
2223
2224static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2225 const struct intel_crtc_state *crtc_state,
2226 const struct drm_connector_state *conn_state)
2227{
2228 struct drm_connector *connector = conn_state->connector;
2229 const struct intel_digital_connector_state *intel_conn_state =
2230 to_intel_digital_connector_state(conn_state);
2231
2232 if (!crtc_state->has_hdmi_sink)
2233 return false;
2234
2235 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2236 return connector->display_info.has_audio;
2237 else
2238 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2239}
2240
2241static enum intel_output_format
2242intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
2243 struct intel_connector *connector,
2244 bool ycbcr_420_output)
2245{
2246 if (!crtc_state->has_hdmi_sink)
2247 return INTEL_OUTPUT_FORMAT_RGB;
2248
2249 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2250 return INTEL_OUTPUT_FORMAT_YCBCR420;
2251 else
2252 return INTEL_OUTPUT_FORMAT_RGB;
2253}
2254
2255static enum intel_output_format
2256intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
2257{
2258 return crtc_state->sink_format;
2259}
2260
2261static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2262 struct intel_crtc_state *crtc_state,
2263 const struct drm_connector_state *conn_state,
2264 bool respect_downstream_limits)
2265{
2266 struct intel_display *display = to_intel_display(encoder);
2267 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2268 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2269 const struct drm_display_info *info = &connector->base.display_info;
2270 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2271 int ret;
2272
2273 crtc_state->sink_format =
2274 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
2275
2276 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2277 drm_dbg_kms(display->drm,
2278 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2279 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2280 }
2281
2282 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2283 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2284 if (ret) {
2285 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2286 !crtc_state->has_hdmi_sink ||
2287 !connector->base.ycbcr_420_allowed ||
2288 !drm_mode_is_420_also(info, adjusted_mode))
2289 return ret;
2290
2291 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2292 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2293 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2294 }
2295
2296 return ret;
2297}
2298
2299static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2300{
2301 return crtc_state->uapi.encoder_mask &&
2302 !is_power_of_2(crtc_state->uapi.encoder_mask);
2303}
2304
2305static bool source_supports_scrambling(struct intel_encoder *encoder)
2306{
2307 /*
2308 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and
2309 * scrambling is supported.
2310 * But there seem to be cases where certain platforms that support
2311 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is
2312 * capped by VBT to less than 340MHz.
2313 *
2314 * In such cases when an HDMI2.0 sink is connected, it creates a
2315 * problem : the platform and the sink both support scrambling but the
2316 * HDMI 1.4 retimer chip doesn't.
2317 *
2318 * So go for scrambling, based on the max tmds clock taking into account,
2319 * restrictions coming from VBT.
2320 */
2321 return intel_hdmi_source_max_tmds_clock(encoder) > 340000;
2322}
2323
2324bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
2325 const struct intel_crtc_state *crtc_state,
2326 const struct drm_connector_state *conn_state)
2327{
2328 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
2329
2330 return intel_has_hdmi_sink(hdmi, conn_state) &&
2331 !intel_hdmi_is_cloned(crtc_state);
2332}
2333
2334int intel_hdmi_compute_config(struct intel_encoder *encoder,
2335 struct intel_crtc_state *pipe_config,
2336 struct drm_connector_state *conn_state)
2337{
2338 struct intel_display *display = to_intel_display(encoder);
2339 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2340 struct drm_connector *connector = conn_state->connector;
2341 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2342 int ret;
2343
2344 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2345 return -EINVAL;
2346
2347 if (!connector->interlace_allowed &&
2348 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2349 return -EINVAL;
2350
2351 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2352
2353 if (pipe_config->has_hdmi_sink)
2354 pipe_config->has_infoframe = true;
2355
2356 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2357 pipe_config->pixel_multiplier = 2;
2358
2359 pipe_config->has_audio =
2360 intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2361 intel_audio_compute_config(encoder, pipe_config, conn_state);
2362
2363 /*
2364 * Try to respect downstream TMDS clock limits first, if
2365 * that fails assume the user might know something we don't.
2366 */
2367 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2368 if (ret)
2369 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2370 if (ret) {
2371 drm_dbg_kms(display->drm,
2372 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2373 pipe_config->hw.adjusted_mode.crtc_clock);
2374 return ret;
2375 }
2376
2377 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2378 ret = intel_panel_fitting(pipe_config, conn_state);
2379 if (ret)
2380 return ret;
2381 }
2382
2383 pipe_config->limited_color_range =
2384 intel_hdmi_limited_color_range(pipe_config, conn_state);
2385
2386 if (conn_state->picture_aspect_ratio)
2387 adjusted_mode->picture_aspect_ratio =
2388 conn_state->picture_aspect_ratio;
2389
2390 pipe_config->lane_count = 4;
2391
2392 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2393 if (scdc->scrambling.low_rates)
2394 pipe_config->hdmi_scrambling = true;
2395
2396 if (pipe_config->port_clock > 340000) {
2397 pipe_config->hdmi_scrambling = true;
2398 pipe_config->hdmi_high_tmds_clock_ratio = true;
2399 }
2400 }
2401
2402 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2403 conn_state);
2404
2405 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2406 drm_dbg_kms(display->drm, "bad AVI infoframe\n");
2407 return -EINVAL;
2408 }
2409
2410 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2411 drm_dbg_kms(display->drm, "bad SPD infoframe\n");
2412 return -EINVAL;
2413 }
2414
2415 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2416 drm_dbg_kms(display->drm, "bad HDMI infoframe\n");
2417 return -EINVAL;
2418 }
2419
2420 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2421 drm_dbg_kms(display->drm, "bad DRM infoframe\n");
2422 return -EINVAL;
2423 }
2424
2425 return 0;
2426}
2427
2428void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2429{
2430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2431
2432 /*
2433 * Give a hand to buggy BIOSen which forget to turn
2434 * the TMDS output buffers back on after a reboot.
2435 */
2436 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2437}
2438
2439static void
2440intel_hdmi_unset_edid(struct drm_connector *connector)
2441{
2442 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2443
2444 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2445 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2446
2447 drm_edid_free(to_intel_connector(connector)->detect_edid);
2448 to_intel_connector(connector)->detect_edid = NULL;
2449}
2450
2451static void
2452intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2453{
2454 struct intel_display *display = to_intel_display(connector->dev);
2455 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2456 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2457 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2458 struct i2c_adapter *ddc = connector->ddc;
2459 enum drm_dp_dual_mode_type type;
2460
2461 type = drm_dp_dual_mode_detect(display->drm, ddc);
2462
2463 /*
2464 * Type 1 DVI adaptors are not required to implement any
2465 * registers, so we can't always detect their presence.
2466 * Ideally we should be able to check the state of the
2467 * CONFIG1 pin, but no such luck on our hardware.
2468 *
2469 * The only method left to us is to check the VBT to see
2470 * if the port is a dual mode capable DP port.
2471 */
2472 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2473 if (!connector->force &&
2474 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2475 drm_dbg_kms(display->drm,
2476 "Assuming DP dual mode adaptor presence based on VBT\n");
2477 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2478 } else {
2479 type = DRM_DP_DUAL_MODE_NONE;
2480 }
2481 }
2482
2483 if (type == DRM_DP_DUAL_MODE_NONE)
2484 return;
2485
2486 hdmi->dp_dual_mode.type = type;
2487 hdmi->dp_dual_mode.max_tmds_clock =
2488 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);
2489
2490 drm_dbg_kms(display->drm,
2491 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2492 drm_dp_get_dual_mode_type_name(type),
2493 hdmi->dp_dual_mode.max_tmds_clock);
2494
2495 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2496 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) &&
2497 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2498 drm_dbg_kms(display->drm,
2499 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2500 hdmi->dp_dual_mode.max_tmds_clock = 0;
2501 }
2502}
2503
2504static bool
2505intel_hdmi_set_edid(struct drm_connector *connector)
2506{
2507 struct intel_display *display = to_intel_display(connector->dev);
2508 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2509 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2510 struct i2c_adapter *ddc = connector->ddc;
2511 intel_wakeref_t wakeref;
2512 const struct drm_edid *drm_edid;
2513 bool connected = false;
2514
2515 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2516
2517 drm_edid = drm_edid_read_ddc(connector, ddc);
2518
2519 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
2520 drm_dbg_kms(display->drm,
2521 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2522 intel_gmbus_force_bit(ddc, true);
2523 drm_edid = drm_edid_read_ddc(connector, ddc);
2524 intel_gmbus_force_bit(ddc, false);
2525 }
2526
2527 /* Below we depend on display info having been updated */
2528 drm_edid_connector_update(connector, drm_edid);
2529
2530 to_intel_connector(connector)->detect_edid = drm_edid;
2531
2532 if (drm_edid_is_digital(drm_edid)) {
2533 intel_hdmi_dp_dual_mode_detect(connector);
2534
2535 connected = true;
2536 }
2537
2538 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2539
2540 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier,
2541 connector->display_info.source_physical_address);
2542
2543 return connected;
2544}
2545
2546static enum drm_connector_status
2547intel_hdmi_detect(struct drm_connector *connector, bool force)
2548{
2549 struct intel_display *display = to_intel_display(connector->dev);
2550 enum drm_connector_status status = connector_status_disconnected;
2551 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2552 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2553 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2554 intel_wakeref_t wakeref;
2555
2556 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
2557 connector->base.id, connector->name);
2558
2559 if (!intel_display_device_enabled(dev_priv))
2560 return connector_status_disconnected;
2561
2562 if (!intel_display_driver_check_access(dev_priv))
2563 return connector->status;
2564
2565 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2566
2567 if (DISPLAY_VER(display) >= 11 &&
2568 !intel_digital_port_connected(encoder))
2569 goto out;
2570
2571 intel_hdmi_unset_edid(connector);
2572
2573 if (intel_hdmi_set_edid(connector))
2574 status = connector_status_connected;
2575
2576out:
2577 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2578
2579 if (status != connector_status_connected)
2580 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2581
2582 return status;
2583}
2584
2585static void
2586intel_hdmi_force(struct drm_connector *connector)
2587{
2588 struct intel_display *display = to_intel_display(connector->dev);
2589 struct drm_i915_private *i915 = to_i915(connector->dev);
2590
2591 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
2592 connector->base.id, connector->name);
2593
2594 if (!intel_display_driver_check_access(i915))
2595 return;
2596
2597 intel_hdmi_unset_edid(connector);
2598
2599 if (connector->status != connector_status_connected)
2600 return;
2601
2602 intel_hdmi_set_edid(connector);
2603}
2604
2605static int intel_hdmi_get_modes(struct drm_connector *connector)
2606{
2607 /* drm_edid_connector_update() done in ->detect() or ->force() */
2608 return drm_edid_connector_add_modes(connector);
2609}
2610
2611static int
2612intel_hdmi_connector_register(struct drm_connector *connector)
2613{
2614 int ret;
2615
2616 ret = intel_connector_register(connector);
2617 if (ret)
2618 return ret;
2619
2620 return ret;
2621}
2622
2623static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2624{
2625 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2626
2627 cec_notifier_conn_unregister(n);
2628
2629 intel_connector_unregister(connector);
2630}
2631
2632static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2633 .detect = intel_hdmi_detect,
2634 .force = intel_hdmi_force,
2635 .fill_modes = drm_helper_probe_single_connector_modes,
2636 .atomic_get_property = intel_digital_connector_atomic_get_property,
2637 .atomic_set_property = intel_digital_connector_atomic_set_property,
2638 .late_register = intel_hdmi_connector_register,
2639 .early_unregister = intel_hdmi_connector_unregister,
2640 .destroy = intel_connector_destroy,
2641 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2642 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2643};
2644
2645static int intel_hdmi_connector_atomic_check(struct drm_connector *connector,
2646 struct drm_atomic_state *state)
2647{
2648 struct intel_display *display = to_intel_display(connector->dev);
2649
2650 if (HAS_DDI(display))
2651 return intel_digital_connector_atomic_check(connector, state);
2652 else
2653 return g4x_hdmi_connector_atomic_check(connector, state);
2654}
2655
2656static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2657 .get_modes = intel_hdmi_get_modes,
2658 .mode_valid = intel_hdmi_mode_valid,
2659 .atomic_check = intel_hdmi_connector_atomic_check,
2660};
2661
2662static void
2663intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2664{
2665 struct intel_display *display = to_intel_display(intel_hdmi);
2666
2667 intel_attach_force_audio_property(connector);
2668 intel_attach_broadcast_rgb_property(connector);
2669 intel_attach_aspect_ratio_property(connector);
2670
2671 intel_attach_hdmi_colorspace_property(connector);
2672 drm_connector_attach_content_type_property(connector);
2673
2674 if (DISPLAY_VER(display) >= 10)
2675 drm_connector_attach_hdr_output_metadata_property(connector);
2676
2677 if (!HAS_GMCH(display))
2678 drm_connector_attach_max_bpc_property(connector, 8, 12);
2679}
2680
2681/*
2682 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2683 * @encoder: intel_encoder
2684 * @connector: drm_connector
2685 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2686 * or reset the high tmds clock ratio for scrambling
2687 * @scrambling: bool to Indicate if the function needs to set or reset
2688 * sink scrambling
2689 *
2690 * This function handles scrambling on HDMI 2.0 capable sinks.
2691 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2692 * it enables scrambling. This should be called before enabling the HDMI
2693 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2694 * detect a scrambled clock within 100 ms.
2695 *
2696 * Returns:
2697 * True on success, false on failure.
2698 */
2699bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2700 struct drm_connector *connector,
2701 bool high_tmds_clock_ratio,
2702 bool scrambling)
2703{
2704 struct intel_display *display = to_intel_display(encoder);
2705 struct drm_scrambling *sink_scrambling =
2706 &connector->display_info.hdmi.scdc.scrambling;
2707
2708 if (!sink_scrambling->supported)
2709 return true;
2710
2711 drm_dbg_kms(display->drm,
2712 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2713 connector->base.id, connector->name,
2714 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2715
2716 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2717 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) &&
2718 drm_scdc_set_scrambling(connector, scrambling);
2719}
2720
2721static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder)
2722{
2723 enum port port = encoder->port;
2724 u8 ddc_pin;
2725
2726 switch (port) {
2727 case PORT_B:
2728 ddc_pin = GMBUS_PIN_DPB;
2729 break;
2730 case PORT_C:
2731 ddc_pin = GMBUS_PIN_DPC;
2732 break;
2733 case PORT_D:
2734 ddc_pin = GMBUS_PIN_DPD_CHV;
2735 break;
2736 default:
2737 MISSING_CASE(port);
2738 ddc_pin = GMBUS_PIN_DPB;
2739 break;
2740 }
2741 return ddc_pin;
2742}
2743
2744static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder)
2745{
2746 enum port port = encoder->port;
2747 u8 ddc_pin;
2748
2749 switch (port) {
2750 case PORT_B:
2751 ddc_pin = GMBUS_PIN_1_BXT;
2752 break;
2753 case PORT_C:
2754 ddc_pin = GMBUS_PIN_2_BXT;
2755 break;
2756 default:
2757 MISSING_CASE(port);
2758 ddc_pin = GMBUS_PIN_1_BXT;
2759 break;
2760 }
2761 return ddc_pin;
2762}
2763
2764static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder)
2765{
2766 enum port port = encoder->port;
2767 u8 ddc_pin;
2768
2769 switch (port) {
2770 case PORT_B:
2771 ddc_pin = GMBUS_PIN_1_BXT;
2772 break;
2773 case PORT_C:
2774 ddc_pin = GMBUS_PIN_2_BXT;
2775 break;
2776 case PORT_D:
2777 ddc_pin = GMBUS_PIN_4_CNP;
2778 break;
2779 case PORT_F:
2780 ddc_pin = GMBUS_PIN_3_BXT;
2781 break;
2782 default:
2783 MISSING_CASE(port);
2784 ddc_pin = GMBUS_PIN_1_BXT;
2785 break;
2786 }
2787 return ddc_pin;
2788}
2789
2790static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder)
2791{
2792 struct intel_display *display = to_intel_display(encoder);
2793 enum port port = encoder->port;
2794
2795 if (intel_encoder_is_combo(encoder))
2796 return GMBUS_PIN_1_BXT + port;
2797 else if (intel_encoder_is_tc(encoder))
2798 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder);
2799
2800 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port));
2801 return GMBUS_PIN_2_BXT;
2802}
2803
2804static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder)
2805{
2806 enum phy phy = intel_encoder_to_phy(encoder);
2807 u8 ddc_pin;
2808
2809 switch (phy) {
2810 case PHY_A:
2811 ddc_pin = GMBUS_PIN_1_BXT;
2812 break;
2813 case PHY_B:
2814 ddc_pin = GMBUS_PIN_2_BXT;
2815 break;
2816 case PHY_C:
2817 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2818 break;
2819 default:
2820 MISSING_CASE(phy);
2821 ddc_pin = GMBUS_PIN_1_BXT;
2822 break;
2823 }
2824 return ddc_pin;
2825}
2826
2827static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder)
2828{
2829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2830 enum phy phy = intel_encoder_to_phy(encoder);
2831
2832 WARN_ON(encoder->port == PORT_C);
2833
2834 /*
2835 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2836 * final two outputs use type-c pins, even though they're actually
2837 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2838 * all outputs.
2839 */
2840 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2841 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2842
2843 return GMBUS_PIN_1_BXT + phy;
2844}
2845
2846static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder)
2847{
2848 struct intel_display *display = to_intel_display(encoder);
2849 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2850 enum phy phy = intel_encoder_to_phy(encoder);
2851
2852 drm_WARN_ON(display->drm, encoder->port == PORT_A);
2853
2854 /*
2855 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2856 * final two outputs use type-c pins, even though they're actually
2857 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2858 * all outputs.
2859 */
2860 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2861 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2862
2863 return GMBUS_PIN_1_BXT + phy;
2864}
2865
2866static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder)
2867{
2868 return intel_encoder_to_phy(encoder) + 1;
2869}
2870
2871static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder)
2872{
2873 enum phy phy = intel_encoder_to_phy(encoder);
2874
2875 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C);
2876
2877 /*
2878 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2879 * except first combo output.
2880 */
2881 if (phy == PHY_A)
2882 return GMBUS_PIN_1_BXT;
2883
2884 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2885}
2886
2887static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder)
2888{
2889 enum port port = encoder->port;
2890 u8 ddc_pin;
2891
2892 switch (port) {
2893 case PORT_B:
2894 ddc_pin = GMBUS_PIN_DPB;
2895 break;
2896 case PORT_C:
2897 ddc_pin = GMBUS_PIN_DPC;
2898 break;
2899 case PORT_D:
2900 ddc_pin = GMBUS_PIN_DPD;
2901 break;
2902 default:
2903 MISSING_CASE(port);
2904 ddc_pin = GMBUS_PIN_DPB;
2905 break;
2906 }
2907 return ddc_pin;
2908}
2909
2910static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)
2911{
2912 struct intel_display *display = to_intel_display(encoder);
2913 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2914 u8 ddc_pin;
2915
2916 if (IS_ALDERLAKE_S(dev_priv))
2917 ddc_pin = adls_encoder_to_ddc_pin(encoder);
2918 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2919 ddc_pin = dg1_encoder_to_ddc_pin(encoder);
2920 else if (IS_ROCKETLAKE(dev_priv))
2921 ddc_pin = rkl_encoder_to_ddc_pin(encoder);
2922 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv))
2923 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder);
2924 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
2925 HAS_PCH_TGP(dev_priv))
2926 ddc_pin = mcc_encoder_to_ddc_pin(encoder);
2927 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2928 ddc_pin = icl_encoder_to_ddc_pin(encoder);
2929 else if (HAS_PCH_CNP(dev_priv))
2930 ddc_pin = cnp_encoder_to_ddc_pin(encoder);
2931 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2932 ddc_pin = bxt_encoder_to_ddc_pin(encoder);
2933 else if (IS_CHERRYVIEW(dev_priv))
2934 ddc_pin = chv_encoder_to_ddc_pin(encoder);
2935 else
2936 ddc_pin = g4x_encoder_to_ddc_pin(encoder);
2937
2938 return ddc_pin;
2939}
2940
2941static struct intel_encoder *
2942get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
2943{
2944 struct intel_display *display = to_intel_display(encoder);
2945 struct intel_encoder *other;
2946
2947 for_each_intel_encoder(display->drm, other) {
2948 struct intel_connector *connector;
2949
2950 if (other == encoder)
2951 continue;
2952
2953 if (!intel_encoder_is_dig_port(other))
2954 continue;
2955
2956 connector = enc_to_dig_port(other)->hdmi.attached_connector;
2957
2958 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
2959 return other;
2960 }
2961
2962 return NULL;
2963}
2964
2965static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2966{
2967 struct intel_display *display = to_intel_display(encoder);
2968 struct intel_encoder *other;
2969 const char *source;
2970 u8 ddc_pin;
2971
2972 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2973 source = "VBT";
2974
2975 if (!ddc_pin) {
2976 ddc_pin = intel_hdmi_default_ddc_pin(encoder);
2977 source = "platform default";
2978 }
2979
2980 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
2981 drm_dbg_kms(display->drm,
2982 "[ENCODER:%d:%s] Invalid DDC pin %d\n",
2983 encoder->base.base.id, encoder->base.name, ddc_pin);
2984 return 0;
2985 }
2986
2987 other = get_encoder_by_ddc_pin(encoder, ddc_pin);
2988 if (other) {
2989 drm_dbg_kms(display->drm,
2990 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n",
2991 encoder->base.base.id, encoder->base.name, ddc_pin,
2992 other->base.base.id, other->base.name);
2993 return 0;
2994 }
2995
2996 drm_dbg_kms(display->drm,
2997 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n",
2998 encoder->base.base.id, encoder->base.name,
2999 ddc_pin, source);
3000
3001 return ddc_pin;
3002}
3003
3004void intel_infoframe_init(struct intel_digital_port *dig_port)
3005{
3006 struct intel_display *display = to_intel_display(dig_port);
3007 struct drm_i915_private *dev_priv =
3008 to_i915(dig_port->base.base.dev);
3009
3010 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3011 dig_port->write_infoframe = vlv_write_infoframe;
3012 dig_port->read_infoframe = vlv_read_infoframe;
3013 dig_port->set_infoframes = vlv_set_infoframes;
3014 dig_port->infoframes_enabled = vlv_infoframes_enabled;
3015 } else if (IS_G4X(dev_priv)) {
3016 dig_port->write_infoframe = g4x_write_infoframe;
3017 dig_port->read_infoframe = g4x_read_infoframe;
3018 dig_port->set_infoframes = g4x_set_infoframes;
3019 dig_port->infoframes_enabled = g4x_infoframes_enabled;
3020 } else if (HAS_DDI(display)) {
3021 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) {
3022 dig_port->write_infoframe = lspcon_write_infoframe;
3023 dig_port->read_infoframe = lspcon_read_infoframe;
3024 dig_port->set_infoframes = lspcon_set_infoframes;
3025 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3026 } else {
3027 dig_port->write_infoframe = hsw_write_infoframe;
3028 dig_port->read_infoframe = hsw_read_infoframe;
3029 dig_port->set_infoframes = hsw_set_infoframes;
3030 dig_port->infoframes_enabled = hsw_infoframes_enabled;
3031 }
3032 } else if (HAS_PCH_IBX(dev_priv)) {
3033 dig_port->write_infoframe = ibx_write_infoframe;
3034 dig_port->read_infoframe = ibx_read_infoframe;
3035 dig_port->set_infoframes = ibx_set_infoframes;
3036 dig_port->infoframes_enabled = ibx_infoframes_enabled;
3037 } else {
3038 dig_port->write_infoframe = cpt_write_infoframe;
3039 dig_port->read_infoframe = cpt_read_infoframe;
3040 dig_port->set_infoframes = cpt_set_infoframes;
3041 dig_port->infoframes_enabled = cpt_infoframes_enabled;
3042 }
3043}
3044
3045void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3046 struct intel_connector *intel_connector)
3047{
3048 struct intel_display *display = to_intel_display(dig_port);
3049 struct drm_connector *connector = &intel_connector->base;
3050 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3051 struct intel_encoder *intel_encoder = &dig_port->base;
3052 struct drm_device *dev = intel_encoder->base.dev;
3053 enum port port = intel_encoder->port;
3054 struct cec_connector_info conn_info;
3055 u8 ddc_pin;
3056
3057 drm_dbg_kms(display->drm,
3058 "Adding HDMI connector on [ENCODER:%d:%s]\n",
3059 intel_encoder->base.base.id, intel_encoder->base.name);
3060
3061 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A))
3062 return;
3063
3064 if (drm_WARN(dev, dig_port->max_lanes < 4,
3065 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3066 dig_port->max_lanes, intel_encoder->base.base.id,
3067 intel_encoder->base.name))
3068 return;
3069
3070 ddc_pin = intel_hdmi_ddc_pin(intel_encoder);
3071 if (!ddc_pin)
3072 return;
3073
3074 drm_connector_init_with_ddc(dev, connector,
3075 &intel_hdmi_connector_funcs,
3076 DRM_MODE_CONNECTOR_HDMIA,
3077 intel_gmbus_get_adapter(display, ddc_pin));
3078
3079 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3080
3081 if (DISPLAY_VER(display) < 12)
3082 connector->interlace_allowed = true;
3083
3084 connector->stereo_allowed = true;
3085
3086 if (DISPLAY_VER(display) >= 10)
3087 connector->ycbcr_420_allowed = true;
3088
3089 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3090 intel_connector->base.polled = intel_connector->polled;
3091
3092 if (HAS_DDI(display))
3093 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3094 else
3095 intel_connector->get_hw_state = intel_connector_get_hw_state;
3096
3097 intel_hdmi_add_properties(intel_hdmi, connector);
3098
3099 intel_connector_attach_encoder(intel_connector, intel_encoder);
3100 intel_hdmi->attached_connector = intel_connector;
3101
3102 if (is_hdcp_supported(display, port)) {
3103 int ret = intel_hdcp_init(intel_connector, dig_port,
3104 &intel_hdmi_hdcp_shim);
3105 if (ret)
3106 drm_dbg_kms(display->drm,
3107 "HDCP init failed, skipping.\n");
3108 }
3109
3110 cec_fill_conn_info_from_drm(&conn_info, connector);
3111
3112 intel_hdmi->cec_notifier =
3113 cec_notifier_conn_register(dev->dev, port_identifier(port),
3114 &conn_info);
3115 if (!intel_hdmi->cec_notifier)
3116 drm_dbg_kms(display->drm, "CEC notifier get failed\n");
3117}
3118
3119/*
3120 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3121 * @vactive: Vactive of a display mode
3122 *
3123 * @return: appropriate dsc slice height for a given mode.
3124 */
3125int intel_hdmi_dsc_get_slice_height(int vactive)
3126{
3127 int slice_height;
3128
3129 /*
3130 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3131 * Select smallest slice height >=96, that results in a valid PPS and
3132 * requires minimum padding lines required for final slice.
3133 *
3134 * Assumption : Vactive is even.
3135 */
3136 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3137 if (vactive % slice_height == 0)
3138 return slice_height;
3139
3140 return 0;
3141}
3142
3143/*
3144 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3145 * and dsc decoder capabilities
3146 *
3147 * @crtc_state: intel crtc_state
3148 * @src_max_slices: maximum slices supported by the DSC encoder
3149 * @src_max_slice_width: maximum slice width supported by DSC encoder
3150 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3151 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3152 *
3153 * @return: num of dsc slices that can be supported by the dsc encoder
3154 * and decoder.
3155 */
3156int
3157intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3158 int src_max_slices, int src_max_slice_width,
3159 int hdmi_max_slices, int hdmi_throughput)
3160{
3161/* Pixel rates in KPixels/sec */
3162#define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3163/*
3164 * Rates at which the source and sink are required to process pixels in each
3165 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3166 */
3167#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3168#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3169
3170/* Spec limits the slice width to 2720 pixels */
3171#define MAX_HDMI_SLICE_WIDTH 2720
3172 int kslice_adjust;
3173 int adjusted_clk_khz;
3174 int min_slices;
3175 int target_slices;
3176 int max_throughput; /* max clock freq. in khz per slice */
3177 int max_slice_width;
3178 int slice_width;
3179 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3180
3181 if (!hdmi_throughput)
3182 return 0;
3183
3184 /*
3185 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3186 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3187 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3188 * dividing adjusted clock value by 10.
3189 */
3190 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3191 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3192 kslice_adjust = 10;
3193 else
3194 kslice_adjust = 5;
3195
3196 /*
3197 * As per spec, the rate at which the source and the sink process
3198 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3199 * This depends upon the pixel clock rate and output formats
3200 * (kslice adjust).
3201 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3202 * at max 340MHz, otherwise they can be processed at max 400MHz.
3203 */
3204
3205 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3206
3207 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3208 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3209 else
3210 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3211
3212 /*
3213 * Taking into account the sink's capability for maximum
3214 * clock per slice (in MHz) as read from HF-VSDB.
3215 */
3216 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3217
3218 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3219 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3220
3221 /*
3222 * Keep on increasing the num of slices/line, starting from min_slices
3223 * per line till we get such a number, for which the slice_width is
3224 * just less than max_slice_width. The slices/line selected should be
3225 * less than or equal to the max horizontal slices that the combination
3226 * of PCON encoder and HDMI decoder can support.
3227 */
3228 slice_width = max_slice_width;
3229
3230 do {
3231 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3232 target_slices = 1;
3233 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3234 target_slices = 2;
3235 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3236 target_slices = 4;
3237 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3238 target_slices = 8;
3239 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3240 target_slices = 12;
3241 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3242 target_slices = 16;
3243 else
3244 return 0;
3245
3246 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3247 if (slice_width >= max_slice_width)
3248 min_slices = target_slices + 1;
3249 } while (slice_width >= max_slice_width);
3250
3251 return target_slices;
3252}
3253
3254/*
3255 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3256 * source and sink capabilities.
3257 *
3258 * @src_fraction_bpp: fractional bpp supported by the source
3259 * @slice_width: dsc slice width supported by the source and sink
3260 * @num_slices: num of slices supported by the source and sink
3261 * @output_format: video output format
3262 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3263 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3264 *
3265 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3266 */
3267int
3268intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3269 int output_format, bool hdmi_all_bpp,
3270 int hdmi_max_chunk_bytes)
3271{
3272 int max_dsc_bpp, min_dsc_bpp;
3273 int target_bytes;
3274 bool bpp_found = false;
3275 int bpp_decrement_x16;
3276 int bpp_target;
3277 int bpp_target_x16;
3278
3279 /*
3280 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3281 * Start with the max bpp and keep on decrementing with
3282 * fractional bpp, if supported by PCON DSC encoder
3283 *
3284 * for each bpp we check if no of bytes can be supported by HDMI sink
3285 */
3286
3287 /* Assuming: bpc as 8*/
3288 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3289 min_dsc_bpp = 6;
3290 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3291 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3292 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3293 min_dsc_bpp = 8;
3294 max_dsc_bpp = 3 * 8; /* 3*bpc */
3295 } else {
3296 /* Assuming 4:2:2 encoding */
3297 min_dsc_bpp = 7;
3298 max_dsc_bpp = 2 * 8; /* 2*bpc */
3299 }
3300
3301 /*
3302 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3303 * Section 7.7.34 : Source shall not enable compressed Video
3304 * Transport with bpp_target settings above 12 bpp unless
3305 * DSC_all_bpp is set to 1.
3306 */
3307 if (!hdmi_all_bpp)
3308 max_dsc_bpp = min(max_dsc_bpp, 12);
3309
3310 /*
3311 * The Sink has a limit of compressed data in bytes for a scanline,
3312 * as described in max_chunk_bytes field in HFVSDB block of edid.
3313 * The no. of bytes depend on the target bits per pixel that the
3314 * source configures. So we start with the max_bpp and calculate
3315 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3316 * till we get the target_chunk_bytes just less than what the sink's
3317 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3318 *
3319 * The decrement is according to the fractional support from PCON DSC
3320 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3321 *
3322 * bpp_target_x16 = bpp_target * 16
3323 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3324 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3325 */
3326
3327 bpp_target = max_dsc_bpp;
3328
3329 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3330 if (!src_fractional_bpp)
3331 src_fractional_bpp = 1;
3332 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3333 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3334
3335 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3336 int bpp;
3337
3338 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3339 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3340 if (target_bytes <= hdmi_max_chunk_bytes) {
3341 bpp_found = true;
3342 break;
3343 }
3344 bpp_target_x16 -= bpp_decrement_x16;
3345 }
3346 if (bpp_found)
3347 return bpp_target_x16;
3348
3349 return 0;
3350}