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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30#include <linux/export.h>
31#include <linux/i2c-algo-bit.h>
32#include <linux/i2c.h>
33
34#include <drm/drm_hdcp.h>
35
36#include "i915_drv.h"
37#include "intel_de.h"
38#include "intel_display_types.h"
39#include "intel_gmbus.h"
40
41struct gmbus_pin {
42 const char *name;
43 enum i915_gpio gpio;
44};
45
46/* Map gmbus pin pairs to names and registers. */
47static const struct gmbus_pin gmbus_pins[] = {
48 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
50 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
51 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
52 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
53 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
54};
55
56static const struct gmbus_pin gmbus_pins_bdw[] = {
57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
58 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
59 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
60 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
61};
62
63static const struct gmbus_pin gmbus_pins_skl[] = {
64 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
65 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
66 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
67};
68
69static const struct gmbus_pin gmbus_pins_bxt[] = {
70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
73};
74
75static const struct gmbus_pin gmbus_pins_cnp[] = {
76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
80};
81
82static const struct gmbus_pin gmbus_pins_icp[] = {
83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
85 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
86 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
87 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
88 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
89 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
90 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
91 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
92};
93
94static const struct gmbus_pin gmbus_pins_dg1[] = {
95 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
96 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
97 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
98 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
99};
100
101/* pin is expected to be valid */
102static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
103 unsigned int pin)
104{
105 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
106 return &gmbus_pins_dg1[pin];
107 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
108 return &gmbus_pins_icp[pin];
109 else if (HAS_PCH_CNP(dev_priv))
110 return &gmbus_pins_cnp[pin];
111 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
112 return &gmbus_pins_bxt[pin];
113 else if (DISPLAY_VER(dev_priv) == 9)
114 return &gmbus_pins_skl[pin];
115 else if (IS_BROADWELL(dev_priv))
116 return &gmbus_pins_bdw[pin];
117 else
118 return &gmbus_pins[pin];
119}
120
121bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
122 unsigned int pin)
123{
124 unsigned int size;
125
126 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
127 size = ARRAY_SIZE(gmbus_pins_dg1);
128 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
129 size = ARRAY_SIZE(gmbus_pins_icp);
130 else if (HAS_PCH_CNP(dev_priv))
131 size = ARRAY_SIZE(gmbus_pins_cnp);
132 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
133 size = ARRAY_SIZE(gmbus_pins_bxt);
134 else if (DISPLAY_VER(dev_priv) == 9)
135 size = ARRAY_SIZE(gmbus_pins_skl);
136 else if (IS_BROADWELL(dev_priv))
137 size = ARRAY_SIZE(gmbus_pins_bdw);
138 else
139 size = ARRAY_SIZE(gmbus_pins);
140
141 return pin < size && get_gmbus_pin(dev_priv, pin)->name;
142}
143
144/* Intel GPIO access functions */
145
146#define I2C_RISEFALL_TIME 10
147
148static inline struct intel_gmbus *
149to_intel_gmbus(struct i2c_adapter *i2c)
150{
151 return container_of(i2c, struct intel_gmbus, adapter);
152}
153
154void
155intel_gmbus_reset(struct drm_i915_private *dev_priv)
156{
157 intel_de_write(dev_priv, GMBUS0, 0);
158 intel_de_write(dev_priv, GMBUS4, 0);
159}
160
161static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
162 bool enable)
163{
164 u32 val;
165
166 /* When using bit bashing for I2C, this bit needs to be set to 1 */
167 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
168 if (!enable)
169 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
170 else
171 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
172 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
173}
174
175static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
176 bool enable)
177{
178 u32 val;
179
180 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
181 if (!enable)
182 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
183 else
184 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
185 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
186}
187
188static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
189 bool enable)
190{
191 u32 val;
192
193 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
194 if (!enable)
195 val |= BXT_GMBUS_GATING_DIS;
196 else
197 val &= ~BXT_GMBUS_GATING_DIS;
198 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
199}
200
201static u32 get_reserved(struct intel_gmbus *bus)
202{
203 struct drm_i915_private *i915 = bus->dev_priv;
204 struct intel_uncore *uncore = &i915->uncore;
205 u32 reserved = 0;
206
207 /* On most chips, these bits must be preserved in software. */
208 if (!IS_I830(i915) && !IS_I845G(i915))
209 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
210 (GPIO_DATA_PULLUP_DISABLE |
211 GPIO_CLOCK_PULLUP_DISABLE);
212
213 return reserved;
214}
215
216static int get_clock(void *data)
217{
218 struct intel_gmbus *bus = data;
219 struct intel_uncore *uncore = &bus->dev_priv->uncore;
220 u32 reserved = get_reserved(bus);
221
222 intel_uncore_write_notrace(uncore,
223 bus->gpio_reg,
224 reserved | GPIO_CLOCK_DIR_MASK);
225 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
226
227 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
228 GPIO_CLOCK_VAL_IN) != 0;
229}
230
231static int get_data(void *data)
232{
233 struct intel_gmbus *bus = data;
234 struct intel_uncore *uncore = &bus->dev_priv->uncore;
235 u32 reserved = get_reserved(bus);
236
237 intel_uncore_write_notrace(uncore,
238 bus->gpio_reg,
239 reserved | GPIO_DATA_DIR_MASK);
240 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
241
242 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
243 GPIO_DATA_VAL_IN) != 0;
244}
245
246static void set_clock(void *data, int state_high)
247{
248 struct intel_gmbus *bus = data;
249 struct intel_uncore *uncore = &bus->dev_priv->uncore;
250 u32 reserved = get_reserved(bus);
251 u32 clock_bits;
252
253 if (state_high)
254 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
255 else
256 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
257 GPIO_CLOCK_VAL_MASK;
258
259 intel_uncore_write_notrace(uncore,
260 bus->gpio_reg,
261 reserved | clock_bits);
262 intel_uncore_posting_read(uncore, bus->gpio_reg);
263}
264
265static void set_data(void *data, int state_high)
266{
267 struct intel_gmbus *bus = data;
268 struct intel_uncore *uncore = &bus->dev_priv->uncore;
269 u32 reserved = get_reserved(bus);
270 u32 data_bits;
271
272 if (state_high)
273 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
274 else
275 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
276 GPIO_DATA_VAL_MASK;
277
278 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
279 intel_uncore_posting_read(uncore, bus->gpio_reg);
280}
281
282static int
283intel_gpio_pre_xfer(struct i2c_adapter *adapter)
284{
285 struct intel_gmbus *bus = container_of(adapter,
286 struct intel_gmbus,
287 adapter);
288 struct drm_i915_private *dev_priv = bus->dev_priv;
289
290 intel_gmbus_reset(dev_priv);
291
292 if (IS_PINEVIEW(dev_priv))
293 pnv_gmbus_clock_gating(dev_priv, false);
294
295 set_data(bus, 1);
296 set_clock(bus, 1);
297 udelay(I2C_RISEFALL_TIME);
298 return 0;
299}
300
301static void
302intel_gpio_post_xfer(struct i2c_adapter *adapter)
303{
304 struct intel_gmbus *bus = container_of(adapter,
305 struct intel_gmbus,
306 adapter);
307 struct drm_i915_private *dev_priv = bus->dev_priv;
308
309 set_data(bus, 1);
310 set_clock(bus, 1);
311
312 if (IS_PINEVIEW(dev_priv))
313 pnv_gmbus_clock_gating(dev_priv, true);
314}
315
316static void
317intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
318{
319 struct drm_i915_private *dev_priv = bus->dev_priv;
320 struct i2c_algo_bit_data *algo;
321
322 algo = &bus->bit_algo;
323
324 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
325 bus->adapter.algo_data = algo;
326 algo->setsda = set_data;
327 algo->setscl = set_clock;
328 algo->getsda = get_data;
329 algo->getscl = get_clock;
330 algo->pre_xfer = intel_gpio_pre_xfer;
331 algo->post_xfer = intel_gpio_post_xfer;
332 algo->udelay = I2C_RISEFALL_TIME;
333 algo->timeout = usecs_to_jiffies(2200);
334 algo->data = bus;
335}
336
337static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
338{
339 DEFINE_WAIT(wait);
340 u32 gmbus2;
341 int ret;
342
343 /* Important: The hw handles only the first bit, so set only one! Since
344 * we also need to check for NAKs besides the hw ready/idle signal, we
345 * need to wake up periodically and check that ourselves.
346 */
347 if (!HAS_GMBUS_IRQ(dev_priv))
348 irq_en = 0;
349
350 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
351 intel_de_write_fw(dev_priv, GMBUS4, irq_en);
352
353 status |= GMBUS_SATOER;
354 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
355 2);
356 if (ret)
357 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
358 50);
359
360 intel_de_write_fw(dev_priv, GMBUS4, 0);
361 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
362
363 if (gmbus2 & GMBUS_SATOER)
364 return -ENXIO;
365
366 return ret;
367}
368
369static int
370gmbus_wait_idle(struct drm_i915_private *dev_priv)
371{
372 DEFINE_WAIT(wait);
373 u32 irq_enable;
374 int ret;
375
376 /* Important: The hw handles only the first bit, so set only one! */
377 irq_enable = 0;
378 if (HAS_GMBUS_IRQ(dev_priv))
379 irq_enable = GMBUS_IDLE_EN;
380
381 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
382 intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
383
384 ret = intel_wait_for_register_fw(&dev_priv->uncore,
385 GMBUS2, GMBUS_ACTIVE, 0,
386 10);
387
388 intel_de_write_fw(dev_priv, GMBUS4, 0);
389 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
390
391 return ret;
392}
393
394static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
395{
396 return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
397 GMBUS_BYTE_COUNT_MAX;
398}
399
400static int
401gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
402 unsigned short addr, u8 *buf, unsigned int len,
403 u32 gmbus0_reg, u32 gmbus1_index)
404{
405 unsigned int size = len;
406 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
407 bool extra_byte_added = false;
408
409 if (burst_read) {
410 /*
411 * As per HW Spec, for 512Bytes need to read extra Byte and
412 * Ignore the extra byte read.
413 */
414 if (len == 512) {
415 extra_byte_added = true;
416 len++;
417 }
418 size = len % 256 + 256;
419 intel_de_write_fw(dev_priv, GMBUS0,
420 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
421 }
422
423 intel_de_write_fw(dev_priv, GMBUS1,
424 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
425 while (len) {
426 int ret;
427 u32 val, loop = 0;
428
429 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
430 if (ret)
431 return ret;
432
433 val = intel_de_read_fw(dev_priv, GMBUS3);
434 do {
435 if (extra_byte_added && len == 1)
436 break;
437
438 *buf++ = val & 0xff;
439 val >>= 8;
440 } while (--len && ++loop < 4);
441
442 if (burst_read && len == size - 4)
443 /* Reset the override bit */
444 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
445 }
446
447 return 0;
448}
449
450/*
451 * HW spec says that 512Bytes in Burst read need special treatment.
452 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
453 * an I2C slave, which supports such a lengthy burst read too for experiments.
454 *
455 * So until things get clarified on HW support, to avoid the burst read length
456 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
457 */
458#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
459
460static int
461gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
462 u32 gmbus0_reg, u32 gmbus1_index)
463{
464 u8 *buf = msg->buf;
465 unsigned int rx_size = msg->len;
466 unsigned int len;
467 int ret;
468
469 do {
470 if (HAS_GMBUS_BURST_READ(dev_priv))
471 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
472 else
473 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
474
475 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
476 gmbus0_reg, gmbus1_index);
477 if (ret)
478 return ret;
479
480 rx_size -= len;
481 buf += len;
482 } while (rx_size != 0);
483
484 return 0;
485}
486
487static int
488gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
489 unsigned short addr, u8 *buf, unsigned int len,
490 u32 gmbus1_index)
491{
492 unsigned int chunk_size = len;
493 u32 val, loop;
494
495 val = loop = 0;
496 while (len && loop < 4) {
497 val |= *buf++ << (8 * loop++);
498 len -= 1;
499 }
500
501 intel_de_write_fw(dev_priv, GMBUS3, val);
502 intel_de_write_fw(dev_priv, GMBUS1,
503 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
504 while (len) {
505 int ret;
506
507 val = loop = 0;
508 do {
509 val |= *buf++ << (8 * loop);
510 } while (--len && ++loop < 4);
511
512 intel_de_write_fw(dev_priv, GMBUS3, val);
513
514 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
515 if (ret)
516 return ret;
517 }
518
519 return 0;
520}
521
522static int
523gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
524 u32 gmbus1_index)
525{
526 u8 *buf = msg->buf;
527 unsigned int tx_size = msg->len;
528 unsigned int len;
529 int ret;
530
531 do {
532 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
533
534 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
535 gmbus1_index);
536 if (ret)
537 return ret;
538
539 buf += len;
540 tx_size -= len;
541 } while (tx_size != 0);
542
543 return 0;
544}
545
546/*
547 * The gmbus controller can combine a 1 or 2 byte write with another read/write
548 * that immediately follows it by using an "INDEX" cycle.
549 */
550static bool
551gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
552{
553 return (i + 1 < num &&
554 msgs[i].addr == msgs[i + 1].addr &&
555 !(msgs[i].flags & I2C_M_RD) &&
556 (msgs[i].len == 1 || msgs[i].len == 2) &&
557 msgs[i + 1].len > 0);
558}
559
560static int
561gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
562 u32 gmbus0_reg)
563{
564 u32 gmbus1_index = 0;
565 u32 gmbus5 = 0;
566 int ret;
567
568 if (msgs[0].len == 2)
569 gmbus5 = GMBUS_2BYTE_INDEX_EN |
570 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
571 if (msgs[0].len == 1)
572 gmbus1_index = GMBUS_CYCLE_INDEX |
573 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
574
575 /* GMBUS5 holds 16-bit index */
576 if (gmbus5)
577 intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
578
579 if (msgs[1].flags & I2C_M_RD)
580 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
581 gmbus1_index);
582 else
583 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
584
585 /* Clear GMBUS5 after each index transfer */
586 if (gmbus5)
587 intel_de_write_fw(dev_priv, GMBUS5, 0);
588
589 return ret;
590}
591
592static int
593do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
594 u32 gmbus0_source)
595{
596 struct intel_gmbus *bus = container_of(adapter,
597 struct intel_gmbus,
598 adapter);
599 struct drm_i915_private *dev_priv = bus->dev_priv;
600 int i = 0, inc, try = 0;
601 int ret = 0;
602
603 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
604 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
605 bxt_gmbus_clock_gating(dev_priv, false);
606 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
607 pch_gmbus_clock_gating(dev_priv, false);
608
609retry:
610 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
611
612 for (; i < num; i += inc) {
613 inc = 1;
614 if (gmbus_is_index_xfer(msgs, i, num)) {
615 ret = gmbus_index_xfer(dev_priv, &msgs[i],
616 gmbus0_source | bus->reg0);
617 inc = 2; /* an index transmission is two msgs */
618 } else if (msgs[i].flags & I2C_M_RD) {
619 ret = gmbus_xfer_read(dev_priv, &msgs[i],
620 gmbus0_source | bus->reg0, 0);
621 } else {
622 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
623 }
624
625 if (!ret)
626 ret = gmbus_wait(dev_priv,
627 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
628 if (ret == -ETIMEDOUT)
629 goto timeout;
630 else if (ret)
631 goto clear_err;
632 }
633
634 /* Generate a STOP condition on the bus. Note that gmbus can't generata
635 * a STOP on the very first cycle. To simplify the code we
636 * unconditionally generate the STOP condition with an additional gmbus
637 * cycle. */
638 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
639
640 /* Mark the GMBUS interface as disabled after waiting for idle.
641 * We will re-enable it at the start of the next xfer,
642 * till then let it sleep.
643 */
644 if (gmbus_wait_idle(dev_priv)) {
645 drm_dbg_kms(&dev_priv->drm,
646 "GMBUS [%s] timed out waiting for idle\n",
647 adapter->name);
648 ret = -ETIMEDOUT;
649 }
650 intel_de_write_fw(dev_priv, GMBUS0, 0);
651 ret = ret ?: i;
652 goto out;
653
654clear_err:
655 /*
656 * Wait for bus to IDLE before clearing NAK.
657 * If we clear the NAK while bus is still active, then it will stay
658 * active and the next transaction may fail.
659 *
660 * If no ACK is received during the address phase of a transaction, the
661 * adapter must report -ENXIO. It is not clear what to return if no ACK
662 * is received at other times. But we have to be careful to not return
663 * spurious -ENXIO because that will prevent i2c and drm edid functions
664 * from retrying. So return -ENXIO only when gmbus properly quiescents -
665 * timing out seems to happen when there _is_ a ddc chip present, but
666 * it's slow responding and only answers on the 2nd retry.
667 */
668 ret = -ENXIO;
669 if (gmbus_wait_idle(dev_priv)) {
670 drm_dbg_kms(&dev_priv->drm,
671 "GMBUS [%s] timed out after NAK\n",
672 adapter->name);
673 ret = -ETIMEDOUT;
674 }
675
676 /* Toggle the Software Clear Interrupt bit. This has the effect
677 * of resetting the GMBUS controller and so clearing the
678 * BUS_ERROR raised by the slave's NAK.
679 */
680 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
681 intel_de_write_fw(dev_priv, GMBUS1, 0);
682 intel_de_write_fw(dev_priv, GMBUS0, 0);
683
684 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
685 adapter->name, msgs[i].addr,
686 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
687
688 /*
689 * Passive adapters sometimes NAK the first probe. Retry the first
690 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
691 * has retries internally. See also the retry loop in
692 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
693 */
694 if (ret == -ENXIO && i == 0 && try++ == 0) {
695 drm_dbg_kms(&dev_priv->drm,
696 "GMBUS [%s] NAK on first message, retry\n",
697 adapter->name);
698 goto retry;
699 }
700
701 goto out;
702
703timeout:
704 drm_dbg_kms(&dev_priv->drm,
705 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
706 bus->adapter.name, bus->reg0 & 0xff);
707 intel_de_write_fw(dev_priv, GMBUS0, 0);
708
709 /*
710 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
711 * instead. Use EAGAIN to have i2c core retry.
712 */
713 ret = -EAGAIN;
714
715out:
716 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
717 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
718 bxt_gmbus_clock_gating(dev_priv, true);
719 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
720 pch_gmbus_clock_gating(dev_priv, true);
721
722 return ret;
723}
724
725static int
726gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
727{
728 struct intel_gmbus *bus =
729 container_of(adapter, struct intel_gmbus, adapter);
730 struct drm_i915_private *dev_priv = bus->dev_priv;
731 intel_wakeref_t wakeref;
732 int ret;
733
734 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
735
736 if (bus->force_bit) {
737 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
738 if (ret < 0)
739 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
740 } else {
741 ret = do_gmbus_xfer(adapter, msgs, num, 0);
742 if (ret == -EAGAIN)
743 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
744 }
745
746 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
747
748 return ret;
749}
750
751int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
752{
753 struct intel_gmbus *bus =
754 container_of(adapter, struct intel_gmbus, adapter);
755 struct drm_i915_private *dev_priv = bus->dev_priv;
756 u8 cmd = DRM_HDCP_DDC_AKSV;
757 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
758 struct i2c_msg msgs[] = {
759 {
760 .addr = DRM_HDCP_DDC_ADDR,
761 .flags = 0,
762 .len = sizeof(cmd),
763 .buf = &cmd,
764 },
765 {
766 .addr = DRM_HDCP_DDC_ADDR,
767 .flags = 0,
768 .len = sizeof(buf),
769 .buf = buf,
770 }
771 };
772 intel_wakeref_t wakeref;
773 int ret;
774
775 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
776 mutex_lock(&dev_priv->gmbus_mutex);
777
778 /*
779 * In order to output Aksv to the receiver, use an indexed write to
780 * pass the i2c command, and tell GMBUS to use the HW-provided value
781 * instead of sourcing GMBUS3 for the data.
782 */
783 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
784
785 mutex_unlock(&dev_priv->gmbus_mutex);
786 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
787
788 return ret;
789}
790
791static u32 gmbus_func(struct i2c_adapter *adapter)
792{
793 return i2c_bit_algo.functionality(adapter) &
794 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
795 /* I2C_FUNC_10BIT_ADDR | */
796 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
797 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
798}
799
800static const struct i2c_algorithm gmbus_algorithm = {
801 .master_xfer = gmbus_xfer,
802 .functionality = gmbus_func
803};
804
805static void gmbus_lock_bus(struct i2c_adapter *adapter,
806 unsigned int flags)
807{
808 struct intel_gmbus *bus = to_intel_gmbus(adapter);
809 struct drm_i915_private *dev_priv = bus->dev_priv;
810
811 mutex_lock(&dev_priv->gmbus_mutex);
812}
813
814static int gmbus_trylock_bus(struct i2c_adapter *adapter,
815 unsigned int flags)
816{
817 struct intel_gmbus *bus = to_intel_gmbus(adapter);
818 struct drm_i915_private *dev_priv = bus->dev_priv;
819
820 return mutex_trylock(&dev_priv->gmbus_mutex);
821}
822
823static void gmbus_unlock_bus(struct i2c_adapter *adapter,
824 unsigned int flags)
825{
826 struct intel_gmbus *bus = to_intel_gmbus(adapter);
827 struct drm_i915_private *dev_priv = bus->dev_priv;
828
829 mutex_unlock(&dev_priv->gmbus_mutex);
830}
831
832static const struct i2c_lock_operations gmbus_lock_ops = {
833 .lock_bus = gmbus_lock_bus,
834 .trylock_bus = gmbus_trylock_bus,
835 .unlock_bus = gmbus_unlock_bus,
836};
837
838/**
839 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
840 * @dev_priv: i915 device private
841 */
842int intel_gmbus_setup(struct drm_i915_private *dev_priv)
843{
844 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
845 struct intel_gmbus *bus;
846 unsigned int pin;
847 int ret;
848
849 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
850 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
851 else if (!HAS_GMCH(dev_priv))
852 /*
853 * Broxton uses the same PCH offsets for South Display Engine,
854 * even though it doesn't have a PCH.
855 */
856 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
857
858 mutex_init(&dev_priv->gmbus_mutex);
859 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
860
861 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
862 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
863 continue;
864
865 bus = &dev_priv->gmbus[pin];
866
867 bus->adapter.owner = THIS_MODULE;
868 bus->adapter.class = I2C_CLASS_DDC;
869 snprintf(bus->adapter.name,
870 sizeof(bus->adapter.name),
871 "i915 gmbus %s",
872 get_gmbus_pin(dev_priv, pin)->name);
873
874 bus->adapter.dev.parent = &pdev->dev;
875 bus->dev_priv = dev_priv;
876
877 bus->adapter.algo = &gmbus_algorithm;
878 bus->adapter.lock_ops = &gmbus_lock_ops;
879
880 /*
881 * We wish to retry with bit banging
882 * after a timed out GMBUS attempt.
883 */
884 bus->adapter.retries = 1;
885
886 /* By default use a conservative clock rate */
887 bus->reg0 = pin | GMBUS_RATE_100KHZ;
888
889 /* gmbus seems to be broken on i830 */
890 if (IS_I830(dev_priv))
891 bus->force_bit = 1;
892
893 intel_gpio_setup(bus, pin);
894
895 ret = i2c_add_adapter(&bus->adapter);
896 if (ret)
897 goto err;
898 }
899
900 intel_gmbus_reset(dev_priv);
901
902 return 0;
903
904err:
905 while (pin--) {
906 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
907 continue;
908
909 bus = &dev_priv->gmbus[pin];
910 i2c_del_adapter(&bus->adapter);
911 }
912 return ret;
913}
914
915struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
916 unsigned int pin)
917{
918 if (drm_WARN_ON(&dev_priv->drm,
919 !intel_gmbus_is_valid_pin(dev_priv, pin)))
920 return NULL;
921
922 return &dev_priv->gmbus[pin].adapter;
923}
924
925void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
926{
927 struct intel_gmbus *bus = to_intel_gmbus(adapter);
928
929 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
930}
931
932void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
933{
934 struct intel_gmbus *bus = to_intel_gmbus(adapter);
935 struct drm_i915_private *dev_priv = bus->dev_priv;
936
937 mutex_lock(&dev_priv->gmbus_mutex);
938
939 bus->force_bit += force_bit ? 1 : -1;
940 drm_dbg_kms(&dev_priv->drm,
941 "%sabling bit-banging on %s. force bit now %d\n",
942 force_bit ? "en" : "dis", adapter->name,
943 bus->force_bit);
944
945 mutex_unlock(&dev_priv->gmbus_mutex);
946}
947
948bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
949{
950 struct intel_gmbus *bus = to_intel_gmbus(adapter);
951
952 return bus->force_bit;
953}
954
955void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
956{
957 struct intel_gmbus *bus;
958 unsigned int pin;
959
960 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
961 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
962 continue;
963
964 bus = &dev_priv->gmbus[pin];
965 i2c_del_adapter(&bus->adapter);
966 }
967}
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30#include <linux/export.h>
31#include <linux/i2c-algo-bit.h>
32#include <linux/i2c.h>
33
34#include <drm/display/drm_hdcp_helper.h>
35
36#include "i915_drv.h"
37#include "i915_irq.h"
38#include "i915_reg.h"
39#include "intel_de.h"
40#include "intel_display_types.h"
41#include "intel_gmbus.h"
42#include "intel_gmbus_regs.h"
43
44struct intel_gmbus {
45 struct i2c_adapter adapter;
46#define GMBUS_FORCE_BIT_RETRY (1U << 31)
47 u32 force_bit;
48 u32 reg0;
49 i915_reg_t gpio_reg;
50 struct i2c_algo_bit_data bit_algo;
51 struct intel_display *display;
52};
53
54enum gmbus_gpio {
55 GPIOA,
56 GPIOB,
57 GPIOC,
58 GPIOD,
59 GPIOE,
60 GPIOF,
61 GPIOG,
62 GPIOH,
63 __GPIOI_UNUSED,
64 GPIOJ,
65 GPIOK,
66 GPIOL,
67 GPIOM,
68 GPION,
69 GPIOO,
70};
71
72struct gmbus_pin {
73 const char *name;
74 enum gmbus_gpio gpio;
75};
76
77/* Map gmbus pin pairs to names and registers. */
78static const struct gmbus_pin gmbus_pins[] = {
79 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
81 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
82 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
83 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
84 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
85};
86
87static const struct gmbus_pin gmbus_pins_bdw[] = {
88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
89 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
90 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
91 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
92};
93
94static const struct gmbus_pin gmbus_pins_skl[] = {
95 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
96 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
97 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
98};
99
100static const struct gmbus_pin gmbus_pins_bxt[] = {
101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
104};
105
106static const struct gmbus_pin gmbus_pins_cnp[] = {
107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
111};
112
113static const struct gmbus_pin gmbus_pins_icp[] = {
114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
123};
124
125static const struct gmbus_pin gmbus_pins_dg1[] = {
126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
130};
131
132static const struct gmbus_pin gmbus_pins_dg2[] = {
133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
138};
139
140static const struct gmbus_pin gmbus_pins_mtp[] = {
141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
150};
151
152static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
153 unsigned int pin)
154{
155 struct drm_i915_private *i915 = to_i915(display->drm);
156 const struct gmbus_pin *pins;
157 size_t size;
158
159 if (INTEL_PCH_TYPE(i915) >= PCH_MTL) {
160 pins = gmbus_pins_mtp;
161 size = ARRAY_SIZE(gmbus_pins_mtp);
162 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
163 pins = gmbus_pins_dg2;
164 size = ARRAY_SIZE(gmbus_pins_dg2);
165 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
166 pins = gmbus_pins_dg1;
167 size = ARRAY_SIZE(gmbus_pins_dg1);
168 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
169 pins = gmbus_pins_icp;
170 size = ARRAY_SIZE(gmbus_pins_icp);
171 } else if (HAS_PCH_CNP(i915)) {
172 pins = gmbus_pins_cnp;
173 size = ARRAY_SIZE(gmbus_pins_cnp);
174 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
175 pins = gmbus_pins_bxt;
176 size = ARRAY_SIZE(gmbus_pins_bxt);
177 } else if (DISPLAY_VER(display) == 9) {
178 pins = gmbus_pins_skl;
179 size = ARRAY_SIZE(gmbus_pins_skl);
180 } else if (IS_BROADWELL(i915)) {
181 pins = gmbus_pins_bdw;
182 size = ARRAY_SIZE(gmbus_pins_bdw);
183 } else {
184 pins = gmbus_pins;
185 size = ARRAY_SIZE(gmbus_pins);
186 }
187
188 if (pin >= size || !pins[pin].name)
189 return NULL;
190
191 return &pins[pin];
192}
193
194bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
195{
196 return get_gmbus_pin(display, pin);
197}
198
199/* Intel GPIO access functions */
200
201#define I2C_RISEFALL_TIME 10
202
203static inline struct intel_gmbus *
204to_intel_gmbus(struct i2c_adapter *i2c)
205{
206 return container_of(i2c, struct intel_gmbus, adapter);
207}
208
209void
210intel_gmbus_reset(struct intel_display *display)
211{
212 intel_de_write(display, GMBUS0(display), 0);
213 intel_de_write(display, GMBUS4(display), 0);
214}
215
216static void pnv_gmbus_clock_gating(struct intel_display *display,
217 bool enable)
218{
219 /* When using bit bashing for I2C, this bit needs to be set to 1 */
220 intel_de_rmw(display, DSPCLK_GATE_D(display),
221 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
222 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
223}
224
225static void pch_gmbus_clock_gating(struct intel_display *display,
226 bool enable)
227{
228 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
229 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
230 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
231}
232
233static void bxt_gmbus_clock_gating(struct intel_display *display,
234 bool enable)
235{
236 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
237 !enable ? BXT_GMBUS_GATING_DIS : 0);
238}
239
240static u32 get_reserved(struct intel_gmbus *bus)
241{
242 struct intel_display *display = bus->display;
243 struct drm_i915_private *i915 = to_i915(display->drm);
244 u32 reserved = 0;
245
246 /* On most chips, these bits must be preserved in software. */
247 if (!IS_I830(i915) && !IS_I845G(i915))
248 reserved = intel_de_read_notrace(display, bus->gpio_reg) &
249 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
250
251 return reserved;
252}
253
254static int get_clock(void *data)
255{
256 struct intel_gmbus *bus = data;
257 struct intel_display *display = bus->display;
258 u32 reserved = get_reserved(bus);
259
260 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
261 intel_de_write_notrace(display, bus->gpio_reg, reserved);
262
263 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
264}
265
266static int get_data(void *data)
267{
268 struct intel_gmbus *bus = data;
269 struct intel_display *display = bus->display;
270 u32 reserved = get_reserved(bus);
271
272 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
273 intel_de_write_notrace(display, bus->gpio_reg, reserved);
274
275 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
276}
277
278static void set_clock(void *data, int state_high)
279{
280 struct intel_gmbus *bus = data;
281 struct intel_display *display = bus->display;
282 u32 reserved = get_reserved(bus);
283 u32 clock_bits;
284
285 if (state_high)
286 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
287 else
288 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
289 GPIO_CLOCK_VAL_MASK;
290
291 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
292 intel_de_posting_read(display, bus->gpio_reg);
293}
294
295static void set_data(void *data, int state_high)
296{
297 struct intel_gmbus *bus = data;
298 struct intel_display *display = bus->display;
299 u32 reserved = get_reserved(bus);
300 u32 data_bits;
301
302 if (state_high)
303 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
304 else
305 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
306 GPIO_DATA_VAL_MASK;
307
308 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
309 intel_de_posting_read(display, bus->gpio_reg);
310}
311
312static int
313intel_gpio_pre_xfer(struct i2c_adapter *adapter)
314{
315 struct intel_gmbus *bus = to_intel_gmbus(adapter);
316 struct intel_display *display = bus->display;
317 struct drm_i915_private *i915 = to_i915(display->drm);
318
319 intel_gmbus_reset(display);
320
321 if (IS_PINEVIEW(i915))
322 pnv_gmbus_clock_gating(display, false);
323
324 set_data(bus, 1);
325 set_clock(bus, 1);
326 udelay(I2C_RISEFALL_TIME);
327 return 0;
328}
329
330static void
331intel_gpio_post_xfer(struct i2c_adapter *adapter)
332{
333 struct intel_gmbus *bus = to_intel_gmbus(adapter);
334 struct intel_display *display = bus->display;
335 struct drm_i915_private *i915 = to_i915(display->drm);
336
337 set_data(bus, 1);
338 set_clock(bus, 1);
339
340 if (IS_PINEVIEW(i915))
341 pnv_gmbus_clock_gating(display, true);
342}
343
344static void
345intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
346{
347 struct i2c_algo_bit_data *algo;
348
349 algo = &bus->bit_algo;
350
351 bus->gpio_reg = gpio_reg;
352 bus->adapter.algo_data = algo;
353 algo->setsda = set_data;
354 algo->setscl = set_clock;
355 algo->getsda = get_data;
356 algo->getscl = get_clock;
357 algo->pre_xfer = intel_gpio_pre_xfer;
358 algo->post_xfer = intel_gpio_post_xfer;
359 algo->udelay = I2C_RISEFALL_TIME;
360 algo->timeout = usecs_to_jiffies(2200);
361 algo->data = bus;
362}
363
364static bool has_gmbus_irq(struct intel_display *display)
365{
366 struct drm_i915_private *i915 = to_i915(display->drm);
367 /*
368 * encoder->shutdown() may want to use GMBUS
369 * after irqs have already been disabled.
370 */
371 return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);
372}
373
374static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
375{
376 DEFINE_WAIT(wait);
377 u32 gmbus2;
378 int ret;
379
380 /* Important: The hw handles only the first bit, so set only one! Since
381 * we also need to check for NAKs besides the hw ready/idle signal, we
382 * need to wake up periodically and check that ourselves.
383 */
384 if (!has_gmbus_irq(display))
385 irq_en = 0;
386
387 add_wait_queue(&display->gmbus.wait_queue, &wait);
388 intel_de_write_fw(display, GMBUS4(display), irq_en);
389
390 status |= GMBUS_SATOER;
391 ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
392 2);
393 if (ret)
394 ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
395 50);
396
397 intel_de_write_fw(display, GMBUS4(display), 0);
398 remove_wait_queue(&display->gmbus.wait_queue, &wait);
399
400 if (gmbus2 & GMBUS_SATOER)
401 return -ENXIO;
402
403 return ret;
404}
405
406static int
407gmbus_wait_idle(struct intel_display *display)
408{
409 DEFINE_WAIT(wait);
410 u32 irq_enable;
411 int ret;
412
413 /* Important: The hw handles only the first bit, so set only one! */
414 irq_enable = 0;
415 if (has_gmbus_irq(display))
416 irq_enable = GMBUS_IDLE_EN;
417
418 add_wait_queue(&display->gmbus.wait_queue, &wait);
419 intel_de_write_fw(display, GMBUS4(display), irq_enable);
420
421 ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10);
422
423 intel_de_write_fw(display, GMBUS4(display), 0);
424 remove_wait_queue(&display->gmbus.wait_queue, &wait);
425
426 return ret;
427}
428
429static unsigned int gmbus_max_xfer_size(struct intel_display *display)
430{
431 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
432 GMBUS_BYTE_COUNT_MAX;
433}
434
435static int
436gmbus_xfer_read_chunk(struct intel_display *display,
437 unsigned short addr, u8 *buf, unsigned int len,
438 u32 gmbus0_reg, u32 gmbus1_index)
439{
440 unsigned int size = len;
441 bool burst_read = len > gmbus_max_xfer_size(display);
442 bool extra_byte_added = false;
443
444 if (burst_read) {
445 /*
446 * As per HW Spec, for 512Bytes need to read extra Byte and
447 * Ignore the extra byte read.
448 */
449 if (len == 512) {
450 extra_byte_added = true;
451 len++;
452 }
453 size = len % 256 + 256;
454 intel_de_write_fw(display, GMBUS0(display),
455 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
456 }
457
458 intel_de_write_fw(display, GMBUS1(display),
459 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
460 while (len) {
461 int ret;
462 u32 val, loop = 0;
463
464 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
465 if (ret)
466 return ret;
467
468 val = intel_de_read_fw(display, GMBUS3(display));
469 do {
470 if (extra_byte_added && len == 1)
471 break;
472
473 *buf++ = val & 0xff;
474 val >>= 8;
475 } while (--len && ++loop < 4);
476
477 if (burst_read && len == size - 4)
478 /* Reset the override bit */
479 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
480 }
481
482 return 0;
483}
484
485/*
486 * HW spec says that 512Bytes in Burst read need special treatment.
487 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
488 * an I2C target, which supports such a lengthy burst read too for experiments.
489 *
490 * So until things get clarified on HW support, to avoid the burst read length
491 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
492 */
493#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
494
495static int
496gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
497 u32 gmbus0_reg, u32 gmbus1_index)
498{
499 struct drm_i915_private *i915 = to_i915(display->drm);
500 u8 *buf = msg->buf;
501 unsigned int rx_size = msg->len;
502 unsigned int len;
503 int ret;
504
505 do {
506 if (HAS_GMBUS_BURST_READ(i915))
507 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
508 else
509 len = min(rx_size, gmbus_max_xfer_size(display));
510
511 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
512 gmbus0_reg, gmbus1_index);
513 if (ret)
514 return ret;
515
516 rx_size -= len;
517 buf += len;
518 } while (rx_size != 0);
519
520 return 0;
521}
522
523static int
524gmbus_xfer_write_chunk(struct intel_display *display,
525 unsigned short addr, u8 *buf, unsigned int len,
526 u32 gmbus1_index)
527{
528 unsigned int chunk_size = len;
529 u32 val, loop;
530
531 val = loop = 0;
532 while (len && loop < 4) {
533 val |= *buf++ << (8 * loop++);
534 len -= 1;
535 }
536
537 intel_de_write_fw(display, GMBUS3(display), val);
538 intel_de_write_fw(display, GMBUS1(display),
539 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
540 while (len) {
541 int ret;
542
543 val = loop = 0;
544 do {
545 val |= *buf++ << (8 * loop);
546 } while (--len && ++loop < 4);
547
548 intel_de_write_fw(display, GMBUS3(display), val);
549
550 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
551 if (ret)
552 return ret;
553 }
554
555 return 0;
556}
557
558static int
559gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
560 u32 gmbus1_index)
561{
562 u8 *buf = msg->buf;
563 unsigned int tx_size = msg->len;
564 unsigned int len;
565 int ret;
566
567 do {
568 len = min(tx_size, gmbus_max_xfer_size(display));
569
570 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
571 gmbus1_index);
572 if (ret)
573 return ret;
574
575 buf += len;
576 tx_size -= len;
577 } while (tx_size != 0);
578
579 return 0;
580}
581
582/*
583 * The gmbus controller can combine a 1 or 2 byte write with another read/write
584 * that immediately follows it by using an "INDEX" cycle.
585 */
586static bool
587gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
588{
589 return (i + 1 < num &&
590 msgs[i].addr == msgs[i + 1].addr &&
591 !(msgs[i].flags & I2C_M_RD) &&
592 (msgs[i].len == 1 || msgs[i].len == 2) &&
593 msgs[i + 1].len > 0);
594}
595
596static int
597gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
598 u32 gmbus0_reg)
599{
600 u32 gmbus1_index = 0;
601 u32 gmbus5 = 0;
602 int ret;
603
604 if (msgs[0].len == 2)
605 gmbus5 = GMBUS_2BYTE_INDEX_EN |
606 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
607 if (msgs[0].len == 1)
608 gmbus1_index = GMBUS_CYCLE_INDEX |
609 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
610
611 /* GMBUS5 holds 16-bit index */
612 if (gmbus5)
613 intel_de_write_fw(display, GMBUS5(display), gmbus5);
614
615 if (msgs[1].flags & I2C_M_RD)
616 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
617 gmbus1_index);
618 else
619 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
620
621 /* Clear GMBUS5 after each index transfer */
622 if (gmbus5)
623 intel_de_write_fw(display, GMBUS5(display), 0);
624
625 return ret;
626}
627
628static int
629do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
630 u32 gmbus0_source)
631{
632 struct intel_gmbus *bus = to_intel_gmbus(adapter);
633 struct intel_display *display = bus->display;
634 struct drm_i915_private *i915 = to_i915(display->drm);
635 int i = 0, inc, try = 0;
636 int ret = 0;
637
638 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
639 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
640 bxt_gmbus_clock_gating(display, false);
641 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
642 pch_gmbus_clock_gating(display, false);
643
644retry:
645 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
646
647 for (; i < num; i += inc) {
648 inc = 1;
649 if (gmbus_is_index_xfer(msgs, i, num)) {
650 ret = gmbus_index_xfer(display, &msgs[i],
651 gmbus0_source | bus->reg0);
652 inc = 2; /* an index transmission is two msgs */
653 } else if (msgs[i].flags & I2C_M_RD) {
654 ret = gmbus_xfer_read(display, &msgs[i],
655 gmbus0_source | bus->reg0, 0);
656 } else {
657 ret = gmbus_xfer_write(display, &msgs[i], 0);
658 }
659
660 if (!ret)
661 ret = gmbus_wait(display,
662 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
663 if (ret == -ETIMEDOUT)
664 goto timeout;
665 else if (ret)
666 goto clear_err;
667 }
668
669 /* Generate a STOP condition on the bus. Note that gmbus can't generata
670 * a STOP on the very first cycle. To simplify the code we
671 * unconditionally generate the STOP condition with an additional gmbus
672 * cycle. */
673 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
674
675 /* Mark the GMBUS interface as disabled after waiting for idle.
676 * We will re-enable it at the start of the next xfer,
677 * till then let it sleep.
678 */
679 if (gmbus_wait_idle(display)) {
680 drm_dbg_kms(display->drm,
681 "GMBUS [%s] timed out waiting for idle\n",
682 adapter->name);
683 ret = -ETIMEDOUT;
684 }
685 intel_de_write_fw(display, GMBUS0(display), 0);
686 ret = ret ?: i;
687 goto out;
688
689clear_err:
690 /*
691 * Wait for bus to IDLE before clearing NAK.
692 * If we clear the NAK while bus is still active, then it will stay
693 * active and the next transaction may fail.
694 *
695 * If no ACK is received during the address phase of a transaction, the
696 * adapter must report -ENXIO. It is not clear what to return if no ACK
697 * is received at other times. But we have to be careful to not return
698 * spurious -ENXIO because that will prevent i2c and drm edid functions
699 * from retrying. So return -ENXIO only when gmbus properly quiescents -
700 * timing out seems to happen when there _is_ a ddc chip present, but
701 * it's slow responding and only answers on the 2nd retry.
702 */
703 ret = -ENXIO;
704 if (gmbus_wait_idle(display)) {
705 drm_dbg_kms(display->drm,
706 "GMBUS [%s] timed out after NAK\n",
707 adapter->name);
708 ret = -ETIMEDOUT;
709 }
710
711 /* Toggle the Software Clear Interrupt bit. This has the effect
712 * of resetting the GMBUS controller and so clearing the
713 * BUS_ERROR raised by the target's NAK.
714 */
715 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
716 intel_de_write_fw(display, GMBUS1(display), 0);
717 intel_de_write_fw(display, GMBUS0(display), 0);
718
719 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
720 adapter->name, msgs[i].addr,
721 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
722
723 /*
724 * Passive adapters sometimes NAK the first probe. Retry the first
725 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
726 * has retries internally. See also the retry loop in
727 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
728 */
729 if (ret == -ENXIO && i == 0 && try++ == 0) {
730 drm_dbg_kms(display->drm,
731 "GMBUS [%s] NAK on first message, retry\n",
732 adapter->name);
733 goto retry;
734 }
735
736 goto out;
737
738timeout:
739 drm_dbg_kms(display->drm,
740 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
741 bus->adapter.name, bus->reg0 & 0xff);
742 intel_de_write_fw(display, GMBUS0(display), 0);
743
744 /*
745 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
746 * instead. Use EAGAIN to have i2c core retry.
747 */
748 ret = -EAGAIN;
749
750out:
751 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
752 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
753 bxt_gmbus_clock_gating(display, true);
754 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
755 pch_gmbus_clock_gating(display, true);
756
757 return ret;
758}
759
760static int
761gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
762{
763 struct intel_gmbus *bus = to_intel_gmbus(adapter);
764 struct intel_display *display = bus->display;
765 struct drm_i915_private *i915 = to_i915(display->drm);
766 intel_wakeref_t wakeref;
767 int ret;
768
769 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
770
771 if (bus->force_bit) {
772 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
773 if (ret < 0)
774 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
775 } else {
776 ret = do_gmbus_xfer(adapter, msgs, num, 0);
777 if (ret == -EAGAIN)
778 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
779 }
780
781 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
782
783 return ret;
784}
785
786int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
787{
788 struct intel_gmbus *bus = to_intel_gmbus(adapter);
789 struct intel_display *display = bus->display;
790 struct drm_i915_private *i915 = to_i915(display->drm);
791 u8 cmd = DRM_HDCP_DDC_AKSV;
792 u8 buf[DRM_HDCP_KSV_LEN] = {};
793 struct i2c_msg msgs[] = {
794 {
795 .addr = DRM_HDCP_DDC_ADDR,
796 .flags = 0,
797 .len = sizeof(cmd),
798 .buf = &cmd,
799 },
800 {
801 .addr = DRM_HDCP_DDC_ADDR,
802 .flags = 0,
803 .len = sizeof(buf),
804 .buf = buf,
805 }
806 };
807 intel_wakeref_t wakeref;
808 int ret;
809
810 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
811 mutex_lock(&display->gmbus.mutex);
812
813 /*
814 * In order to output Aksv to the receiver, use an indexed write to
815 * pass the i2c command, and tell GMBUS to use the HW-provided value
816 * instead of sourcing GMBUS3 for the data.
817 */
818 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
819
820 mutex_unlock(&display->gmbus.mutex);
821 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
822
823 return ret;
824}
825
826static u32 gmbus_func(struct i2c_adapter *adapter)
827{
828 return i2c_bit_algo.functionality(adapter) &
829 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
830 /* I2C_FUNC_10BIT_ADDR | */
831 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
832 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
833}
834
835static const struct i2c_algorithm gmbus_algorithm = {
836 .master_xfer = gmbus_xfer,
837 .functionality = gmbus_func
838};
839
840static void gmbus_lock_bus(struct i2c_adapter *adapter,
841 unsigned int flags)
842{
843 struct intel_gmbus *bus = to_intel_gmbus(adapter);
844 struct intel_display *display = bus->display;
845
846 mutex_lock(&display->gmbus.mutex);
847}
848
849static int gmbus_trylock_bus(struct i2c_adapter *adapter,
850 unsigned int flags)
851{
852 struct intel_gmbus *bus = to_intel_gmbus(adapter);
853 struct intel_display *display = bus->display;
854
855 return mutex_trylock(&display->gmbus.mutex);
856}
857
858static void gmbus_unlock_bus(struct i2c_adapter *adapter,
859 unsigned int flags)
860{
861 struct intel_gmbus *bus = to_intel_gmbus(adapter);
862 struct intel_display *display = bus->display;
863
864 mutex_unlock(&display->gmbus.mutex);
865}
866
867static const struct i2c_lock_operations gmbus_lock_ops = {
868 .lock_bus = gmbus_lock_bus,
869 .trylock_bus = gmbus_trylock_bus,
870 .unlock_bus = gmbus_unlock_bus,
871};
872
873/**
874 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
875 * @display: display device
876 */
877int intel_gmbus_setup(struct intel_display *display)
878{
879 struct drm_i915_private *i915 = to_i915(display->drm);
880 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
881 unsigned int pin;
882 int ret;
883
884 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
885 display->gmbus.mmio_base = VLV_DISPLAY_BASE;
886 else if (!HAS_GMCH(display))
887 /*
888 * Broxton uses the same PCH offsets for South Display Engine,
889 * even though it doesn't have a PCH.
890 */
891 display->gmbus.mmio_base = PCH_DISPLAY_BASE;
892
893 mutex_init(&display->gmbus.mutex);
894 init_waitqueue_head(&display->gmbus.wait_queue);
895
896 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
897 const struct gmbus_pin *gmbus_pin;
898 struct intel_gmbus *bus;
899
900 gmbus_pin = get_gmbus_pin(display, pin);
901 if (!gmbus_pin)
902 continue;
903
904 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
905 if (!bus) {
906 ret = -ENOMEM;
907 goto err;
908 }
909
910 bus->adapter.owner = THIS_MODULE;
911 snprintf(bus->adapter.name,
912 sizeof(bus->adapter.name),
913 "i915 gmbus %s", gmbus_pin->name);
914
915 bus->adapter.dev.parent = &pdev->dev;
916 bus->display = display;
917
918 bus->adapter.algo = &gmbus_algorithm;
919 bus->adapter.lock_ops = &gmbus_lock_ops;
920
921 /*
922 * We wish to retry with bit banging
923 * after a timed out GMBUS attempt.
924 */
925 bus->adapter.retries = 1;
926
927 /* By default use a conservative clock rate */
928 bus->reg0 = pin | GMBUS_RATE_100KHZ;
929
930 /* gmbus seems to be broken on i830 */
931 if (IS_I830(i915))
932 bus->force_bit = 1;
933
934 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
935
936 ret = i2c_add_adapter(&bus->adapter);
937 if (ret) {
938 kfree(bus);
939 goto err;
940 }
941
942 display->gmbus.bus[pin] = bus;
943 }
944
945 intel_gmbus_reset(display);
946
947 return 0;
948
949err:
950 intel_gmbus_teardown(display);
951
952 return ret;
953}
954
955struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
956 unsigned int pin)
957{
958 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
959 !display->gmbus.bus[pin]))
960 return NULL;
961
962 return &display->gmbus.bus[pin]->adapter;
963}
964
965void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
966{
967 struct intel_gmbus *bus = to_intel_gmbus(adapter);
968 struct intel_display *display = bus->display;
969
970 mutex_lock(&display->gmbus.mutex);
971
972 bus->force_bit += force_bit ? 1 : -1;
973 drm_dbg_kms(display->drm,
974 "%sabling bit-banging on %s. force bit now %d\n",
975 force_bit ? "en" : "dis", adapter->name,
976 bus->force_bit);
977
978 mutex_unlock(&display->gmbus.mutex);
979}
980
981bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
982{
983 struct intel_gmbus *bus = to_intel_gmbus(adapter);
984
985 return bus->force_bit;
986}
987
988void intel_gmbus_teardown(struct intel_display *display)
989{
990 unsigned int pin;
991
992 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
993 struct intel_gmbus *bus;
994
995 bus = display->gmbus.bus[pin];
996 if (!bus)
997 continue;
998
999 i2c_del_adapter(&bus->adapter);
1000
1001 kfree(bus);
1002 display->gmbus.bus[pin] = NULL;
1003 }
1004}
1005
1006void intel_gmbus_irq_handler(struct intel_display *display)
1007{
1008 wake_up_all(&display->gmbus.wait_queue);
1009}