1/* SPDX-License-Identifier: MIT
 2 *
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef _INTEL_DSB_H
 7#define _INTEL_DSB_H
 8
 9#include <linux/types.h>
10
11#include "i915_reg.h"
12
 
 
13struct intel_crtc_state;
14struct i915_vma;
 
15
16enum dsb_id {
17	INVALID_DSB = -1,
18	DSB1,
19	DSB2,
20	DSB3,
21	MAX_DSB_PER_PIPE
22};
23
24struct intel_dsb {
25	enum dsb_id id;
26	u32 *cmd_buf;
27	struct i915_vma *vma;
28
29	/*
30	 * free_pos will point the first free entry position
31	 * and help in calculating tail of command buffer.
32	 */
33	int free_pos;
34
35	/*
36	 * ins_start_offset will help to store start address of the dsb
37	 * instuction and help in identifying the batch of auto-increment
38	 * register.
39	 */
40	u32 ins_start_offset;
41};
42
43void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
44void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
45void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
 
 
 
 
46			 i915_reg_t reg, u32 val);
47void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
48				 i915_reg_t reg, u32 val);
49void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
50
51#endif

 1/* SPDX-License-Identifier: MIT
 2 *
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef _INTEL_DSB_H
 7#define _INTEL_DSB_H
 8
 9#include <linux/types.h>
10
11#include "i915_reg_defs.h"
12
13struct intel_atomic_state;
14struct intel_crtc;
15struct intel_crtc_state;
16struct intel_display;
17struct intel_dsb;
18
19enum pipe;
20
21enum intel_dsb_id {
22	INTEL_DSB_0,
23	INTEL_DSB_1,
24	INTEL_DSB_2,
 
25
26	I915_MAX_DSBS,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
27};
28
29struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
30				    struct intel_crtc *crtc,
31				    enum intel_dsb_id dsb_id,
32				    unsigned int max_cmds);
33void intel_dsb_finish(struct intel_dsb *dsb);
34void intel_dsb_cleanup(struct intel_dsb *dsb);
35void intel_dsb_reg_write(struct intel_dsb *dsb,
36			 i915_reg_t reg, u32 val);
37void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
38				 i915_reg_t reg, u32 val);
39void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
40				i915_reg_t reg, u32 mask, u32 val);
41void intel_dsb_noop(struct intel_dsb *dsb, int count);
42void intel_dsb_nonpost_start(struct intel_dsb *dsb);
43void intel_dsb_nonpost_end(struct intel_dsb *dsb);
44void intel_dsb_interrupt(struct intel_dsb *dsb);
45void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
46void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
47void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
48				 struct intel_dsb *dsb);
49void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
50				struct intel_dsb *dsb,
51				int lower, int upper);
52void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
53				 struct intel_dsb *dsb,
54				 int lower, int upper);
55void intel_dsb_vblank_evade(struct intel_atomic_state *state,
56			    struct intel_dsb *dsb);
57void intel_dsb_chain(struct intel_atomic_state *state,
58		     struct intel_dsb *dsb,
59		     struct intel_dsb *chained_dsb,
60		     bool wait_for_vblank);
61
62void intel_dsb_commit(struct intel_dsb *dsb,
63		      bool wait_for_vblank);
64void intel_dsb_wait(struct intel_dsb *dsb);
65
66void intel_dsb_irq_handler(struct intel_display *display,
67			   enum pipe pipe, enum intel_dsb_id dsb_id);
68
69#endif